1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * SPI bus driver for the Topcliff PCH used by Intel SoCs
4 *
5 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
6 */
7
8 #include <linux/delay.h>
9 #include <linux/pci.h>
10 #include <linux/wait.h>
11 #include <linux/spi/spi.h>
12 #include <linux/interrupt.h>
13 #include <linux/sched.h>
14 #include <linux/spi/spidev.h>
15 #include <linux/module.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
18
19 #include <linux/dmaengine.h>
20 #include <linux/pch_dma.h>
21
22 /* Register offsets */
23 #define PCH_SPCR 0x00 /* SPI control register */
24 #define PCH_SPBRR 0x04 /* SPI baud rate register */
25 #define PCH_SPSR 0x08 /* SPI status register */
26 #define PCH_SPDWR 0x0C /* SPI write data register */
27 #define PCH_SPDRR 0x10 /* SPI read data register */
28 #define PCH_SSNXCR 0x18 /* SSN Expand Control Register */
29 #define PCH_SRST 0x1C /* SPI reset register */
30 #define PCH_ADDRESS_SIZE 0x20
31
32 #define PCH_SPSR_TFD 0x000007C0
33 #define PCH_SPSR_RFD 0x0000F800
34
35 #define PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11)
36 #define PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6)
37
38 #define PCH_RX_THOLD 7
39 #define PCH_RX_THOLD_MAX 15
40
41 #define PCH_TX_THOLD 2
42
43 #define PCH_MAX_BAUDRATE 5000000
44 #define PCH_MAX_FIFO_DEPTH 16
45
46 #define STATUS_RUNNING 1
47 #define STATUS_EXITING 2
48 #define PCH_SLEEP_TIME 10
49
50 #define SSN_LOW 0x02U
51 #define SSN_HIGH 0x03U
52 #define SSN_NO_CONTROL 0x00U
53 #define PCH_MAX_CS 0xFF
54 #define PCI_DEVICE_ID_GE_SPI 0x8816
55
56 #define SPCR_SPE_BIT (1 << 0)
57 #define SPCR_MSTR_BIT (1 << 1)
58 #define SPCR_LSBF_BIT (1 << 4)
59 #define SPCR_CPHA_BIT (1 << 5)
60 #define SPCR_CPOL_BIT (1 << 6)
61 #define SPCR_TFIE_BIT (1 << 8)
62 #define SPCR_RFIE_BIT (1 << 9)
63 #define SPCR_FIE_BIT (1 << 10)
64 #define SPCR_ORIE_BIT (1 << 11)
65 #define SPCR_MDFIE_BIT (1 << 12)
66 #define SPCR_FICLR_BIT (1 << 24)
67 #define SPSR_TFI_BIT (1 << 0)
68 #define SPSR_RFI_BIT (1 << 1)
69 #define SPSR_FI_BIT (1 << 2)
70 #define SPSR_ORF_BIT (1 << 3)
71 #define SPBRR_SIZE_BIT (1 << 10)
72
73 #define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
74 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
75
76 #define SPCR_RFIC_FIELD 20
77 #define SPCR_TFIC_FIELD 16
78
79 #define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1)
80 #define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD)
81 #define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD)
82
83 #define PCH_CLOCK_HZ 50000000
84 #define PCH_MAX_SPBR 1023
85
86 /* Definition for ML7213/ML7223/ML7831 by LAPIS Semiconductor */
87 #define PCI_DEVICE_ID_ML7213_SPI 0x802c
88 #define PCI_DEVICE_ID_ML7223_SPI 0x800F
89 #define PCI_DEVICE_ID_ML7831_SPI 0x8816
90
91 /*
92 * Set the number of SPI instance max
93 * Intel EG20T PCH : 1ch
94 * LAPIS Semiconductor ML7213 IOH : 2ch
95 * LAPIS Semiconductor ML7223 IOH : 1ch
96 * LAPIS Semiconductor ML7831 IOH : 1ch
97 */
98 #define PCH_SPI_MAX_DEV 2
99
100 #define PCH_BUF_SIZE 4096
101 #define PCH_DMA_TRANS_SIZE 12
102
103 static int use_dma = 1;
104
105 struct pch_spi_dma_ctrl {
106 struct pci_dev *dma_dev;
107 struct dma_async_tx_descriptor *desc_tx;
108 struct dma_async_tx_descriptor *desc_rx;
109 struct pch_dma_slave param_tx;
110 struct pch_dma_slave param_rx;
111 struct dma_chan *chan_tx;
112 struct dma_chan *chan_rx;
113 struct scatterlist *sg_tx_p;
114 struct scatterlist *sg_rx_p;
115 struct scatterlist sg_tx;
116 struct scatterlist sg_rx;
117 int nent;
118 void *tx_buf_virt;
119 void *rx_buf_virt;
120 dma_addr_t tx_buf_dma;
121 dma_addr_t rx_buf_dma;
122 };
123 /**
124 * struct pch_spi_data - Holds the SPI channel specific details
125 * @io_remap_addr: The remapped PCI base address
126 * @io_base_addr: Base address
127 * @master: Pointer to the SPI master structure
128 * @work: Reference to work queue handler
129 * @wait: Wait queue for waking up upon receiving an
130 * interrupt.
131 * @transfer_complete: Status of SPI Transfer
132 * @bcurrent_msg_processing: Status flag for message processing
133 * @lock: Lock for protecting this structure
134 * @queue: SPI Message queue
135 * @status: Status of the SPI driver
136 * @bpw_len: Length of data to be transferred in bits per
137 * word
138 * @transfer_active: Flag showing active transfer
139 * @tx_index: Transmit data count; for bookkeeping during
140 * transfer
141 * @rx_index: Receive data count; for bookkeeping during
142 * transfer
143 * @pkt_tx_buff: Buffer for data to be transmitted
144 * @pkt_rx_buff: Buffer for received data
145 * @n_curnt_chip: The chip number that this SPI driver currently
146 * operates on
147 * @current_chip: Reference to the current chip that this SPI
148 * driver currently operates on
149 * @current_msg: The current message that this SPI driver is
150 * handling
151 * @cur_trans: The current transfer that this SPI driver is
152 * handling
153 * @board_dat: Reference to the SPI device data structure
154 * @plat_dev: platform_device structure
155 * @ch: SPI channel number
156 * @dma: Local DMA information
157 * @use_dma: True if DMA is to be used
158 * @irq_reg_sts: Status of IRQ registration
159 * @save_total_len: Save length while data is being transferred
160 */
161 struct pch_spi_data {
162 void __iomem *io_remap_addr;
163 unsigned long io_base_addr;
164 struct spi_master *master;
165 struct work_struct work;
166 wait_queue_head_t wait;
167 u8 transfer_complete;
168 u8 bcurrent_msg_processing;
169 spinlock_t lock;
170 struct list_head queue;
171 u8 status;
172 u32 bpw_len;
173 u8 transfer_active;
174 u32 tx_index;
175 u32 rx_index;
176 u16 *pkt_tx_buff;
177 u16 *pkt_rx_buff;
178 u8 n_curnt_chip;
179 struct spi_device *current_chip;
180 struct spi_message *current_msg;
181 struct spi_transfer *cur_trans;
182 struct pch_spi_board_data *board_dat;
183 struct platform_device *plat_dev;
184 int ch;
185 struct pch_spi_dma_ctrl dma;
186 int use_dma;
187 u8 irq_reg_sts;
188 int save_total_len;
189 };
190
191 /**
192 * struct pch_spi_board_data - Holds the SPI device specific details
193 * @pdev: Pointer to the PCI device
194 * @suspend_sts: Status of suspend
195 * @num: The number of SPI device instance
196 */
197 struct pch_spi_board_data {
198 struct pci_dev *pdev;
199 u8 suspend_sts;
200 int num;
201 };
202
203 struct pch_pd_dev_save {
204 int num;
205 struct platform_device *pd_save[PCH_SPI_MAX_DEV];
206 struct pch_spi_board_data *board_dat;
207 };
208
209 static const struct pci_device_id pch_spi_pcidev_id[] = {
210 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, },
211 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
212 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
213 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_SPI), 1, },
214 { }
215 };
216
217 /**
218 * pch_spi_writereg() - Performs register writes
219 * @master: Pointer to struct spi_master.
220 * @idx: Register offset.
221 * @val: Value to be written to register.
222 */
pch_spi_writereg(struct spi_master * master,int idx,u32 val)223 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
224 {
225 struct pch_spi_data *data = spi_master_get_devdata(master);
226 iowrite32(val, (data->io_remap_addr + idx));
227 }
228
229 /**
230 * pch_spi_readreg() - Performs register reads
231 * @master: Pointer to struct spi_master.
232 * @idx: Register offset.
233 */
pch_spi_readreg(struct spi_master * master,int idx)234 static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
235 {
236 struct pch_spi_data *data = spi_master_get_devdata(master);
237 return ioread32(data->io_remap_addr + idx);
238 }
239
pch_spi_setclr_reg(struct spi_master * master,int idx,u32 set,u32 clr)240 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
241 u32 set, u32 clr)
242 {
243 u32 tmp = pch_spi_readreg(master, idx);
244 tmp = (tmp & ~clr) | set;
245 pch_spi_writereg(master, idx, tmp);
246 }
247
pch_spi_set_master_mode(struct spi_master * master)248 static void pch_spi_set_master_mode(struct spi_master *master)
249 {
250 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
251 }
252
253 /**
254 * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
255 * @master: Pointer to struct spi_master.
256 */
pch_spi_clear_fifo(struct spi_master * master)257 static void pch_spi_clear_fifo(struct spi_master *master)
258 {
259 pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
260 pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
261 }
262
pch_spi_handler_sub(struct pch_spi_data * data,u32 reg_spsr_val,void __iomem * io_remap_addr)263 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
264 void __iomem *io_remap_addr)
265 {
266 u32 n_read, tx_index, rx_index, bpw_len;
267 u16 *pkt_rx_buffer, *pkt_tx_buff;
268 int read_cnt;
269 u32 reg_spcr_val;
270 void __iomem *spsr;
271 void __iomem *spdrr;
272 void __iomem *spdwr;
273
274 spsr = io_remap_addr + PCH_SPSR;
275 iowrite32(reg_spsr_val, spsr);
276
277 if (data->transfer_active) {
278 rx_index = data->rx_index;
279 tx_index = data->tx_index;
280 bpw_len = data->bpw_len;
281 pkt_rx_buffer = data->pkt_rx_buff;
282 pkt_tx_buff = data->pkt_tx_buff;
283
284 spdrr = io_remap_addr + PCH_SPDRR;
285 spdwr = io_remap_addr + PCH_SPDWR;
286
287 n_read = PCH_READABLE(reg_spsr_val);
288
289 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
290 pkt_rx_buffer[rx_index++] = ioread32(spdrr);
291 if (tx_index < bpw_len)
292 iowrite32(pkt_tx_buff[tx_index++], spdwr);
293 }
294
295 /* disable RFI if not needed */
296 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
297 reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
298 reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
299
300 /* reset rx threshold */
301 reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
302 reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
303
304 iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
305 }
306
307 /* update counts */
308 data->tx_index = tx_index;
309 data->rx_index = rx_index;
310
311 /* if transfer complete interrupt */
312 if (reg_spsr_val & SPSR_FI_BIT) {
313 if ((tx_index == bpw_len) && (rx_index == tx_index)) {
314 /* disable interrupts */
315 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
316 PCH_ALL);
317
318 /* transfer is completed;
319 inform pch_spi_process_messages */
320 data->transfer_complete = true;
321 data->transfer_active = false;
322 wake_up(&data->wait);
323 } else {
324 dev_vdbg(&data->master->dev,
325 "%s : Transfer is not completed",
326 __func__);
327 }
328 }
329 }
330 }
331
332 /**
333 * pch_spi_handler() - Interrupt handler
334 * @irq: The interrupt number.
335 * @dev_id: Pointer to struct pch_spi_board_data.
336 */
pch_spi_handler(int irq,void * dev_id)337 static irqreturn_t pch_spi_handler(int irq, void *dev_id)
338 {
339 u32 reg_spsr_val;
340 void __iomem *spsr;
341 void __iomem *io_remap_addr;
342 irqreturn_t ret = IRQ_NONE;
343 struct pch_spi_data *data = dev_id;
344 struct pch_spi_board_data *board_dat = data->board_dat;
345
346 if (board_dat->suspend_sts) {
347 dev_dbg(&board_dat->pdev->dev,
348 "%s returning due to suspend\n", __func__);
349 return IRQ_NONE;
350 }
351
352 io_remap_addr = data->io_remap_addr;
353 spsr = io_remap_addr + PCH_SPSR;
354
355 reg_spsr_val = ioread32(spsr);
356
357 if (reg_spsr_val & SPSR_ORF_BIT) {
358 dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__);
359 if (data->current_msg->complete) {
360 data->transfer_complete = true;
361 data->current_msg->status = -EIO;
362 data->current_msg->complete(data->current_msg->context);
363 data->bcurrent_msg_processing = false;
364 data->current_msg = NULL;
365 data->cur_trans = NULL;
366 }
367 }
368
369 if (data->use_dma)
370 return IRQ_NONE;
371
372 /* Check if the interrupt is for SPI device */
373 if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
374 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
375 ret = IRQ_HANDLED;
376 }
377
378 dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
379 __func__, ret);
380
381 return ret;
382 }
383
384 /**
385 * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
386 * @master: Pointer to struct spi_master.
387 * @speed_hz: Baud rate.
388 */
pch_spi_set_baud_rate(struct spi_master * master,u32 speed_hz)389 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
390 {
391 u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
392
393 /* if baud rate is less than we can support limit it */
394 if (n_spbr > PCH_MAX_SPBR)
395 n_spbr = PCH_MAX_SPBR;
396
397 pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
398 }
399
400 /**
401 * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
402 * @master: Pointer to struct spi_master.
403 * @bits_per_word: Bits per word for SPI transfer.
404 */
pch_spi_set_bits_per_word(struct spi_master * master,u8 bits_per_word)405 static void pch_spi_set_bits_per_word(struct spi_master *master,
406 u8 bits_per_word)
407 {
408 if (bits_per_word == 8)
409 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
410 else
411 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
412 }
413
414 /**
415 * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
416 * @spi: Pointer to struct spi_device.
417 */
pch_spi_setup_transfer(struct spi_device * spi)418 static void pch_spi_setup_transfer(struct spi_device *spi)
419 {
420 u32 flags = 0;
421
422 dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
423 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
424 spi->max_speed_hz);
425 pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
426
427 /* set bits per word */
428 pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
429
430 if (!(spi->mode & SPI_LSB_FIRST))
431 flags |= SPCR_LSBF_BIT;
432 if (spi->mode & SPI_CPOL)
433 flags |= SPCR_CPOL_BIT;
434 if (spi->mode & SPI_CPHA)
435 flags |= SPCR_CPHA_BIT;
436 pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
437 (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
438
439 /* Clear the FIFO by toggling FICLR to 1 and back to 0 */
440 pch_spi_clear_fifo(spi->master);
441 }
442
443 /**
444 * pch_spi_reset() - Clears SPI registers
445 * @master: Pointer to struct spi_master.
446 */
pch_spi_reset(struct spi_master * master)447 static void pch_spi_reset(struct spi_master *master)
448 {
449 /* write 1 to reset SPI */
450 pch_spi_writereg(master, PCH_SRST, 0x1);
451
452 /* clear reset */
453 pch_spi_writereg(master, PCH_SRST, 0x0);
454 }
455
pch_spi_transfer(struct spi_device * pspi,struct spi_message * pmsg)456 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
457 {
458
459 struct spi_transfer *transfer;
460 struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
461 int retval;
462 unsigned long flags;
463
464 spin_lock_irqsave(&data->lock, flags);
465 /* validate Tx/Rx buffers and Transfer length */
466 list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
467 if (!transfer->tx_buf && !transfer->rx_buf) {
468 dev_err(&pspi->dev,
469 "%s Tx and Rx buffer NULL\n", __func__);
470 retval = -EINVAL;
471 goto err_return_spinlock;
472 }
473
474 if (!transfer->len) {
475 dev_err(&pspi->dev, "%s Transfer length invalid\n",
476 __func__);
477 retval = -EINVAL;
478 goto err_return_spinlock;
479 }
480
481 dev_dbg(&pspi->dev,
482 "%s Tx/Rx buffer valid. Transfer length valid\n",
483 __func__);
484 }
485 spin_unlock_irqrestore(&data->lock, flags);
486
487 /* We won't process any messages if we have been asked to terminate */
488 if (data->status == STATUS_EXITING) {
489 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
490 retval = -ESHUTDOWN;
491 goto err_out;
492 }
493
494 /* If suspended ,return -EINVAL */
495 if (data->board_dat->suspend_sts) {
496 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
497 retval = -EINVAL;
498 goto err_out;
499 }
500
501 /* set status of message */
502 pmsg->actual_length = 0;
503 dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
504
505 pmsg->status = -EINPROGRESS;
506 spin_lock_irqsave(&data->lock, flags);
507 /* add message to queue */
508 list_add_tail(&pmsg->queue, &data->queue);
509 spin_unlock_irqrestore(&data->lock, flags);
510
511 dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
512
513 schedule_work(&data->work);
514 dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
515
516 retval = 0;
517
518 err_out:
519 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
520 return retval;
521 err_return_spinlock:
522 dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
523 spin_unlock_irqrestore(&data->lock, flags);
524 return retval;
525 }
526
pch_spi_select_chip(struct pch_spi_data * data,struct spi_device * pspi)527 static inline void pch_spi_select_chip(struct pch_spi_data *data,
528 struct spi_device *pspi)
529 {
530 if (data->current_chip != NULL) {
531 if (pspi->chip_select != data->n_curnt_chip) {
532 dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
533 data->current_chip = NULL;
534 }
535 }
536
537 data->current_chip = pspi;
538
539 data->n_curnt_chip = data->current_chip->chip_select;
540
541 dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
542 pch_spi_setup_transfer(pspi);
543 }
544
pch_spi_set_tx(struct pch_spi_data * data,int * bpw)545 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
546 {
547 int size;
548 u32 n_writes;
549 int j;
550 struct spi_message *pmsg, *tmp;
551 const u8 *tx_buf;
552 const u16 *tx_sbuf;
553
554 /* set baud rate if needed */
555 if (data->cur_trans->speed_hz) {
556 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
557 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
558 }
559
560 /* set bits per word if needed */
561 if (data->cur_trans->bits_per_word &&
562 (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
563 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
564 pch_spi_set_bits_per_word(data->master,
565 data->cur_trans->bits_per_word);
566 *bpw = data->cur_trans->bits_per_word;
567 } else {
568 *bpw = data->current_msg->spi->bits_per_word;
569 }
570
571 /* reset Tx/Rx index */
572 data->tx_index = 0;
573 data->rx_index = 0;
574
575 data->bpw_len = data->cur_trans->len / (*bpw / 8);
576
577 /* find alloc size */
578 size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
579
580 /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
581 data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
582 if (data->pkt_tx_buff != NULL) {
583 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
584 if (!data->pkt_rx_buff) {
585 kfree(data->pkt_tx_buff);
586 data->pkt_tx_buff = NULL;
587 }
588 }
589
590 if (!data->pkt_rx_buff) {
591 /* flush queue and set status of all transfers to -ENOMEM */
592 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
593 pmsg->status = -ENOMEM;
594
595 if (pmsg->complete)
596 pmsg->complete(pmsg->context);
597
598 /* delete from queue */
599 list_del_init(&pmsg->queue);
600 }
601 return;
602 }
603
604 /* copy Tx Data */
605 if (data->cur_trans->tx_buf != NULL) {
606 if (*bpw == 8) {
607 tx_buf = data->cur_trans->tx_buf;
608 for (j = 0; j < data->bpw_len; j++)
609 data->pkt_tx_buff[j] = *tx_buf++;
610 } else {
611 tx_sbuf = data->cur_trans->tx_buf;
612 for (j = 0; j < data->bpw_len; j++)
613 data->pkt_tx_buff[j] = *tx_sbuf++;
614 }
615 }
616
617 /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
618 n_writes = data->bpw_len;
619 if (n_writes > PCH_MAX_FIFO_DEPTH)
620 n_writes = PCH_MAX_FIFO_DEPTH;
621
622 dev_dbg(&data->master->dev,
623 "\n%s:Pulling down SSN low - writing 0x2 to SSNXCR\n",
624 __func__);
625 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
626
627 for (j = 0; j < n_writes; j++)
628 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
629
630 /* update tx_index */
631 data->tx_index = j;
632
633 /* reset transfer complete flag */
634 data->transfer_complete = false;
635 data->transfer_active = true;
636 }
637
pch_spi_nomore_transfer(struct pch_spi_data * data)638 static void pch_spi_nomore_transfer(struct pch_spi_data *data)
639 {
640 struct spi_message *pmsg, *tmp;
641 dev_dbg(&data->master->dev, "%s called\n", __func__);
642 /* Invoke complete callback
643 * [To the spi core..indicating end of transfer] */
644 data->current_msg->status = 0;
645
646 if (data->current_msg->complete) {
647 dev_dbg(&data->master->dev,
648 "%s:Invoking callback of SPI core\n", __func__);
649 data->current_msg->complete(data->current_msg->context);
650 }
651
652 /* update status in global variable */
653 data->bcurrent_msg_processing = false;
654
655 dev_dbg(&data->master->dev,
656 "%s:data->bcurrent_msg_processing = false\n", __func__);
657
658 data->current_msg = NULL;
659 data->cur_trans = NULL;
660
661 /* check if we have items in list and not suspending
662 * return 1 if list empty */
663 if ((list_empty(&data->queue) == 0) &&
664 (!data->board_dat->suspend_sts) &&
665 (data->status != STATUS_EXITING)) {
666 /* We have some more work to do (either there is more tranint
667 * bpw;sfer requests in the current message or there are
668 *more messages)
669 */
670 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
671 schedule_work(&data->work);
672 } else if (data->board_dat->suspend_sts ||
673 data->status == STATUS_EXITING) {
674 dev_dbg(&data->master->dev,
675 "%s suspend/remove initiated, flushing queue\n",
676 __func__);
677 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
678 pmsg->status = -EIO;
679
680 if (pmsg->complete)
681 pmsg->complete(pmsg->context);
682
683 /* delete from queue */
684 list_del_init(&pmsg->queue);
685 }
686 }
687 }
688
pch_spi_set_ir(struct pch_spi_data * data)689 static void pch_spi_set_ir(struct pch_spi_data *data)
690 {
691 /* enable interrupts, set threshold, enable SPI */
692 if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
693 /* set receive threshold to PCH_RX_THOLD */
694 pch_spi_setclr_reg(data->master, PCH_SPCR,
695 PCH_RX_THOLD << SPCR_RFIC_FIELD |
696 SPCR_FIE_BIT | SPCR_RFIE_BIT |
697 SPCR_ORIE_BIT | SPCR_SPE_BIT,
698 MASK_RFIC_SPCR_BITS | PCH_ALL);
699 else
700 /* set receive threshold to maximum */
701 pch_spi_setclr_reg(data->master, PCH_SPCR,
702 PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
703 SPCR_FIE_BIT | SPCR_ORIE_BIT |
704 SPCR_SPE_BIT,
705 MASK_RFIC_SPCR_BITS | PCH_ALL);
706
707 /* Wait until the transfer completes; go to sleep after
708 initiating the transfer. */
709 dev_dbg(&data->master->dev,
710 "%s:waiting for transfer to get over\n", __func__);
711
712 wait_event_interruptible(data->wait, data->transfer_complete);
713
714 /* clear all interrupts */
715 pch_spi_writereg(data->master, PCH_SPSR,
716 pch_spi_readreg(data->master, PCH_SPSR));
717 /* Disable interrupts and SPI transfer */
718 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
719 /* clear FIFO */
720 pch_spi_clear_fifo(data->master);
721 }
722
pch_spi_copy_rx_data(struct pch_spi_data * data,int bpw)723 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
724 {
725 int j;
726 u8 *rx_buf;
727 u16 *rx_sbuf;
728
729 /* copy Rx Data */
730 if (!data->cur_trans->rx_buf)
731 return;
732
733 if (bpw == 8) {
734 rx_buf = data->cur_trans->rx_buf;
735 for (j = 0; j < data->bpw_len; j++)
736 *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
737 } else {
738 rx_sbuf = data->cur_trans->rx_buf;
739 for (j = 0; j < data->bpw_len; j++)
740 *rx_sbuf++ = data->pkt_rx_buff[j];
741 }
742 }
743
pch_spi_copy_rx_data_for_dma(struct pch_spi_data * data,int bpw)744 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
745 {
746 int j;
747 u8 *rx_buf;
748 u16 *rx_sbuf;
749 const u8 *rx_dma_buf;
750 const u16 *rx_dma_sbuf;
751
752 /* copy Rx Data */
753 if (!data->cur_trans->rx_buf)
754 return;
755
756 if (bpw == 8) {
757 rx_buf = data->cur_trans->rx_buf;
758 rx_dma_buf = data->dma.rx_buf_virt;
759 for (j = 0; j < data->bpw_len; j++)
760 *rx_buf++ = *rx_dma_buf++ & 0xFF;
761 data->cur_trans->rx_buf = rx_buf;
762 } else {
763 rx_sbuf = data->cur_trans->rx_buf;
764 rx_dma_sbuf = data->dma.rx_buf_virt;
765 for (j = 0; j < data->bpw_len; j++)
766 *rx_sbuf++ = *rx_dma_sbuf++;
767 data->cur_trans->rx_buf = rx_sbuf;
768 }
769 }
770
pch_spi_start_transfer(struct pch_spi_data * data)771 static int pch_spi_start_transfer(struct pch_spi_data *data)
772 {
773 struct pch_spi_dma_ctrl *dma;
774 unsigned long flags;
775 int rtn;
776
777 dma = &data->dma;
778
779 spin_lock_irqsave(&data->lock, flags);
780
781 /* disable interrupts, SPI set enable */
782 pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
783
784 spin_unlock_irqrestore(&data->lock, flags);
785
786 /* Wait until the transfer completes; go to sleep after
787 initiating the transfer. */
788 dev_dbg(&data->master->dev,
789 "%s:waiting for transfer to get over\n", __func__);
790 rtn = wait_event_interruptible_timeout(data->wait,
791 data->transfer_complete,
792 msecs_to_jiffies(2 * HZ));
793 if (!rtn)
794 dev_err(&data->master->dev,
795 "%s wait-event timeout\n", __func__);
796
797 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
798 DMA_FROM_DEVICE);
799
800 dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
801 DMA_FROM_DEVICE);
802 memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
803
804 async_tx_ack(dma->desc_rx);
805 async_tx_ack(dma->desc_tx);
806 kfree(dma->sg_tx_p);
807 kfree(dma->sg_rx_p);
808
809 spin_lock_irqsave(&data->lock, flags);
810
811 /* clear fifo threshold, disable interrupts, disable SPI transfer */
812 pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
813 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
814 SPCR_SPE_BIT);
815 /* clear all interrupts */
816 pch_spi_writereg(data->master, PCH_SPSR,
817 pch_spi_readreg(data->master, PCH_SPSR));
818 /* clear FIFO */
819 pch_spi_clear_fifo(data->master);
820
821 spin_unlock_irqrestore(&data->lock, flags);
822
823 return rtn;
824 }
825
pch_dma_rx_complete(void * arg)826 static void pch_dma_rx_complete(void *arg)
827 {
828 struct pch_spi_data *data = arg;
829
830 /* transfer is completed;inform pch_spi_process_messages_dma */
831 data->transfer_complete = true;
832 wake_up_interruptible(&data->wait);
833 }
834
pch_spi_filter(struct dma_chan * chan,void * slave)835 static bool pch_spi_filter(struct dma_chan *chan, void *slave)
836 {
837 struct pch_dma_slave *param = slave;
838
839 if ((chan->chan_id == param->chan_id) &&
840 (param->dma_dev == chan->device->dev)) {
841 chan->private = param;
842 return true;
843 } else {
844 return false;
845 }
846 }
847
pch_spi_request_dma(struct pch_spi_data * data,int bpw)848 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
849 {
850 dma_cap_mask_t mask;
851 struct dma_chan *chan;
852 struct pci_dev *dma_dev;
853 struct pch_dma_slave *param;
854 struct pch_spi_dma_ctrl *dma;
855 unsigned int width;
856
857 if (bpw == 8)
858 width = PCH_DMA_WIDTH_1_BYTE;
859 else
860 width = PCH_DMA_WIDTH_2_BYTES;
861
862 dma = &data->dma;
863 dma_cap_zero(mask);
864 dma_cap_set(DMA_SLAVE, mask);
865
866 /* Get DMA's dev information */
867 dma_dev = pci_get_slot(data->board_dat->pdev->bus,
868 PCI_DEVFN(PCI_SLOT(data->board_dat->pdev->devfn), 0));
869
870 /* Set Tx DMA */
871 param = &dma->param_tx;
872 param->dma_dev = &dma_dev->dev;
873 param->chan_id = data->ch * 2; /* Tx = 0, 2 */
874 param->tx_reg = data->io_base_addr + PCH_SPDWR;
875 param->width = width;
876 chan = dma_request_channel(mask, pch_spi_filter, param);
877 if (!chan) {
878 dev_err(&data->master->dev,
879 "ERROR: dma_request_channel FAILS(Tx)\n");
880 goto out;
881 }
882 dma->chan_tx = chan;
883
884 /* Set Rx DMA */
885 param = &dma->param_rx;
886 param->dma_dev = &dma_dev->dev;
887 param->chan_id = data->ch * 2 + 1; /* Rx = Tx + 1 */
888 param->rx_reg = data->io_base_addr + PCH_SPDRR;
889 param->width = width;
890 chan = dma_request_channel(mask, pch_spi_filter, param);
891 if (!chan) {
892 dev_err(&data->master->dev,
893 "ERROR: dma_request_channel FAILS(Rx)\n");
894 dma_release_channel(dma->chan_tx);
895 dma->chan_tx = NULL;
896 goto out;
897 }
898 dma->chan_rx = chan;
899
900 dma->dma_dev = dma_dev;
901 return;
902 out:
903 pci_dev_put(dma_dev);
904 data->use_dma = 0;
905 }
906
pch_spi_release_dma(struct pch_spi_data * data)907 static void pch_spi_release_dma(struct pch_spi_data *data)
908 {
909 struct pch_spi_dma_ctrl *dma;
910
911 dma = &data->dma;
912 if (dma->chan_tx) {
913 dma_release_channel(dma->chan_tx);
914 dma->chan_tx = NULL;
915 }
916 if (dma->chan_rx) {
917 dma_release_channel(dma->chan_rx);
918 dma->chan_rx = NULL;
919 }
920
921 pci_dev_put(dma->dma_dev);
922 }
923
pch_spi_handle_dma(struct pch_spi_data * data,int * bpw)924 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
925 {
926 const u8 *tx_buf;
927 const u16 *tx_sbuf;
928 u8 *tx_dma_buf;
929 u16 *tx_dma_sbuf;
930 struct scatterlist *sg;
931 struct dma_async_tx_descriptor *desc_tx;
932 struct dma_async_tx_descriptor *desc_rx;
933 int num;
934 int i;
935 int size;
936 int rem;
937 int head;
938 unsigned long flags;
939 struct pch_spi_dma_ctrl *dma;
940
941 dma = &data->dma;
942
943 /* set baud rate if needed */
944 if (data->cur_trans->speed_hz) {
945 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
946 spin_lock_irqsave(&data->lock, flags);
947 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
948 spin_unlock_irqrestore(&data->lock, flags);
949 }
950
951 /* set bits per word if needed */
952 if (data->cur_trans->bits_per_word &&
953 (data->current_msg->spi->bits_per_word !=
954 data->cur_trans->bits_per_word)) {
955 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
956 spin_lock_irqsave(&data->lock, flags);
957 pch_spi_set_bits_per_word(data->master,
958 data->cur_trans->bits_per_word);
959 spin_unlock_irqrestore(&data->lock, flags);
960 *bpw = data->cur_trans->bits_per_word;
961 } else {
962 *bpw = data->current_msg->spi->bits_per_word;
963 }
964 data->bpw_len = data->cur_trans->len / (*bpw / 8);
965
966 if (data->bpw_len > PCH_BUF_SIZE) {
967 data->bpw_len = PCH_BUF_SIZE;
968 data->cur_trans->len -= PCH_BUF_SIZE;
969 }
970
971 /* copy Tx Data */
972 if (data->cur_trans->tx_buf != NULL) {
973 if (*bpw == 8) {
974 tx_buf = data->cur_trans->tx_buf;
975 tx_dma_buf = dma->tx_buf_virt;
976 for (i = 0; i < data->bpw_len; i++)
977 *tx_dma_buf++ = *tx_buf++;
978 } else {
979 tx_sbuf = data->cur_trans->tx_buf;
980 tx_dma_sbuf = dma->tx_buf_virt;
981 for (i = 0; i < data->bpw_len; i++)
982 *tx_dma_sbuf++ = *tx_sbuf++;
983 }
984 }
985
986 /* Calculate Rx parameter for DMA transmitting */
987 if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
988 if (data->bpw_len % PCH_DMA_TRANS_SIZE) {
989 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
990 rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
991 } else {
992 num = data->bpw_len / PCH_DMA_TRANS_SIZE;
993 rem = PCH_DMA_TRANS_SIZE;
994 }
995 size = PCH_DMA_TRANS_SIZE;
996 } else {
997 num = 1;
998 size = data->bpw_len;
999 rem = data->bpw_len;
1000 }
1001 dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
1002 __func__, num, size, rem);
1003 spin_lock_irqsave(&data->lock, flags);
1004
1005 /* set receive fifo threshold and transmit fifo threshold */
1006 pch_spi_setclr_reg(data->master, PCH_SPCR,
1007 ((size - 1) << SPCR_RFIC_FIELD) |
1008 (PCH_TX_THOLD << SPCR_TFIC_FIELD),
1009 MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
1010
1011 spin_unlock_irqrestore(&data->lock, flags);
1012
1013 /* RX */
1014 dma->sg_rx_p = kmalloc_array(num, sizeof(*dma->sg_rx_p), GFP_ATOMIC);
1015 if (!dma->sg_rx_p)
1016 return;
1017
1018 sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1019 /* offset, length setting */
1020 sg = dma->sg_rx_p;
1021 for (i = 0; i < num; i++, sg++) {
1022 if (i == (num - 2)) {
1023 sg->offset = size * i;
1024 sg->offset = sg->offset * (*bpw / 8);
1025 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1026 sg->offset);
1027 sg_dma_len(sg) = rem;
1028 } else if (i == (num - 1)) {
1029 sg->offset = size * (i - 1) + rem;
1030 sg->offset = sg->offset * (*bpw / 8);
1031 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1032 sg->offset);
1033 sg_dma_len(sg) = size;
1034 } else {
1035 sg->offset = size * i;
1036 sg->offset = sg->offset * (*bpw / 8);
1037 sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1038 sg->offset);
1039 sg_dma_len(sg) = size;
1040 }
1041 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1042 }
1043 sg = dma->sg_rx_p;
1044 desc_rx = dmaengine_prep_slave_sg(dma->chan_rx, sg,
1045 num, DMA_DEV_TO_MEM,
1046 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1047 if (!desc_rx) {
1048 dev_err(&data->master->dev,
1049 "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1050 return;
1051 }
1052 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1053 desc_rx->callback = pch_dma_rx_complete;
1054 desc_rx->callback_param = data;
1055 dma->nent = num;
1056 dma->desc_rx = desc_rx;
1057
1058 /* Calculate Tx parameter for DMA transmitting */
1059 if (data->bpw_len > PCH_MAX_FIFO_DEPTH) {
1060 head = PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE;
1061 if (data->bpw_len % PCH_DMA_TRANS_SIZE > 4) {
1062 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1063 rem = data->bpw_len % PCH_DMA_TRANS_SIZE - head;
1064 } else {
1065 num = data->bpw_len / PCH_DMA_TRANS_SIZE;
1066 rem = data->bpw_len % PCH_DMA_TRANS_SIZE +
1067 PCH_DMA_TRANS_SIZE - head;
1068 }
1069 size = PCH_DMA_TRANS_SIZE;
1070 } else {
1071 num = 1;
1072 size = data->bpw_len;
1073 rem = data->bpw_len;
1074 head = 0;
1075 }
1076
1077 dma->sg_tx_p = kmalloc_array(num, sizeof(*dma->sg_tx_p), GFP_ATOMIC);
1078 if (!dma->sg_tx_p)
1079 return;
1080
1081 sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1082 /* offset, length setting */
1083 sg = dma->sg_tx_p;
1084 for (i = 0; i < num; i++, sg++) {
1085 if (i == 0) {
1086 sg->offset = 0;
1087 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size + head,
1088 sg->offset);
1089 sg_dma_len(sg) = size + head;
1090 } else if (i == (num - 1)) {
1091 sg->offset = head + size * i;
1092 sg->offset = sg->offset * (*bpw / 8);
1093 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1094 sg->offset);
1095 sg_dma_len(sg) = rem;
1096 } else {
1097 sg->offset = head + size * i;
1098 sg->offset = sg->offset * (*bpw / 8);
1099 sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1100 sg->offset);
1101 sg_dma_len(sg) = size;
1102 }
1103 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1104 }
1105 sg = dma->sg_tx_p;
1106 desc_tx = dmaengine_prep_slave_sg(dma->chan_tx,
1107 sg, num, DMA_MEM_TO_DEV,
1108 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1109 if (!desc_tx) {
1110 dev_err(&data->master->dev,
1111 "%s:dmaengine_prep_slave_sg Failed\n", __func__);
1112 return;
1113 }
1114 dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1115 desc_tx->callback = NULL;
1116 desc_tx->callback_param = data;
1117 dma->nent = num;
1118 dma->desc_tx = desc_tx;
1119
1120 dev_dbg(&data->master->dev, "%s:Pulling down SSN low - writing 0x2 to SSNXCR\n", __func__);
1121
1122 spin_lock_irqsave(&data->lock, flags);
1123 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1124 desc_rx->tx_submit(desc_rx);
1125 desc_tx->tx_submit(desc_tx);
1126 spin_unlock_irqrestore(&data->lock, flags);
1127
1128 /* reset transfer complete flag */
1129 data->transfer_complete = false;
1130 }
1131
pch_spi_process_messages(struct work_struct * pwork)1132 static void pch_spi_process_messages(struct work_struct *pwork)
1133 {
1134 struct spi_message *pmsg, *tmp;
1135 struct pch_spi_data *data;
1136 int bpw;
1137
1138 data = container_of(pwork, struct pch_spi_data, work);
1139 dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1140
1141 spin_lock(&data->lock);
1142 /* check if suspend has been initiated;if yes flush queue */
1143 if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1144 dev_dbg(&data->master->dev,
1145 "%s suspend/remove initiated, flushing queue\n", __func__);
1146 list_for_each_entry_safe(pmsg, tmp, data->queue.next, queue) {
1147 pmsg->status = -EIO;
1148
1149 if (pmsg->complete) {
1150 spin_unlock(&data->lock);
1151 pmsg->complete(pmsg->context);
1152 spin_lock(&data->lock);
1153 }
1154
1155 /* delete from queue */
1156 list_del_init(&pmsg->queue);
1157 }
1158
1159 spin_unlock(&data->lock);
1160 return;
1161 }
1162
1163 data->bcurrent_msg_processing = true;
1164 dev_dbg(&data->master->dev,
1165 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1166
1167 /* Get the message from the queue and delete it from there. */
1168 data->current_msg = list_entry(data->queue.next, struct spi_message,
1169 queue);
1170
1171 list_del_init(&data->current_msg->queue);
1172
1173 data->current_msg->status = 0;
1174
1175 pch_spi_select_chip(data, data->current_msg->spi);
1176
1177 spin_unlock(&data->lock);
1178
1179 if (data->use_dma)
1180 pch_spi_request_dma(data,
1181 data->current_msg->spi->bits_per_word);
1182 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
1183 do {
1184 int cnt;
1185 /* If we are already processing a message get the next
1186 transfer structure from the message otherwise retrieve
1187 the 1st transfer request from the message. */
1188 spin_lock(&data->lock);
1189 if (data->cur_trans == NULL) {
1190 data->cur_trans =
1191 list_entry(data->current_msg->transfers.next,
1192 struct spi_transfer, transfer_list);
1193 dev_dbg(&data->master->dev,
1194 "%s :Getting 1st transfer message\n",
1195 __func__);
1196 } else {
1197 data->cur_trans =
1198 list_entry(data->cur_trans->transfer_list.next,
1199 struct spi_transfer, transfer_list);
1200 dev_dbg(&data->master->dev,
1201 "%s :Getting next transfer message\n",
1202 __func__);
1203 }
1204 spin_unlock(&data->lock);
1205
1206 if (!data->cur_trans->len)
1207 goto out;
1208 cnt = (data->cur_trans->len - 1) / PCH_BUF_SIZE + 1;
1209 data->save_total_len = data->cur_trans->len;
1210 if (data->use_dma) {
1211 int i;
1212 char *save_rx_buf = data->cur_trans->rx_buf;
1213
1214 for (i = 0; i < cnt; i++) {
1215 pch_spi_handle_dma(data, &bpw);
1216 if (!pch_spi_start_transfer(data)) {
1217 data->transfer_complete = true;
1218 data->current_msg->status = -EIO;
1219 data->current_msg->complete
1220 (data->current_msg->context);
1221 data->bcurrent_msg_processing = false;
1222 data->current_msg = NULL;
1223 data->cur_trans = NULL;
1224 goto out;
1225 }
1226 pch_spi_copy_rx_data_for_dma(data, bpw);
1227 }
1228 data->cur_trans->rx_buf = save_rx_buf;
1229 } else {
1230 pch_spi_set_tx(data, &bpw);
1231 pch_spi_set_ir(data);
1232 pch_spi_copy_rx_data(data, bpw);
1233 kfree(data->pkt_rx_buff);
1234 data->pkt_rx_buff = NULL;
1235 kfree(data->pkt_tx_buff);
1236 data->pkt_tx_buff = NULL;
1237 }
1238 /* increment message count */
1239 data->cur_trans->len = data->save_total_len;
1240 data->current_msg->actual_length += data->cur_trans->len;
1241
1242 dev_dbg(&data->master->dev,
1243 "%s:data->current_msg->actual_length=%d\n",
1244 __func__, data->current_msg->actual_length);
1245
1246 spi_transfer_delay_exec(data->cur_trans);
1247
1248 spin_lock(&data->lock);
1249
1250 /* No more transfer in this message. */
1251 if ((data->cur_trans->transfer_list.next) ==
1252 &(data->current_msg->transfers)) {
1253 pch_spi_nomore_transfer(data);
1254 }
1255
1256 spin_unlock(&data->lock);
1257
1258 } while (data->cur_trans != NULL);
1259
1260 out:
1261 pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH);
1262 if (data->use_dma)
1263 pch_spi_release_dma(data);
1264 }
1265
pch_spi_free_resources(struct pch_spi_board_data * board_dat,struct pch_spi_data * data)1266 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1267 struct pch_spi_data *data)
1268 {
1269 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1270
1271 flush_work(&data->work);
1272 }
1273
pch_spi_get_resources(struct pch_spi_board_data * board_dat,struct pch_spi_data * data)1274 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1275 struct pch_spi_data *data)
1276 {
1277 dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1278
1279 /* reset PCH SPI h/w */
1280 pch_spi_reset(data->master);
1281 dev_dbg(&board_dat->pdev->dev,
1282 "%s pch_spi_reset invoked successfully\n", __func__);
1283
1284 dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1285
1286 return 0;
1287 }
1288
pch_free_dma_buf(struct pch_spi_board_data * board_dat,struct pch_spi_data * data)1289 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1290 struct pch_spi_data *data)
1291 {
1292 struct pch_spi_dma_ctrl *dma;
1293
1294 dma = &data->dma;
1295 if (dma->tx_buf_dma)
1296 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1297 dma->tx_buf_virt, dma->tx_buf_dma);
1298 if (dma->rx_buf_dma)
1299 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1300 dma->rx_buf_virt, dma->rx_buf_dma);
1301 }
1302
pch_alloc_dma_buf(struct pch_spi_board_data * board_dat,struct pch_spi_data * data)1303 static int pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1304 struct pch_spi_data *data)
1305 {
1306 struct pch_spi_dma_ctrl *dma;
1307 int ret;
1308
1309 dma = &data->dma;
1310 ret = 0;
1311 /* Get Consistent memory for Tx DMA */
1312 dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1313 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1314 if (!dma->tx_buf_virt)
1315 ret = -ENOMEM;
1316
1317 /* Get Consistent memory for Rx DMA */
1318 dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1319 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1320 if (!dma->rx_buf_virt)
1321 ret = -ENOMEM;
1322
1323 return ret;
1324 }
1325
pch_spi_pd_probe(struct platform_device * plat_dev)1326 static int pch_spi_pd_probe(struct platform_device *plat_dev)
1327 {
1328 int ret;
1329 struct spi_master *master;
1330 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1331 struct pch_spi_data *data;
1332
1333 dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1334
1335 master = spi_alloc_master(&board_dat->pdev->dev,
1336 sizeof(struct pch_spi_data));
1337 if (!master) {
1338 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1339 plat_dev->id);
1340 return -ENOMEM;
1341 }
1342
1343 data = spi_master_get_devdata(master);
1344 data->master = master;
1345
1346 platform_set_drvdata(plat_dev, data);
1347
1348 /* baseaddress + address offset) */
1349 data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1350 PCH_ADDRESS_SIZE * plat_dev->id;
1351 data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0);
1352 if (!data->io_remap_addr) {
1353 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1354 ret = -ENOMEM;
1355 goto err_pci_iomap;
1356 }
1357 data->io_remap_addr += PCH_ADDRESS_SIZE * plat_dev->id;
1358
1359 dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1360 plat_dev->id, data->io_remap_addr);
1361
1362 /* initialize members of SPI master */
1363 master->num_chipselect = PCH_MAX_CS;
1364 master->transfer = pch_spi_transfer;
1365 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1366 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1367 master->max_speed_hz = PCH_MAX_BAUDRATE;
1368
1369 data->board_dat = board_dat;
1370 data->plat_dev = plat_dev;
1371 data->n_curnt_chip = 255;
1372 data->status = STATUS_RUNNING;
1373 data->ch = plat_dev->id;
1374 data->use_dma = use_dma;
1375
1376 INIT_LIST_HEAD(&data->queue);
1377 spin_lock_init(&data->lock);
1378 INIT_WORK(&data->work, pch_spi_process_messages);
1379 init_waitqueue_head(&data->wait);
1380
1381 ret = pch_spi_get_resources(board_dat, data);
1382 if (ret) {
1383 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1384 goto err_spi_get_resources;
1385 }
1386
1387 ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1388 IRQF_SHARED, KBUILD_MODNAME, data);
1389 if (ret) {
1390 dev_err(&plat_dev->dev,
1391 "%s request_irq failed\n", __func__);
1392 goto err_request_irq;
1393 }
1394 data->irq_reg_sts = true;
1395
1396 pch_spi_set_master_mode(master);
1397
1398 if (use_dma) {
1399 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1400 ret = pch_alloc_dma_buf(board_dat, data);
1401 if (ret)
1402 goto err_spi_register_master;
1403 }
1404
1405 ret = spi_register_master(master);
1406 if (ret != 0) {
1407 dev_err(&plat_dev->dev,
1408 "%s spi_register_master FAILED\n", __func__);
1409 goto err_spi_register_master;
1410 }
1411
1412 return 0;
1413
1414 err_spi_register_master:
1415 pch_free_dma_buf(board_dat, data);
1416 free_irq(board_dat->pdev->irq, data);
1417 err_request_irq:
1418 pch_spi_free_resources(board_dat, data);
1419 err_spi_get_resources:
1420 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1421 err_pci_iomap:
1422 spi_master_put(master);
1423
1424 return ret;
1425 }
1426
pch_spi_pd_remove(struct platform_device * plat_dev)1427 static int pch_spi_pd_remove(struct platform_device *plat_dev)
1428 {
1429 struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1430 struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1431 int count;
1432 unsigned long flags;
1433
1434 dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1435 __func__, plat_dev->id, board_dat->pdev->irq);
1436
1437 if (use_dma)
1438 pch_free_dma_buf(board_dat, data);
1439
1440 /* check for any pending messages; no action is taken if the queue
1441 * is still full; but at least we tried. Unload anyway */
1442 count = 500;
1443 spin_lock_irqsave(&data->lock, flags);
1444 data->status = STATUS_EXITING;
1445 while ((list_empty(&data->queue) == 0) && --count) {
1446 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1447 __func__);
1448 spin_unlock_irqrestore(&data->lock, flags);
1449 msleep(PCH_SLEEP_TIME);
1450 spin_lock_irqsave(&data->lock, flags);
1451 }
1452 spin_unlock_irqrestore(&data->lock, flags);
1453
1454 pch_spi_free_resources(board_dat, data);
1455 /* disable interrupts & free IRQ */
1456 if (data->irq_reg_sts) {
1457 /* disable interrupts */
1458 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1459 data->irq_reg_sts = false;
1460 free_irq(board_dat->pdev->irq, data);
1461 }
1462
1463 pci_iounmap(board_dat->pdev, data->io_remap_addr);
1464 spi_unregister_master(data->master);
1465
1466 return 0;
1467 }
1468 #ifdef CONFIG_PM
pch_spi_pd_suspend(struct platform_device * pd_dev,pm_message_t state)1469 static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1470 pm_message_t state)
1471 {
1472 u8 count;
1473 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1474 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1475
1476 dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1477
1478 if (!board_dat) {
1479 dev_err(&pd_dev->dev,
1480 "%s pci_get_drvdata returned NULL\n", __func__);
1481 return -EFAULT;
1482 }
1483
1484 /* check if the current message is processed:
1485 Only after thats done the transfer will be suspended */
1486 count = 255;
1487 while ((--count) > 0) {
1488 if (!(data->bcurrent_msg_processing))
1489 break;
1490 msleep(PCH_SLEEP_TIME);
1491 }
1492
1493 /* Free IRQ */
1494 if (data->irq_reg_sts) {
1495 /* disable all interrupts */
1496 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1497 pch_spi_reset(data->master);
1498 free_irq(board_dat->pdev->irq, data);
1499
1500 data->irq_reg_sts = false;
1501 dev_dbg(&pd_dev->dev,
1502 "%s free_irq invoked successfully.\n", __func__);
1503 }
1504
1505 return 0;
1506 }
1507
pch_spi_pd_resume(struct platform_device * pd_dev)1508 static int pch_spi_pd_resume(struct platform_device *pd_dev)
1509 {
1510 struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1511 struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1512 int retval;
1513
1514 if (!board_dat) {
1515 dev_err(&pd_dev->dev,
1516 "%s pci_get_drvdata returned NULL\n", __func__);
1517 return -EFAULT;
1518 }
1519
1520 if (!data->irq_reg_sts) {
1521 /* register IRQ */
1522 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1523 IRQF_SHARED, KBUILD_MODNAME, data);
1524 if (retval < 0) {
1525 dev_err(&pd_dev->dev,
1526 "%s request_irq failed\n", __func__);
1527 return retval;
1528 }
1529
1530 /* reset PCH SPI h/w */
1531 pch_spi_reset(data->master);
1532 pch_spi_set_master_mode(data->master);
1533 data->irq_reg_sts = true;
1534 }
1535 return 0;
1536 }
1537 #else
1538 #define pch_spi_pd_suspend NULL
1539 #define pch_spi_pd_resume NULL
1540 #endif
1541
1542 static struct platform_driver pch_spi_pd_driver = {
1543 .driver = {
1544 .name = "pch-spi",
1545 },
1546 .probe = pch_spi_pd_probe,
1547 .remove = pch_spi_pd_remove,
1548 .suspend = pch_spi_pd_suspend,
1549 .resume = pch_spi_pd_resume
1550 };
1551
pch_spi_probe(struct pci_dev * pdev,const struct pci_device_id * id)1552 static int pch_spi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1553 {
1554 struct pch_spi_board_data *board_dat;
1555 struct platform_device *pd_dev = NULL;
1556 int retval;
1557 int i;
1558 struct pch_pd_dev_save *pd_dev_save;
1559
1560 pd_dev_save = kzalloc(sizeof(*pd_dev_save), GFP_KERNEL);
1561 if (!pd_dev_save)
1562 return -ENOMEM;
1563
1564 board_dat = kzalloc(sizeof(*board_dat), GFP_KERNEL);
1565 if (!board_dat) {
1566 retval = -ENOMEM;
1567 goto err_no_mem;
1568 }
1569
1570 retval = pci_request_regions(pdev, KBUILD_MODNAME);
1571 if (retval) {
1572 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1573 goto pci_request_regions;
1574 }
1575
1576 board_dat->pdev = pdev;
1577 board_dat->num = id->driver_data;
1578 pd_dev_save->num = id->driver_data;
1579 pd_dev_save->board_dat = board_dat;
1580
1581 retval = pci_enable_device(pdev);
1582 if (retval) {
1583 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1584 goto pci_enable_device;
1585 }
1586
1587 for (i = 0; i < board_dat->num; i++) {
1588 pd_dev = platform_device_alloc("pch-spi", i);
1589 if (!pd_dev) {
1590 dev_err(&pdev->dev, "platform_device_alloc failed\n");
1591 retval = -ENOMEM;
1592 goto err_platform_device;
1593 }
1594 pd_dev_save->pd_save[i] = pd_dev;
1595 pd_dev->dev.parent = &pdev->dev;
1596
1597 retval = platform_device_add_data(pd_dev, board_dat,
1598 sizeof(*board_dat));
1599 if (retval) {
1600 dev_err(&pdev->dev,
1601 "platform_device_add_data failed\n");
1602 platform_device_put(pd_dev);
1603 goto err_platform_device;
1604 }
1605
1606 retval = platform_device_add(pd_dev);
1607 if (retval) {
1608 dev_err(&pdev->dev, "platform_device_add failed\n");
1609 platform_device_put(pd_dev);
1610 goto err_platform_device;
1611 }
1612 }
1613
1614 pci_set_drvdata(pdev, pd_dev_save);
1615
1616 return 0;
1617
1618 err_platform_device:
1619 while (--i >= 0)
1620 platform_device_unregister(pd_dev_save->pd_save[i]);
1621 pci_disable_device(pdev);
1622 pci_enable_device:
1623 pci_release_regions(pdev);
1624 pci_request_regions:
1625 kfree(board_dat);
1626 err_no_mem:
1627 kfree(pd_dev_save);
1628
1629 return retval;
1630 }
1631
pch_spi_remove(struct pci_dev * pdev)1632 static void pch_spi_remove(struct pci_dev *pdev)
1633 {
1634 int i;
1635 struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1636
1637 dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1638
1639 for (i = 0; i < pd_dev_save->num; i++)
1640 platform_device_unregister(pd_dev_save->pd_save[i]);
1641
1642 pci_disable_device(pdev);
1643 pci_release_regions(pdev);
1644 kfree(pd_dev_save->board_dat);
1645 kfree(pd_dev_save);
1646 }
1647
pch_spi_suspend(struct device * dev)1648 static int __maybe_unused pch_spi_suspend(struct device *dev)
1649 {
1650 struct pch_pd_dev_save *pd_dev_save = dev_get_drvdata(dev);
1651
1652 dev_dbg(dev, "%s ENTRY\n", __func__);
1653
1654 pd_dev_save->board_dat->suspend_sts = true;
1655
1656 return 0;
1657 }
1658
pch_spi_resume(struct device * dev)1659 static int __maybe_unused pch_spi_resume(struct device *dev)
1660 {
1661 struct pch_pd_dev_save *pd_dev_save = dev_get_drvdata(dev);
1662
1663 dev_dbg(dev, "%s ENTRY\n", __func__);
1664
1665 /* set suspend status to false */
1666 pd_dev_save->board_dat->suspend_sts = false;
1667
1668 return 0;
1669 }
1670
1671 static SIMPLE_DEV_PM_OPS(pch_spi_pm_ops, pch_spi_suspend, pch_spi_resume);
1672
1673 static struct pci_driver pch_spi_pcidev_driver = {
1674 .name = "pch_spi",
1675 .id_table = pch_spi_pcidev_id,
1676 .probe = pch_spi_probe,
1677 .remove = pch_spi_remove,
1678 .driver.pm = &pch_spi_pm_ops,
1679 };
1680
pch_spi_init(void)1681 static int __init pch_spi_init(void)
1682 {
1683 int ret;
1684 ret = platform_driver_register(&pch_spi_pd_driver);
1685 if (ret)
1686 return ret;
1687
1688 ret = pci_register_driver(&pch_spi_pcidev_driver);
1689 if (ret) {
1690 platform_driver_unregister(&pch_spi_pd_driver);
1691 return ret;
1692 }
1693
1694 return 0;
1695 }
1696 module_init(pch_spi_init);
1697
pch_spi_exit(void)1698 static void __exit pch_spi_exit(void)
1699 {
1700 pci_unregister_driver(&pch_spi_pcidev_driver);
1701 platform_driver_unregister(&pch_spi_pd_driver);
1702 }
1703 module_exit(pch_spi_exit);
1704
1705 module_param(use_dma, int, 0644);
1706 MODULE_PARM_DESC(use_dma,
1707 "to use DMA for data transfers pass 1 else 0; default 1");
1708
1709 MODULE_LICENSE("GPL");
1710 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semiconductor ML7xxx IOH SPI Driver");
1711 MODULE_DEVICE_TABLE(pci, pch_spi_pcidev_id);
1712
1713