1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
4  * Authors:
5  *	Srinivas Kandagatla <srinivas.kandagatla@st.com>
6  */
7 
8 #include <linux/init.h>
9 #include <linux/module.h>
10 #include <linux/slab.h>
11 #include <linux/err.h>
12 #include <linux/io.h>
13 #include <linux/of.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_gpio.h> /* of_get_named_gpio() */
16 #include <linux/of_address.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/regmap.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/platform_device.h>
24 #include "core.h"
25 
26 /* PIO Block registers */
27 /* PIO output */
28 #define REG_PIO_POUT			0x00
29 /* Set bits of POUT */
30 #define REG_PIO_SET_POUT		0x04
31 /* Clear bits of POUT */
32 #define REG_PIO_CLR_POUT		0x08
33 /* PIO input */
34 #define REG_PIO_PIN			0x10
35 /* PIO configuration */
36 #define REG_PIO_PC(n)			(0x20 + (n) * 0x10)
37 /* Set bits of PC[2:0] */
38 #define REG_PIO_SET_PC(n)		(0x24 + (n) * 0x10)
39 /* Clear bits of PC[2:0] */
40 #define REG_PIO_CLR_PC(n)		(0x28 + (n) * 0x10)
41 /* PIO input comparison */
42 #define REG_PIO_PCOMP			0x50
43 /* Set bits of PCOMP */
44 #define REG_PIO_SET_PCOMP		0x54
45 /* Clear bits of PCOMP */
46 #define REG_PIO_CLR_PCOMP		0x58
47 /* PIO input comparison mask */
48 #define REG_PIO_PMASK			0x60
49 /* Set bits of PMASK */
50 #define REG_PIO_SET_PMASK		0x64
51 /* Clear bits of PMASK */
52 #define REG_PIO_CLR_PMASK		0x68
53 
54 #define ST_GPIO_DIRECTION_BIDIR	0x1
55 #define ST_GPIO_DIRECTION_OUT	0x2
56 #define ST_GPIO_DIRECTION_IN	0x4
57 
58 /*
59  *  Packed style retime configuration.
60  *  There are two registers cfg0 and cfg1 in this style for each bank.
61  *  Each field in this register is 8 bit corresponding to 8 pins in the bank.
62  */
63 #define RT_P_CFGS_PER_BANK			2
64 #define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg)	REG_FIELD(reg, 0, 7)
65 #define RT_P_CFG0_DELAY_0_FIELD(reg)		REG_FIELD(reg, 16, 23)
66 #define RT_P_CFG0_DELAY_1_FIELD(reg)		REG_FIELD(reg, 24, 31)
67 #define RT_P_CFG1_INVERTCLK_FIELD(reg)		REG_FIELD(reg, 0, 7)
68 #define RT_P_CFG1_RETIME_FIELD(reg)		REG_FIELD(reg, 8, 15)
69 #define RT_P_CFG1_CLKNOTDATA_FIELD(reg)		REG_FIELD(reg, 16, 23)
70 #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg)	REG_FIELD(reg, 24, 31)
71 
72 /*
73  * Dedicated style retime Configuration register
74  * each register is dedicated per pin.
75  */
76 #define RT_D_CFGS_PER_BANK		8
77 #define RT_D_CFG_CLK_SHIFT		0
78 #define RT_D_CFG_CLK_MASK		(0x3 << 0)
79 #define RT_D_CFG_CLKNOTDATA_SHIFT	2
80 #define RT_D_CFG_CLKNOTDATA_MASK	BIT(2)
81 #define RT_D_CFG_DELAY_SHIFT		3
82 #define RT_D_CFG_DELAY_MASK		(0xf << 3)
83 #define RT_D_CFG_DELAY_INNOTOUT_SHIFT	7
84 #define RT_D_CFG_DELAY_INNOTOUT_MASK	BIT(7)
85 #define RT_D_CFG_DOUBLE_EDGE_SHIFT	8
86 #define RT_D_CFG_DOUBLE_EDGE_MASK	BIT(8)
87 #define RT_D_CFG_INVERTCLK_SHIFT	9
88 #define RT_D_CFG_INVERTCLK_MASK		BIT(9)
89 #define RT_D_CFG_RETIME_SHIFT		10
90 #define RT_D_CFG_RETIME_MASK		BIT(10)
91 
92 /*
93  * Pinconf is represented in an opaque unsigned long variable.
94  * Below is the bit allocation details for each possible configuration.
95  * All the bit fields can be encapsulated into four variables
96  * (direction, retime-type, retime-clk, retime-delay)
97  *
98  *	 +----------------+
99  *[31:28]| reserved-3     |
100  *	 +----------------+-------------
101  *[27]   |	oe	  |		|
102  *	 +----------------+		v
103  *[26]   |	pu	  |	[Direction	]
104  *	 +----------------+		^
105  *[25]   |	od	  |		|
106  *	 +----------------+-------------
107  *[24]   | reserved-2     |
108  *	 +----------------+-------------
109  *[23]   |    retime      |		|
110  *	 +----------------+		|
111  *[22]   | retime-invclk  |		|
112  *	 +----------------+		v
113  *[21]   |retime-clknotdat|	[Retime-type	]
114  *	 +----------------+		^
115  *[20]   | retime-de      |		|
116  *	 +----------------+-------------
117  *[19:18]| retime-clk     |------>[Retime-Clk	]
118  *	 +----------------+
119  *[17:16]|  reserved-1    |
120  *	 +----------------+
121  *[15..0]| retime-delay   |------>[Retime Delay]
122  *	 +----------------+
123  */
124 
125 #define ST_PINCONF_UNPACK(conf, param)\
126 				((conf >> ST_PINCONF_ ##param ##_SHIFT) \
127 				& ST_PINCONF_ ##param ##_MASK)
128 
129 #define ST_PINCONF_PACK(conf, val, param)	(conf |=\
130 				((val & ST_PINCONF_ ##param ##_MASK) << \
131 					ST_PINCONF_ ##param ##_SHIFT))
132 
133 /* Output enable */
134 #define ST_PINCONF_OE_MASK		0x1
135 #define ST_PINCONF_OE_SHIFT		27
136 #define ST_PINCONF_OE			BIT(27)
137 #define ST_PINCONF_UNPACK_OE(conf)	ST_PINCONF_UNPACK(conf, OE)
138 #define ST_PINCONF_PACK_OE(conf)	ST_PINCONF_PACK(conf, 1, OE)
139 
140 /* Pull Up */
141 #define ST_PINCONF_PU_MASK		0x1
142 #define ST_PINCONF_PU_SHIFT		26
143 #define ST_PINCONF_PU			BIT(26)
144 #define ST_PINCONF_UNPACK_PU(conf)	ST_PINCONF_UNPACK(conf, PU)
145 #define ST_PINCONF_PACK_PU(conf)	ST_PINCONF_PACK(conf, 1, PU)
146 
147 /* Open Drain */
148 #define ST_PINCONF_OD_MASK		0x1
149 #define ST_PINCONF_OD_SHIFT		25
150 #define ST_PINCONF_OD			BIT(25)
151 #define ST_PINCONF_UNPACK_OD(conf)	ST_PINCONF_UNPACK(conf, OD)
152 #define ST_PINCONF_PACK_OD(conf)	ST_PINCONF_PACK(conf, 1, OD)
153 
154 #define ST_PINCONF_RT_MASK		0x1
155 #define ST_PINCONF_RT_SHIFT		23
156 #define ST_PINCONF_RT			BIT(23)
157 #define ST_PINCONF_UNPACK_RT(conf)	ST_PINCONF_UNPACK(conf, RT)
158 #define ST_PINCONF_PACK_RT(conf)	ST_PINCONF_PACK(conf, 1, RT)
159 
160 #define ST_PINCONF_RT_INVERTCLK_MASK	0x1
161 #define ST_PINCONF_RT_INVERTCLK_SHIFT	22
162 #define ST_PINCONF_RT_INVERTCLK		BIT(22)
163 #define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \
164 			ST_PINCONF_UNPACK(conf, RT_INVERTCLK)
165 #define ST_PINCONF_PACK_RT_INVERTCLK(conf) \
166 			ST_PINCONF_PACK(conf, 1, RT_INVERTCLK)
167 
168 #define ST_PINCONF_RT_CLKNOTDATA_MASK	0x1
169 #define ST_PINCONF_RT_CLKNOTDATA_SHIFT	21
170 #define ST_PINCONF_RT_CLKNOTDATA	BIT(21)
171 #define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf)	\
172 				ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA)
173 #define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \
174 				ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA)
175 
176 #define ST_PINCONF_RT_DOUBLE_EDGE_MASK	0x1
177 #define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT	20
178 #define ST_PINCONF_RT_DOUBLE_EDGE	BIT(20)
179 #define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \
180 				ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE)
181 #define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \
182 				ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE)
183 
184 #define ST_PINCONF_RT_CLK_MASK		0x3
185 #define ST_PINCONF_RT_CLK_SHIFT		18
186 #define ST_PINCONF_RT_CLK		BIT(18)
187 #define ST_PINCONF_UNPACK_RT_CLK(conf)	ST_PINCONF_UNPACK(conf, RT_CLK)
188 #define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK)
189 
190 /* RETIME_DELAY in Pico Secs */
191 #define ST_PINCONF_RT_DELAY_MASK	0xffff
192 #define ST_PINCONF_RT_DELAY_SHIFT	0
193 #define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY)
194 #define ST_PINCONF_PACK_RT_DELAY(conf, val) \
195 				ST_PINCONF_PACK(conf, val, RT_DELAY)
196 
197 #define ST_GPIO_PINS_PER_BANK	(8)
198 #define OF_GPIO_ARGS_MIN	(4)
199 #define OF_RT_ARGS_MIN		(2)
200 
201 #define gpio_range_to_bank(chip) \
202 		container_of(chip, struct st_gpio_bank, range)
203 
204 #define pc_to_bank(pc) \
205 		container_of(pc, struct st_gpio_bank, pc)
206 
207 enum st_retime_style {
208 	st_retime_style_none,
209 	st_retime_style_packed,
210 	st_retime_style_dedicated,
211 };
212 
213 struct st_retime_dedicated {
214 	struct regmap_field *rt[ST_GPIO_PINS_PER_BANK];
215 };
216 
217 struct st_retime_packed {
218 	struct regmap_field *clk1notclk0;
219 	struct regmap_field *delay_0;
220 	struct regmap_field *delay_1;
221 	struct regmap_field *invertclk;
222 	struct regmap_field *retime;
223 	struct regmap_field *clknotdata;
224 	struct regmap_field *double_edge;
225 };
226 
227 struct st_pio_control {
228 	u32 rt_pin_mask;
229 	struct regmap_field *alt, *oe, *pu, *od;
230 	/* retiming */
231 	union {
232 		struct st_retime_packed		rt_p;
233 		struct st_retime_dedicated	rt_d;
234 	} rt;
235 };
236 
237 struct st_pctl_data {
238 	const enum st_retime_style	rt_style;
239 	const unsigned int		*input_delays;
240 	const int			ninput_delays;
241 	const unsigned int		*output_delays;
242 	const int			noutput_delays;
243 	/* register offset information */
244 	const int alt, oe, pu, od, rt;
245 };
246 
247 struct st_pinconf {
248 	int		pin;
249 	const char	*name;
250 	unsigned long	config;
251 	int		altfunc;
252 };
253 
254 struct st_pmx_func {
255 	const char	*name;
256 	const char	**groups;
257 	unsigned	ngroups;
258 };
259 
260 struct st_pctl_group {
261 	const char		*name;
262 	unsigned int		*pins;
263 	unsigned		npins;
264 	struct st_pinconf	*pin_conf;
265 };
266 
267 /*
268  * Edge triggers are not supported at hardware level, it is supported by
269  * software by exploiting the level trigger support in hardware.
270  * Software uses a virtual register (EDGE_CONF) for edge trigger configuration
271  * of each gpio pin in a GPIO bank.
272  *
273  * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
274  * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
275  *
276  * bit allocation per pin is:
277  * Bits:  [0 - 3] | [4 - 7]  [8 - 11] ... ... ... ...  [ 28 - 31]
278  *       --------------------------------------------------------
279  *       |  pin-0  |  pin-2 | pin-3  | ... ... ... ... | pin -7 |
280  *       --------------------------------------------------------
281  *
282  *  A pin can have one of following the values in its edge configuration field.
283  *
284  *	-------   ----------------------------
285  *	[0-3]	- Description
286  *	-------   ----------------------------
287  *	0000	- No edge IRQ.
288  *	0001	- Falling edge IRQ.
289  *	0010	- Rising edge IRQ.
290  *	0011	- Rising and Falling edge IRQ.
291  *	-------   ----------------------------
292  */
293 
294 #define ST_IRQ_EDGE_CONF_BITS_PER_PIN	4
295 #define ST_IRQ_EDGE_MASK		0xf
296 #define ST_IRQ_EDGE_FALLING		BIT(0)
297 #define ST_IRQ_EDGE_RISING		BIT(1)
298 #define ST_IRQ_EDGE_BOTH		(BIT(0) | BIT(1))
299 
300 #define ST_IRQ_RISING_EDGE_CONF(pin) \
301 	(ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
302 
303 #define ST_IRQ_FALLING_EDGE_CONF(pin) \
304 	(ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
305 
306 #define ST_IRQ_BOTH_EDGE_CONF(pin) \
307 	(ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
308 
309 #define ST_IRQ_EDGE_CONF(conf, pin) \
310 	(conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK)
311 
312 struct st_gpio_bank {
313 	struct gpio_chip		gpio_chip;
314 	struct pinctrl_gpio_range	range;
315 	void __iomem			*base;
316 	struct st_pio_control		pc;
317 	unsigned long			irq_edge_conf;
318 	spinlock_t                      lock;
319 };
320 
321 struct st_pinctrl {
322 	struct device			*dev;
323 	struct pinctrl_dev		*pctl;
324 	struct st_gpio_bank		*banks;
325 	int				nbanks;
326 	struct st_pmx_func		*functions;
327 	int				nfunctions;
328 	struct st_pctl_group		*groups;
329 	int				ngroups;
330 	struct regmap			*regmap;
331 	const struct st_pctl_data	*data;
332 	void __iomem			*irqmux_base;
333 };
334 
335 /* SOC specific data */
336 
337 static const unsigned int stih407_delays[] = {0, 300, 500, 750, 1000, 1250,
338 			1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 };
339 
340 static const struct st_pctl_data  stih407_data = {
341 	.rt_style       = st_retime_style_dedicated,
342 	.input_delays   = stih407_delays,
343 	.ninput_delays  = ARRAY_SIZE(stih407_delays),
344 	.output_delays  = stih407_delays,
345 	.noutput_delays = ARRAY_SIZE(stih407_delays),
346 	.alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
347 };
348 
349 static const struct st_pctl_data stih407_flashdata = {
350 	.rt_style	= st_retime_style_none,
351 	.input_delays	= stih407_delays,
352 	.ninput_delays	= ARRAY_SIZE(stih407_delays),
353 	.output_delays	= stih407_delays,
354 	.noutput_delays = ARRAY_SIZE(stih407_delays),
355 	.alt = 0,
356 	.oe = -1, /* Not Available */
357 	.pu = -1, /* Not Available */
358 	.od = 60,
359 	.rt = 100,
360 };
361 
st_get_pio_control(struct pinctrl_dev * pctldev,int pin)362 static struct st_pio_control *st_get_pio_control(
363 			struct pinctrl_dev *pctldev, int pin)
364 {
365 	struct pinctrl_gpio_range *range =
366 			 pinctrl_find_gpio_range_from_pin(pctldev, pin);
367 	struct st_gpio_bank *bank = gpio_range_to_bank(range);
368 
369 	return &bank->pc;
370 }
371 
372 /* Low level functions.. */
st_gpio_bank(int gpio)373 static inline int st_gpio_bank(int gpio)
374 {
375 	return gpio/ST_GPIO_PINS_PER_BANK;
376 }
377 
st_gpio_pin(int gpio)378 static inline int st_gpio_pin(int gpio)
379 {
380 	return gpio%ST_GPIO_PINS_PER_BANK;
381 }
382 
st_pinconf_set_config(struct st_pio_control * pc,int pin,unsigned long config)383 static void st_pinconf_set_config(struct st_pio_control *pc,
384 				int pin, unsigned long config)
385 {
386 	struct regmap_field *output_enable = pc->oe;
387 	struct regmap_field *pull_up = pc->pu;
388 	struct regmap_field *open_drain = pc->od;
389 	unsigned int oe_value, pu_value, od_value;
390 	unsigned long mask = BIT(pin);
391 
392 	if (output_enable) {
393 		regmap_field_read(output_enable, &oe_value);
394 		oe_value &= ~mask;
395 		if (config & ST_PINCONF_OE)
396 			oe_value |= mask;
397 		regmap_field_write(output_enable, oe_value);
398 	}
399 
400 	if (pull_up) {
401 		regmap_field_read(pull_up, &pu_value);
402 		pu_value &= ~mask;
403 		if (config & ST_PINCONF_PU)
404 			pu_value |= mask;
405 		regmap_field_write(pull_up, pu_value);
406 	}
407 
408 	if (open_drain) {
409 		regmap_field_read(open_drain, &od_value);
410 		od_value &= ~mask;
411 		if (config & ST_PINCONF_OD)
412 			od_value |= mask;
413 		regmap_field_write(open_drain, od_value);
414 	}
415 }
416 
st_pctl_set_function(struct st_pio_control * pc,int pin_id,int function)417 static void st_pctl_set_function(struct st_pio_control *pc,
418 				int pin_id, int function)
419 {
420 	struct regmap_field *alt = pc->alt;
421 	unsigned int val;
422 	int pin = st_gpio_pin(pin_id);
423 	int offset = pin * 4;
424 
425 	if (!alt)
426 		return;
427 
428 	regmap_field_read(alt, &val);
429 	val &= ~(0xf << offset);
430 	val |= function << offset;
431 	regmap_field_write(alt, val);
432 }
433 
st_pctl_get_pin_function(struct st_pio_control * pc,int pin)434 static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin)
435 {
436 	struct regmap_field *alt = pc->alt;
437 	unsigned int val;
438 	int offset = pin * 4;
439 
440 	if (!alt)
441 		return 0;
442 
443 	regmap_field_read(alt, &val);
444 
445 	return (val >> offset) & 0xf;
446 }
447 
st_pinconf_delay_to_bit(unsigned int delay,const struct st_pctl_data * data,unsigned long config)448 static unsigned long st_pinconf_delay_to_bit(unsigned int delay,
449 	const struct st_pctl_data *data, unsigned long config)
450 {
451 	const unsigned int *delay_times;
452 	int num_delay_times, i, closest_index = -1;
453 	unsigned int closest_divergence = UINT_MAX;
454 
455 	if (ST_PINCONF_UNPACK_OE(config)) {
456 		delay_times = data->output_delays;
457 		num_delay_times = data->noutput_delays;
458 	} else {
459 		delay_times = data->input_delays;
460 		num_delay_times = data->ninput_delays;
461 	}
462 
463 	for (i = 0; i < num_delay_times; i++) {
464 		unsigned int divergence = abs(delay - delay_times[i]);
465 
466 		if (divergence == 0)
467 			return i;
468 
469 		if (divergence < closest_divergence) {
470 			closest_divergence = divergence;
471 			closest_index = i;
472 		}
473 	}
474 
475 	pr_warn("Attempt to set delay %d, closest available %d\n",
476 	     delay, delay_times[closest_index]);
477 
478 	return closest_index;
479 }
480 
st_pinconf_bit_to_delay(unsigned int index,const struct st_pctl_data * data,unsigned long output)481 static unsigned long st_pinconf_bit_to_delay(unsigned int index,
482 	const struct st_pctl_data *data, unsigned long output)
483 {
484 	const unsigned int *delay_times;
485 	int num_delay_times;
486 
487 	if (output) {
488 		delay_times = data->output_delays;
489 		num_delay_times = data->noutput_delays;
490 	} else {
491 		delay_times = data->input_delays;
492 		num_delay_times = data->ninput_delays;
493 	}
494 
495 	if (index < num_delay_times) {
496 		return delay_times[index];
497 	} else {
498 		pr_warn("Delay not found in/out delay list\n");
499 		return 0;
500 	}
501 }
502 
st_regmap_field_bit_set_clear_pin(struct regmap_field * field,int enable,int pin)503 static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field,
504 	int enable, int pin)
505 {
506 	unsigned int val = 0;
507 
508 	regmap_field_read(field, &val);
509 	if (enable)
510 		val |= BIT(pin);
511 	else
512 		val &= ~BIT(pin);
513 	regmap_field_write(field, val);
514 }
515 
st_pinconf_set_retime_packed(struct st_pinctrl * info,struct st_pio_control * pc,unsigned long config,int pin)516 static void st_pinconf_set_retime_packed(struct st_pinctrl *info,
517 	struct st_pio_control *pc,	unsigned long config, int pin)
518 {
519 	const struct st_pctl_data *data = info->data;
520 	struct st_retime_packed *rt_p = &pc->rt.rt_p;
521 	unsigned int delay;
522 
523 	st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0,
524 				ST_PINCONF_UNPACK_RT_CLK(config), pin);
525 
526 	st_regmap_field_bit_set_clear_pin(rt_p->clknotdata,
527 				ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin);
528 
529 	st_regmap_field_bit_set_clear_pin(rt_p->double_edge,
530 				ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin);
531 
532 	st_regmap_field_bit_set_clear_pin(rt_p->invertclk,
533 				ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin);
534 
535 	st_regmap_field_bit_set_clear_pin(rt_p->retime,
536 				ST_PINCONF_UNPACK_RT(config), pin);
537 
538 	delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config),
539 					data, config);
540 	/* 2 bit delay, lsb */
541 	st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin);
542 	/* 2 bit delay, msb */
543 	st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin);
544 }
545 
st_pinconf_set_retime_dedicated(struct st_pinctrl * info,struct st_pio_control * pc,unsigned long config,int pin)546 static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info,
547 	struct st_pio_control *pc, unsigned long config, int pin)
548 {
549 	int input	= ST_PINCONF_UNPACK_OE(config) ? 0 : 1;
550 	int clk		= ST_PINCONF_UNPACK_RT_CLK(config);
551 	int clknotdata	= ST_PINCONF_UNPACK_RT_CLKNOTDATA(config);
552 	int double_edge	= ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config);
553 	int invertclk	= ST_PINCONF_UNPACK_RT_INVERTCLK(config);
554 	int retime	= ST_PINCONF_UNPACK_RT(config);
555 
556 	unsigned long delay = st_pinconf_delay_to_bit(
557 			ST_PINCONF_UNPACK_RT_DELAY(config),
558 			info->data, config);
559 	struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
560 
561 	unsigned long retime_config =
562 		((clk) << RT_D_CFG_CLK_SHIFT) |
563 		((delay) << RT_D_CFG_DELAY_SHIFT) |
564 		((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) |
565 		((retime) << RT_D_CFG_RETIME_SHIFT) |
566 		((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) |
567 		((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) |
568 		((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT);
569 
570 	regmap_field_write(rt_d->rt[pin], retime_config);
571 }
572 
st_pinconf_get_direction(struct st_pio_control * pc,int pin,unsigned long * config)573 static void st_pinconf_get_direction(struct st_pio_control *pc,
574 	int pin, unsigned long *config)
575 {
576 	unsigned int oe_value, pu_value, od_value;
577 
578 	if (pc->oe) {
579 		regmap_field_read(pc->oe, &oe_value);
580 		if (oe_value & BIT(pin))
581 			ST_PINCONF_PACK_OE(*config);
582 	}
583 
584 	if (pc->pu) {
585 		regmap_field_read(pc->pu, &pu_value);
586 		if (pu_value & BIT(pin))
587 			ST_PINCONF_PACK_PU(*config);
588 	}
589 
590 	if (pc->od) {
591 		regmap_field_read(pc->od, &od_value);
592 		if (od_value & BIT(pin))
593 			ST_PINCONF_PACK_OD(*config);
594 	}
595 }
596 
st_pinconf_get_retime_packed(struct st_pinctrl * info,struct st_pio_control * pc,int pin,unsigned long * config)597 static int st_pinconf_get_retime_packed(struct st_pinctrl *info,
598 	struct st_pio_control *pc,	int pin, unsigned long *config)
599 {
600 	const struct st_pctl_data *data = info->data;
601 	struct st_retime_packed *rt_p = &pc->rt.rt_p;
602 	unsigned int delay_bits, delay, delay0, delay1, val;
603 	int output = ST_PINCONF_UNPACK_OE(*config);
604 
605 	if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin)))
606 		ST_PINCONF_PACK_RT(*config);
607 
608 	if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin)))
609 		ST_PINCONF_PACK_RT_CLK(*config, 1);
610 
611 	if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin)))
612 		ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
613 
614 	if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin)))
615 		ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
616 
617 	if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin)))
618 		ST_PINCONF_PACK_RT_INVERTCLK(*config);
619 
620 	regmap_field_read(rt_p->delay_0, &delay0);
621 	regmap_field_read(rt_p->delay_1, &delay1);
622 	delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) |
623 			(((delay0 & BIT(pin)) ? 1 : 0));
624 	delay =  st_pinconf_bit_to_delay(delay_bits, data, output);
625 	ST_PINCONF_PACK_RT_DELAY(*config, delay);
626 
627 	return 0;
628 }
629 
st_pinconf_get_retime_dedicated(struct st_pinctrl * info,struct st_pio_control * pc,int pin,unsigned long * config)630 static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info,
631 	struct st_pio_control *pc,	int pin, unsigned long *config)
632 {
633 	unsigned int value;
634 	unsigned long delay_bits, delay, rt_clk;
635 	int output = ST_PINCONF_UNPACK_OE(*config);
636 	struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
637 
638 	regmap_field_read(rt_d->rt[pin], &value);
639 
640 	rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT;
641 	ST_PINCONF_PACK_RT_CLK(*config, rt_clk);
642 
643 	delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT;
644 	delay =  st_pinconf_bit_to_delay(delay_bits, info->data, output);
645 	ST_PINCONF_PACK_RT_DELAY(*config, delay);
646 
647 	if (value & RT_D_CFG_CLKNOTDATA_MASK)
648 		ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
649 
650 	if (value & RT_D_CFG_DOUBLE_EDGE_MASK)
651 		ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
652 
653 	if (value & RT_D_CFG_INVERTCLK_MASK)
654 		ST_PINCONF_PACK_RT_INVERTCLK(*config);
655 
656 	if (value & RT_D_CFG_RETIME_MASK)
657 		ST_PINCONF_PACK_RT(*config);
658 
659 	return 0;
660 }
661 
662 /* GPIO related functions */
663 
__st_gpio_set(struct st_gpio_bank * bank,unsigned offset,int value)664 static inline void __st_gpio_set(struct st_gpio_bank *bank,
665 	unsigned offset, int value)
666 {
667 	if (value)
668 		writel(BIT(offset), bank->base + REG_PIO_SET_POUT);
669 	else
670 		writel(BIT(offset), bank->base + REG_PIO_CLR_POUT);
671 }
672 
st_gpio_direction(struct st_gpio_bank * bank,unsigned int gpio,unsigned int direction)673 static void st_gpio_direction(struct st_gpio_bank *bank,
674 		unsigned int gpio, unsigned int direction)
675 {
676 	int offset = st_gpio_pin(gpio);
677 	int i = 0;
678 	/**
679 	 * There are three configuration registers (PIOn_PC0, PIOn_PC1
680 	 * and PIOn_PC2) for each port. These are used to configure the
681 	 * PIO port pins. Each pin can be configured as an input, output,
682 	 * bidirectional, or alternative function pin. Three bits, one bit
683 	 * from each of the three registers, configure the corresponding bit of
684 	 * the port. Valid bit settings is:
685 	 *
686 	 * PC2		PC1		PC0	Direction.
687 	 * 0		0		0	[Input Weak pull-up]
688 	 * 0		0 or 1		1	[Bidirection]
689 	 * 0		1		0	[Output]
690 	 * 1		0		0	[Input]
691 	 *
692 	 * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits
693 	 * individually.
694 	 */
695 	for (i = 0; i <= 2; i++) {
696 		if (direction & BIT(i))
697 			writel(BIT(offset), bank->base + REG_PIO_SET_PC(i));
698 		else
699 			writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i));
700 	}
701 }
702 
st_gpio_get(struct gpio_chip * chip,unsigned offset)703 static int st_gpio_get(struct gpio_chip *chip, unsigned offset)
704 {
705 	struct st_gpio_bank *bank = gpiochip_get_data(chip);
706 
707 	return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset));
708 }
709 
st_gpio_set(struct gpio_chip * chip,unsigned offset,int value)710 static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
711 {
712 	struct st_gpio_bank *bank = gpiochip_get_data(chip);
713 	__st_gpio_set(bank, offset, value);
714 }
715 
st_gpio_direction_input(struct gpio_chip * chip,unsigned offset)716 static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
717 {
718 	pinctrl_gpio_direction_input(chip->base + offset);
719 
720 	return 0;
721 }
722 
st_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)723 static int st_gpio_direction_output(struct gpio_chip *chip,
724 	unsigned offset, int value)
725 {
726 	struct st_gpio_bank *bank = gpiochip_get_data(chip);
727 
728 	__st_gpio_set(bank, offset, value);
729 	pinctrl_gpio_direction_output(chip->base + offset);
730 
731 	return 0;
732 }
733 
st_gpio_get_direction(struct gpio_chip * chip,unsigned offset)734 static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
735 {
736 	struct st_gpio_bank *bank = gpiochip_get_data(chip);
737 	struct st_pio_control pc = bank->pc;
738 	unsigned long config;
739 	unsigned int direction = 0;
740 	unsigned int function;
741 	unsigned int value;
742 	int i = 0;
743 
744 	/* Alternate function direction is handled by Pinctrl */
745 	function = st_pctl_get_pin_function(&pc, offset);
746 	if (function) {
747 		st_pinconf_get_direction(&pc, offset, &config);
748 		if (ST_PINCONF_UNPACK_OE(config))
749 			return GPIO_LINE_DIRECTION_OUT;
750 
751 		return GPIO_LINE_DIRECTION_IN;
752 	}
753 
754 	/*
755 	 * GPIO direction is handled differently
756 	 * - See st_gpio_direction() above for an explanation
757 	 */
758 	for (i = 0; i <= 2; i++) {
759 		value = readl(bank->base + REG_PIO_PC(i));
760 		direction |= ((value >> offset) & 0x1) << i;
761 	}
762 
763 	if (direction == ST_GPIO_DIRECTION_IN)
764 		return GPIO_LINE_DIRECTION_IN;
765 
766 	return GPIO_LINE_DIRECTION_OUT;
767 }
768 
769 /* Pinctrl Groups */
st_pctl_get_groups_count(struct pinctrl_dev * pctldev)770 static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev)
771 {
772 	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
773 
774 	return info->ngroups;
775 }
776 
st_pctl_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)777 static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev,
778 				       unsigned selector)
779 {
780 	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
781 
782 	return info->groups[selector].name;
783 }
784 
st_pctl_get_group_pins(struct pinctrl_dev * pctldev,unsigned selector,const unsigned ** pins,unsigned * npins)785 static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev,
786 	unsigned selector, const unsigned **pins, unsigned *npins)
787 {
788 	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
789 
790 	if (selector >= info->ngroups)
791 		return -EINVAL;
792 
793 	*pins = info->groups[selector].pins;
794 	*npins = info->groups[selector].npins;
795 
796 	return 0;
797 }
798 
st_pctl_find_group_by_name(const struct st_pinctrl * info,const char * name)799 static inline const struct st_pctl_group *st_pctl_find_group_by_name(
800 	const struct st_pinctrl *info, const char *name)
801 {
802 	int i;
803 
804 	for (i = 0; i < info->ngroups; i++) {
805 		if (!strcmp(info->groups[i].name, name))
806 			return &info->groups[i];
807 	}
808 
809 	return NULL;
810 }
811 
st_pctl_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned * num_maps)812 static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
813 	struct device_node *np, struct pinctrl_map **map, unsigned *num_maps)
814 {
815 	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
816 	const struct st_pctl_group *grp;
817 	struct device *dev = info->dev;
818 	struct pinctrl_map *new_map;
819 	struct device_node *parent;
820 	int map_num, i;
821 
822 	grp = st_pctl_find_group_by_name(info, np->name);
823 	if (!grp) {
824 		dev_err(dev, "unable to find group for node %pOFn\n", np);
825 		return -EINVAL;
826 	}
827 
828 	map_num = grp->npins + 1;
829 	new_map = devm_kcalloc(dev, map_num, sizeof(*new_map), GFP_KERNEL);
830 	if (!new_map)
831 		return -ENOMEM;
832 
833 	parent = of_get_parent(np);
834 	if (!parent) {
835 		devm_kfree(dev, new_map);
836 		return -EINVAL;
837 	}
838 
839 	*map = new_map;
840 	*num_maps = map_num;
841 	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
842 	new_map[0].data.mux.function = parent->name;
843 	new_map[0].data.mux.group = np->name;
844 	of_node_put(parent);
845 
846 	/* create config map per pin */
847 	new_map++;
848 	for (i = 0; i < grp->npins; i++) {
849 		new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
850 		new_map[i].data.configs.group_or_pin =
851 				pin_get_name(pctldev, grp->pins[i]);
852 		new_map[i].data.configs.configs = &grp->pin_conf[i].config;
853 		new_map[i].data.configs.num_configs = 1;
854 	}
855 	dev_info(dev, "maps: function %s group %s num %d\n",
856 		(*map)->data.mux.function, grp->name, map_num);
857 
858 	return 0;
859 }
860 
st_pctl_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,unsigned num_maps)861 static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev,
862 			struct pinctrl_map *map, unsigned num_maps)
863 {
864 }
865 
866 static const struct pinctrl_ops st_pctlops = {
867 	.get_groups_count	= st_pctl_get_groups_count,
868 	.get_group_pins		= st_pctl_get_group_pins,
869 	.get_group_name		= st_pctl_get_group_name,
870 	.dt_node_to_map		= st_pctl_dt_node_to_map,
871 	.dt_free_map		= st_pctl_dt_free_map,
872 };
873 
874 /* Pinmux */
st_pmx_get_funcs_count(struct pinctrl_dev * pctldev)875 static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
876 {
877 	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
878 
879 	return info->nfunctions;
880 }
881 
st_pmx_get_fname(struct pinctrl_dev * pctldev,unsigned selector)882 static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev,
883 	unsigned selector)
884 {
885 	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
886 
887 	return info->functions[selector].name;
888 }
889 
st_pmx_get_groups(struct pinctrl_dev * pctldev,unsigned selector,const char * const ** grps,unsigned * const ngrps)890 static int st_pmx_get_groups(struct pinctrl_dev *pctldev,
891 	unsigned selector, const char * const **grps, unsigned * const ngrps)
892 {
893 	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
894 	*grps = info->functions[selector].groups;
895 	*ngrps = info->functions[selector].ngroups;
896 
897 	return 0;
898 }
899 
st_pmx_set_mux(struct pinctrl_dev * pctldev,unsigned fselector,unsigned group)900 static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
901 			unsigned group)
902 {
903 	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
904 	struct st_pinconf *conf = info->groups[group].pin_conf;
905 	struct st_pio_control *pc;
906 	int i;
907 
908 	for (i = 0; i < info->groups[group].npins; i++) {
909 		pc = st_get_pio_control(pctldev, conf[i].pin);
910 		st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc);
911 	}
912 
913 	return 0;
914 }
915 
st_pmx_set_gpio_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned gpio,bool input)916 static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,
917 			struct pinctrl_gpio_range *range, unsigned gpio,
918 			bool input)
919 {
920 	struct st_gpio_bank *bank = gpio_range_to_bank(range);
921 	/*
922 	 * When a PIO bank is used in its primary function mode (altfunc = 0)
923 	 * Output Enable (OE), Open Drain(OD), and Pull Up (PU)
924 	 * for the primary PIO functions are driven by the related PIO block
925 	 */
926 	st_pctl_set_function(&bank->pc, gpio, 0);
927 	st_gpio_direction(bank, gpio, input ?
928 		ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT);
929 
930 	return 0;
931 }
932 
933 static const struct pinmux_ops st_pmxops = {
934 	.get_functions_count	= st_pmx_get_funcs_count,
935 	.get_function_name	= st_pmx_get_fname,
936 	.get_function_groups	= st_pmx_get_groups,
937 	.set_mux		= st_pmx_set_mux,
938 	.gpio_set_direction	= st_pmx_set_gpio_direction,
939 	.strict			= true,
940 };
941 
942 /* Pinconf  */
st_pinconf_get_retime(struct st_pinctrl * info,struct st_pio_control * pc,int pin,unsigned long * config)943 static void st_pinconf_get_retime(struct st_pinctrl *info,
944 	struct st_pio_control *pc, int pin, unsigned long *config)
945 {
946 	if (info->data->rt_style == st_retime_style_packed)
947 		st_pinconf_get_retime_packed(info, pc, pin, config);
948 	else if (info->data->rt_style == st_retime_style_dedicated)
949 		if ((BIT(pin) & pc->rt_pin_mask))
950 			st_pinconf_get_retime_dedicated(info, pc,
951 					pin, config);
952 }
953 
st_pinconf_set_retime(struct st_pinctrl * info,struct st_pio_control * pc,int pin,unsigned long config)954 static void st_pinconf_set_retime(struct st_pinctrl *info,
955 	struct st_pio_control *pc, int pin, unsigned long config)
956 {
957 	if (info->data->rt_style == st_retime_style_packed)
958 		st_pinconf_set_retime_packed(info, pc, config, pin);
959 	else if (info->data->rt_style == st_retime_style_dedicated)
960 		if ((BIT(pin) & pc->rt_pin_mask))
961 			st_pinconf_set_retime_dedicated(info, pc,
962 							config, pin);
963 }
964 
st_pinconf_set(struct pinctrl_dev * pctldev,unsigned pin_id,unsigned long * configs,unsigned num_configs)965 static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id,
966 			unsigned long *configs, unsigned num_configs)
967 {
968 	int pin = st_gpio_pin(pin_id);
969 	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
970 	struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
971 	int i;
972 
973 	for (i = 0; i < num_configs; i++) {
974 		st_pinconf_set_config(pc, pin, configs[i]);
975 		st_pinconf_set_retime(info, pc, pin, configs[i]);
976 	} /* for each config */
977 
978 	return 0;
979 }
980 
st_pinconf_get(struct pinctrl_dev * pctldev,unsigned pin_id,unsigned long * config)981 static int st_pinconf_get(struct pinctrl_dev *pctldev,
982 			     unsigned pin_id, unsigned long *config)
983 {
984 	int pin = st_gpio_pin(pin_id);
985 	struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
986 	struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
987 
988 	*config = 0;
989 	st_pinconf_get_direction(pc, pin, config);
990 	st_pinconf_get_retime(info, pc, pin, config);
991 
992 	return 0;
993 }
994 
st_pinconf_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned pin_id)995 static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev,
996 				   struct seq_file *s, unsigned pin_id)
997 {
998 	struct st_pio_control *pc;
999 	unsigned long config;
1000 	unsigned int function;
1001 	int offset = st_gpio_pin(pin_id);
1002 	char f[16];
1003 	int oe;
1004 
1005 	mutex_unlock(&pctldev->mutex);
1006 	pc = st_get_pio_control(pctldev, pin_id);
1007 	st_pinconf_get(pctldev, pin_id, &config);
1008 	mutex_lock(&pctldev->mutex);
1009 
1010 	function = st_pctl_get_pin_function(pc, offset);
1011 	if (function)
1012 		snprintf(f, 10, "Alt Fn %u", function);
1013 	else
1014 		snprintf(f, 5, "GPIO");
1015 
1016 	oe = st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset);
1017 	seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n"
1018 		"\t\t[retime:%ld,invclk:%ld,clknotdat:%ld,"
1019 		"de:%ld,rt-clk:%ld,rt-delay:%ld]",
1020 		(oe == GPIO_LINE_DIRECTION_OUT),
1021 		ST_PINCONF_UNPACK_PU(config),
1022 		ST_PINCONF_UNPACK_OD(config),
1023 		f,
1024 		ST_PINCONF_UNPACK_RT(config),
1025 		ST_PINCONF_UNPACK_RT_INVERTCLK(config),
1026 		ST_PINCONF_UNPACK_RT_CLKNOTDATA(config),
1027 		ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config),
1028 		ST_PINCONF_UNPACK_RT_CLK(config),
1029 		ST_PINCONF_UNPACK_RT_DELAY(config));
1030 }
1031 
1032 static const struct pinconf_ops st_confops = {
1033 	.pin_config_get		= st_pinconf_get,
1034 	.pin_config_set		= st_pinconf_set,
1035 	.pin_config_dbg_show	= st_pinconf_dbg_show,
1036 };
1037 
st_pctl_dt_child_count(struct st_pinctrl * info,struct device_node * np)1038 static void st_pctl_dt_child_count(struct st_pinctrl *info,
1039 				     struct device_node *np)
1040 {
1041 	struct device_node *child;
1042 	for_each_child_of_node(np, child) {
1043 		if (of_property_read_bool(child, "gpio-controller")) {
1044 			info->nbanks++;
1045 		} else {
1046 			info->nfunctions++;
1047 			info->ngroups += of_get_child_count(child);
1048 		}
1049 	}
1050 }
1051 
st_pctl_dt_setup_retime_packed(struct st_pinctrl * info,int bank,struct st_pio_control * pc)1052 static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info,
1053 	int bank, struct st_pio_control *pc)
1054 {
1055 	struct device *dev = info->dev;
1056 	struct regmap *rm = info->regmap;
1057 	const struct st_pctl_data *data = info->data;
1058 	/* 2 registers per bank */
1059 	int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4;
1060 	struct st_retime_packed *rt_p = &pc->rt.rt_p;
1061 	/* cfg0 */
1062 	struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg);
1063 	struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg);
1064 	struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg);
1065 	/* cfg1 */
1066 	struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4);
1067 	struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4);
1068 	struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4);
1069 	struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4);
1070 
1071 	rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0);
1072 	rt_p->delay_0	= devm_regmap_field_alloc(dev, rm, delay_0);
1073 	rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1);
1074 	rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk);
1075 	rt_p->retime = devm_regmap_field_alloc(dev, rm, retime);
1076 	rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata);
1077 	rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge);
1078 
1079 	if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) ||
1080 		 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) ||
1081 		 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) ||
1082 		 IS_ERR(rt_p->double_edge))
1083 		return -EINVAL;
1084 
1085 	return 0;
1086 }
1087 
st_pctl_dt_setup_retime_dedicated(struct st_pinctrl * info,int bank,struct st_pio_control * pc)1088 static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info,
1089 	int bank, struct st_pio_control *pc)
1090 {
1091 	struct device *dev = info->dev;
1092 	struct regmap *rm = info->regmap;
1093 	const struct st_pctl_data *data = info->data;
1094 	/* 8 registers per bank */
1095 	int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4;
1096 	struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
1097 	unsigned int j;
1098 	u32 pin_mask = pc->rt_pin_mask;
1099 
1100 	for (j = 0; j < RT_D_CFGS_PER_BANK; j++) {
1101 		if (BIT(j) & pin_mask) {
1102 			struct reg_field reg = REG_FIELD(reg_offset, 0, 31);
1103 			rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg);
1104 			if (IS_ERR(rt_d->rt[j]))
1105 				return -EINVAL;
1106 			reg_offset += 4;
1107 		}
1108 	}
1109 	return 0;
1110 }
1111 
st_pctl_dt_setup_retime(struct st_pinctrl * info,int bank,struct st_pio_control * pc)1112 static int st_pctl_dt_setup_retime(struct st_pinctrl *info,
1113 	int bank, struct st_pio_control *pc)
1114 {
1115 	const struct st_pctl_data *data = info->data;
1116 	if (data->rt_style  == st_retime_style_packed)
1117 		return st_pctl_dt_setup_retime_packed(info, bank, pc);
1118 	else if (data->rt_style == st_retime_style_dedicated)
1119 		return st_pctl_dt_setup_retime_dedicated(info, bank, pc);
1120 
1121 	return -EINVAL;
1122 }
1123 
1124 
st_pc_get_value(struct device * dev,struct regmap * regmap,int bank,int data,int lsb,int msb)1125 static struct regmap_field *st_pc_get_value(struct device *dev,
1126 					    struct regmap *regmap, int bank,
1127 					    int data, int lsb, int msb)
1128 {
1129 	struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb);
1130 
1131 	if (data < 0)
1132 		return NULL;
1133 
1134 	return devm_regmap_field_alloc(dev, regmap, reg);
1135 }
1136 
st_parse_syscfgs(struct st_pinctrl * info,int bank,struct device_node * np)1137 static void st_parse_syscfgs(struct st_pinctrl *info, int bank,
1138 			     struct device_node *np)
1139 {
1140 	const struct st_pctl_data *data = info->data;
1141 	/**
1142 	 * For a given shared register like OE/PU/OD, there are 8 bits per bank
1143 	 * 0:7 belongs to bank0, 8:15 belongs to bank1 ...
1144 	 * So each register is shared across 4 banks.
1145 	 */
1146 	int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK;
1147 	int msb = lsb + ST_GPIO_PINS_PER_BANK - 1;
1148 	struct st_pio_control *pc = &info->banks[bank].pc;
1149 	struct device *dev = info->dev;
1150 	struct regmap *regmap  = info->regmap;
1151 
1152 	pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31);
1153 	pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb);
1154 	pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb);
1155 	pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb);
1156 
1157 	/* retime avaiable for all pins by default */
1158 	pc->rt_pin_mask = 0xff;
1159 	of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask);
1160 	st_pctl_dt_setup_retime(info, bank, pc);
1161 
1162 	return;
1163 }
1164 
1165 /*
1166  * Each pin is represented in of the below forms.
1167  * <bank offset mux direction rt_type rt_delay rt_clk>
1168  */
st_pctl_dt_parse_groups(struct device_node * np,struct st_pctl_group * grp,struct st_pinctrl * info,int idx)1169 static int st_pctl_dt_parse_groups(struct device_node *np,
1170 	struct st_pctl_group *grp, struct st_pinctrl *info, int idx)
1171 {
1172 	/* bank pad direction val altfunction */
1173 	const __be32 *list;
1174 	struct property *pp;
1175 	struct device *dev = info->dev;
1176 	struct st_pinconf *conf;
1177 	struct device_node *pins;
1178 	int i = 0, npins = 0, nr_props, ret = 0;
1179 
1180 	pins = of_get_child_by_name(np, "st,pins");
1181 	if (!pins)
1182 		return -ENODATA;
1183 
1184 	for_each_property_of_node(pins, pp) {
1185 		/* Skip those we do not want to proceed */
1186 		if (!strcmp(pp->name, "name"))
1187 			continue;
1188 
1189 		if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) {
1190 			npins++;
1191 		} else {
1192 			pr_warn("Invalid st,pins in %pOFn node\n", np);
1193 			ret = -EINVAL;
1194 			goto out_put_node;
1195 		}
1196 	}
1197 
1198 	grp->npins = npins;
1199 	grp->name = np->name;
1200 	grp->pins = devm_kcalloc(dev, npins, sizeof(*grp->pins), GFP_KERNEL);
1201 	grp->pin_conf = devm_kcalloc(dev, npins, sizeof(*grp->pin_conf), GFP_KERNEL);
1202 
1203 	if (!grp->pins || !grp->pin_conf) {
1204 		ret = -ENOMEM;
1205 		goto out_put_node;
1206 	}
1207 
1208 	/* <bank offset mux direction rt_type rt_delay rt_clk> */
1209 	for_each_property_of_node(pins, pp) {
1210 		if (!strcmp(pp->name, "name"))
1211 			continue;
1212 		nr_props = pp->length/sizeof(u32);
1213 		list = pp->value;
1214 		conf = &grp->pin_conf[i];
1215 
1216 		/* bank & offset */
1217 		be32_to_cpup(list++);
1218 		be32_to_cpup(list++);
1219 		conf->pin = of_get_named_gpio(pins, pp->name, 0);
1220 		conf->name = pp->name;
1221 		grp->pins[i] = conf->pin;
1222 		/* mux */
1223 		conf->altfunc = be32_to_cpup(list++);
1224 		conf->config = 0;
1225 		/* direction */
1226 		conf->config |= be32_to_cpup(list++);
1227 		/* rt_type rt_delay rt_clk */
1228 		if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) {
1229 			/* rt_type */
1230 			conf->config |= be32_to_cpup(list++);
1231 			/* rt_delay */
1232 			conf->config |= be32_to_cpup(list++);
1233 			/* rt_clk */
1234 			if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN)
1235 				conf->config |= be32_to_cpup(list++);
1236 		}
1237 		i++;
1238 	}
1239 
1240 out_put_node:
1241 	of_node_put(pins);
1242 
1243 	return ret;
1244 }
1245 
st_pctl_parse_functions(struct device_node * np,struct st_pinctrl * info,u32 index,int * grp_index)1246 static int st_pctl_parse_functions(struct device_node *np,
1247 			struct st_pinctrl *info, u32 index, int *grp_index)
1248 {
1249 	struct device *dev = info->dev;
1250 	struct device_node *child;
1251 	struct st_pmx_func *func;
1252 	struct st_pctl_group *grp;
1253 	int ret, i;
1254 
1255 	func = &info->functions[index];
1256 	func->name = np->name;
1257 	func->ngroups = of_get_child_count(np);
1258 	if (func->ngroups == 0)
1259 		return dev_err_probe(dev, -EINVAL, "No groups defined\n");
1260 	func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
1261 	if (!func->groups)
1262 		return -ENOMEM;
1263 
1264 	i = 0;
1265 	for_each_child_of_node(np, child) {
1266 		func->groups[i] = child->name;
1267 		grp = &info->groups[*grp_index];
1268 		*grp_index += 1;
1269 		ret = st_pctl_dt_parse_groups(child, grp, info, i++);
1270 		if (ret) {
1271 			of_node_put(child);
1272 			return ret;
1273 		}
1274 	}
1275 	dev_info(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups);
1276 
1277 	return 0;
1278 }
1279 
st_gpio_irq_mask(struct irq_data * d)1280 static void st_gpio_irq_mask(struct irq_data *d)
1281 {
1282 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1283 	struct st_gpio_bank *bank = gpiochip_get_data(gc);
1284 
1285 	writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK);
1286 }
1287 
st_gpio_irq_unmask(struct irq_data * d)1288 static void st_gpio_irq_unmask(struct irq_data *d)
1289 {
1290 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1291 	struct st_gpio_bank *bank = gpiochip_get_data(gc);
1292 
1293 	writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK);
1294 }
1295 
st_gpio_irq_request_resources(struct irq_data * d)1296 static int st_gpio_irq_request_resources(struct irq_data *d)
1297 {
1298 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1299 
1300 	st_gpio_direction_input(gc, d->hwirq);
1301 
1302 	return gpiochip_lock_as_irq(gc, d->hwirq);
1303 }
1304 
st_gpio_irq_release_resources(struct irq_data * d)1305 static void st_gpio_irq_release_resources(struct irq_data *d)
1306 {
1307 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1308 
1309 	gpiochip_unlock_as_irq(gc, d->hwirq);
1310 }
1311 
st_gpio_irq_set_type(struct irq_data * d,unsigned type)1312 static int st_gpio_irq_set_type(struct irq_data *d, unsigned type)
1313 {
1314 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1315 	struct st_gpio_bank *bank = gpiochip_get_data(gc);
1316 	unsigned long flags;
1317 	int comp, pin = d->hwirq;
1318 	u32 val;
1319 	u32 pin_edge_conf = 0;
1320 
1321 	switch (type) {
1322 	case IRQ_TYPE_LEVEL_HIGH:
1323 		comp = 0;
1324 		break;
1325 	case IRQ_TYPE_EDGE_FALLING:
1326 		comp = 0;
1327 		pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin);
1328 		break;
1329 	case IRQ_TYPE_LEVEL_LOW:
1330 		comp = 1;
1331 		break;
1332 	case IRQ_TYPE_EDGE_RISING:
1333 		comp = 1;
1334 		pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin);
1335 		break;
1336 	case IRQ_TYPE_EDGE_BOTH:
1337 		comp = st_gpio_get(&bank->gpio_chip, pin);
1338 		pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin);
1339 		break;
1340 	default:
1341 		return -EINVAL;
1342 	}
1343 
1344 	spin_lock_irqsave(&bank->lock, flags);
1345 	bank->irq_edge_conf &=  ~(ST_IRQ_EDGE_MASK << (
1346 				pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN));
1347 	bank->irq_edge_conf |= pin_edge_conf;
1348 	spin_unlock_irqrestore(&bank->lock, flags);
1349 
1350 	val = readl(bank->base + REG_PIO_PCOMP);
1351 	val &= ~BIT(pin);
1352 	val |= (comp << pin);
1353 	writel(val, bank->base + REG_PIO_PCOMP);
1354 
1355 	return 0;
1356 }
1357 
1358 /*
1359  * As edge triggers are not supported at hardware level, it is supported by
1360  * software by exploiting the level trigger support in hardware.
1361  *
1362  * Steps for detection raising edge interrupt in software.
1363  *
1364  * Step 1: CONFIGURE pin to detect level LOW interrupts.
1365  *
1366  * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,
1367  * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt.
1368  * IGNORE calling the actual interrupt handler for the pin at this stage.
1369  *
1370  * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
1371  * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then
1372  * DISPATCH the interrupt to the interrupt handler of the pin.
1373  *
1374  *		 step-1  ________     __________
1375  *				|     | step - 3
1376  *			        |     |
1377  *			step -2 |_____|
1378  *
1379  * falling edge is also detected int the same way.
1380  *
1381  */
__gpio_irq_handler(struct st_gpio_bank * bank)1382 static void __gpio_irq_handler(struct st_gpio_bank *bank)
1383 {
1384 	unsigned long port_in, port_mask, port_comp, active_irqs;
1385 	unsigned long bank_edge_mask, flags;
1386 	int n, val, ecfg;
1387 
1388 	spin_lock_irqsave(&bank->lock, flags);
1389 	bank_edge_mask = bank->irq_edge_conf;
1390 	spin_unlock_irqrestore(&bank->lock, flags);
1391 
1392 	for (;;) {
1393 		port_in = readl(bank->base + REG_PIO_PIN);
1394 		port_comp = readl(bank->base + REG_PIO_PCOMP);
1395 		port_mask = readl(bank->base + REG_PIO_PMASK);
1396 
1397 		active_irqs = (port_in ^ port_comp) & port_mask;
1398 
1399 		if (active_irqs == 0)
1400 			break;
1401 
1402 		for_each_set_bit(n, &active_irqs, BITS_PER_LONG) {
1403 			/* check if we are detecting fake edges ... */
1404 			ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n);
1405 
1406 			if (ecfg) {
1407 				/* edge detection. */
1408 				val = st_gpio_get(&bank->gpio_chip, n);
1409 
1410 				writel(BIT(n),
1411 					val ? bank->base + REG_PIO_SET_PCOMP :
1412 					bank->base + REG_PIO_CLR_PCOMP);
1413 
1414 				if (ecfg != ST_IRQ_EDGE_BOTH &&
1415 					!((ecfg & ST_IRQ_EDGE_FALLING) ^ val))
1416 					continue;
1417 			}
1418 
1419 			generic_handle_domain_irq(bank->gpio_chip.irq.domain, n);
1420 		}
1421 	}
1422 }
1423 
st_gpio_irq_handler(struct irq_desc * desc)1424 static void st_gpio_irq_handler(struct irq_desc *desc)
1425 {
1426 	/* interrupt dedicated per bank */
1427 	struct irq_chip *chip = irq_desc_get_chip(desc);
1428 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1429 	struct st_gpio_bank *bank = gpiochip_get_data(gc);
1430 
1431 	chained_irq_enter(chip, desc);
1432 	__gpio_irq_handler(bank);
1433 	chained_irq_exit(chip, desc);
1434 }
1435 
st_gpio_irqmux_handler(struct irq_desc * desc)1436 static void st_gpio_irqmux_handler(struct irq_desc *desc)
1437 {
1438 	struct irq_chip *chip = irq_desc_get_chip(desc);
1439 	struct st_pinctrl *info = irq_desc_get_handler_data(desc);
1440 	unsigned long status;
1441 	int n;
1442 
1443 	chained_irq_enter(chip, desc);
1444 
1445 	status = readl(info->irqmux_base);
1446 
1447 	for_each_set_bit(n, &status, info->nbanks)
1448 		__gpio_irq_handler(&info->banks[n]);
1449 
1450 	chained_irq_exit(chip, desc);
1451 }
1452 
1453 static const struct gpio_chip st_gpio_template = {
1454 	.request		= gpiochip_generic_request,
1455 	.free			= gpiochip_generic_free,
1456 	.get			= st_gpio_get,
1457 	.set			= st_gpio_set,
1458 	.direction_input	= st_gpio_direction_input,
1459 	.direction_output	= st_gpio_direction_output,
1460 	.get_direction		= st_gpio_get_direction,
1461 	.ngpio			= ST_GPIO_PINS_PER_BANK,
1462 };
1463 
1464 static struct irq_chip st_gpio_irqchip = {
1465 	.name			= "GPIO",
1466 	.irq_request_resources	= st_gpio_irq_request_resources,
1467 	.irq_release_resources	= st_gpio_irq_release_resources,
1468 	.irq_disable		= st_gpio_irq_mask,
1469 	.irq_mask		= st_gpio_irq_mask,
1470 	.irq_unmask		= st_gpio_irq_unmask,
1471 	.irq_set_type		= st_gpio_irq_set_type,
1472 	.flags			= IRQCHIP_SKIP_SET_WAKE,
1473 };
1474 
st_gpiolib_register_bank(struct st_pinctrl * info,int bank_nr,struct device_node * np)1475 static int st_gpiolib_register_bank(struct st_pinctrl *info,
1476 	int bank_nr, struct device_node *np)
1477 {
1478 	struct st_gpio_bank *bank = &info->banks[bank_nr];
1479 	struct pinctrl_gpio_range *range = &bank->range;
1480 	struct device *dev = info->dev;
1481 	int bank_num = of_alias_get_id(np, "gpio");
1482 	struct resource res, irq_res;
1483 	int err;
1484 
1485 	if (of_address_to_resource(np, 0, &res))
1486 		return -ENODEV;
1487 
1488 	bank->base = devm_ioremap_resource(dev, &res);
1489 	if (IS_ERR(bank->base))
1490 		return PTR_ERR(bank->base);
1491 
1492 	bank->gpio_chip = st_gpio_template;
1493 	bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;
1494 	bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;
1495 	bank->gpio_chip.of_node = np;
1496 	bank->gpio_chip.parent = dev;
1497 	spin_lock_init(&bank->lock);
1498 
1499 	of_property_read_string(np, "st,bank-name", &range->name);
1500 	bank->gpio_chip.label = range->name;
1501 
1502 	range->id = bank_num;
1503 	range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK;
1504 	range->npins = bank->gpio_chip.ngpio;
1505 	range->gc = &bank->gpio_chip;
1506 
1507 	/**
1508 	 * GPIO bank can have one of the two possible types of
1509 	 * interrupt-wirings.
1510 	 *
1511 	 * First type is via irqmux, single interrupt is used by multiple
1512 	 * gpio banks. This reduces number of overall interrupts numbers
1513 	 * required. All these banks belong to a single pincontroller.
1514 	 *		  _________
1515 	 *		 |	   |----> [gpio-bank (n)    ]
1516 	 *		 |	   |----> [gpio-bank (n + 1)]
1517 	 *	[irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
1518 	 *		 |	   |----> [gpio-bank (...  )]
1519 	 *		 |_________|----> [gpio-bank (n + 7)]
1520 	 *
1521 	 * Second type has a dedicated interrupt per each gpio bank.
1522 	 *
1523 	 *	[irqN]----> [gpio-bank (n)]
1524 	 */
1525 
1526 	if (of_irq_to_resource(np, 0, &irq_res) > 0) {
1527 		struct gpio_irq_chip *girq;
1528 		int gpio_irq = irq_res.start;
1529 
1530 		/* This is not a valid IRQ */
1531 		if (gpio_irq <= 0) {
1532 			dev_err(dev, "invalid IRQ for %pOF bank\n", np);
1533 			goto skip_irq;
1534 		}
1535 		/* We need to have a mux as well */
1536 		if (!info->irqmux_base) {
1537 			dev_err(dev, "no irqmux for %pOF bank\n", np);
1538 			goto skip_irq;
1539 		}
1540 
1541 		girq = &bank->gpio_chip.irq;
1542 		girq->chip = &st_gpio_irqchip;
1543 		girq->parent_handler = st_gpio_irq_handler;
1544 		girq->num_parents = 1;
1545 		girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
1546 					     GFP_KERNEL);
1547 		if (!girq->parents)
1548 			return -ENOMEM;
1549 		girq->parents[0] = gpio_irq;
1550 		girq->default_type = IRQ_TYPE_NONE;
1551 		girq->handler = handle_simple_irq;
1552 	}
1553 
1554 skip_irq:
1555 	err  = gpiochip_add_data(&bank->gpio_chip, bank);
1556 	if (err)
1557 		return dev_err_probe(dev, err, "Failed to add gpiochip(%d)!\n", bank_num);
1558 	dev_info(dev, "%s bank added.\n", range->name);
1559 
1560 	return 0;
1561 }
1562 
1563 static const struct of_device_id st_pctl_of_match[] = {
1564 	{ .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data},
1565 	{ .compatible = "st,stih407-front-pinctrl", .data = &stih407_data},
1566 	{ .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data},
1567 	{ .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata},
1568 	{ /* sentinel */ }
1569 };
1570 
st_pctl_probe_dt(struct platform_device * pdev,struct pinctrl_desc * pctl_desc,struct st_pinctrl * info)1571 static int st_pctl_probe_dt(struct platform_device *pdev,
1572 	struct pinctrl_desc *pctl_desc, struct st_pinctrl *info)
1573 {
1574 	struct device *dev = &pdev->dev;
1575 	int ret = 0;
1576 	int i = 0, j = 0, k = 0, bank;
1577 	struct pinctrl_pin_desc *pdesc;
1578 	struct device_node *np = dev->of_node;
1579 	struct device_node *child;
1580 	int grp_index = 0;
1581 	int irq = 0;
1582 
1583 	st_pctl_dt_child_count(info, np);
1584 	if (!info->nbanks)
1585 		return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n");
1586 
1587 	dev_info(dev, "nbanks = %d\n", info->nbanks);
1588 	dev_info(dev, "nfunctions = %d\n", info->nfunctions);
1589 	dev_info(dev, "ngroups = %d\n", info->ngroups);
1590 
1591 	info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
1592 
1593 	info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
1594 
1595 	info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL);
1596 
1597 	if (!info->functions || !info->groups || !info->banks)
1598 		return -ENOMEM;
1599 
1600 	info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1601 	if (IS_ERR(info->regmap))
1602 		return dev_err_probe(dev, PTR_ERR(info->regmap), "No syscfg phandle specified\n");
1603 	info->data = of_match_node(st_pctl_of_match, np)->data;
1604 
1605 	irq = platform_get_irq(pdev, 0);
1606 
1607 	if (irq > 0) {
1608 		info->irqmux_base = devm_platform_ioremap_resource_byname(pdev, "irqmux");
1609 		if (IS_ERR(info->irqmux_base))
1610 			return PTR_ERR(info->irqmux_base);
1611 
1612 		irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler,
1613 						 info);
1614 	}
1615 
1616 	pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK;
1617 	pdesc =	devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL);
1618 	if (!pdesc)
1619 		return -ENOMEM;
1620 
1621 	pctl_desc->pins = pdesc;
1622 
1623 	bank = 0;
1624 	for_each_child_of_node(np, child) {
1625 		if (of_property_read_bool(child, "gpio-controller")) {
1626 			const char *bank_name = NULL;
1627 			char **pin_names;
1628 
1629 			ret = st_gpiolib_register_bank(info, bank, child);
1630 			if (ret) {
1631 				of_node_put(child);
1632 				return ret;
1633 			}
1634 
1635 			k = info->banks[bank].range.pin_base;
1636 			bank_name = info->banks[bank].range.name;
1637 
1638 			pin_names = devm_kasprintf_strarray(dev, bank_name, ST_GPIO_PINS_PER_BANK);
1639 			if (IS_ERR(pin_names)) {
1640 				of_node_put(child);
1641 				return PTR_ERR(pin_names);
1642 			}
1643 
1644 			for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) {
1645 				pdesc->number = k;
1646 				pdesc->name = pin_names[j];
1647 				pdesc++;
1648 			}
1649 			st_parse_syscfgs(info, bank, child);
1650 			bank++;
1651 		} else {
1652 			ret = st_pctl_parse_functions(child, info,
1653 							i++, &grp_index);
1654 			if (ret) {
1655 				dev_err(dev, "No functions found.\n");
1656 				of_node_put(child);
1657 				return ret;
1658 			}
1659 		}
1660 	}
1661 
1662 	return 0;
1663 }
1664 
st_pctl_probe(struct platform_device * pdev)1665 static int st_pctl_probe(struct platform_device *pdev)
1666 {
1667 	struct device *dev = &pdev->dev;
1668 	struct st_pinctrl *info;
1669 	struct pinctrl_desc *pctl_desc;
1670 	int ret, i;
1671 
1672 	if (!dev->of_node) {
1673 		dev_err(dev, "device node not found.\n");
1674 		return -EINVAL;
1675 	}
1676 
1677 	pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL);
1678 	if (!pctl_desc)
1679 		return -ENOMEM;
1680 
1681 	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
1682 	if (!info)
1683 		return -ENOMEM;
1684 
1685 	info->dev = dev;
1686 	platform_set_drvdata(pdev, info);
1687 	ret = st_pctl_probe_dt(pdev, pctl_desc, info);
1688 	if (ret)
1689 		return ret;
1690 
1691 	pctl_desc->owner	= THIS_MODULE;
1692 	pctl_desc->pctlops	= &st_pctlops;
1693 	pctl_desc->pmxops	= &st_pmxops;
1694 	pctl_desc->confops	= &st_confops;
1695 	pctl_desc->name		= dev_name(dev);
1696 
1697 	info->pctl = devm_pinctrl_register(dev, pctl_desc, info);
1698 	if (IS_ERR(info->pctl))
1699 		return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n");
1700 
1701 	for (i = 0; i < info->nbanks; i++)
1702 		pinctrl_add_gpio_range(info->pctl, &info->banks[i].range);
1703 
1704 	return 0;
1705 }
1706 
1707 static struct platform_driver st_pctl_driver = {
1708 	.driver = {
1709 		.name = "st-pinctrl",
1710 		.of_match_table = st_pctl_of_match,
1711 	},
1712 	.probe = st_pctl_probe,
1713 };
1714 
st_pctl_init(void)1715 static int __init st_pctl_init(void)
1716 {
1717 	return platform_driver_register(&st_pctl_driver);
1718 }
1719 arch_initcall(st_pctl_init);
1720