1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_PHY_H__
6 #define __RTW89_PHY_H__
7
8 #include "core.h"
9
10 #define RTW89_PHY_ADDR_OFFSET 0x10000
11 #define RTW89_RF_ADDR_ADSEL_MASK BIT(16)
12
13 #define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr)
14 #define PHY_HEADLINE_VALID 0xf
15 #define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr)
16 #define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \
17 FIELD_PREP(GENMASK(7, 0), cv))
18
19 #define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr)
20 #define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr)
21 #define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr)
22 #define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr)
23 #define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; })
24 #define PHY_COND_BRANCH_IF 0x8
25 #define PHY_COND_BRANCH_ELIF 0x9
26 #define PHY_COND_BRANCH_ELSE 0xa
27 #define PHY_COND_BRANCH_END 0xb
28 #define PHY_COND_CHECK 0x4
29 #define PHY_COND_DONT_CARE 0xff
30
31 #define RA_MASK_CCK_RATES GENMASK_ULL(3, 0)
32 #define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4)
33 #define RA_MASK_SUBCCK_RATES 0x5ULL
34 #define RA_MASK_SUBOFDM_RATES 0x10ULL
35 #define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12)
36 #define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24)
37 #define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36)
38 #define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48)
39 #define RA_MASK_HT_RATES GENMASK_ULL(55, 12)
40 #define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12)
41 #define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24)
42 #define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36)
43 #define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48)
44 #define RA_MASK_VHT_RATES GENMASK_ULL(57, 12)
45 #define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12)
46 #define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24)
47 #define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36)
48 #define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48)
49 #define RA_MASK_HE_RATES GENMASK_ULL(59, 12)
50
51 #define CFO_TRK_ENABLE_TH (2 << 2)
52 #define CFO_TRK_STOP_TH_4 (30 << 2)
53 #define CFO_TRK_STOP_TH_3 (20 << 2)
54 #define CFO_TRK_STOP_TH_2 (10 << 2)
55 #define CFO_TRK_STOP_TH_1 (00 << 2)
56 #define CFO_TRK_STOP_TH (2 << 2)
57 #define CFO_SW_COMP_FINE_TUNE (2 << 2)
58 #define CFO_PERIOD_CNT 15
59 #define CFO_BOUND 32
60 #define CFO_TP_UPPER 100
61 #define CFO_TP_LOWER 50
62 #define CFO_COMP_PERIOD 250
63 #define CFO_COMP_WEIGHT 8
64 #define MAX_CFO_TOLERANCE 30
65
66 #define CCX_MAX_PERIOD 2097
67 #define CCX_MAX_PERIOD_UNIT 32
68 #define MS_TO_4US_RATIO 250
69 #define ENV_MNTR_FAIL_DWORD 0xffffffff
70 #define ENV_MNTR_IFSCLM_HIS_MAX 127
71 #define PERMIL 1000
72 #define PERCENT 100
73 #define IFS_CLM_TH0_UPPER 64
74 #define IFS_CLM_TH_MUL 4
75 #define IFS_CLM_TH_START_IDX 0
76
77 #define TIA0_GAIN_A 12
78 #define TIA0_GAIN_G 16
79 #define LNA0_GAIN (-24)
80 #define U4_MAX_BIT 3
81 #define U8_MAX_BIT 7
82 #define DIG_GAIN_SHIFT 2
83 #define DIG_GAIN 8
84
85 #define LNA_IDX_MAX 6
86 #define LNA_IDX_MIN 0
87 #define TIA_IDX_MAX 1
88 #define TIA_IDX_MIN 0
89 #define RXB_IDX_MAX 31
90 #define RXB_IDX_MIN 0
91
92 #define IGI_RSSI_MAX 110
93 #define PD_TH_MAX_RSSI 70
94 #define PD_TH_MIN_RSSI 8
95 #define CCKPD_TH_MIN_RSSI (-18)
96 #define PD_TH_BW160_CMP_VAL 9
97 #define PD_TH_BW80_CMP_VAL 6
98 #define PD_TH_BW40_CMP_VAL 3
99 #define PD_TH_BW20_CMP_VAL 0
100 #define PD_TH_CMP_VAL 3
101 #define PD_TH_SB_FLTR_CMP_VAL 7
102
103 #define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT)
104 #define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL)
105 #define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA)
106 #define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD)
107 #define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA)
108
109 enum rtw89_phy_c2h_ra_func {
110 RTW89_PHY_C2H_FUNC_STS_RPT,
111 RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT,
112 RTW89_PHY_C2H_FUNC_TXSTS,
113 RTW89_PHY_C2H_FUNC_RA_MAX,
114 };
115
116 enum rtw89_phy_c2h_class {
117 RTW89_PHY_C2H_CLASS_RUA,
118 RTW89_PHY_C2H_CLASS_RA,
119 RTW89_PHY_C2H_CLASS_DM,
120 RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10,
121 RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17,
122 RTW89_PHY_C2H_CLASS_MAX,
123 };
124
125 enum rtw89_env_monitor_result_level {
126 RTW89_PHY_ENV_MON_CCX_FAIL = 0,
127 RTW89_PHY_ENV_MON_NHM = BIT(0),
128 RTW89_PHY_ENV_MON_CLM = BIT(1),
129 RTW89_PHY_ENV_MON_FAHM = BIT(2),
130 RTW89_PHY_ENV_MON_IFS_CLM = BIT(3),
131 RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4),
132 };
133
134 #define CCX_US_BASE_RATIO 4
135 enum rtw89_ccx_unit {
136 RTW89_CCX_4_US = 0,
137 RTW89_CCX_8_US = 1,
138 RTW89_CCX_16_US = 2,
139 RTW89_CCX_32_US = 3
140 };
141
142 enum rtw89_phy_status_ie_type {
143 RTW89_PHYSTS_IE00_CMN_CCK = 0,
144 RTW89_PHYSTS_IE01_CMN_OFDM = 1,
145 RTW89_PHYSTS_IE02_CMN_EXT_AX = 2,
146 RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3,
147 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4,
148 RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5,
149 RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6,
150 RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7,
151 RTW89_PHYSTS_IE08_FTR_CH = 8,
152 RTW89_PHYSTS_IE09_FTR_0 = 9,
153 RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10,
154 RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11,
155 RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12,
156 RTW89_PHYSTS_IE13_DL_MU_DEF = 13,
157 RTW89_PHYSTS_IE14_TB_UL_CQI = 14,
158 RTW89_PHYSTS_IE15_TB_UL_DEF = 15,
159 RTW89_PHYSTS_IE16_RSVD16 = 16,
160 RTW89_PHYSTS_IE17_TB_UL_CTRL = 17,
161 RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18,
162 RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19,
163 RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20,
164 RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21,
165 RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22,
166 RTW89_PHYSTS_IE23_RSVD23 = 23,
167 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A = 24,
168 RTW89_PHYSTS_IE25_OFDM_TD_PATH_B = 25,
169 RTW89_PHYSTS_IE26_OFDM_TD_PATH_C = 26,
170 RTW89_PHYSTS_IE27_OFDM_TD_PATH_D = 27,
171 RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28,
172 RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29,
173 RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30,
174 RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31,
175
176 /* keep last */
177 RTW89_PHYSTS_IE_NUM,
178 RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1
179 };
180
181 enum rtw89_phy_status_bitmap {
182 RTW89_TD_SEARCH_FAIL = 0,
183 RTW89_BRK_BY_TX_PKT = 1,
184 RTW89_CCA_SPOOF = 2,
185 RTW89_OFDM_BRK = 3,
186 RTW89_CCK_BRK = 4,
187 RTW89_DL_MU_SPOOFING = 5,
188 RTW89_HE_MU = 6,
189 RTW89_VHT_MU = 7,
190 RTW89_UL_TB_SPOOFING = 8,
191 RTW89_RSVD_9 = 9,
192 RTW89_TRIG_BASE_PPDU = 10,
193 RTW89_CCK_PKT = 11,
194 RTW89_LEGACY_OFDM_PKT = 12,
195 RTW89_HT_PKT = 13,
196 RTW89_VHT_PKT = 14,
197 RTW89_HE_PKT = 15,
198
199 RTW89_PHYSTS_BITMAP_NUM
200 };
201
202 enum rtw89_dig_gain_type {
203 RTW89_DIG_GAIN_LNA_G = 0,
204 RTW89_DIG_GAIN_TIA_G = 1,
205 RTW89_DIG_GAIN_LNA_A = 2,
206 RTW89_DIG_GAIN_TIA_A = 3,
207 RTW89_DIG_GAIN_MAX = 4
208 };
209
210 enum rtw89_dig_gain_lna_idx {
211 RTW89_DIG_GAIN_LNA_IDX1 = 1,
212 RTW89_DIG_GAIN_LNA_IDX2 = 2,
213 RTW89_DIG_GAIN_LNA_IDX3 = 3,
214 RTW89_DIG_GAIN_LNA_IDX4 = 4,
215 RTW89_DIG_GAIN_LNA_IDX5 = 5,
216 RTW89_DIG_GAIN_LNA_IDX6 = 6
217 };
218
219 enum rtw89_dig_gain_tia_idx {
220 RTW89_DIG_GAIN_TIA_IDX0 = 0,
221 RTW89_DIG_GAIN_TIA_IDX1 = 1
222 };
223
224 enum rtw89_tssi_bandedge_cfg {
225 RTW89_TSSI_BANDEDGE_FLAT,
226 RTW89_TSSI_BANDEDGE_LOW,
227 RTW89_TSSI_BANDEDGE_MID,
228 RTW89_TSSI_BANDEDGE_HIGH,
229
230 RTW89_TSSI_CFG_NUM,
231 };
232
233 enum rtw89_tssi_sbw_idx {
234 RTW89_TSSI_SBW20,
235 RTW89_TSSI_SBW40_0,
236 RTW89_TSSI_SBW40_1,
237 RTW89_TSSI_SBW80_0,
238 RTW89_TSSI_SBW80_1,
239 RTW89_TSSI_SBW80_2,
240 RTW89_TSSI_SBW80_3,
241 RTW89_TSSI_SBW160_0,
242 RTW89_TSSI_SBW160_1,
243 RTW89_TSSI_SBW160_2,
244 RTW89_TSSI_SBW160_3,
245 RTW89_TSSI_SBW160_4,
246 RTW89_TSSI_SBW160_5,
247 RTW89_TSSI_SBW160_6,
248 RTW89_TSSI_SBW160_7,
249
250 RTW89_TSSI_SBW_NUM,
251 };
252
253 struct rtw89_txpwr_byrate_cfg {
254 enum rtw89_band band;
255 enum rtw89_nss nss;
256 enum rtw89_rate_section rs;
257 u8 shf;
258 u8 len;
259 u32 data;
260 };
261
262 #define DELTA_SWINGIDX_SIZE 30
263
264 struct rtw89_txpwr_track_cfg {
265 const s8 (*delta_swingidx_6gb_n)[DELTA_SWINGIDX_SIZE];
266 const s8 (*delta_swingidx_6gb_p)[DELTA_SWINGIDX_SIZE];
267 const s8 (*delta_swingidx_6ga_n)[DELTA_SWINGIDX_SIZE];
268 const s8 (*delta_swingidx_6ga_p)[DELTA_SWINGIDX_SIZE];
269 const s8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE];
270 const s8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE];
271 const s8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE];
272 const s8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE];
273 const s8 *delta_swingidx_2gb_n;
274 const s8 *delta_swingidx_2gb_p;
275 const s8 *delta_swingidx_2ga_n;
276 const s8 *delta_swingidx_2ga_p;
277 const s8 *delta_swingidx_2g_cck_b_n;
278 const s8 *delta_swingidx_2g_cck_b_p;
279 const s8 *delta_swingidx_2g_cck_a_n;
280 const s8 *delta_swingidx_2g_cck_a_p;
281 };
282
283 struct rtw89_phy_dig_gain_cfg {
284 const struct rtw89_reg_def *table;
285 u8 size;
286 };
287
288 struct rtw89_phy_dig_gain_table {
289 const struct rtw89_phy_dig_gain_cfg *cfg_lna_g;
290 const struct rtw89_phy_dig_gain_cfg *cfg_tia_g;
291 const struct rtw89_phy_dig_gain_cfg *cfg_lna_a;
292 const struct rtw89_phy_dig_gain_cfg *cfg_tia_a;
293 };
294
295 struct rtw89_phy_tssi_dbw_table {
296 u32 data[RTW89_TSSI_CFG_NUM][RTW89_TSSI_SBW_NUM];
297 };
298
299 struct rtw89_phy_reg3_tbl {
300 const struct rtw89_reg3_def *reg3;
301 int size;
302 };
303
304 #define DECLARE_PHY_REG3_TBL(_name) \
305 const struct rtw89_phy_reg3_tbl _name ## _tbl = { \
306 .reg3 = _name, \
307 .size = ARRAY_SIZE(_name), \
308 }
309
310 struct rtw89_nbi_reg_def {
311 struct rtw89_reg_def notch1_idx;
312 struct rtw89_reg_def notch1_frac_idx;
313 struct rtw89_reg_def notch1_en;
314 struct rtw89_reg_def notch2_idx;
315 struct rtw89_reg_def notch2_frac_idx;
316 struct rtw89_reg_def notch2_en;
317 };
318
319 extern const u8 rtw89_rs_idx_max[RTW89_RS_MAX];
320 extern const u8 rtw89_rs_nss_max[RTW89_RS_MAX];
321
rtw89_phy_write8(struct rtw89_dev * rtwdev,u32 addr,u8 data)322 static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev,
323 u32 addr, u8 data)
324 {
325 rtw89_write8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data);
326 }
327
rtw89_phy_write16(struct rtw89_dev * rtwdev,u32 addr,u16 data)328 static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev,
329 u32 addr, u16 data)
330 {
331 rtw89_write16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data);
332 }
333
rtw89_phy_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data)334 static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev,
335 u32 addr, u32 data)
336 {
337 rtw89_write32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data);
338 }
339
rtw89_phy_write32_set(struct rtw89_dev * rtwdev,u32 addr,u32 bits)340 static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev,
341 u32 addr, u32 bits)
342 {
343 rtw89_write32_set(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits);
344 }
345
rtw89_phy_write32_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bits)346 static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev,
347 u32 addr, u32 bits)
348 {
349 rtw89_write32_clr(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits);
350 }
351
rtw89_phy_write32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data)352 static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev,
353 u32 addr, u32 mask, u32 data)
354 {
355 rtw89_write32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask, data);
356 }
357
rtw89_phy_read8(struct rtw89_dev * rtwdev,u32 addr)358 static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr)
359 {
360 return rtw89_read8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET);
361 }
362
rtw89_phy_read16(struct rtw89_dev * rtwdev,u32 addr)363 static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr)
364 {
365 return rtw89_read16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET);
366 }
367
rtw89_phy_read32(struct rtw89_dev * rtwdev,u32 addr)368 static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr)
369 {
370 return rtw89_read32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET);
371 }
372
rtw89_phy_read32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)373 static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev,
374 u32 addr, u32 mask)
375 {
376 return rtw89_read32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask);
377 }
378
379 enum rtw89_rfk_flag {
380 RTW89_RFK_F_WRF = 0,
381 RTW89_RFK_F_WM = 1,
382 RTW89_RFK_F_WS = 2,
383 RTW89_RFK_F_WC = 3,
384 RTW89_RFK_F_DELAY = 4,
385 RTW89_RFK_F_NUM,
386 };
387
388 struct rtw89_rfk_tbl {
389 const struct rtw89_reg5_def *defs;
390 u32 size;
391 };
392
393 #define RTW89_DECLARE_RFK_TBL(_name) \
394 const struct rtw89_rfk_tbl _name ## _tbl = { \
395 .defs = _name, \
396 .size = ARRAY_SIZE(_name), \
397 }
398
399 #define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data) \
400 {.flag = RTW89_RFK_F_WRF, \
401 .path = _path, \
402 .addr = _addr, \
403 .mask = _mask, \
404 .data = _data,}
405
406 #define RTW89_DECL_RFK_WM(_addr, _mask, _data) \
407 {.flag = RTW89_RFK_F_WM, \
408 .addr = _addr, \
409 .mask = _mask, \
410 .data = _data,}
411
412 #define RTW89_DECL_RFK_WS(_addr, _mask) \
413 {.flag = RTW89_RFK_F_WS, \
414 .addr = _addr, \
415 .mask = _mask,}
416
417 #define RTW89_DECL_RFK_WC(_addr, _mask) \
418 {.flag = RTW89_RFK_F_WC, \
419 .addr = _addr, \
420 .mask = _mask,}
421
422 #define RTW89_DECL_RFK_DELAY(_data) \
423 {.flag = RTW89_RFK_F_DELAY, \
424 .data = _data,}
425
426 void
427 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl);
428
429 #define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f) \
430 do { \
431 typeof(dev) __dev = (dev); \
432 if (cond) \
433 rtw89_rfk_parser(__dev, (tbl_t)); \
434 else \
435 rtw89_rfk_parser(__dev, (tbl_f)); \
436 } while (0)
437
438 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
439 const struct rtw89_phy_reg3_tbl *tbl);
440 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
441 struct rtw89_channel_params *param,
442 enum rtw89_bandwidth dbw);
443 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
444 u32 addr, u32 mask);
445 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
446 u32 addr, u32 mask);
447 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
448 u32 addr, u32 mask, u32 data);
449 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
450 u32 addr, u32 mask, u32 data);
451 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev);
452 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev);
453 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
454 const struct rtw89_reg2_def *reg,
455 enum rtw89_rf_path rf_path,
456 void *extra_data);
457 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev);
458 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
459 u32 data, enum rtw89_phy_idx phy_idx);
460 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
461 const struct rtw89_txpwr_table *tbl);
462 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev,
463 const struct rtw89_rate_desc *rate_desc);
464 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev,
465 struct rtw89_txpwr_limit *lmt,
466 u8 ntx);
467 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev,
468 struct rtw89_txpwr_limit_ru *lmt_ru,
469 u8 ntx);
470 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev,
471 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch);
472 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta);
473 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev);
474 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,
475 u32 changed);
476 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
477 struct ieee80211_vif *vif,
478 const struct cfg80211_bitrate_mask *mask);
479 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
480 u32 len, u8 class, u8 func);
481 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev);
482 void rtw89_phy_cfo_track_work(struct work_struct *work);
483 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
484 struct rtw89_rx_phy_ppdu *phy_ppdu);
485 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev);
486 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev);
487 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
488 u32 val);
489 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev);
490 void rtw89_phy_dig(struct rtw89_dev *rtwdev);
491 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
492 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
493 enum rtw89_mac_idx mac_idx,
494 enum rtw89_tssi_bandedge_cfg bandedge_cfg);
495
496 #endif
497