1 /*
2 * NXP Wireless LAN device driver: SDIO specific definitions
3 *
4 * Copyright 2011-2020 NXP
5 *
6 * This software file (the "File") is distributed by NXP
7 * under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
13 *
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
17 * this warranty disclaimer.
18 */
19
20 #ifndef _MWIFIEX_SDIO_H
21 #define _MWIFIEX_SDIO_H
22
23
24 #include <linux/completion.h>
25 #include <linux/mmc/sdio.h>
26 #include <linux/mmc/sdio_ids.h>
27 #include <linux/mmc/sdio_func.h>
28 #include <linux/mmc/card.h>
29 #include <linux/mmc/host.h>
30
31 #include "main.h"
32
33 #define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
34 #define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
35 #define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
36 #define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
37 #define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin"
38 #define SD8801_DEFAULT_FW_NAME "mrvl/sd8801_uapsta.bin"
39 #define SD8977_DEFAULT_FW_NAME "mrvl/sdsd8977_combo_v2.bin"
40 #define SD8987_DEFAULT_FW_NAME "mrvl/sd8987_uapsta.bin"
41 #define SD8997_DEFAULT_FW_NAME "mrvl/sdsd8997_combo_v4.bin"
42 #define SD8997_SDIOUART_FW_NAME "mrvl/sdiouart8997_combo_v4.bin"
43
44 #define BLOCK_MODE 1
45 #define BYTE_MODE 0
46
47 #define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
48
49 #define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
50
51 #define MWIFIEX_MAX_FUNC2_REG_NUM 13
52 #define MWIFIEX_SDIO_SCRATCH_SIZE 10
53
54 #define SDIO_MPA_ADDR_BASE 0x1000
55 #define CTRL_PORT 0
56 #define CTRL_PORT_MASK 0x0001
57
58 #define CMD_PORT_UPLD_INT_MASK (0x1U<<6)
59 #define CMD_PORT_DNLD_INT_MASK (0x1U<<7)
60 #define HOST_TERM_CMD53 (0x1U << 2)
61 #define REG_PORT 0
62 #define MEM_PORT 0x10000
63
64 #define CMD53_NEW_MODE (0x1U << 0)
65 #define CMD_PORT_RD_LEN_EN (0x1U << 2)
66 #define CMD_PORT_AUTO_EN (0x1U << 0)
67 #define CMD_PORT_SLCT 0x8000
68 #define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U)
69 #define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U)
70
71 #define MWIFIEX_MP_AGGR_BUF_SIZE_16K (16384)
72 #define MWIFIEX_MP_AGGR_BUF_SIZE_32K (32768)
73 /* we leave one block of 256 bytes for DMA alignment*/
74 #define MWIFIEX_MP_AGGR_BUF_SIZE_MAX (65280)
75
76 /* Misc. Config Register : Auto Re-enable interrupts */
77 #define AUTO_RE_ENABLE_INT BIT(4)
78
79 /* Host Control Registers : Configuration */
80 #define CONFIGURATION_REG 0x00
81 /* Host Control Registers : Host power up */
82 #define HOST_POWER_UP (0x1U << 1)
83
84 /* Host Control Registers : Upload host interrupt mask */
85 #define UP_LD_HOST_INT_MASK (0x1U)
86 /* Host Control Registers : Download host interrupt mask */
87 #define DN_LD_HOST_INT_MASK (0x2U)
88
89 /* Host Control Registers : Upload host interrupt status */
90 #define UP_LD_HOST_INT_STATUS (0x1U)
91 /* Host Control Registers : Download host interrupt status */
92 #define DN_LD_HOST_INT_STATUS (0x2U)
93
94 /* Host Control Registers : Host interrupt status */
95 #define CARD_INT_STATUS_REG 0x28
96
97 /* Card Control Registers : Card I/O ready */
98 #define CARD_IO_READY (0x1U << 3)
99 /* Card Control Registers : Download card ready */
100 #define DN_LD_CARD_RDY (0x1U << 0)
101
102 /* Max retry number of CMD53 write */
103 #define MAX_WRITE_IOMEM_RETRY 2
104
105 /* SDIO Tx aggregation in progress ? */
106 #define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
107
108 /* SDIO Tx aggregation buffer room for next packet ? */
109 #define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
110 <= a->mpa_tx.buf_size)
111
112 /* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
113 #define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
114 memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
115 payload, pkt_len); \
116 a->mpa_tx.buf_len += pkt_len; \
117 if (!a->mpa_tx.pkt_cnt) \
118 a->mpa_tx.start_port = port; \
119 if (a->mpa_tx.start_port <= port) \
120 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \
121 else \
122 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+ \
123 (a->max_ports - \
124 a->mp_end_port))); \
125 a->mpa_tx.pkt_cnt++; \
126 } while (0)
127
128 /* SDIO Tx aggregation limit ? */
129 #define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
130 (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
131
132 /* Reset SDIO Tx aggregation buffer parameters */
133 #define MP_TX_AGGR_BUF_RESET(a) do { \
134 a->mpa_tx.pkt_cnt = 0; \
135 a->mpa_tx.buf_len = 0; \
136 a->mpa_tx.ports = 0; \
137 a->mpa_tx.start_port = 0; \
138 } while (0)
139
140 /* SDIO Rx aggregation limit ? */
141 #define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
142 (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
143
144 /* SDIO Rx aggregation in progress ? */
145 #define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
146
147 /* SDIO Rx aggregation buffer room for next packet ? */
148 #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
149 ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
150
151 /* Reset SDIO Rx aggregation buffer parameters */
152 #define MP_RX_AGGR_BUF_RESET(a) do { \
153 a->mpa_rx.pkt_cnt = 0; \
154 a->mpa_rx.buf_len = 0; \
155 a->mpa_rx.ports = 0; \
156 a->mpa_rx.start_port = 0; \
157 } while (0)
158
159 /* data structure for SDIO MPA TX */
160 struct mwifiex_sdio_mpa_tx {
161 /* multiport tx aggregation buffer pointer */
162 u8 *buf;
163 u32 buf_len;
164 u32 pkt_cnt;
165 u32 ports;
166 u16 start_port;
167 u8 enabled;
168 u32 buf_size;
169 u32 pkt_aggr_limit;
170 };
171
172 struct mwifiex_sdio_mpa_rx {
173 u8 *buf;
174 u32 buf_len;
175 u32 pkt_cnt;
176 u32 ports;
177 u16 start_port;
178
179 struct sk_buff **skb_arr;
180 u32 *len_arr;
181
182 u8 enabled;
183 u32 buf_size;
184 u32 pkt_aggr_limit;
185 };
186
187 int mwifiex_bus_register(void);
188 void mwifiex_bus_unregister(void);
189
190 struct mwifiex_sdio_card_reg {
191 u8 start_rd_port;
192 u8 start_wr_port;
193 u8 base_0_reg;
194 u8 base_1_reg;
195 u8 poll_reg;
196 u8 host_int_enable;
197 u8 host_int_rsr_reg;
198 u8 host_int_status_reg;
199 u8 host_int_mask_reg;
200 u8 host_strap_reg;
201 u8 host_strap_mask;
202 u8 host_strap_value;
203 u8 status_reg_0;
204 u8 status_reg_1;
205 u8 sdio_int_mask;
206 u32 data_port_mask;
207 u8 io_port_0_reg;
208 u8 io_port_1_reg;
209 u8 io_port_2_reg;
210 u8 max_mp_regs;
211 u8 rd_bitmap_l;
212 u8 rd_bitmap_u;
213 u8 rd_bitmap_1l;
214 u8 rd_bitmap_1u;
215 u8 wr_bitmap_l;
216 u8 wr_bitmap_u;
217 u8 wr_bitmap_1l;
218 u8 wr_bitmap_1u;
219 u8 rd_len_p0_l;
220 u8 rd_len_p0_u;
221 u8 card_misc_cfg_reg;
222 u8 card_cfg_2_1_reg;
223 u8 cmd_rd_len_0;
224 u8 cmd_rd_len_1;
225 u8 cmd_rd_len_2;
226 u8 cmd_rd_len_3;
227 u8 cmd_cfg_0;
228 u8 cmd_cfg_1;
229 u8 cmd_cfg_2;
230 u8 cmd_cfg_3;
231 u8 fw_dump_host_ready;
232 u8 fw_dump_ctrl;
233 u8 fw_dump_start;
234 u8 fw_dump_end;
235 u8 func1_dump_reg_start;
236 u8 func1_dump_reg_end;
237 u8 func1_scratch_reg;
238 u8 func1_spec_reg_num;
239 u8 func1_spec_reg_table[MWIFIEX_MAX_FUNC2_REG_NUM];
240 };
241
242 struct sdio_mmc_card {
243 struct sdio_func *func;
244 struct mwifiex_adapter *adapter;
245
246 struct completion fw_done;
247 const char *firmware;
248 const char *firmware_sdiouart;
249 const struct mwifiex_sdio_card_reg *reg;
250 u8 max_ports;
251 u8 mp_agg_pkt_limit;
252 u16 tx_buf_size;
253 u32 mp_tx_agg_buf_size;
254 u32 mp_rx_agg_buf_size;
255
256 u32 mp_rd_bitmap;
257 u32 mp_wr_bitmap;
258
259 u16 mp_end_port;
260 u32 mp_data_port_mask;
261
262 u8 curr_rd_port;
263 u8 curr_wr_port;
264
265 u8 *mp_regs;
266 bool supports_sdio_new_mode;
267 bool has_control_mask;
268 bool can_dump_fw;
269 bool fw_dump_enh;
270 bool can_auto_tdls;
271 bool can_ext_scan;
272
273 struct mwifiex_sdio_mpa_tx mpa_tx;
274 struct mwifiex_sdio_mpa_rx mpa_rx;
275
276 struct work_struct work;
277 unsigned long work_flags;
278 };
279
280 struct mwifiex_sdio_device {
281 const char *firmware;
282 const char *firmware_sdiouart;
283 const struct mwifiex_sdio_card_reg *reg;
284 u8 max_ports;
285 u8 mp_agg_pkt_limit;
286 u16 tx_buf_size;
287 u32 mp_tx_agg_buf_size;
288 u32 mp_rx_agg_buf_size;
289 bool supports_sdio_new_mode;
290 bool has_control_mask;
291 bool can_dump_fw;
292 bool fw_dump_enh;
293 bool can_auto_tdls;
294 bool can_ext_scan;
295 };
296
297 /*
298 * .cmdrsp_complete handler
299 */
mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter * adapter,struct sk_buff * skb)300 static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
301 struct sk_buff *skb)
302 {
303 dev_kfree_skb_any(skb);
304 return 0;
305 }
306
307 /*
308 * .event_complete handler
309 */
mwifiex_sdio_event_complete(struct mwifiex_adapter * adapter,struct sk_buff * skb)310 static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
311 struct sk_buff *skb)
312 {
313 dev_kfree_skb_any(skb);
314 return 0;
315 }
316
317 static inline bool
mp_rx_aggr_port_limit_reached(struct sdio_mmc_card * card)318 mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
319 {
320 u8 tmp;
321
322 if (card->curr_rd_port < card->mpa_rx.start_port) {
323 if (card->supports_sdio_new_mode)
324 tmp = card->mp_end_port >> 1;
325 else
326 tmp = card->mp_agg_pkt_limit;
327
328 if (((card->max_ports - card->mpa_rx.start_port) +
329 card->curr_rd_port) >= tmp)
330 return true;
331 }
332
333 if (!card->supports_sdio_new_mode)
334 return false;
335
336 if ((card->curr_rd_port - card->mpa_rx.start_port) >=
337 (card->mp_end_port >> 1))
338 return true;
339
340 return false;
341 }
342
343 static inline bool
mp_tx_aggr_port_limit_reached(struct sdio_mmc_card * card)344 mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
345 {
346 u16 tmp;
347
348 if (card->curr_wr_port < card->mpa_tx.start_port) {
349 if (card->supports_sdio_new_mode)
350 tmp = card->mp_end_port >> 1;
351 else
352 tmp = card->mp_agg_pkt_limit;
353
354 if (((card->max_ports - card->mpa_tx.start_port) +
355 card->curr_wr_port) >= tmp)
356 return true;
357 }
358
359 if (!card->supports_sdio_new_mode)
360 return false;
361
362 if ((card->curr_wr_port - card->mpa_tx.start_port) >=
363 (card->mp_end_port >> 1))
364 return true;
365
366 return false;
367 }
368
369 /* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
mp_rx_aggr_setup(struct sdio_mmc_card * card,u16 rx_len,u8 port)370 static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
371 u16 rx_len, u8 port)
372 {
373 card->mpa_rx.buf_len += rx_len;
374
375 if (!card->mpa_rx.pkt_cnt)
376 card->mpa_rx.start_port = port;
377
378 if (card->supports_sdio_new_mode) {
379 card->mpa_rx.ports |= (1 << port);
380 } else {
381 if (card->mpa_rx.start_port <= port)
382 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt);
383 else
384 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1);
385 }
386 card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = NULL;
387 card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = rx_len;
388 card->mpa_rx.pkt_cnt++;
389 }
390 #endif /* _MWIFIEX_SDIO_H */
391