1 /* version dependencies have been confined to a separate file */
2 
3 /* Tunable parameters */
4 #define TX_RING_ENTRIES 64	/* 64-512?*/
5 
6 #define RX_RING_ENTRIES 16 /* Do not change */
7 /* Internal constants */
8 #define TX_RING_BUFFER_SIZE	(TX_RING_ENTRIES*sizeof(tx_packet))
9 #define RX_BUFFER_SIZE 1546 /* ethenet packet size */
10 #define METH_RX_BUFF_SIZE 4096
11 #define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
12 #define RX_BUFFER_OFFSET (sizeof(rx_status_vector)+2) /* staus vector + 2 bytes of padding */
13 #define RX_BUCKET_SIZE 256
14 
15 /* For more detailed explanations of what each field menas,
16    see Nick's great comments to #defines below (or docs, if
17    you are lucky enough toget hold of them :)*/
18 
19 /* tx status vector is written over tx command header upon
20    dma completion. */
21 
22 typedef struct tx_status_vector {
23 	u64		sent:1; /* always set to 1...*/
24 	u64		pad0:34;/* always set to 0 */
25 	u64		flags:9;			/*I'm too lazy to specify each one separately at the moment*/
26 	u64		col_retry_cnt:4;	/*collision retry count*/
27 	u64		len:16;				/*Transmit length in bytes*/
28 } tx_status_vector;
29 
30 /*
31  * Each packet is 128 bytes long.
32  * It consists of header, 0-3 concatination
33  * buffer pointers and up to 120 data bytes.
34  */
35 typedef struct tx_packet_hdr {
36 	u64		pad1:36; /*should be filled with 0 */
37 	u64		cat_ptr3_valid:1,	/*Concatination pointer valid flags*/
38 			cat_ptr2_valid:1,
39 			cat_ptr1_valid:1;
40 	u64		tx_int_flag:1;		/*Generate TX intrrupt when packet has been sent*/
41 	u64		term_dma_flag:1;	/*Terminate transmit DMA on transmit abort conditions*/
42 	u64		data_offset:7;		/*Starting byte offset in ring data block*/
43 	u64		data_len:16;		/*Length of valid data in bytes-1*/
44 } tx_packet_hdr;
45 typedef union tx_cat_ptr {
46 	struct {
47 		u64		pad2:16; /* should be 0 */
48 		u64		len:16;				/*length of buffer data - 1*/
49 		u64		start_addr:29;		/*Physical starting address*/
50 		u64		pad1:3; /* should be zero */
51 	} form;
52 	u64 raw;
53 } tx_cat_ptr;
54 
55 typedef struct tx_packet {
56 	union {
57 		tx_packet_hdr header;
58 		tx_status_vector res;
59 		u64 raw;
60 	}header;
61 	union {
62 		tx_cat_ptr cat_buf[3];
63 		char dt[120];
64 	} data;
65 } tx_packet;
66 
67 typedef union rx_status_vector {
68 	volatile struct {
69 		u64		pad1:1;/*fill it with ones*/
70 		u64		pad2:15;/*fill with 0*/
71 		u64		ip_chk_sum:16;
72 		u64		seq_num:5;
73 		u64		mac_addr_match:1;
74 		u64		mcast_addr_match:1;
75 		u64		carrier_event_seen:1;
76 		u64		bad_packet:1;
77 		u64		long_event_seen:1;
78 		u64		invalid_preamble:1;
79 		u64		broadcast:1;
80 		u64		multicast:1;
81 		u64		crc_error:1;
82 		u64		huh:1;/*???*/
83 		u64		rx_code_violation:1;
84 		u64		rx_len:16;
85 	} parsed;
86 	volatile u64 raw;
87 } rx_status_vector;
88 
89 typedef struct rx_packet {
90 	rx_status_vector status;
91         u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */
92         u16 pad2;
93 	char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */
94 } rx_packet;
95 
96 #define TX_INFO_RPTR    0x00FF0000
97 #define TX_INFO_WPTR    0x000000FF
98 
99 	/* Bits in METH_MAC */
100 
101 #define SGI_MAC_RESET		BIT(0)	/* 0: MAC110 active in run mode, 1: Global reset signal to MAC110 core is active */
102 #define METH_PHY_FDX		BIT(1) /* 0: Disable full duplex, 1: Enable full duplex */
103 #define METH_PHY_LOOP	BIT(2) /* 0: Normal operation, follows 10/100mbit and M10T/MII select, 1: loops internal MII bus */
104 				       /*    selects ignored */
105 #define METH_100MBIT		BIT(3) /* 0: 10meg mode, 1: 100meg mode */
106 #define METH_PHY_MII		BIT(4) /* 0: MII selected, 1: SIA selected */
107 				       /*   Note: when loopback is set this bit becomes collision control.  Setting this bit will */
108 				       /*         cause a collision to be reported. */
109 
110 				       /* Bits 5 and 6 are used to determine the Destination address filter mode */
111 #define METH_ACCEPT_MY 0			/* 00: Accept PHY address only */
112 #define METH_ACCEPT_MCAST 0x20	/* 01: Accept physical, broadcast, and multicast filter matches only */
113 #define METH_ACCEPT_AMCAST 0x40	/* 10: Accept physical, broadcast, and all multicast packets */
114 #define METH_PROMISC 0x60		/* 11: Promiscious mode */
115 
116 #define METH_PHY_LINK_FAIL	BIT(7) /* 0: Link failure detection disabled, 1: Hardware scans for link failure in PHY */
117 
118 #define METH_MAC_IPG	0x1ffff00
119 
120 #define METH_DEFAULT_IPG ((17<<15) | (11<<22) | (21<<8))
121 						/* 0x172e5c00 */ /* 23, 23, 23 */ /*0x54A9500 *//*21,21,21*/
122 				       /* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */
123 				       /* The gap depends on the clock speed of the link, 80ns per increment for 100baseT, 800ns  */
124 				       /* per increment for 10BaseT */
125 
126 				       /* Bits 15 through 21 are used to determine IPGR1 */
127 
128 				       /* Bits 22 through 28 are used to determine IPGR2 */
129 
130 #define METH_REV_SHIFT 29       /* Bits 29 through 31 are used to determine the revision */
131 				       /* 000: Initial revision */
132 				       /* 001: First revision, Improved TX concatenation */
133 
134 
135 /* DMA control bits */
136 #define METH_RX_OFFSET_SHIFT 12 /* Bits 12:14 of DMA control register indicate starting offset of packet data for RX operation */
137 #define METH_RX_DEPTH_SHIFT 4 /* Bits 8:4 define RX fifo depth -- when # of RX fifo entries != depth, interrupt is generted */
138 
139 #define METH_DMA_TX_EN BIT(1) /* enable TX DMA */
140 #define METH_DMA_TX_INT_EN BIT(0) /* enable TX Buffer Empty interrupt */
141 #define METH_DMA_RX_EN BIT(15) /* Enable RX */
142 #define METH_DMA_RX_INT_EN BIT(9) /* Enable interrupt on RX packet */
143 
144 /* RX FIFO MCL Info bits */
145 #define METH_RX_FIFO_WPTR(x)   (((x)>>16)&0xf)
146 #define METH_RX_FIFO_RPTR(x)   (((x)>>8)&0xf)
147 #define METH_RX_FIFO_DEPTH(x)  ((x)&0x1f)
148 
149 /* RX status bits */
150 
151 #define METH_RX_ST_VALID BIT(63)
152 #define METH_RX_ST_RCV_CODE_VIOLATION BIT(16)
153 #define METH_RX_ST_DRBL_NBL BIT(17)
154 #define METH_RX_ST_CRC_ERR BIT(18)
155 #define METH_RX_ST_MCAST_PKT BIT(19)
156 #define METH_RX_ST_BCAST_PKT BIT(20)
157 #define METH_RX_ST_INV_PREAMBLE_CTX BIT(21)
158 #define METH_RX_ST_LONG_EVT_SEEN BIT(22)
159 #define METH_RX_ST_BAD_PACKET BIT(23)
160 #define METH_RX_ST_CARRIER_EVT_SEEN BIT(24)
161 #define METH_RX_ST_MCAST_FILTER_MATCH BIT(25)
162 #define METH_RX_ST_PHYS_ADDR_MATCH BIT(26)
163 
164 #define METH_RX_STATUS_ERRORS \
165 	( \
166 	METH_RX_ST_RCV_CODE_VIOLATION| \
167 	METH_RX_ST_CRC_ERR| \
168 	METH_RX_ST_INV_PREAMBLE_CTX| \
169 	METH_RX_ST_LONG_EVT_SEEN| \
170 	METH_RX_ST_BAD_PACKET| \
171 	METH_RX_ST_CARRIER_EVT_SEEN \
172 	)
173 	/* Bits in METH_INT */
174 	/* Write _1_ to corresponding bit to clear */
175 #define METH_INT_TX_EMPTY	BIT(0)	/* 0: No interrupt pending, 1: The TX ring buffer is empty */
176 #define METH_INT_TX_PKT		BIT(1)	/* 0: No interrupt pending */
177 					      	/* 1: A TX message had the INT request bit set, the packet has been sent. */
178 #define METH_INT_TX_LINK_FAIL	BIT(2)	/* 0: No interrupt pending, 1: PHY has reported a link failure */
179 #define METH_INT_MEM_ERROR	BIT(3)	/* 0: No interrupt pending */
180 						/* 1: A memory error occurred during DMA, DMA stopped, Fatal */
181 #define METH_INT_TX_ABORT		BIT(4)	/* 0: No interrupt pending, 1: The TX aborted operation, DMA stopped, FATAL */
182 #define METH_INT_RX_THRESHOLD	BIT(5)	/* 0: No interrupt pending, 1: Selected receive threshold condition Valid */
183 #define METH_INT_RX_UNDERFLOW	BIT(6)	/* 0: No interrupt pending, 1: FIFO was empty, packet could not be queued */
184 #define METH_INT_RX_OVERFLOW		BIT(7)	/* 0: No interrupt pending, 1: DMA FIFO Overflow, DMA stopped, FATAL */
185 
186 /*#define METH_INT_RX_RPTR_MASK 0x0001F00*/		/* Bits 8 through 12 alias of RX read-pointer */
187 #define METH_INT_RX_RPTR_MASK 0x0000F00		/* Bits 8 through 11 alias of RX read-pointer - so, is Rx FIFO 16 or 32 entry?*/
188 
189 						/* Bits 13 through 15 are always 0. */
190 
191 #define METH_INT_TX_RPTR_MASK	0x1FF0000        /* Bits 16 through 24 alias of TX read-pointer */
192 
193 #define METH_INT_RX_SEQ_MASK	0x2E000000	/* Bits 25 through 29 are the starting seq number for the message at the */
194 
195 						/* top of the queue */
196 
197 #define METH_INT_ERROR	(METH_INT_TX_LINK_FAIL| \
198 			METH_INT_MEM_ERROR| \
199 			METH_INT_TX_ABORT| \
200 			METH_INT_RX_OVERFLOW| \
201 			METH_INT_RX_UNDERFLOW)
202 
203 #define METH_INT_MCAST_HASH		BIT(30) /* If RX DMA is enabled the hash select logic output is latched here */
204 
205 /* TX status bits */
206 #define METH_TX_ST_DONE      BIT(63) /* TX complete */
207 #define METH_TX_ST_SUCCESS   BIT(23) /* Packet was transmitted successfully */
208 #define METH_TX_ST_TOOLONG   BIT(24) /* TX abort due to excessive length */
209 #define METH_TX_ST_UNDERRUN  BIT(25) /* TX abort due to underrun (?) */
210 #define METH_TX_ST_EXCCOLL   BIT(26) /* TX abort due to excess collisions */
211 #define METH_TX_ST_DEFER     BIT(27) /* TX abort due to excess deferals */
212 #define METH_TX_ST_LATECOLL  BIT(28) /* TX abort due to late collision */
213 
214 
215 /* Tx command header bits */
216 #define METH_TX_CMD_INT_EN BIT(24) /* Generate TX interrupt when packet is sent */
217 
218 /* Phy MDIO interface busy flag */
219 #define MDIO_BUSY    BIT(16)
220 #define MDIO_DATA_MASK 0xFFFF
221 /* PHY defines */
222 #define PHY_QS6612X    0x0181441    /* Quality TX */
223 #define PHY_ICS1889    0x0015F41    /* ICS FX */
224 #define PHY_ICS1890    0x0015F42    /* ICS TX */
225 #define PHY_DP83840    0x20005C0    /* National TX */
226 
227 #define ADVANCE_RX_PTR(x)  x=(x+1)&(RX_RING_ENTRIES-1)
228