1 /*
2 * Copyright 2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
5 * Copyright 2007-2009 Stuart Bennett
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 */
26
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/drm_fourcc.h>
29
30 #include "nouveau_drv.h"
31 #include "nouveau_reg.h"
32 #include "nouveau_encoder.h"
33 #include "nouveau_connector.h"
34 #include "nouveau_crtc.h"
35 #include "hw.h"
36 #include "nvreg.h"
37
38 #include <drm/i2c/sil164.h>
39
40 #include <subdev/i2c.h>
41
42 #define FP_TG_CONTROL_ON (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | \
43 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS | \
44 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS)
45 #define FP_TG_CONTROL_OFF (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE | \
46 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE | \
47 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE)
48
is_fpc_off(uint32_t fpc)49 static inline bool is_fpc_off(uint32_t fpc)
50 {
51 return ((fpc & (FP_TG_CONTROL_ON | FP_TG_CONTROL_OFF)) ==
52 FP_TG_CONTROL_OFF);
53 }
54
nv04_dfp_get_bound_head(struct drm_device * dev,struct dcb_output * dcbent)55 int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent)
56 {
57 /* special case of nv_read_tmds to find crtc associated with an output.
58 * this does not give a correct answer for off-chip dvi, but there's no
59 * use for such an answer anyway
60 */
61 int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2;
62
63 NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL,
64 NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | 0x4);
65 return ((NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA) & 0x8) >> 3) ^ ramdac;
66 }
67
nv04_dfp_bind_head(struct drm_device * dev,struct dcb_output * dcbent,int head,bool dl)68 void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent,
69 int head, bool dl)
70 {
71 /* The BIOS scripts don't do this for us, sadly
72 * Luckily we do know the values ;-)
73 *
74 * head < 0 indicates we wish to force a setting with the overrideval
75 * (for VT restore etc.)
76 */
77
78 int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2;
79 uint8_t tmds04 = 0x80;
80
81 if (head != ramdac)
82 tmds04 = 0x88;
83
84 if (dcbent->type == DCB_OUTPUT_LVDS)
85 tmds04 |= 0x01;
86
87 nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04);
88
89 if (dl) /* dual link */
90 nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08);
91 }
92
nv04_dfp_disable(struct drm_device * dev,int head)93 void nv04_dfp_disable(struct drm_device *dev, int head)
94 {
95 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
96
97 if (NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL) &
98 FP_TG_CONTROL_ON) {
99 /* digital remnants must be cleaned before new crtc
100 * values programmed. delay is time for the vga stuff
101 * to realise it's in control again
102 */
103 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
104 FP_TG_CONTROL_OFF);
105 msleep(50);
106 }
107 /* don't inadvertently turn it on when state written later */
108 crtcstate[head].fp_control = FP_TG_CONTROL_OFF;
109 crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] &=
110 ~NV_CIO_CRE_LCD_ROUTE_MASK;
111 }
112
nv04_dfp_update_fp_control(struct drm_encoder * encoder,int mode)113 void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode)
114 {
115 struct drm_device *dev = encoder->dev;
116 struct drm_crtc *crtc;
117 struct nouveau_crtc *nv_crtc;
118 uint32_t *fpc;
119
120 if (mode == DRM_MODE_DPMS_ON) {
121 nv_crtc = nouveau_crtc(encoder->crtc);
122 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
123
124 if (is_fpc_off(*fpc)) {
125 /* using saved value is ok, as (is_digital && dpms_on &&
126 * fp_control==OFF) is (at present) *only* true when
127 * fpc's most recent change was by below "off" code
128 */
129 *fpc = nv_crtc->dpms_saved_fp_control;
130 }
131
132 nv_crtc->fp_users |= 1 << nouveau_encoder(encoder)->dcb->index;
133 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_FP_TG_CONTROL, *fpc);
134 } else {
135 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
136 nv_crtc = nouveau_crtc(crtc);
137 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
138
139 nv_crtc->fp_users &= ~(1 << nouveau_encoder(encoder)->dcb->index);
140 if (!is_fpc_off(*fpc) && !nv_crtc->fp_users) {
141 nv_crtc->dpms_saved_fp_control = *fpc;
142 /* cut the FP output */
143 *fpc &= ~FP_TG_CONTROL_ON;
144 *fpc |= FP_TG_CONTROL_OFF;
145 NVWriteRAMDAC(dev, nv_crtc->index,
146 NV_PRAMDAC_FP_TG_CONTROL, *fpc);
147 }
148 }
149 }
150 }
151
get_tmds_slave(struct drm_encoder * encoder)152 static struct drm_encoder *get_tmds_slave(struct drm_encoder *encoder)
153 {
154 struct drm_device *dev = encoder->dev;
155 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
156 struct drm_encoder *slave;
157
158 if (dcb->type != DCB_OUTPUT_TMDS || dcb->location == DCB_LOC_ON_CHIP)
159 return NULL;
160
161 /* Some BIOSes (e.g. the one in a Quadro FX1000) report several
162 * TMDS transmitters at the same I2C address, in the same I2C
163 * bus. This can still work because in that case one of them is
164 * always hard-wired to a reasonable configuration using straps,
165 * and the other one needs to be programmed.
166 *
167 * I don't think there's a way to know which is which, even the
168 * blob programs the one exposed via I2C for *both* heads, so
169 * let's do the same.
170 */
171 list_for_each_entry(slave, &dev->mode_config.encoder_list, head) {
172 struct dcb_output *slave_dcb = nouveau_encoder(slave)->dcb;
173
174 if (slave_dcb->type == DCB_OUTPUT_TMDS && get_slave_funcs(slave) &&
175 slave_dcb->tmdsconf.slave_addr == dcb->tmdsconf.slave_addr)
176 return slave;
177 }
178
179 return NULL;
180 }
181
nv04_dfp_mode_fixup(struct drm_encoder * encoder,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)182 static bool nv04_dfp_mode_fixup(struct drm_encoder *encoder,
183 const struct drm_display_mode *mode,
184 struct drm_display_mode *adjusted_mode)
185 {
186 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
187 struct nouveau_connector *nv_connector =
188 nv04_encoder_get_connector(nv_encoder);
189
190 if (!nv_connector->native_mode ||
191 nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
192 mode->hdisplay > nv_connector->native_mode->hdisplay ||
193 mode->vdisplay > nv_connector->native_mode->vdisplay) {
194 nv_encoder->mode = *adjusted_mode;
195
196 } else {
197 nv_encoder->mode = *nv_connector->native_mode;
198 adjusted_mode->clock = nv_connector->native_mode->clock;
199 }
200
201 return true;
202 }
203
nv04_dfp_prepare_sel_clk(struct drm_device * dev,struct nouveau_encoder * nv_encoder,int head)204 static void nv04_dfp_prepare_sel_clk(struct drm_device *dev,
205 struct nouveau_encoder *nv_encoder, int head)
206 {
207 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
208 uint32_t bits1618 = nv_encoder->dcb->or & DCB_OUTPUT_A ? 0x10000 : 0x40000;
209
210 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP)
211 return;
212
213 /* SEL_CLK is only used on the primary ramdac
214 * It toggles spread spectrum PLL output and sets the bindings of PLLs
215 * to heads on digital outputs
216 */
217 if (head)
218 state->sel_clk |= bits1618;
219 else
220 state->sel_clk &= ~bits1618;
221
222 /* nv30:
223 * bit 0 NVClk spread spectrum on/off
224 * bit 2 MemClk spread spectrum on/off
225 * bit 4 PixClk1 spread spectrum on/off toggle
226 * bit 6 PixClk2 spread spectrum on/off toggle
227 *
228 * nv40 (observations from bios behaviour and mmio traces):
229 * bits 4&6 as for nv30
230 * bits 5&7 head dependent as for bits 4&6, but do not appear with 4&6;
231 * maybe a different spread mode
232 * bits 8&10 seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
233 * The logic behind turning spread spectrum on/off in the first place,
234 * and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
235 * entry has the necessary info)
236 */
237 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && nv04_display(dev)->saved_reg.sel_clk & 0xf0) {
238 int shift = (nv04_display(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1;
239
240 state->sel_clk &= ~0xf0;
241 state->sel_clk |= (head ? 0x40 : 0x10) << shift;
242 }
243 }
244
nv04_dfp_prepare(struct drm_encoder * encoder)245 static void nv04_dfp_prepare(struct drm_encoder *encoder)
246 {
247 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
248 const struct drm_encoder_helper_funcs *helper = encoder->helper_private;
249 struct drm_device *dev = encoder->dev;
250 int head = nouveau_crtc(encoder->crtc)->index;
251 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
252 uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX];
253 uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX];
254
255 helper->dpms(encoder, DRM_MODE_DPMS_OFF);
256
257 nv04_dfp_prepare_sel_clk(dev, nv_encoder, head);
258
259 *cr_lcd = (*cr_lcd & ~NV_CIO_CRE_LCD_ROUTE_MASK) | 0x3;
260
261 if (nv_two_heads(dev)) {
262 if (nv_encoder->dcb->location == DCB_LOC_ON_CHIP)
263 *cr_lcd |= head ? 0x0 : 0x8;
264 else {
265 *cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30;
266 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS)
267 *cr_lcd |= 0x30;
268 if ((*cr_lcd & 0x30) == (*cr_lcd_oth & 0x30)) {
269 /* avoid being connected to both crtcs */
270 *cr_lcd_oth &= ~0x30;
271 NVWriteVgaCrtc(dev, head ^ 1,
272 NV_CIO_CRE_LCD__INDEX,
273 *cr_lcd_oth);
274 }
275 }
276 }
277 }
278
279
nv04_dfp_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)280 static void nv04_dfp_mode_set(struct drm_encoder *encoder,
281 struct drm_display_mode *mode,
282 struct drm_display_mode *adjusted_mode)
283 {
284 struct drm_device *dev = encoder->dev;
285 struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
286 struct nouveau_drm *drm = nouveau_drm(dev);
287 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
288 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
289 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
290 struct nouveau_connector *nv_connector = nouveau_crtc_connector_get(nv_crtc);
291 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
292 struct drm_display_mode *output_mode = &nv_encoder->mode;
293 struct drm_connector *connector = &nv_connector->base;
294 const struct drm_framebuffer *fb = encoder->crtc->primary->fb;
295 uint32_t mode_ratio, panel_ratio;
296
297 NV_DEBUG(drm, "Output mode on CRTC %d:\n", nv_crtc->index);
298 drm_mode_debug_printmodeline(output_mode);
299
300 /* Initialize the FP registers in this CRTC. */
301 regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
302 regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
303 if (!nv_gf4_disp_arch(dev) ||
304 (output_mode->hsync_start - output_mode->hdisplay) >=
305 drm->vbios.digital_min_front_porch)
306 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay;
307 else
308 regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - drm->vbios.digital_min_front_porch - 1;
309 regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1;
310 regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
311 regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew;
312 regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1;
313
314 regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
315 regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
316 regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1;
317 regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1;
318 regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
319 regp->fp_vert_regs[FP_VALID_START] = 0;
320 regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1;
321
322 /* bit26: a bit seen on some g7x, no as yet discernable purpose */
323 regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
324 (savep->fp_control & (1 << 26 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG));
325 /* Deal with vsync/hsync polarity */
326 /* LVDS screens do set this, but modes with +ve syncs are very rare */
327 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
328 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
329 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
330 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
331 /* panel scaling first, as native would get set otherwise */
332 if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
333 nv_connector->scaling_mode == DRM_MODE_SCALE_CENTER) /* panel handles it */
334 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER;
335 else if (adjusted_mode->hdisplay == output_mode->hdisplay &&
336 adjusted_mode->vdisplay == output_mode->vdisplay) /* native mode */
337 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE;
338 else /* gpu needs to scale */
339 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE;
340 if (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
341 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
342 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP &&
343 output_mode->clock > 165000)
344 regp->fp_control |= (2 << 24);
345 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) {
346 bool duallink = false, dummy;
347 if (nv_connector->edid &&
348 nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
349 duallink = (((u8 *)nv_connector->edid)[121] == 2);
350 } else {
351 nouveau_bios_parse_lvds_table(dev, output_mode->clock,
352 &duallink, &dummy);
353 }
354
355 if (duallink)
356 regp->fp_control |= (8 << 28);
357 } else
358 if (output_mode->clock > 165000)
359 regp->fp_control |= (8 << 28);
360
361 regp->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
362 NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
363 NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
364 NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
365 NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
366 NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
367 NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
368
369 /* We want automatic scaling */
370 regp->fp_debug_1 = 0;
371 /* This can override HTOTAL and VTOTAL */
372 regp->fp_debug_2 = 0;
373
374 /* Use 20.12 fixed point format to avoid floats */
375 mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay;
376 panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay;
377 /* if ratios are equal, SCALE_ASPECT will automatically (and correctly)
378 * get treated the same as SCALE_FULLSCREEN */
379 if (nv_connector->scaling_mode == DRM_MODE_SCALE_ASPECT &&
380 mode_ratio != panel_ratio) {
381 uint32_t diff, scale;
382 bool divide_by_2 = nv_gf4_disp_arch(dev);
383
384 if (mode_ratio < panel_ratio) {
385 /* vertical needs to expand to glass size (automatic)
386 * horizontal needs to be scaled at vertical scale factor
387 * to maintain aspect */
388
389 scale = (1 << 12) * adjusted_mode->vdisplay / output_mode->vdisplay;
390 regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE |
391 XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE);
392
393 /* restrict area of screen used, horizontally */
394 diff = output_mode->hdisplay -
395 output_mode->vdisplay * mode_ratio / (1 << 12);
396 regp->fp_horiz_regs[FP_VALID_START] += diff / 2;
397 regp->fp_horiz_regs[FP_VALID_END] -= diff / 2;
398 }
399
400 if (mode_ratio > panel_ratio) {
401 /* horizontal needs to expand to glass size (automatic)
402 * vertical needs to be scaled at horizontal scale factor
403 * to maintain aspect */
404
405 scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay;
406 regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE |
407 XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE);
408
409 /* restrict area of screen used, vertically */
410 diff = output_mode->vdisplay -
411 (1 << 12) * output_mode->hdisplay / mode_ratio;
412 regp->fp_vert_regs[FP_VALID_START] += diff / 2;
413 regp->fp_vert_regs[FP_VALID_END] -= diff / 2;
414 }
415 }
416
417 /* Output property. */
418 if ((nv_connector->dithering_mode == DITHERING_MODE_ON) ||
419 (nv_connector->dithering_mode == DITHERING_MODE_AUTO &&
420 fb->format->depth > connector->display_info.bpc * 3)) {
421 if (drm->client.device.info.chipset == 0x11)
422 regp->dither = savep->dither | 0x00010000;
423 else {
424 int i;
425 regp->dither = savep->dither | 0x00000001;
426 for (i = 0; i < 3; i++) {
427 regp->dither_regs[i] = 0xe4e4e4e4;
428 regp->dither_regs[i + 3] = 0x44444444;
429 }
430 }
431 } else {
432 if (drm->client.device.info.chipset != 0x11) {
433 /* reset them */
434 int i;
435 for (i = 0; i < 3; i++) {
436 regp->dither_regs[i] = savep->dither_regs[i];
437 regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
438 }
439 }
440 regp->dither = savep->dither;
441 }
442
443 regp->fp_margin_color = 0;
444 }
445
nv04_dfp_commit(struct drm_encoder * encoder)446 static void nv04_dfp_commit(struct drm_encoder *encoder)
447 {
448 struct drm_device *dev = encoder->dev;
449 struct nouveau_drm *drm = nouveau_drm(dev);
450 const struct drm_encoder_helper_funcs *helper = encoder->helper_private;
451 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
452 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
453 struct dcb_output *dcbe = nv_encoder->dcb;
454 int head = nouveau_crtc(encoder->crtc)->index;
455 struct drm_encoder *slave_encoder;
456
457 if (dcbe->type == DCB_OUTPUT_TMDS)
458 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock);
459 else if (dcbe->type == DCB_OUTPUT_LVDS)
460 call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock);
461
462 /* update fp_control state for any changes made by scripts,
463 * so correct value is written at DPMS on */
464 nv04_display(dev)->mode_reg.crtc_reg[head].fp_control =
465 NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
466
467 /* This could use refinement for flatpanels, but it should work this way */
468 if (drm->client.device.info.chipset < 0x44)
469 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
470 else
471 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
472
473 /* Init external transmitters */
474 slave_encoder = get_tmds_slave(encoder);
475 if (slave_encoder)
476 get_slave_funcs(slave_encoder)->mode_set(
477 slave_encoder, &nv_encoder->mode, &nv_encoder->mode);
478
479 helper->dpms(encoder, DRM_MODE_DPMS_ON);
480
481 NV_DEBUG(drm, "Output %s is running on CRTC %d using output %c\n",
482 nv04_encoder_get_connector(nv_encoder)->base.name,
483 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
484 }
485
nv04_dfp_update_backlight(struct drm_encoder * encoder,int mode)486 static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
487 {
488 #ifdef __powerpc__
489 struct drm_device *dev = encoder->dev;
490 struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
491 struct pci_dev *pdev = to_pci_dev(dev->dev);
492
493 /* BIOS scripts usually take care of the backlight, thanks
494 * Apple for your consistency.
495 */
496 if (pdev->device == 0x0174 || pdev->device == 0x0179 ||
497 pdev->device == 0x0189 || pdev->device == 0x0329) {
498 if (mode == DRM_MODE_DPMS_ON) {
499 nvif_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 1 << 31);
500 nvif_mask(device, NV_PCRTC_GPIO_EXT, 3, 1);
501 } else {
502 nvif_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0);
503 nvif_mask(device, NV_PCRTC_GPIO_EXT, 3, 0);
504 }
505 }
506 #endif
507 }
508
is_powersaving_dpms(int mode)509 static inline bool is_powersaving_dpms(int mode)
510 {
511 return mode != DRM_MODE_DPMS_ON && mode != NV_DPMS_CLEARED;
512 }
513
nv04_lvds_dpms(struct drm_encoder * encoder,int mode)514 static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
515 {
516 struct drm_device *dev = encoder->dev;
517 struct drm_crtc *crtc = encoder->crtc;
518 struct nouveau_drm *drm = nouveau_drm(dev);
519 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
520 bool was_powersaving = is_powersaving_dpms(nv_encoder->last_dpms);
521
522 if (nv_encoder->last_dpms == mode)
523 return;
524 nv_encoder->last_dpms = mode;
525
526 NV_DEBUG(drm, "Setting dpms mode %d on lvds encoder (output %d)\n",
527 mode, nv_encoder->dcb->index);
528
529 if (was_powersaving && is_powersaving_dpms(mode))
530 return;
531
532 if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
533 /* when removing an output, crtc may not be set, but PANEL_OFF
534 * must still be run
535 */
536 int head = crtc ? nouveau_crtc(crtc)->index :
537 nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
538
539 if (mode == DRM_MODE_DPMS_ON) {
540 call_lvds_script(dev, nv_encoder->dcb, head,
541 LVDS_PANEL_ON, nv_encoder->mode.clock);
542 } else
543 /* pxclk of 0 is fine for PANEL_OFF, and for a
544 * disconnected LVDS encoder there is no native_mode
545 */
546 call_lvds_script(dev, nv_encoder->dcb, head,
547 LVDS_PANEL_OFF, 0);
548 }
549
550 nv04_dfp_update_backlight(encoder, mode);
551 nv04_dfp_update_fp_control(encoder, mode);
552
553 if (mode == DRM_MODE_DPMS_ON)
554 nv04_dfp_prepare_sel_clk(dev, nv_encoder, nouveau_crtc(crtc)->index);
555 else {
556 nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
557 nv04_display(dev)->mode_reg.sel_clk &= ~0xf0;
558 }
559 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
560 }
561
nv04_tmds_dpms(struct drm_encoder * encoder,int mode)562 static void nv04_tmds_dpms(struct drm_encoder *encoder, int mode)
563 {
564 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
565 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
566
567 if (nv_encoder->last_dpms == mode)
568 return;
569 nv_encoder->last_dpms = mode;
570
571 NV_DEBUG(drm, "Setting dpms mode %d on tmds encoder (output %d)\n",
572 mode, nv_encoder->dcb->index);
573
574 nv04_dfp_update_backlight(encoder, mode);
575 nv04_dfp_update_fp_control(encoder, mode);
576 }
577
nv04_dfp_save(struct drm_encoder * encoder)578 static void nv04_dfp_save(struct drm_encoder *encoder)
579 {
580 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
581 struct drm_device *dev = encoder->dev;
582
583 if (nv_two_heads(dev))
584 nv_encoder->restore.head =
585 nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
586 }
587
nv04_dfp_restore(struct drm_encoder * encoder)588 static void nv04_dfp_restore(struct drm_encoder *encoder)
589 {
590 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
591 struct drm_device *dev = encoder->dev;
592 int head = nv_encoder->restore.head;
593
594 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) {
595 struct nouveau_connector *connector =
596 nv04_encoder_get_connector(nv_encoder);
597
598 if (connector && connector->native_mode)
599 call_lvds_script(dev, nv_encoder->dcb, head,
600 LVDS_PANEL_ON,
601 connector->native_mode->clock);
602
603 } else if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) {
604 int clock = nouveau_hw_pllvals_to_clk
605 (&nv04_display(dev)->saved_reg.crtc_reg[head].pllvals);
606
607 run_tmds_table(dev, nv_encoder->dcb, head, clock);
608 }
609
610 nv_encoder->last_dpms = NV_DPMS_CLEARED;
611 }
612
nv04_dfp_destroy(struct drm_encoder * encoder)613 static void nv04_dfp_destroy(struct drm_encoder *encoder)
614 {
615 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
616
617 if (get_slave_funcs(encoder))
618 get_slave_funcs(encoder)->destroy(encoder);
619
620 drm_encoder_cleanup(encoder);
621 kfree(nv_encoder);
622 }
623
nv04_tmds_slave_init(struct drm_encoder * encoder)624 static void nv04_tmds_slave_init(struct drm_encoder *encoder)
625 {
626 struct drm_device *dev = encoder->dev;
627 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
628 struct nouveau_drm *drm = nouveau_drm(dev);
629 struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
630 struct nvkm_i2c_bus *bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_PRI);
631 struct nvkm_i2c_bus_probe info[] = {
632 {
633 {
634 .type = "sil164",
635 .addr = (dcb->tmdsconf.slave_addr == 0x7 ? 0x3a : 0x38),
636 .platform_data = &(struct sil164_encoder_params) {
637 SIL164_INPUT_EDGE_RISING
638 }
639 }, 0
640 },
641 { }
642 };
643 int type;
644
645 if (!nv_gf4_disp_arch(dev) || !bus || get_tmds_slave(encoder))
646 return;
647
648 type = nvkm_i2c_bus_probe(bus, "TMDS transmitter", info, NULL, NULL);
649 if (type < 0)
650 return;
651
652 drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
653 &bus->i2c, &info[type].dev);
654 }
655
656 static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = {
657 .dpms = nv04_lvds_dpms,
658 .mode_fixup = nv04_dfp_mode_fixup,
659 .prepare = nv04_dfp_prepare,
660 .commit = nv04_dfp_commit,
661 .mode_set = nv04_dfp_mode_set,
662 .detect = NULL,
663 };
664
665 static const struct drm_encoder_helper_funcs nv04_tmds_helper_funcs = {
666 .dpms = nv04_tmds_dpms,
667 .mode_fixup = nv04_dfp_mode_fixup,
668 .prepare = nv04_dfp_prepare,
669 .commit = nv04_dfp_commit,
670 .mode_set = nv04_dfp_mode_set,
671 .detect = NULL,
672 };
673
674 static const struct drm_encoder_funcs nv04_dfp_funcs = {
675 .destroy = nv04_dfp_destroy,
676 };
677
678 int
nv04_dfp_create(struct drm_connector * connector,struct dcb_output * entry)679 nv04_dfp_create(struct drm_connector *connector, struct dcb_output *entry)
680 {
681 const struct drm_encoder_helper_funcs *helper;
682 struct nouveau_encoder *nv_encoder = NULL;
683 struct drm_encoder *encoder;
684 int type;
685
686 switch (entry->type) {
687 case DCB_OUTPUT_TMDS:
688 type = DRM_MODE_ENCODER_TMDS;
689 helper = &nv04_tmds_helper_funcs;
690 break;
691 case DCB_OUTPUT_LVDS:
692 type = DRM_MODE_ENCODER_LVDS;
693 helper = &nv04_lvds_helper_funcs;
694 break;
695 default:
696 return -EINVAL;
697 }
698
699 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
700 if (!nv_encoder)
701 return -ENOMEM;
702
703 nv_encoder->enc_save = nv04_dfp_save;
704 nv_encoder->enc_restore = nv04_dfp_restore;
705
706 encoder = to_drm_encoder(nv_encoder);
707
708 nv_encoder->dcb = entry;
709 nv_encoder->or = ffs(entry->or) - 1;
710
711 drm_encoder_init(connector->dev, encoder, &nv04_dfp_funcs, type, NULL);
712 drm_encoder_helper_add(encoder, helper);
713
714 encoder->possible_crtcs = entry->heads;
715 encoder->possible_clones = 0;
716
717 if (entry->type == DCB_OUTPUT_TMDS &&
718 entry->location != DCB_LOC_ON_CHIP)
719 nv04_tmds_slave_init(encoder);
720
721 drm_connector_attach_encoder(connector, encoder);
722 return 0;
723 }
724