1 /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef _I915_REG_H_ 26 #define _I915_REG_H_ 27 28 #include "i915_reg_defs.h" 29 30 /** 31 * DOC: The i915 register macro definition style guide 32 * 33 * Follow the style described here for new macros, and while changing existing 34 * macros. Do **not** mass change existing definitions just to update the style. 35 * 36 * File Layout 37 * ~~~~~~~~~~~ 38 * 39 * Keep helper macros near the top. For example, _PIPE() and friends. 40 * 41 * Prefix macros that generally should not be used outside of this file with 42 * underscore '_'. For example, _PIPE() and friends, single instances of 43 * registers that are defined solely for the use by function-like macros. 44 * 45 * Avoid using the underscore prefixed macros outside of this file. There are 46 * exceptions, but keep them to a minimum. 47 * 48 * There are two basic types of register definitions: Single registers and 49 * register groups. Register groups are registers which have two or more 50 * instances, for example one per pipe, port, transcoder, etc. Register groups 51 * should be defined using function-like macros. 52 * 53 * For single registers, define the register offset first, followed by register 54 * contents. 55 * 56 * For register groups, define the register instance offsets first, prefixed 57 * with underscore, followed by a function-like macro choosing the right 58 * instance based on the parameter, followed by register contents. 59 * 60 * Define the register contents (i.e. bit and bit field macros) from most 61 * significant to least significant bit. Indent the register content macros 62 * using two extra spaces between ``#define`` and the macro name. 63 * 64 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents 65 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already 66 * shifted in place, so they can be directly OR'd together. For convenience, 67 * function-like macros may be used to define bit fields, but do note that the 68 * macros may be needed to read as well as write the register contents. 69 * 70 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name. 71 * 72 * Group the register and its contents together without blank lines, separate 73 * from other registers and their contents with one blank line. 74 * 75 * Indent macro values from macro names using TABs. Align values vertically. Use 76 * braces in macro values as needed to avoid unintended precedence after macro 77 * substitution. Use spaces in macro values according to kernel coding 78 * style. Use lower case in hexadecimal values. 79 * 80 * Naming 81 * ~~~~~~ 82 * 83 * Try to name registers according to the specs. If the register name changes in 84 * the specs from platform to another, stick to the original name. 85 * 86 * Try to re-use existing register macro definitions. Only add new macros for 87 * new register offsets, or when the register contents have changed enough to 88 * warrant a full redefinition. 89 * 90 * When a register macro changes for a new platform, prefix the new macro using 91 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The 92 * prefix signifies the start platform/generation using the register. 93 * 94 * When a bit (field) macro changes or gets added for a new platform, while 95 * retaining the existing register macro, add a platform acronym or generation 96 * suffix to the name. For example, ``_SKL`` or ``_GEN8``. 97 * 98 * Examples 99 * ~~~~~~~~ 100 * 101 * (Note that the values in the example are indented using spaces instead of 102 * TABs to avoid misalignment in generated documentation. Use TABs in the 103 * definitions.):: 104 * 105 * #define _FOO_A 0xf000 106 * #define _FOO_B 0xf001 107 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B) 108 * #define FOO_ENABLE REG_BIT(31) 109 * #define FOO_MODE_MASK REG_GENMASK(19, 16) 110 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0) 111 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1) 112 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2) 113 * 114 * #define BAR _MMIO(0xb000) 115 * #define GEN8_BAR _MMIO(0xb888) 116 */ 117 118 #define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset) 119 120 /* 121 * Given the first two numbers __a and __b of arbitrarily many evenly spaced 122 * numbers, pick the 0-based __index'th value. 123 * 124 * Always prefer this over _PICK() if the numbers are evenly spaced. 125 */ 126 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a))) 127 128 /* 129 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number. 130 * 131 * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced. 132 */ 133 #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) 134 135 /* 136 * Named helper wrappers around _PICK_EVEN() and _PICK(). 137 */ 138 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) 139 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) 140 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) 141 #define _PORT(port, a, b) _PICK_EVEN(port, a, b) 142 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) 143 #define _PHY(phy, a, b) _PICK_EVEN(phy, a, b) 144 145 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) 146 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) 147 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) 148 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) 149 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) 150 #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b)) 151 152 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) 153 154 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 155 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) 156 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) 157 #define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__)) 158 159 160 /* 161 * Device info offset array based helpers for groups of registers with unevenly 162 * spaced base offsets. 163 */ 164 #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \ 165 INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \ 166 DISPLAY_MMIO_BASE(dev_priv)) 167 #define _TRANS2(tran, reg) (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \ 168 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \ 169 DISPLAY_MMIO_BASE(dev_priv)) 170 #define _MMIO_TRANS2(tran, reg) _MMIO(_TRANS2(tran, reg)) 171 #define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \ 172 INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \ 173 DISPLAY_MMIO_BASE(dev_priv)) 174 175 #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) 176 #define _MASKED_FIELD(mask, value) ({ \ 177 if (__builtin_constant_p(mask)) \ 178 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \ 179 if (__builtin_constant_p(value)) \ 180 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \ 181 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \ 182 BUILD_BUG_ON_MSG((value) & ~(mask), \ 183 "Incorrect value for mask"); \ 184 __MASKED_FIELD(mask, value); }) 185 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) 186 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) 187 188 #define GU_CNTL _MMIO(0x101010) 189 #define LMEM_INIT REG_BIT(7) 190 191 #define GEN6_STOLEN_RESERVED _MMIO(0x1082C0) 192 #define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20) 193 #define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18) 194 #define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4) 195 #define GEN6_STOLEN_RESERVED_1M (0 << 4) 196 #define GEN6_STOLEN_RESERVED_512K (1 << 4) 197 #define GEN6_STOLEN_RESERVED_256K (2 << 4) 198 #define GEN6_STOLEN_RESERVED_128K (3 << 4) 199 #define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5) 200 #define GEN7_STOLEN_RESERVED_1M (0 << 5) 201 #define GEN7_STOLEN_RESERVED_256K (1 << 5) 202 #define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7) 203 #define GEN8_STOLEN_RESERVED_1M (0 << 7) 204 #define GEN8_STOLEN_RESERVED_2M (1 << 7) 205 #define GEN8_STOLEN_RESERVED_4M (2 << 7) 206 #define GEN8_STOLEN_RESERVED_8M (3 << 7) 207 #define GEN6_STOLEN_RESERVED_ENABLE (1 << 0) 208 #define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20) 209 210 #define _VGA_MSR_WRITE _MMIO(0x3c2) 211 212 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 213 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 214 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) 215 216 /* 217 * Reset registers 218 */ 219 #define DEBUG_RESET_I830 _MMIO(0x6070) 220 #define DEBUG_RESET_FULL (1 << 7) 221 #define DEBUG_RESET_RENDER (1 << 8) 222 #define DEBUG_RESET_DISPLAY (1 << 9) 223 224 /* 225 * IOSF sideband 226 */ 227 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100) 228 #define IOSF_DEVFN_SHIFT 24 229 #define IOSF_OPCODE_SHIFT 16 230 #define IOSF_PORT_SHIFT 8 231 #define IOSF_BYTE_ENABLES_SHIFT 4 232 #define IOSF_BAR_SHIFT 1 233 #define IOSF_SB_BUSY (1 << 0) 234 #define IOSF_PORT_BUNIT 0x03 235 #define IOSF_PORT_PUNIT 0x04 236 #define IOSF_PORT_NC 0x11 237 #define IOSF_PORT_DPIO 0x12 238 #define IOSF_PORT_GPIO_NC 0x13 239 #define IOSF_PORT_CCK 0x14 240 #define IOSF_PORT_DPIO_2 0x1a 241 #define IOSF_PORT_FLISDSI 0x1b 242 #define IOSF_PORT_GPIO_SC 0x48 243 #define IOSF_PORT_GPIO_SUS 0xa8 244 #define IOSF_PORT_CCU 0xa9 245 #define CHV_IOSF_PORT_GPIO_N 0x13 246 #define CHV_IOSF_PORT_GPIO_SE 0x48 247 #define CHV_IOSF_PORT_GPIO_E 0xa8 248 #define CHV_IOSF_PORT_GPIO_SW 0xb2 249 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104) 250 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108) 251 252 /* DPIO registers */ 253 #define DPIO_DEVFN 0 254 255 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110) 256 #define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */ 257 #define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */ 258 #define DPIO_SFR_BYPASS (1 << 1) 259 #define DPIO_CMNRST (1 << 0) 260 261 #define DPIO_PHY(pipe) ((pipe) >> 1) 262 263 /* 264 * Per pipe/PLL DPIO regs 265 */ 266 #define _VLV_PLL_DW3_CH0 0x800c 267 #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 268 #define DPIO_POST_DIV_DAC 0 269 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 270 #define DPIO_POST_DIV_LVDS1 2 271 #define DPIO_POST_DIV_LVDS2 3 272 #define DPIO_K_SHIFT (24) /* 4 bits */ 273 #define DPIO_P1_SHIFT (21) /* 3 bits */ 274 #define DPIO_P2_SHIFT (16) /* 5 bits */ 275 #define DPIO_N_SHIFT (12) /* 4 bits */ 276 #define DPIO_ENABLE_CALIBRATION (1 << 11) 277 #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 278 #define DPIO_M2DIV_MASK 0xff 279 #define _VLV_PLL_DW3_CH1 0x802c 280 #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 281 282 #define _VLV_PLL_DW5_CH0 0x8014 283 #define DPIO_REFSEL_OVERRIDE 27 284 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 285 #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 286 #define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 287 #define DPIO_PLL_REFCLK_SEL_MASK 3 288 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 289 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 290 #define _VLV_PLL_DW5_CH1 0x8034 291 #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 292 293 #define _VLV_PLL_DW7_CH0 0x801c 294 #define _VLV_PLL_DW7_CH1 0x803c 295 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 296 297 #define _VLV_PLL_DW8_CH0 0x8040 298 #define _VLV_PLL_DW8_CH1 0x8060 299 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 300 301 #define VLV_PLL_DW9_BCAST 0xc044 302 #define _VLV_PLL_DW9_CH0 0x8044 303 #define _VLV_PLL_DW9_CH1 0x8064 304 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 305 306 #define _VLV_PLL_DW10_CH0 0x8048 307 #define _VLV_PLL_DW10_CH1 0x8068 308 #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 309 310 #define _VLV_PLL_DW11_CH0 0x804c 311 #define _VLV_PLL_DW11_CH1 0x806c 312 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 313 314 /* Spec for ref block start counts at DW10 */ 315 #define VLV_REF_DW13 0x80ac 316 317 #define VLV_CMN_DW0 0x8100 318 319 /* 320 * Per DDI channel DPIO regs 321 */ 322 323 #define _VLV_PCS_DW0_CH0 0x8200 324 #define _VLV_PCS_DW0_CH1 0x8400 325 #define DPIO_PCS_TX_LANE2_RESET (1 << 16) 326 #define DPIO_PCS_TX_LANE1_RESET (1 << 7) 327 #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4) 328 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3) 329 #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 330 331 #define _VLV_PCS01_DW0_CH0 0x200 332 #define _VLV_PCS23_DW0_CH0 0x400 333 #define _VLV_PCS01_DW0_CH1 0x2600 334 #define _VLV_PCS23_DW0_CH1 0x2800 335 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 336 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 337 338 #define _VLV_PCS_DW1_CH0 0x8204 339 #define _VLV_PCS_DW1_CH1 0x8404 340 #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23) 341 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22) 342 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21) 343 #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 344 #define DPIO_PCS_CLK_SOFT_RESET (1 << 5) 345 #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 346 347 #define _VLV_PCS01_DW1_CH0 0x204 348 #define _VLV_PCS23_DW1_CH0 0x404 349 #define _VLV_PCS01_DW1_CH1 0x2604 350 #define _VLV_PCS23_DW1_CH1 0x2804 351 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 352 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 353 354 #define _VLV_PCS_DW8_CH0 0x8220 355 #define _VLV_PCS_DW8_CH1 0x8420 356 #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) 357 #define CHV_PCS_USEDCLKCHANNEL (1 << 21) 358 #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 359 360 #define _VLV_PCS01_DW8_CH0 0x0220 361 #define _VLV_PCS23_DW8_CH0 0x0420 362 #define _VLV_PCS01_DW8_CH1 0x2620 363 #define _VLV_PCS23_DW8_CH1 0x2820 364 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 365 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 366 367 #define _VLV_PCS_DW9_CH0 0x8224 368 #define _VLV_PCS_DW9_CH1 0x8424 369 #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13) 370 #define DPIO_PCS_TX2MARGIN_000 (0 << 13) 371 #define DPIO_PCS_TX2MARGIN_101 (1 << 13) 372 #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10) 373 #define DPIO_PCS_TX1MARGIN_000 (0 << 10) 374 #define DPIO_PCS_TX1MARGIN_101 (1 << 10) 375 #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 376 377 #define _VLV_PCS01_DW9_CH0 0x224 378 #define _VLV_PCS23_DW9_CH0 0x424 379 #define _VLV_PCS01_DW9_CH1 0x2624 380 #define _VLV_PCS23_DW9_CH1 0x2824 381 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) 382 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) 383 384 #define _CHV_PCS_DW10_CH0 0x8228 385 #define _CHV_PCS_DW10_CH1 0x8428 386 #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30) 387 #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31) 388 #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24) 389 #define DPIO_PCS_TX2DEEMP_9P5 (0 << 24) 390 #define DPIO_PCS_TX2DEEMP_6P0 (2 << 24) 391 #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16) 392 #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16) 393 #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16) 394 #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 395 396 #define _VLV_PCS01_DW10_CH0 0x0228 397 #define _VLV_PCS23_DW10_CH0 0x0428 398 #define _VLV_PCS01_DW10_CH1 0x2628 399 #define _VLV_PCS23_DW10_CH1 0x2828 400 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 401 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 402 403 #define _VLV_PCS_DW11_CH0 0x822c 404 #define _VLV_PCS_DW11_CH1 0x842c 405 #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24) 406 #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3) 407 #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1) 408 #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0) 409 #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 410 411 #define _VLV_PCS01_DW11_CH0 0x022c 412 #define _VLV_PCS23_DW11_CH0 0x042c 413 #define _VLV_PCS01_DW11_CH1 0x262c 414 #define _VLV_PCS23_DW11_CH1 0x282c 415 #define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) 416 #define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) 417 418 #define _VLV_PCS01_DW12_CH0 0x0230 419 #define _VLV_PCS23_DW12_CH0 0x0430 420 #define _VLV_PCS01_DW12_CH1 0x2630 421 #define _VLV_PCS23_DW12_CH1 0x2830 422 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) 423 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) 424 425 #define _VLV_PCS_DW12_CH0 0x8230 426 #define _VLV_PCS_DW12_CH1 0x8430 427 #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20) 428 #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16) 429 #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8) 430 #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6) 431 #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0) 432 #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 433 434 #define _VLV_PCS_DW14_CH0 0x8238 435 #define _VLV_PCS_DW14_CH1 0x8438 436 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 437 438 #define _VLV_PCS_DW23_CH0 0x825c 439 #define _VLV_PCS_DW23_CH1 0x845c 440 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 441 442 #define _VLV_TX_DW2_CH0 0x8288 443 #define _VLV_TX_DW2_CH1 0x8488 444 #define DPIO_SWING_MARGIN000_SHIFT 16 445 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) 446 #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 447 #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 448 449 #define _VLV_TX_DW3_CH0 0x828c 450 #define _VLV_TX_DW3_CH1 0x848c 451 /* The following bit for CHV phy */ 452 #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27) 453 #define DPIO_SWING_MARGIN101_SHIFT 16 454 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) 455 #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 456 457 #define _VLV_TX_DW4_CH0 0x8290 458 #define _VLV_TX_DW4_CH1 0x8490 459 #define DPIO_SWING_DEEMPH9P5_SHIFT 24 460 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 461 #define DPIO_SWING_DEEMPH6P0_SHIFT 16 462 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) 463 #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 464 465 #define _VLV_TX3_DW4_CH0 0x690 466 #define _VLV_TX3_DW4_CH1 0x2a90 467 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 468 469 #define _VLV_TX_DW5_CH0 0x8294 470 #define _VLV_TX_DW5_CH1 0x8494 471 #define DPIO_TX_OCALINIT_EN (1 << 31) 472 #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 473 474 #define _VLV_TX_DW11_CH0 0x82ac 475 #define _VLV_TX_DW11_CH1 0x84ac 476 #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 477 478 #define _VLV_TX_DW14_CH0 0x82b8 479 #define _VLV_TX_DW14_CH1 0x84b8 480 #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 481 482 /* CHV dpPhy registers */ 483 #define _CHV_PLL_DW0_CH0 0x8000 484 #define _CHV_PLL_DW0_CH1 0x8180 485 #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 486 487 #define _CHV_PLL_DW1_CH0 0x8004 488 #define _CHV_PLL_DW1_CH1 0x8184 489 #define DPIO_CHV_N_DIV_SHIFT 8 490 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 491 #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 492 493 #define _CHV_PLL_DW2_CH0 0x8008 494 #define _CHV_PLL_DW2_CH1 0x8188 495 #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 496 497 #define _CHV_PLL_DW3_CH0 0x800c 498 #define _CHV_PLL_DW3_CH1 0x818c 499 #define DPIO_CHV_FRAC_DIV_EN (1 << 16) 500 #define DPIO_CHV_FIRST_MOD (0 << 8) 501 #define DPIO_CHV_SECOND_MOD (1 << 8) 502 #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 503 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) 504 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 505 506 #define _CHV_PLL_DW6_CH0 0x8018 507 #define _CHV_PLL_DW6_CH1 0x8198 508 #define DPIO_CHV_GAIN_CTRL_SHIFT 16 509 #define DPIO_CHV_INT_COEFF_SHIFT 8 510 #define DPIO_CHV_PROP_COEFF_SHIFT 0 511 #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 512 513 #define _CHV_PLL_DW8_CH0 0x8020 514 #define _CHV_PLL_DW8_CH1 0x81A0 515 #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 516 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) 517 #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) 518 519 #define _CHV_PLL_DW9_CH0 0x8024 520 #define _CHV_PLL_DW9_CH1 0x81A4 521 #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ 522 #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) 523 #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ 524 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) 525 526 #define _CHV_CMN_DW0_CH0 0x8100 527 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 528 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 529 #define DPIO_ALLDL_POWERDOWN (1 << 1) 530 #define DPIO_ANYDL_POWERDOWN (1 << 0) 531 532 #define _CHV_CMN_DW5_CH0 0x8114 533 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) 534 #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) 535 #define CHV_BUFRIGHTENA1_FORCE (3 << 20) 536 #define CHV_BUFRIGHTENA1_MASK (3 << 20) 537 #define CHV_BUFLEFTENA1_DISABLE (0 << 22) 538 #define CHV_BUFLEFTENA1_NORMAL (1 << 22) 539 #define CHV_BUFLEFTENA1_FORCE (3 << 22) 540 #define CHV_BUFLEFTENA1_MASK (3 << 22) 541 542 #define _CHV_CMN_DW13_CH0 0x8134 543 #define _CHV_CMN_DW0_CH1 0x8080 544 #define DPIO_CHV_S1_DIV_SHIFT 21 545 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 546 #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 547 #define DPIO_CHV_K_DIV_SHIFT 4 548 #define DPIO_PLL_FREQLOCK (1 << 1) 549 #define DPIO_PLL_LOCK (1 << 0) 550 #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 551 552 #define _CHV_CMN_DW14_CH0 0x8138 553 #define _CHV_CMN_DW1_CH1 0x8084 554 #define DPIO_AFC_RECAL (1 << 14) 555 #define DPIO_DCLKP_EN (1 << 13) 556 #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ 557 #define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ 558 #define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ 559 #define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ 560 #define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ 561 #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ 562 #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ 563 #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ 564 #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 565 566 #define _CHV_CMN_DW19_CH0 0x814c 567 #define _CHV_CMN_DW6_CH1 0x8098 568 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ 569 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ 570 #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ 571 #define CHV_CMN_USEDCLKCHANNEL (1 << 13) 572 573 #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) 574 575 #define CHV_CMN_DW28 0x8170 576 #define DPIO_CL1POWERDOWNEN (1 << 23) 577 #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) 578 #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) 579 #define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) 580 #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) 581 #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) 582 583 #define CHV_CMN_DW30 0x8178 584 #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) 585 #define DPIO_LRC_BYPASS (1 << 3) 586 587 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 588 (lane) * 0x200 + (offset)) 589 590 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 591 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 592 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 593 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 594 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 595 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 596 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 597 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 598 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 599 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 600 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 601 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 602 #define DPIO_FRC_LATENCY_SHFIT 8 603 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 604 #define DPIO_UPAR_SHIFT 30 605 606 /* BXT PHY registers */ 607 #define _BXT_PHY0_BASE 0x6C000 608 #define _BXT_PHY1_BASE 0x162000 609 #define _BXT_PHY2_BASE 0x163000 610 #define BXT_PHY_BASE(phy) _PHY3((phy), _BXT_PHY0_BASE, \ 611 _BXT_PHY1_BASE, \ 612 _BXT_PHY2_BASE) 613 614 #define _BXT_PHY(phy, reg) \ 615 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg)) 616 617 #define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 618 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \ 619 (reg_ch1) - _BXT_PHY0_BASE)) 620 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \ 621 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)) 622 623 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) 624 #define MIPIO_RST_CTRL (1 << 2) 625 626 #define _BXT_PHY_CTL_DDI_A 0x64C00 627 #define _BXT_PHY_CTL_DDI_B 0x64C10 628 #define _BXT_PHY_CTL_DDI_C 0x64C20 629 #define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10) 630 #define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9) 631 #define BXT_PHY_LANE_ENABLED (1 << 8) 632 #define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \ 633 _BXT_PHY_CTL_DDI_B) 634 635 #define _PHY_CTL_FAMILY_EDP 0x64C80 636 #define _PHY_CTL_FAMILY_DDI 0x64C90 637 #define _PHY_CTL_FAMILY_DDI_C 0x64CA0 638 #define COMMON_RESET_DIS (1 << 31) 639 #define BXT_PHY_CTL_FAMILY(phy) _MMIO_PHY3((phy), _PHY_CTL_FAMILY_DDI, \ 640 _PHY_CTL_FAMILY_EDP, \ 641 _PHY_CTL_FAMILY_DDI_C) 642 643 /* BXT PHY PLL registers */ 644 #define _PORT_PLL_A 0x46074 645 #define _PORT_PLL_B 0x46078 646 #define _PORT_PLL_C 0x4607c 647 #define PORT_PLL_ENABLE REG_BIT(31) 648 #define PORT_PLL_LOCK REG_BIT(30) 649 #define PORT_PLL_REF_SEL REG_BIT(27) 650 #define PORT_PLL_POWER_ENABLE REG_BIT(26) 651 #define PORT_PLL_POWER_STATE REG_BIT(25) 652 #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) 653 654 #define _PORT_PLL_EBB_0_A 0x162034 655 #define _PORT_PLL_EBB_0_B 0x6C034 656 #define _PORT_PLL_EBB_0_C 0x6C340 657 #define PORT_PLL_P1_MASK REG_GENMASK(15, 13) 658 #define PORT_PLL_P1(p1) REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1)) 659 #define PORT_PLL_P2_MASK REG_GENMASK(12, 8) 660 #define PORT_PLL_P2(p2) REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2)) 661 #define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 662 _PORT_PLL_EBB_0_B, \ 663 _PORT_PLL_EBB_0_C) 664 665 #define _PORT_PLL_EBB_4_A 0x162038 666 #define _PORT_PLL_EBB_4_B 0x6C038 667 #define _PORT_PLL_EBB_4_C 0x6C344 668 #define PORT_PLL_RECALIBRATE REG_BIT(14) 669 #define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13) 670 #define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 671 _PORT_PLL_EBB_4_B, \ 672 _PORT_PLL_EBB_4_C) 673 674 #define _PORT_PLL_0_A 0x162100 675 #define _PORT_PLL_0_B 0x6C100 676 #define _PORT_PLL_0_C 0x6C380 677 /* PORT_PLL_0_A */ 678 #define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0) 679 #define PORT_PLL_M2_INT(m2_int) REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int)) 680 /* PORT_PLL_1_A */ 681 #define PORT_PLL_N_MASK REG_GENMASK(11, 8) 682 #define PORT_PLL_N(n) REG_FIELD_PREP(PORT_PLL_N_MASK, (n)) 683 /* PORT_PLL_2_A */ 684 #define PORT_PLL_M2_FRAC_MASK REG_GENMASK(21, 0) 685 #define PORT_PLL_M2_FRAC(m2_frac) REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac)) 686 /* PORT_PLL_3_A */ 687 #define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16) 688 /* PORT_PLL_6_A */ 689 #define PORT_PLL_GAIN_CTL_MASK REG_GENMASK(18, 16) 690 #define PORT_PLL_GAIN_CTL(x) REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x)) 691 #define PORT_PLL_INT_COEFF_MASK REG_GENMASK(12, 8) 692 #define PORT_PLL_INT_COEFF(x) REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x)) 693 #define PORT_PLL_PROP_COEFF_MASK REG_GENMASK(3, 0) 694 #define PORT_PLL_PROP_COEFF(x) REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x)) 695 /* PORT_PLL_8_A */ 696 #define PORT_PLL_TARGET_CNT_MASK REG_GENMASK(9, 0) 697 #define PORT_PLL_TARGET_CNT(x) REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x)) 698 /* PORT_PLL_9_A */ 699 #define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1) 700 #define PORT_PLL_LOCK_THRESHOLD(x) REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x)) 701 /* PORT_PLL_10_A */ 702 #define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27) 703 #define PORT_PLL_DCO_AMP_MASK REG_GENMASK(13, 10) 704 #define PORT_PLL_DCO_AMP(x) REG_FIELD_PREP(PORT_PLL_DCO_AMP_MASK, (x)) 705 #define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \ 706 _PORT_PLL_0_B, \ 707 _PORT_PLL_0_C) 708 #define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \ 709 (idx) * 4) 710 711 /* BXT PHY common lane registers */ 712 #define _PORT_CL1CM_DW0_A 0x162000 713 #define _PORT_CL1CM_DW0_BC 0x6C000 714 #define PHY_POWER_GOOD (1 << 16) 715 #define PHY_RESERVED (1 << 7) 716 #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC) 717 718 #define _PORT_CL1CM_DW9_A 0x162024 719 #define _PORT_CL1CM_DW9_BC 0x6C024 720 #define IREF0RC_OFFSET_SHIFT 8 721 #define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT) 722 #define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC) 723 724 #define _PORT_CL1CM_DW10_A 0x162028 725 #define _PORT_CL1CM_DW10_BC 0x6C028 726 #define IREF1RC_OFFSET_SHIFT 8 727 #define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT) 728 #define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC) 729 730 #define _PORT_CL1CM_DW28_A 0x162070 731 #define _PORT_CL1CM_DW28_BC 0x6C070 732 #define OCL1_POWER_DOWN_EN (1 << 23) 733 #define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22) 734 #define SUS_CLK_CONFIG 0x3 735 #define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC) 736 737 #define _PORT_CL1CM_DW30_A 0x162078 738 #define _PORT_CL1CM_DW30_BC 0x6C078 739 #define OCL2_LDOFUSE_PWR_DIS (1 << 6) 740 #define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC) 741 742 /* The spec defines this only for BXT PHY0, but lets assume that this 743 * would exist for PHY1 too if it had a second channel. 744 */ 745 #define _PORT_CL2CM_DW6_A 0x162358 746 #define _PORT_CL2CM_DW6_BC 0x6C358 747 #define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC) 748 #define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28) 749 750 /* BXT PHY Ref registers */ 751 #define _PORT_REF_DW3_A 0x16218C 752 #define _PORT_REF_DW3_BC 0x6C18C 753 #define GRC_DONE (1 << 22) 754 #define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC) 755 756 #define _PORT_REF_DW6_A 0x162198 757 #define _PORT_REF_DW6_BC 0x6C198 758 #define GRC_CODE_SHIFT 24 759 #define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT) 760 #define GRC_CODE_FAST_SHIFT 16 761 #define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT) 762 #define GRC_CODE_SLOW_SHIFT 8 763 #define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT) 764 #define GRC_CODE_NOM_MASK 0xFF 765 #define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC) 766 767 #define _PORT_REF_DW8_A 0x1621A0 768 #define _PORT_REF_DW8_BC 0x6C1A0 769 #define GRC_DIS (1 << 15) 770 #define GRC_RDY_OVRD (1 << 1) 771 #define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC) 772 773 /* BXT PHY PCS registers */ 774 #define _PORT_PCS_DW10_LN01_A 0x162428 775 #define _PORT_PCS_DW10_LN01_B 0x6C428 776 #define _PORT_PCS_DW10_LN01_C 0x6C828 777 #define _PORT_PCS_DW10_GRP_A 0x162C28 778 #define _PORT_PCS_DW10_GRP_B 0x6CC28 779 #define _PORT_PCS_DW10_GRP_C 0x6CE28 780 #define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 781 _PORT_PCS_DW10_LN01_B, \ 782 _PORT_PCS_DW10_LN01_C) 783 #define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 784 _PORT_PCS_DW10_GRP_B, \ 785 _PORT_PCS_DW10_GRP_C) 786 787 #define TX2_SWING_CALC_INIT (1 << 31) 788 #define TX1_SWING_CALC_INIT (1 << 30) 789 790 #define _PORT_PCS_DW12_LN01_A 0x162430 791 #define _PORT_PCS_DW12_LN01_B 0x6C430 792 #define _PORT_PCS_DW12_LN01_C 0x6C830 793 #define _PORT_PCS_DW12_LN23_A 0x162630 794 #define _PORT_PCS_DW12_LN23_B 0x6C630 795 #define _PORT_PCS_DW12_LN23_C 0x6CA30 796 #define _PORT_PCS_DW12_GRP_A 0x162c30 797 #define _PORT_PCS_DW12_GRP_B 0x6CC30 798 #define _PORT_PCS_DW12_GRP_C 0x6CE30 799 #define LANESTAGGER_STRAP_OVRD (1 << 6) 800 #define LANE_STAGGER_MASK 0x1F 801 #define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 802 _PORT_PCS_DW12_LN01_B, \ 803 _PORT_PCS_DW12_LN01_C) 804 #define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 805 _PORT_PCS_DW12_LN23_B, \ 806 _PORT_PCS_DW12_LN23_C) 807 #define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 808 _PORT_PCS_DW12_GRP_B, \ 809 _PORT_PCS_DW12_GRP_C) 810 811 /* BXT PHY TX registers */ 812 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ 813 ((lane) & 1) * 0x80) 814 815 #define _PORT_TX_DW2_LN0_A 0x162508 816 #define _PORT_TX_DW2_LN0_B 0x6C508 817 #define _PORT_TX_DW2_LN0_C 0x6C908 818 #define _PORT_TX_DW2_GRP_A 0x162D08 819 #define _PORT_TX_DW2_GRP_B 0x6CD08 820 #define _PORT_TX_DW2_GRP_C 0x6CF08 821 #define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 822 _PORT_TX_DW2_LN0_B, \ 823 _PORT_TX_DW2_LN0_C) 824 #define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 825 _PORT_TX_DW2_GRP_B, \ 826 _PORT_TX_DW2_GRP_C) 827 #define MARGIN_000_SHIFT 16 828 #define MARGIN_000 (0xFF << MARGIN_000_SHIFT) 829 #define UNIQ_TRANS_SCALE_SHIFT 8 830 #define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT) 831 832 #define _PORT_TX_DW3_LN0_A 0x16250C 833 #define _PORT_TX_DW3_LN0_B 0x6C50C 834 #define _PORT_TX_DW3_LN0_C 0x6C90C 835 #define _PORT_TX_DW3_GRP_A 0x162D0C 836 #define _PORT_TX_DW3_GRP_B 0x6CD0C 837 #define _PORT_TX_DW3_GRP_C 0x6CF0C 838 #define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 839 _PORT_TX_DW3_LN0_B, \ 840 _PORT_TX_DW3_LN0_C) 841 #define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 842 _PORT_TX_DW3_GRP_B, \ 843 _PORT_TX_DW3_GRP_C) 844 #define SCALE_DCOMP_METHOD (1 << 26) 845 #define UNIQUE_TRANGE_EN_METHOD (1 << 27) 846 847 #define _PORT_TX_DW4_LN0_A 0x162510 848 #define _PORT_TX_DW4_LN0_B 0x6C510 849 #define _PORT_TX_DW4_LN0_C 0x6C910 850 #define _PORT_TX_DW4_GRP_A 0x162D10 851 #define _PORT_TX_DW4_GRP_B 0x6CD10 852 #define _PORT_TX_DW4_GRP_C 0x6CF10 853 #define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 854 _PORT_TX_DW4_LN0_B, \ 855 _PORT_TX_DW4_LN0_C) 856 #define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 857 _PORT_TX_DW4_GRP_B, \ 858 _PORT_TX_DW4_GRP_C) 859 #define DEEMPH_SHIFT 24 860 #define DE_EMPHASIS (0xFF << DEEMPH_SHIFT) 861 862 #define _PORT_TX_DW5_LN0_A 0x162514 863 #define _PORT_TX_DW5_LN0_B 0x6C514 864 #define _PORT_TX_DW5_LN0_C 0x6C914 865 #define _PORT_TX_DW5_GRP_A 0x162D14 866 #define _PORT_TX_DW5_GRP_B 0x6CD14 867 #define _PORT_TX_DW5_GRP_C 0x6CF14 868 #define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 869 _PORT_TX_DW5_LN0_B, \ 870 _PORT_TX_DW5_LN0_C) 871 #define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \ 872 _PORT_TX_DW5_GRP_B, \ 873 _PORT_TX_DW5_GRP_C) 874 #define DCC_DELAY_RANGE_1 (1 << 9) 875 #define DCC_DELAY_RANGE_2 (1 << 8) 876 877 #define _PORT_TX_DW14_LN0_A 0x162538 878 #define _PORT_TX_DW14_LN0_B 0x6C538 879 #define _PORT_TX_DW14_LN0_C 0x6C938 880 #define LATENCY_OPTIM_SHIFT 30 881 #define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT) 882 #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \ 883 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \ 884 _PORT_TX_DW14_LN0_C) + \ 885 _BXT_LANE_OFFSET(lane)) 886 887 /* UAIMI scratch pad register 1 */ 888 #define UAIMI_SPR1 _MMIO(0x4F074) 889 /* SKL VccIO mask */ 890 #define SKL_VCCIO_MASK 0x1 891 /* SKL balance leg register */ 892 #define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C) 893 /* I_boost values */ 894 #define BALANCE_LEG_SHIFT(port) (8 + 3 * (port)) 895 #define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port))) 896 /* Balance leg disable bits */ 897 #define BALANCE_LEG_DISABLE_SHIFT 23 898 #define BALANCE_LEG_DISABLE(port) (1 << (23 + (port))) 899 900 /* 901 * Fence registers 902 * [0-7] @ 0x2000 gen2,gen3 903 * [8-15] @ 0x3000 945,g33,pnv 904 * 905 * [0-15] @ 0x3000 gen4,gen5 906 * 907 * [0-15] @ 0x100000 gen6,vlv,chv 908 * [0-31] @ 0x100000 gen7+ 909 */ 910 #define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4) 911 #define I830_FENCE_START_MASK 0x07f80000 912 #define I830_FENCE_TILING_Y_SHIFT 12 913 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 914 #define I830_FENCE_PITCH_SHIFT 4 915 #define I830_FENCE_REG_VALID (1 << 0) 916 #define I915_FENCE_MAX_PITCH_VAL 4 917 #define I830_FENCE_MAX_PITCH_VAL 6 918 #define I830_FENCE_MAX_SIZE_VAL (1 << 8) 919 920 #define I915_FENCE_START_MASK 0x0ff00000 921 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 922 923 #define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8) 924 #define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4) 925 #define I965_FENCE_PITCH_SHIFT 2 926 #define I965_FENCE_TILING_Y_SHIFT 1 927 #define I965_FENCE_REG_VALID (1 << 0) 928 #define I965_FENCE_MAX_PITCH_VAL 0x0400 929 930 #define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8) 931 #define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4) 932 #define GEN6_FENCE_PITCH_SHIFT 32 933 #define GEN7_FENCE_MAX_PITCH_VAL 0x0800 934 935 936 /* control register for cpu gtt access */ 937 #define TILECTL _MMIO(0x101000) 938 #define TILECTL_SWZCTL (1 << 0) 939 #define TILECTL_TLBPF (1 << 1) 940 #define TILECTL_TLB_PREFETCH_DIS (1 << 2) 941 #define TILECTL_BACKSNOOP_DIS (1 << 3) 942 943 /* 944 * Instruction and interrupt control regs 945 */ 946 #define PGTBL_CTL _MMIO(0x02020) 947 #define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 948 #define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 949 #define PGTBL_ER _MMIO(0x02024) 950 #define PRB0_BASE (0x2030 - 0x30) 951 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */ 952 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */ 953 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */ 954 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */ 955 #define SRB2_BASE (0x2120 - 0x30) /* 830 */ 956 #define SRB3_BASE (0x2130 - 0x30) /* 830 */ 957 #define RENDER_RING_BASE 0x02000 958 #define BSD_RING_BASE 0x04000 959 #define GEN6_BSD_RING_BASE 0x12000 960 #define GEN8_BSD2_RING_BASE 0x1c000 961 #define GEN11_BSD_RING_BASE 0x1c0000 962 #define GEN11_BSD2_RING_BASE 0x1c4000 963 #define GEN11_BSD3_RING_BASE 0x1d0000 964 #define GEN11_BSD4_RING_BASE 0x1d4000 965 #define XEHP_BSD5_RING_BASE 0x1e0000 966 #define XEHP_BSD6_RING_BASE 0x1e4000 967 #define XEHP_BSD7_RING_BASE 0x1f0000 968 #define XEHP_BSD8_RING_BASE 0x1f4000 969 #define VEBOX_RING_BASE 0x1a000 970 #define GEN11_VEBOX_RING_BASE 0x1c8000 971 #define GEN11_VEBOX2_RING_BASE 0x1d8000 972 #define XEHP_VEBOX3_RING_BASE 0x1e8000 973 #define XEHP_VEBOX4_RING_BASE 0x1f8000 974 #define GEN12_COMPUTE0_RING_BASE 0x1a000 975 #define GEN12_COMPUTE1_RING_BASE 0x1c000 976 #define GEN12_COMPUTE2_RING_BASE 0x1e000 977 #define GEN12_COMPUTE3_RING_BASE 0x26000 978 #define BLT_RING_BASE 0x22000 979 #define DG1_GSC_HECI1_BASE 0x00258000 980 #define DG1_GSC_HECI2_BASE 0x00259000 981 #define DG2_GSC_HECI1_BASE 0x00373000 982 #define DG2_GSC_HECI2_BASE 0x00374000 983 984 985 986 #define HSW_GTT_CACHE_EN _MMIO(0x4024) 987 #define GTT_CACHE_EN_ALL 0xF0007FFF 988 #define GEN7_WR_WATERMARK _MMIO(0x4028) 989 #define GEN7_GFX_PRIO_CTRL _MMIO(0x402C) 990 #define ARB_MODE _MMIO(0x4030) 991 #define ARB_MODE_SWIZZLE_SNB (1 << 4) 992 #define ARB_MODE_SWIZZLE_IVB (1 << 5) 993 #define GEN7_GFX_PEND_TLB0 _MMIO(0x4034) 994 #define GEN7_GFX_PEND_TLB1 _MMIO(0x4038) 995 /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 996 #define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4) 997 #define GEN7_LRA_LIMITS_REG_NUM 13 998 #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) 999 #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) 1000 1001 #define GEN7_ERR_INT _MMIO(0x44040) 1002 #define ERR_INT_POISON (1 << 31) 1003 #define ERR_INT_MMIO_UNCLAIMED (1 << 13) 1004 #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) 1005 #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) 1006 #define ERR_INT_PIPE_CRC_DONE_B (1 << 5) 1007 #define ERR_INT_FIFO_UNDERRUN_B (1 << 3) 1008 #define ERR_INT_PIPE_CRC_DONE_A (1 << 2) 1009 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3)) 1010 #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) 1011 #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 1012 1013 #define FPGA_DBG _MMIO(0x42300) 1014 #define FPGA_DBG_RM_NOCLAIM REG_BIT(31) 1015 1016 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028) 1017 #define CLAIM_ER_CLR REG_BIT(31) 1018 #define CLAIM_ER_OVERFLOW REG_BIT(16) 1019 #define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0) 1020 1021 #define DERRMR _MMIO(0x44050) 1022 /* Note that HBLANK events are reserved on bdw+ */ 1023 #define DERRMR_PIPEA_SCANLINE (1 << 0) 1024 #define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1) 1025 #define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2) 1026 #define DERRMR_PIPEA_VBLANK (1 << 3) 1027 #define DERRMR_PIPEA_HBLANK (1 << 5) 1028 #define DERRMR_PIPEB_SCANLINE (1 << 8) 1029 #define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9) 1030 #define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10) 1031 #define DERRMR_PIPEB_VBLANK (1 << 11) 1032 #define DERRMR_PIPEB_HBLANK (1 << 13) 1033 /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 1034 #define DERRMR_PIPEC_SCANLINE (1 << 14) 1035 #define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15) 1036 #define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20) 1037 #define DERRMR_PIPEC_VBLANK (1 << 21) 1038 #define DERRMR_PIPEC_HBLANK (1 << 22) 1039 1040 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030) 1041 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034) 1042 #define SCPD0 _MMIO(0x209c) /* 915+ only */ 1043 #define SCPD_FBC_IGNORE_3D (1 << 6) 1044 #define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5) 1045 #define GEN2_IER _MMIO(0x20a0) 1046 #define GEN2_IIR _MMIO(0x20a4) 1047 #define GEN2_IMR _MMIO(0x20a8) 1048 #define GEN2_ISR _MMIO(0x20ac) 1049 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060) 1050 #define GINT_DIS (1 << 22) 1051 #define GCFG_DIS (1 << 8) 1052 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064) 1053 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084) 1054 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0) 1055 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4) 1056 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8) 1057 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac) 1058 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120) 1059 #define VLV_PCBR_ADDR_SHIFT 12 1060 1061 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */ 1062 #define EIR _MMIO(0x20b0) 1063 #define EMR _MMIO(0x20b4) 1064 #define ESR _MMIO(0x20b8) 1065 #define GM45_ERROR_PAGE_TABLE (1 << 5) 1066 #define GM45_ERROR_MEM_PRIV (1 << 4) 1067 #define I915_ERROR_PAGE_TABLE (1 << 4) 1068 #define GM45_ERROR_CP_PRIV (1 << 3) 1069 #define I915_ERROR_MEMORY_REFRESH (1 << 1) 1070 #define I915_ERROR_INSTRUCTION (1 << 0) 1071 #define INSTPM _MMIO(0x20c0) 1072 #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ 1073 #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts 1074 will not assert AGPBUSY# and will only 1075 be delivered when out of C3. */ 1076 #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ 1077 #define INSTPM_TLB_INVALIDATE (1 << 9) 1078 #define INSTPM_SYNC_FLUSH (1 << 5) 1079 #define MEM_MODE _MMIO(0x20cc) 1080 #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ 1081 #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ 1082 #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */ 1083 #define FW_BLC _MMIO(0x20d8) 1084 #define FW_BLC2 _MMIO(0x20dc) 1085 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ 1086 #define FW_BLC_SELF_EN_MASK (1 << 31) 1087 #define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */ 1088 #define FW_BLC_SELF_EN (1 << 15) /* 945 only */ 1089 #define MM_BURST_LENGTH 0x00700000 1090 #define MM_FIFO_WATERMARK 0x0001F000 1091 #define LM_BURST_LENGTH 0x00000700 1092 #define LM_FIFO_WATERMARK 0x0000001F 1093 #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ 1094 1095 #define _MBUS_ABOX0_CTL 0x45038 1096 #define _MBUS_ABOX1_CTL 0x45048 1097 #define _MBUS_ABOX2_CTL 0x4504C 1098 #define MBUS_ABOX_CTL(x) _MMIO(_PICK(x, _MBUS_ABOX0_CTL, \ 1099 _MBUS_ABOX1_CTL, \ 1100 _MBUS_ABOX2_CTL)) 1101 #define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) 1102 #define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) 1103 #define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) 1104 #define MBUS_ABOX_B_CREDIT(x) ((x) << 16) 1105 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) 1106 #define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) 1107 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) 1108 #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) 1109 1110 #define _PIPEA_MBUS_DBOX_CTL 0x7003C 1111 #define _PIPEB_MBUS_DBOX_CTL 0x7103C 1112 #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \ 1113 _PIPEB_MBUS_DBOX_CTL) 1114 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK REG_GENMASK(24, 20) /* tgl+ */ 1115 #define MBUS_DBOX_B2B_TRANSACTIONS_MAX(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_MAX_MASK, x) 1116 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK REG_GENMASK(19, 17) /* tgl+ */ 1117 #define MBUS_DBOX_B2B_TRANSACTIONS_DELAY(x) REG_FIELD_PREP(MBUS_DBOX_B2B_TRANSACTIONS_DELAY_MASK, x) 1118 #define MBUS_DBOX_REGULATE_B2B_TRANSACTIONS_EN REG_BIT(16) /* tgl+ */ 1119 #define MBUS_DBOX_BW_CREDIT_MASK REG_GENMASK(15, 14) 1120 #define MBUS_DBOX_BW_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_BW_CREDIT_MASK, x) 1121 #define MBUS_DBOX_B_CREDIT_MASK REG_GENMASK(12, 8) 1122 #define MBUS_DBOX_B_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_B_CREDIT_MASK, x) 1123 #define MBUS_DBOX_A_CREDIT_MASK REG_GENMASK(3, 0) 1124 #define MBUS_DBOX_A_CREDIT(x) REG_FIELD_PREP(MBUS_DBOX_A_CREDIT_MASK, x) 1125 1126 #define MBUS_UBOX_CTL _MMIO(0x4503C) 1127 #define MBUS_BBOX_CTL_S1 _MMIO(0x45040) 1128 #define MBUS_BBOX_CTL_S2 _MMIO(0x45044) 1129 1130 #define MBUS_CTL _MMIO(0x4438C) 1131 #define MBUS_JOIN REG_BIT(31) 1132 #define MBUS_HASHING_MODE_MASK REG_BIT(30) 1133 #define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0) 1134 #define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1) 1135 #define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26) 1136 #define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe) 1137 #define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7) 1138 1139 #define HDPORT_STATE _MMIO(0x45050) 1140 #define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12) 1141 #define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1) 1142 #define HDPORT_ENABLED REG_BIT(0) 1143 1144 /* Make render/texture TLB fetches lower priorty than associated data 1145 * fetches. This is not turned on by default 1146 */ 1147 #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 1148 1149 /* Isoch request wait on GTT enable (Display A/B/C streams). 1150 * Make isoch requests stall on the TLB update. May cause 1151 * display underruns (test mode only) 1152 */ 1153 #define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 1154 1155 /* Block grant count for isoch requests when block count is 1156 * set to a finite value. 1157 */ 1158 #define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 1159 #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 1160 #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 1161 #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 1162 #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 1163 1164 /* Enable render writes to complete in C2/C3/C4 power states. 1165 * If this isn't enabled, render writes are prevented in low 1166 * power states. That seems bad to me. 1167 */ 1168 #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 1169 1170 /* This acknowledges an async flip immediately instead 1171 * of waiting for 2TLB fetches. 1172 */ 1173 #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 1174 1175 /* Enables non-sequential data reads through arbiter 1176 */ 1177 #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 1178 1179 /* Disable FSB snooping of cacheable write cycles from binner/render 1180 * command stream 1181 */ 1182 #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 1183 1184 /* Arbiter time slice for non-isoch streams */ 1185 #define MI_ARB_TIME_SLICE_MASK (7 << 5) 1186 #define MI_ARB_TIME_SLICE_1 (0 << 5) 1187 #define MI_ARB_TIME_SLICE_2 (1 << 5) 1188 #define MI_ARB_TIME_SLICE_4 (2 << 5) 1189 #define MI_ARB_TIME_SLICE_6 (3 << 5) 1190 #define MI_ARB_TIME_SLICE_8 (4 << 5) 1191 #define MI_ARB_TIME_SLICE_10 (5 << 5) 1192 #define MI_ARB_TIME_SLICE_14 (6 << 5) 1193 #define MI_ARB_TIME_SLICE_16 (7 << 5) 1194 1195 /* Low priority grace period page size */ 1196 #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 1197 #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 1198 1199 /* Disable display A/B trickle feed */ 1200 #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 1201 1202 /* Set display plane priority */ 1203 #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 1204 #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 1205 1206 #define MI_STATE _MMIO(0x20e4) /* gen2 only */ 1207 #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 1208 #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 1209 1210 /* On modern GEN architectures interrupt control consists of two sets 1211 * of registers. The first set pertains to the ring generating the 1212 * interrupt. The second control is for the functional block generating the 1213 * interrupt. These are PM, GT, DE, etc. 1214 * 1215 * Luckily *knocks on wood* all the ring interrupt bits match up with the 1216 * GT interrupt bits, so we don't need to duplicate the defines. 1217 * 1218 * These defines should cover us well from SNB->HSW with minor exceptions 1219 * it can also work on ILK. 1220 */ 1221 #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 1222 #define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 1223 #define GT_BLT_USER_INTERRUPT (1 << 22) 1224 #define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 1225 #define GT_BSD_USER_INTERRUPT (1 << 12) 1226 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 1227 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */ 1228 #define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 1229 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 1230 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 1231 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) 1232 #define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 1233 #define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 1234 #define GT_RENDER_USER_INTERRUPT (1 << 0) 1235 1236 #define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 1237 #define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 1238 1239 #define GT_PARITY_ERROR(dev_priv) \ 1240 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 1241 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 1242 1243 /* These are all the "old" interrupts */ 1244 #define ILK_BSD_USER_INTERRUPT (1 << 5) 1245 1246 #define I915_PM_INTERRUPT (1 << 31) 1247 #define I915_ISP_INTERRUPT (1 << 22) 1248 #define I915_LPE_PIPE_B_INTERRUPT (1 << 21) 1249 #define I915_LPE_PIPE_A_INTERRUPT (1 << 20) 1250 #define I915_MIPIC_INTERRUPT (1 << 19) 1251 #define I915_MIPIA_INTERRUPT (1 << 18) 1252 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18) 1253 #define I915_DISPLAY_PORT_INTERRUPT (1 << 17) 1254 #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16) 1255 #define I915_MASTER_ERROR_INTERRUPT (1 << 15) 1256 #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14) 1257 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */ 1258 #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13) 1259 #define I915_HWB_OOM_INTERRUPT (1 << 13) 1260 #define I915_LPE_PIPE_C_INTERRUPT (1 << 12) 1261 #define I915_SYNC_STATUS_INTERRUPT (1 << 12) 1262 #define I915_MISC_INTERRUPT (1 << 11) 1263 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11) 1264 #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10) 1265 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10) 1266 #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9) 1267 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9) 1268 #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8) 1269 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8) 1270 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7) 1271 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6) 1272 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5) 1273 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4) 1274 #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3) 1275 #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2) 1276 #define I915_DEBUG_INTERRUPT (1 << 2) 1277 #define I915_WINVALID_INTERRUPT (1 << 1) 1278 #define I915_USER_INTERRUPT (1 << 1) 1279 #define I915_ASLE_INTERRUPT (1 << 0) 1280 #define I915_BSD_USER_INTERRUPT (1 << 25) 1281 1282 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) 1283 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000 1284 1285 /* DisplayPort Audio w/ LPE */ 1286 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) 1287 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) 1288 1289 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20) 1290 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30) 1291 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34) 1292 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \ 1293 _VLV_AUD_PORT_EN_B_DBG, \ 1294 _VLV_AUD_PORT_EN_C_DBG, \ 1295 _VLV_AUD_PORT_EN_D_DBG) 1296 #define VLV_AMP_MUTE (1 << 1) 1297 1298 #define GEN6_BSD_RNCID _MMIO(0x12198) 1299 1300 #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) 1301 #define GEN7_FF_SCHED_MASK 0x0077070 1302 #define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 1303 #define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19) 1304 #define GEN7_FF_TS_SCHED_HS1 (0x5 << 16) 1305 #define GEN7_FF_TS_SCHED_HS0 (0x3 << 16) 1306 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16) 1307 #define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */ 1308 #define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 1309 #define GEN7_FF_VS_SCHED_HS1 (0x5 << 12) 1310 #define GEN7_FF_VS_SCHED_HS0 (0x3 << 12) 1311 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */ 1312 #define GEN7_FF_VS_SCHED_HW (0x0 << 12) 1313 #define GEN7_FF_DS_SCHED_HS1 (0x5 << 4) 1314 #define GEN7_FF_DS_SCHED_HS0 (0x3 << 4) 1315 #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ 1316 #define GEN7_FF_DS_SCHED_HW (0x0 << 4) 1317 1318 /* 1319 * Framebuffer compression (915+ only) 1320 */ 1321 1322 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ 1323 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ 1324 #define FBC_CONTROL _MMIO(0x3208) 1325 #define FBC_CTL_EN REG_BIT(31) 1326 #define FBC_CTL_PERIODIC REG_BIT(30) 1327 #define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16) 1328 #define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) 1329 #define FBC_CTL_STOP_ON_MOD REG_BIT(15) 1330 #define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ 1331 #define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */ 1332 #define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) 1333 #define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) 1334 #define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 1335 #define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) 1336 #define FBC_COMMAND _MMIO(0x320c) 1337 #define FBC_CMD_COMPRESS REG_BIT(0) 1338 #define FBC_STATUS _MMIO(0x3210) 1339 #define FBC_STAT_COMPRESSING REG_BIT(31) 1340 #define FBC_STAT_COMPRESSED REG_BIT(30) 1341 #define FBC_STAT_MODIFIED REG_BIT(29) 1342 #define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0) 1343 #define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */ 1344 #define FBC_CTL_FENCE_DBL REG_BIT(4) 1345 #define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2) 1346 #define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0) 1347 #define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1) 1348 #define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2) 1349 #define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3) 1350 #define FBC_CTL_CPU_FENCE_EN REG_BIT(1) 1351 #define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0) 1352 #define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane)) 1353 #define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */ 1354 #define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */ 1355 #define FBC_MOD_NUM_MASK REG_GENMASK(31, 1) 1356 #define FBC_MOD_NUM_VALID REG_BIT(0) 1357 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */ 1358 #define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */ 1359 #define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0) 1360 #define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1) 1361 #define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2) 1362 #define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3) 1363 1364 #define FBC_LL_SIZE (1536) 1365 1366 /* Framebuffer compression for GM45+ */ 1367 #define DPFC_CB_BASE _MMIO(0x3200) 1368 #define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240) 1369 #define DPFC_CONTROL _MMIO(0x3208) 1370 #define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248) 1371 #define DPFC_CTL_EN REG_BIT(31) 1372 #define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */ 1373 #define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane)) 1374 #define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */ 1375 #define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */ 1376 #define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane)) 1377 #define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */ 1378 #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */ 1379 #define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */ 1380 #define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */ 1381 #define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */ 1382 #define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6) 1383 #define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0) 1384 #define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1) 1385 #define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2) 1386 #define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0) 1387 #define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence)) 1388 #define DPFC_RECOMP_CTL _MMIO(0x320c) 1389 #define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c) 1390 #define DPFC_RECOMP_STALL_EN REG_BIT(27) 1391 #define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16) 1392 #define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0) 1393 #define DPFC_STATUS _MMIO(0x3210) 1394 #define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250) 1395 #define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16) 1396 #define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0) 1397 #define DPFC_STATUS2 _MMIO(0x3214) 1398 #define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254) 1399 #define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0) 1400 #define DPFC_FENCE_YOFF _MMIO(0x3218) 1401 #define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258) 1402 #define DPFC_CHICKEN _MMIO(0x3224) 1403 #define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264) 1404 #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */ 1405 #define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */ 1406 #define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */ 1407 #define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */ 1408 #define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */ 1409 1410 #define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268) 1411 #define FBC_STRIDE_OVERRIDE REG_BIT(15) 1412 #define FBC_STRIDE_MASK REG_GENMASK(14, 0) 1413 #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x)) 1414 1415 #define ILK_FBC_RT_BASE _MMIO(0x2128) 1416 #define ILK_FBC_RT_VALID REG_BIT(0) 1417 #define SNB_FBC_FRONT_BUFFER REG_BIT(1) 1418 1419 #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) 1420 #define ILK_FBCQ_DIS (1 << 22) 1421 #define ILK_PABSTRETCH_DIS REG_BIT(21) 1422 #define ILK_SABSTRETCH_DIS REG_BIT(20) 1423 #define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20) 1424 #define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0) 1425 #define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1) 1426 #define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2) 1427 #define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3) 1428 #define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18) 1429 #define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0) 1430 #define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1) 1431 #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2) 1432 #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3) 1433 1434 1435 /* 1436 * Framebuffer compression for Sandybridge 1437 * 1438 * The following two registers are of type GTTMMADR 1439 */ 1440 #define SNB_DPFC_CTL_SA _MMIO(0x100100) 1441 #define SNB_DPFC_FENCE_EN REG_BIT(29) 1442 #define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0) 1443 #define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence)) 1444 #define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) 1445 1446 /* Framebuffer compression for Ivybridge */ 1447 #define IVB_FBC_RT_BASE _MMIO(0x7020) 1448 #define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024) 1449 1450 #define IPS_CTL _MMIO(0x43408) 1451 #define IPS_ENABLE (1 << 31) 1452 1453 #define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384) 1454 #define FBC_REND_NUKE REG_BIT(2) 1455 #define FBC_REND_CACHE_CLEAN REG_BIT(1) 1456 1457 /* 1458 * GPIO regs 1459 */ 1460 #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \ 1461 4 * (gpio)) 1462 1463 # define GPIO_CLOCK_DIR_MASK (1 << 0) 1464 # define GPIO_CLOCK_DIR_IN (0 << 1) 1465 # define GPIO_CLOCK_DIR_OUT (1 << 1) 1466 # define GPIO_CLOCK_VAL_MASK (1 << 2) 1467 # define GPIO_CLOCK_VAL_OUT (1 << 3) 1468 # define GPIO_CLOCK_VAL_IN (1 << 4) 1469 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 1470 # define GPIO_DATA_DIR_MASK (1 << 8) 1471 # define GPIO_DATA_DIR_IN (0 << 9) 1472 # define GPIO_DATA_DIR_OUT (1 << 9) 1473 # define GPIO_DATA_VAL_MASK (1 << 10) 1474 # define GPIO_DATA_VAL_OUT (1 << 11) 1475 # define GPIO_DATA_VAL_IN (1 << 12) 1476 # define GPIO_DATA_PULLUP_DISABLE (1 << 13) 1477 1478 #define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ 1479 #define GMBUS_AKSV_SELECT (1 << 11) 1480 #define GMBUS_RATE_100KHZ (0 << 8) 1481 #define GMBUS_RATE_50KHZ (1 << 8) 1482 #define GMBUS_RATE_400KHZ (2 << 8) /* reserved on Pineview */ 1483 #define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */ 1484 #define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */ 1485 #define GMBUS_BYTE_CNT_OVERRIDE (1 << 6) 1486 1487 #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ 1488 #define GMBUS_SW_CLR_INT (1 << 31) 1489 #define GMBUS_SW_RDY (1 << 30) 1490 #define GMBUS_ENT (1 << 29) /* enable timeout */ 1491 #define GMBUS_CYCLE_NONE (0 << 25) 1492 #define GMBUS_CYCLE_WAIT (1 << 25) 1493 #define GMBUS_CYCLE_INDEX (2 << 25) 1494 #define GMBUS_CYCLE_STOP (4 << 25) 1495 #define GMBUS_BYTE_COUNT_SHIFT 16 1496 #define GMBUS_BYTE_COUNT_MAX 256U 1497 #define GEN9_GMBUS_BYTE_COUNT_MAX 511U 1498 #define GMBUS_SLAVE_INDEX_SHIFT 8 1499 #define GMBUS_SLAVE_ADDR_SHIFT 1 1500 #define GMBUS_SLAVE_READ (1 << 0) 1501 #define GMBUS_SLAVE_WRITE (0 << 0) 1502 #define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ 1503 #define GMBUS_INUSE (1 << 15) 1504 #define GMBUS_HW_WAIT_PHASE (1 << 14) 1505 #define GMBUS_STALL_TIMEOUT (1 << 13) 1506 #define GMBUS_INT (1 << 12) 1507 #define GMBUS_HW_RDY (1 << 11) 1508 #define GMBUS_SATOER (1 << 10) 1509 #define GMBUS_ACTIVE (1 << 9) 1510 #define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ 1511 #define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ 1512 #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4) 1513 #define GMBUS_NAK_EN (1 << 3) 1514 #define GMBUS_IDLE_EN (1 << 2) 1515 #define GMBUS_HW_WAIT_EN (1 << 1) 1516 #define GMBUS_HW_RDY_EN (1 << 0) 1517 #define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ 1518 #define GMBUS_2BYTE_INDEX_EN (1 << 31) 1519 1520 /* 1521 * Clock control & power management 1522 */ 1523 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014) 1524 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018) 1525 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030) 1526 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 1527 1528 #define VGA0 _MMIO(0x6000) 1529 #define VGA1 _MMIO(0x6004) 1530 #define VGA_PD _MMIO(0x6010) 1531 #define VGA0_PD_P2_DIV_4 (1 << 7) 1532 #define VGA0_PD_P1_DIV_2 (1 << 5) 1533 #define VGA0_PD_P1_SHIFT 0 1534 #define VGA0_PD_P1_MASK (0x1f << 0) 1535 #define VGA1_PD_P2_DIV_4 (1 << 15) 1536 #define VGA1_PD_P1_DIV_2 (1 << 13) 1537 #define VGA1_PD_P1_SHIFT 8 1538 #define VGA1_PD_P1_MASK (0x1f << 8) 1539 #define DPLL_VCO_ENABLE (1 << 31) 1540 #define DPLL_SDVO_HIGH_SPEED (1 << 30) 1541 #define DPLL_DVO_2X_MODE (1 << 30) 1542 #define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 1543 #define DPLL_SYNCLOCK_ENABLE (1 << 29) 1544 #define DPLL_REF_CLK_ENABLE_VLV (1 << 29) 1545 #define DPLL_VGA_MODE_DIS (1 << 28) 1546 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 1547 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 1548 #define DPLL_MODE_MASK (3 << 26) 1549 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 1550 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 1551 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 1552 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 1553 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 1554 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 1555 #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 1556 #define DPLL_LOCK_VLV (1 << 15) 1557 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14) 1558 #define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13) 1559 #define DPLL_SSC_REF_CLK_CHV (1 << 13) 1560 #define DPLL_PORTC_READY_MASK (0xf << 4) 1561 #define DPLL_PORTB_READY_MASK (0xf) 1562 1563 #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 1564 1565 /* Additional CHV pll/phy registers */ 1566 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240) 1567 #define DPLL_PORTD_READY_MASK (0xf) 1568 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100) 1569 #define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27)) 1570 #define PHY_LDO_DELAY_0NS 0x0 1571 #define PHY_LDO_DELAY_200NS 0x1 1572 #define PHY_LDO_DELAY_600NS 0x2 1573 #define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23)) 1574 #define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11)) 1575 #define PHY_CH_SU_PSR 0x1 1576 #define PHY_CH_DEEP_PSR 0x7 1577 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2)) 1578 #define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 1579 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104) 1580 #define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30)) 1581 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch)))) 1582 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)))) 1583 1584 /* 1585 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 1586 * this field (only one bit may be set). 1587 */ 1588 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 1589 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16 1590 #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 1591 /* i830, required in DVO non-gang */ 1592 #define PLL_P2_DIVIDE_BY_4 (1 << 23) 1593 #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 1594 #define PLL_REF_INPUT_DREFCLK (0 << 13) 1595 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 1596 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 1597 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 1598 #define PLL_REF_INPUT_MASK (3 << 13) 1599 #define PLL_LOAD_PULSE_PHASE_SHIFT 9 1600 /* Ironlake */ 1601 # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 1602 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 1603 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9) 1604 # define DPLL_FPA1_P1_POST_DIV_SHIFT 0 1605 # define DPLL_FPA1_P1_POST_DIV_MASK 0xff 1606 1607 /* 1608 * Parallel to Serial Load Pulse phase selection. 1609 * Selects the phase for the 10X DPLL clock for the PCIe 1610 * digital display port. The range is 4 to 13; 10 or more 1611 * is just a flip delay. The default is 6 1612 */ 1613 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 1614 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 1615 /* 1616 * SDVO multiplier for 945G/GM. Not used on 965. 1617 */ 1618 #define SDVO_MULTIPLIER_MASK 0x000000ff 1619 #define SDVO_MULTIPLIER_SHIFT_HIRES 4 1620 #define SDVO_MULTIPLIER_SHIFT_VGA 0 1621 1622 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c) 1623 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020) 1624 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c) 1625 #define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 1626 1627 /* 1628 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 1629 * 1630 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 1631 */ 1632 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 1633 #define DPLL_MD_UDI_DIVIDER_SHIFT 24 1634 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 1635 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 1636 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 1637 /* 1638 * SDVO/UDI pixel multiplier. 1639 * 1640 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 1641 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 1642 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 1643 * dummy bytes in the datastream at an increased clock rate, with both sides of 1644 * the link knowing how many bytes are fill. 1645 * 1646 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 1647 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 1648 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 1649 * through an SDVO command. 1650 * 1651 * This register field has values of multiplication factor minus 1, with 1652 * a maximum multiplier of 5 for SDVO. 1653 */ 1654 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 1655 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 1656 /* 1657 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 1658 * This best be set to the default value (3) or the CRT won't work. No, 1659 * I don't entirely understand what this does... 1660 */ 1661 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 1662 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 1663 1664 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024) 1665 1666 #define _FPA0 0x6040 1667 #define _FPA1 0x6044 1668 #define _FPB0 0x6048 1669 #define _FPB1 0x604c 1670 #define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0) 1671 #define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1) 1672 #define FP_N_DIV_MASK 0x003f0000 1673 #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 1674 #define FP_N_DIV_SHIFT 16 1675 #define FP_M1_DIV_MASK 0x00003f00 1676 #define FP_M1_DIV_SHIFT 8 1677 #define FP_M2_DIV_MASK 0x0000003f 1678 #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 1679 #define FP_M2_DIV_SHIFT 0 1680 #define DPLL_TEST _MMIO(0x606c) 1681 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 1682 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 1683 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 1684 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 1685 #define DPLLB_TEST_N_BYPASS (1 << 19) 1686 #define DPLLB_TEST_M_BYPASS (1 << 18) 1687 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 1688 #define DPLLA_TEST_N_BYPASS (1 << 3) 1689 #define DPLLA_TEST_M_BYPASS (1 << 2) 1690 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 1691 #define D_STATE _MMIO(0x6104) 1692 #define DSTATE_GFX_RESET_I830 (1 << 6) 1693 #define DSTATE_PLL_D3_OFF (1 << 3) 1694 #define DSTATE_GFX_CLOCK_GATING (1 << 1) 1695 #define DSTATE_DOT_CLOCK_GATING (1 << 0) 1696 #define DSPCLK_GATE_D _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200) 1697 # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 1698 # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 1699 # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 1700 # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 1701 # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 1702 # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 1703 # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 1704 # define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */ 1705 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 1706 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 1707 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 1708 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 1709 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 1710 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 1711 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 1712 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 1713 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 1714 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 1715 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 1716 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 1717 # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 1718 # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 1719 # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 1720 # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 1721 # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 1722 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 1723 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 1724 # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 1725 # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 1726 /* 1727 * This bit must be set on the 830 to prevent hangs when turning off the 1728 * overlay scaler. 1729 */ 1730 # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 1731 # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 1732 # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 1733 # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 1734 # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 1735 1736 #define RENCLK_GATE_D1 _MMIO(0x6204) 1737 # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 1738 # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 1739 # define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 1740 # define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 1741 # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 1742 # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 1743 # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 1744 # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 1745 # define MAG_CLOCK_GATE_DISABLE (1 << 5) 1746 /* This bit must be unset on 855,865 */ 1747 # define MECI_CLOCK_GATE_DISABLE (1 << 4) 1748 # define DCMP_CLOCK_GATE_DISABLE (1 << 3) 1749 # define MEC_CLOCK_GATE_DISABLE (1 << 2) 1750 # define MECO_CLOCK_GATE_DISABLE (1 << 1) 1751 /* This bit must be set on 855,865. */ 1752 # define SV_CLOCK_GATE_DISABLE (1 << 0) 1753 # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 1754 # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 1755 # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 1756 # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 1757 # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 1758 # define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 1759 # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 1760 # define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 1761 # define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 1762 # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 1763 # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 1764 # define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 1765 # define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 1766 # define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 1767 # define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 1768 # define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 1769 # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 1770 1771 # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 1772 /* This bit must always be set on 965G/965GM */ 1773 # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 1774 # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 1775 # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 1776 # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 1777 # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 1778 # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 1779 /* This bit must always be set on 965G */ 1780 # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 1781 # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 1782 # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 1783 # define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 1784 # define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 1785 # define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 1786 # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 1787 # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 1788 # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 1789 # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 1790 # define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 1791 # define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 1792 # define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 1793 # define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 1794 # define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 1795 # define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 1796 # define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 1797 # define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 1798 # define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 1799 1800 #define RENCLK_GATE_D2 _MMIO(0x6208) 1801 #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 1802 #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 1803 #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 1804 1805 #define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */ 1806 #define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 1807 1808 #define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */ 1809 #define DEUC _MMIO(0x6214) /* CRL only */ 1810 1811 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500) 1812 #define FW_CSPWRDWNEN (1 << 15) 1813 1814 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504) 1815 1816 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508) 1817 #define CDCLK_FREQ_SHIFT 4 1818 #define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 1819 #define CZCLK_FREQ_MASK 0xf 1820 1821 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C) 1822 #define PFI_CREDIT_63 (9 << 28) /* chv only */ 1823 #define PFI_CREDIT_31 (8 << 28) /* chv only */ 1824 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */ 1825 #define PFI_CREDIT_RESEND (1 << 27) 1826 #define VGA_FAST_MODE_DISABLE (1 << 14) 1827 1828 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) 1829 1830 /* 1831 * Palette regs 1832 */ 1833 #define _PALETTE_A 0xa000 1834 #define _PALETTE_B 0xa800 1835 #define _CHV_PALETTE_C 0xc000 1836 #define PALETTE_RED_MASK REG_GENMASK(23, 16) 1837 #define PALETTE_GREEN_MASK REG_GENMASK(15, 8) 1838 #define PALETTE_BLUE_MASK REG_GENMASK(7, 0) 1839 #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ 1840 _PICK((pipe), _PALETTE_A, \ 1841 _PALETTE_B, _CHV_PALETTE_C) + \ 1842 (i) * 4) 1843 1844 #define PEG_BAND_GAP_DATA _MMIO(0x14d68) 1845 1846 #define BXT_RP_STATE_CAP _MMIO(0x138170) 1847 #define GEN9_RP_STATE_LIMITS _MMIO(0x138148) 1848 #define XEHPSDV_RP_STATE_CAP _MMIO(0x250014) 1849 1850 #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8) 1851 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 1852 #define PROCHOT_MASK REG_BIT(1) 1853 #define THERMAL_LIMIT_MASK REG_BIT(2) 1854 #define RATL_MASK REG_BIT(6) 1855 #define VR_THERMALERT_MASK REG_BIT(7) 1856 #define VR_TDC_MASK REG_BIT(8) 1857 #define POWER_LIMIT_4_MASK REG_BIT(9) 1858 #define POWER_LIMIT_1_MASK REG_BIT(11) 1859 #define POWER_LIMIT_2_MASK REG_BIT(12) 1860 1861 #define CHV_CLK_CTL1 _MMIO(0x101100) 1862 #define VLV_CLK_CTL2 _MMIO(0x101104) 1863 #define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 1864 1865 /* 1866 * Overlay regs 1867 */ 1868 1869 #define OVADD _MMIO(0x30000) 1870 #define DOVSTA _MMIO(0x30008) 1871 #define OC_BUF (0x3 << 20) 1872 #define OGAMC5 _MMIO(0x30010) 1873 #define OGAMC4 _MMIO(0x30014) 1874 #define OGAMC3 _MMIO(0x30018) 1875 #define OGAMC2 _MMIO(0x3001c) 1876 #define OGAMC1 _MMIO(0x30020) 1877 #define OGAMC0 _MMIO(0x30024) 1878 1879 /* 1880 * GEN9 clock gating regs 1881 */ 1882 #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) 1883 #define DARBF_GATING_DIS (1 << 27) 1884 #define PWM2_GATING_DIS (1 << 14) 1885 #define PWM1_GATING_DIS (1 << 13) 1886 1887 #define GEN9_CLKGATE_DIS_3 _MMIO(0x46538) 1888 #define TGL_VRH_GATING_DIS REG_BIT(31) 1889 #define DPT_GATING_DIS REG_BIT(22) 1890 1891 #define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C) 1892 #define BXT_GMBUS_GATING_DIS (1 << 14) 1893 1894 #define GEN9_CLKGATE_DIS_5 _MMIO(0x46540) 1895 #define DPCE_GATING_DIS REG_BIT(17) 1896 1897 #define _CLKGATE_DIS_PSL_A 0x46520 1898 #define _CLKGATE_DIS_PSL_B 0x46524 1899 #define _CLKGATE_DIS_PSL_C 0x46528 1900 #define DUPS1_GATING_DIS (1 << 15) 1901 #define DUPS2_GATING_DIS (1 << 19) 1902 #define DUPS3_GATING_DIS (1 << 23) 1903 #define CURSOR_GATING_DIS REG_BIT(28) 1904 #define DPF_GATING_DIS (1 << 10) 1905 #define DPF_RAM_GATING_DIS (1 << 9) 1906 #define DPFR_GATING_DIS (1 << 8) 1907 1908 #define CLKGATE_DIS_PSL(pipe) \ 1909 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) 1910 1911 /* 1912 * Display engine regs 1913 */ 1914 1915 /* Pipe A CRC regs */ 1916 #define _PIPE_CRC_CTL_A 0x60050 1917 #define PIPE_CRC_ENABLE REG_BIT(31) 1918 /* skl+ source selection */ 1919 #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) 1920 #define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0) 1921 #define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2) 1922 #define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4) 1923 #define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6) 1924 #define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7) 1925 #define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5) 1926 #define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3) 1927 #define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1) 1928 /* ivb+ source selection */ 1929 #define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29) 1930 #define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0) 1931 #define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1) 1932 #define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2) 1933 /* ilk+ source selection */ 1934 #define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28) 1935 #define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0) 1936 #define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1) 1937 #define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2) 1938 /* embedded DP port on the north display block */ 1939 #define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4) 1940 #define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5) 1941 /* vlv source selection */ 1942 #define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27) 1943 #define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0) 1944 #define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1) 1945 #define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2) 1946 /* with DP port the pipe source is invalid */ 1947 #define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3) 1948 #define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6) 1949 #define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7) 1950 /* gen3+ source selection */ 1951 #define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28) 1952 #define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0) 1953 #define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1) 1954 #define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2) 1955 /* with DP/TV port the pipe source is invalid */ 1956 #define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3) 1957 #define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4) 1958 #define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5) 1959 #define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6) 1960 #define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7) 1961 /* gen2 doesn't have source selection bits */ 1962 #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) 1963 1964 #define _PIPE_CRC_RES_1_A_IVB 0x60064 1965 #define _PIPE_CRC_RES_2_A_IVB 0x60068 1966 #define _PIPE_CRC_RES_3_A_IVB 0x6006c 1967 #define _PIPE_CRC_RES_4_A_IVB 0x60070 1968 #define _PIPE_CRC_RES_5_A_IVB 0x60074 1969 1970 #define _PIPE_CRC_RES_RED_A 0x60060 1971 #define _PIPE_CRC_RES_GREEN_A 0x60064 1972 #define _PIPE_CRC_RES_BLUE_A 0x60068 1973 #define _PIPE_CRC_RES_RES1_A_I915 0x6006c 1974 #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 1975 1976 /* Pipe B CRC regs */ 1977 #define _PIPE_CRC_RES_1_B_IVB 0x61064 1978 #define _PIPE_CRC_RES_2_B_IVB 0x61068 1979 #define _PIPE_CRC_RES_3_B_IVB 0x6106c 1980 #define _PIPE_CRC_RES_4_B_IVB 0x61070 1981 #define _PIPE_CRC_RES_5_B_IVB 0x61074 1982 1983 #define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) 1984 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) 1985 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) 1986 #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) 1987 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) 1988 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) 1989 1990 #define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) 1991 #define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) 1992 #define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) 1993 #define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) 1994 #define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 1995 1996 /* Pipe A timing regs */ 1997 #define _HTOTAL_A 0x60000 1998 #define _HBLANK_A 0x60004 1999 #define _HSYNC_A 0x60008 2000 #define _VTOTAL_A 0x6000c 2001 #define _VBLANK_A 0x60010 2002 #define _VSYNC_A 0x60014 2003 #define _EXITLINE_A 0x60018 2004 #define _PIPEASRC 0x6001c 2005 #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16) 2006 #define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w)) 2007 #define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0) 2008 #define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h)) 2009 #define _BCLRPAT_A 0x60020 2010 #define _VSYNCSHIFT_A 0x60028 2011 #define _PIPE_MULT_A 0x6002c 2012 2013 /* Pipe B timing regs */ 2014 #define _HTOTAL_B 0x61000 2015 #define _HBLANK_B 0x61004 2016 #define _HSYNC_B 0x61008 2017 #define _VTOTAL_B 0x6100c 2018 #define _VBLANK_B 0x61010 2019 #define _VSYNC_B 0x61014 2020 #define _PIPEBSRC 0x6101c 2021 #define _BCLRPAT_B 0x61020 2022 #define _VSYNCSHIFT_B 0x61028 2023 #define _PIPE_MULT_B 0x6102c 2024 2025 /* DSI 0 timing regs */ 2026 #define _HTOTAL_DSI0 0x6b000 2027 #define _HSYNC_DSI0 0x6b008 2028 #define _VTOTAL_DSI0 0x6b00c 2029 #define _VSYNC_DSI0 0x6b014 2030 #define _VSYNCSHIFT_DSI0 0x6b028 2031 2032 /* DSI 1 timing regs */ 2033 #define _HTOTAL_DSI1 0x6b800 2034 #define _HSYNC_DSI1 0x6b808 2035 #define _VTOTAL_DSI1 0x6b80c 2036 #define _VSYNC_DSI1 0x6b814 2037 #define _VSYNCSHIFT_DSI1 0x6b828 2038 2039 #define TRANSCODER_A_OFFSET 0x60000 2040 #define TRANSCODER_B_OFFSET 0x61000 2041 #define TRANSCODER_C_OFFSET 0x62000 2042 #define CHV_TRANSCODER_C_OFFSET 0x63000 2043 #define TRANSCODER_D_OFFSET 0x63000 2044 #define TRANSCODER_EDP_OFFSET 0x6f000 2045 #define TRANSCODER_DSI0_OFFSET 0x6b000 2046 #define TRANSCODER_DSI1_OFFSET 0x6b800 2047 2048 #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) 2049 #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) 2050 #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A) 2051 #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) 2052 #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) 2053 #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) 2054 #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) 2055 #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) 2056 #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) 2057 #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) 2058 2059 #define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A) 2060 #define EXITLINE_ENABLE REG_BIT(31) 2061 #define EXITLINE_MASK REG_GENMASK(12, 0) 2062 #define EXITLINE_SHIFT 0 2063 2064 /* VRR registers */ 2065 #define _TRANS_VRR_CTL_A 0x60420 2066 #define _TRANS_VRR_CTL_B 0x61420 2067 #define _TRANS_VRR_CTL_C 0x62420 2068 #define _TRANS_VRR_CTL_D 0x63420 2069 #define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A) 2070 #define VRR_CTL_VRR_ENABLE REG_BIT(31) 2071 #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) 2072 #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) 2073 #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) 2074 #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) 2075 #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) 2076 #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) 2077 #define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) 2078 2079 #define _TRANS_VRR_VMAX_A 0x60424 2080 #define _TRANS_VRR_VMAX_B 0x61424 2081 #define _TRANS_VRR_VMAX_C 0x62424 2082 #define _TRANS_VRR_VMAX_D 0x63424 2083 #define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A) 2084 #define VRR_VMAX_MASK REG_GENMASK(19, 0) 2085 2086 #define _TRANS_VRR_VMIN_A 0x60434 2087 #define _TRANS_VRR_VMIN_B 0x61434 2088 #define _TRANS_VRR_VMIN_C 0x62434 2089 #define _TRANS_VRR_VMIN_D 0x63434 2090 #define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A) 2091 #define VRR_VMIN_MASK REG_GENMASK(15, 0) 2092 2093 #define _TRANS_VRR_VMAXSHIFT_A 0x60428 2094 #define _TRANS_VRR_VMAXSHIFT_B 0x61428 2095 #define _TRANS_VRR_VMAXSHIFT_C 0x62428 2096 #define _TRANS_VRR_VMAXSHIFT_D 0x63428 2097 #define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \ 2098 _TRANS_VRR_VMAXSHIFT_A) 2099 #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) 2100 #define VRR_VMAXSHIFT_DEC REG_BIT(16) 2101 #define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) 2102 2103 #define _TRANS_VRR_STATUS_A 0x6042C 2104 #define _TRANS_VRR_STATUS_B 0x6142C 2105 #define _TRANS_VRR_STATUS_C 0x6242C 2106 #define _TRANS_VRR_STATUS_D 0x6342C 2107 #define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A) 2108 #define VRR_STATUS_VMAX_REACHED REG_BIT(31) 2109 #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) 2110 #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) 2111 #define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) 2112 #define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) 2113 #define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) 2114 #define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) 2115 #define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) 2116 #define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) 2117 #define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) 2118 #define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) 2119 #define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) 2120 #define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) 2121 #define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) 2122 2123 #define _TRANS_VRR_VTOTAL_PREV_A 0x60480 2124 #define _TRANS_VRR_VTOTAL_PREV_B 0x61480 2125 #define _TRANS_VRR_VTOTAL_PREV_C 0x62480 2126 #define _TRANS_VRR_VTOTAL_PREV_D 0x63480 2127 #define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \ 2128 _TRANS_VRR_VTOTAL_PREV_A) 2129 #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) 2130 #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) 2131 #define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) 2132 #define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) 2133 2134 #define _TRANS_VRR_FLIPLINE_A 0x60438 2135 #define _TRANS_VRR_FLIPLINE_B 0x61438 2136 #define _TRANS_VRR_FLIPLINE_C 0x62438 2137 #define _TRANS_VRR_FLIPLINE_D 0x63438 2138 #define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \ 2139 _TRANS_VRR_FLIPLINE_A) 2140 #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) 2141 2142 #define _TRANS_VRR_STATUS2_A 0x6043C 2143 #define _TRANS_VRR_STATUS2_B 0x6143C 2144 #define _TRANS_VRR_STATUS2_C 0x6243C 2145 #define _TRANS_VRR_STATUS2_D 0x6343C 2146 #define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A) 2147 #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) 2148 2149 #define _TRANS_PUSH_A 0x60A70 2150 #define _TRANS_PUSH_B 0x61A70 2151 #define _TRANS_PUSH_C 0x62A70 2152 #define _TRANS_PUSH_D 0x63A70 2153 #define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A) 2154 #define TRANS_PUSH_EN REG_BIT(31) 2155 #define TRANS_PUSH_SEND REG_BIT(30) 2156 2157 /* 2158 * HSW+ eDP PSR registers 2159 * 2160 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one 2161 * instance of it 2162 */ 2163 #define _SRD_CTL_A 0x60800 2164 #define _SRD_CTL_EDP 0x6f800 2165 #define EDP_PSR_CTL(tran) _MMIO(_TRANS2(tran, _SRD_CTL_A)) 2166 #define EDP_PSR_ENABLE (1 << 31) 2167 #define BDW_PSR_SINGLE_FRAME (1 << 30) 2168 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */ 2169 #define EDP_PSR_LINK_STANDBY (1 << 27) 2170 #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3 << 25) 2171 #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0 << 25) 2172 #define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1 << 25) 2173 #define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2 << 25) 2174 #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3 << 25) 2175 #define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 2176 #define EDP_PSR_SKIP_AUX_EXIT (1 << 12) 2177 #define EDP_PSR_TP1_TP2_SEL (0 << 11) 2178 #define EDP_PSR_TP1_TP3_SEL (1 << 11) 2179 #define EDP_PSR_CRC_ENABLE (1 << 10) /* BDW+ */ 2180 #define EDP_PSR_TP2_TP3_TIME_500us (0 << 8) 2181 #define EDP_PSR_TP2_TP3_TIME_100us (1 << 8) 2182 #define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8) 2183 #define EDP_PSR_TP2_TP3_TIME_0us (3 << 8) 2184 #define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */ 2185 #define EDP_PSR_TP1_TIME_500us (0 << 4) 2186 #define EDP_PSR_TP1_TIME_100us (1 << 4) 2187 #define EDP_PSR_TP1_TIME_2500us (2 << 4) 2188 #define EDP_PSR_TP1_TIME_0us (3 << 4) 2189 #define EDP_PSR_IDLE_FRAME_SHIFT 0 2190 2191 /* 2192 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative 2193 * to transcoder and bits defined for each one as if using no shift (i.e. as if 2194 * it was for TRANSCODER_EDP) 2195 */ 2196 #define EDP_PSR_IMR _MMIO(0x64834) 2197 #define EDP_PSR_IIR _MMIO(0x64838) 2198 #define _PSR_IMR_A 0x60814 2199 #define _PSR_IIR_A 0x60818 2200 #define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A) 2201 #define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A) 2202 #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \ 2203 0 : ((trans) - TRANSCODER_A + 1) * 8) 2204 #define EDP_PSR_TRANS_MASK(trans) (0x7 << _EDP_PSR_TRANS_SHIFT(trans)) 2205 #define EDP_PSR_ERROR(trans) (0x4 << _EDP_PSR_TRANS_SHIFT(trans)) 2206 #define EDP_PSR_POST_EXIT(trans) (0x2 << _EDP_PSR_TRANS_SHIFT(trans)) 2207 #define EDP_PSR_PRE_ENTRY(trans) (0x1 << _EDP_PSR_TRANS_SHIFT(trans)) 2208 2209 #define _SRD_AUX_DATA_A 0x60814 2210 #define _SRD_AUX_DATA_EDP 0x6f814 2211 #define EDP_PSR_AUX_DATA(tran, i) _MMIO(_TRANS2(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */ 2212 2213 #define _SRD_STATUS_A 0x60840 2214 #define _SRD_STATUS_EDP 0x6f840 2215 #define EDP_PSR_STATUS(tran) _MMIO(_TRANS2(tran, _SRD_STATUS_A)) 2216 #define EDP_PSR_STATUS_STATE_MASK (7 << 29) 2217 #define EDP_PSR_STATUS_STATE_SHIFT 29 2218 #define EDP_PSR_STATUS_STATE_IDLE (0 << 29) 2219 #define EDP_PSR_STATUS_STATE_SRDONACK (1 << 29) 2220 #define EDP_PSR_STATUS_STATE_SRDENT (2 << 29) 2221 #define EDP_PSR_STATUS_STATE_BUFOFF (3 << 29) 2222 #define EDP_PSR_STATUS_STATE_BUFON (4 << 29) 2223 #define EDP_PSR_STATUS_STATE_AUXACK (5 << 29) 2224 #define EDP_PSR_STATUS_STATE_SRDOFFACK (6 << 29) 2225 #define EDP_PSR_STATUS_LINK_MASK (3 << 26) 2226 #define EDP_PSR_STATUS_LINK_FULL_OFF (0 << 26) 2227 #define EDP_PSR_STATUS_LINK_FULL_ON (1 << 26) 2228 #define EDP_PSR_STATUS_LINK_STANDBY (2 << 26) 2229 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 2230 #define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 2231 #define EDP_PSR_STATUS_COUNT_SHIFT 16 2232 #define EDP_PSR_STATUS_COUNT_MASK 0xf 2233 #define EDP_PSR_STATUS_AUX_ERROR (1 << 15) 2234 #define EDP_PSR_STATUS_AUX_SENDING (1 << 12) 2235 #define EDP_PSR_STATUS_SENDING_IDLE (1 << 9) 2236 #define EDP_PSR_STATUS_SENDING_TP2_TP3 (1 << 8) 2237 #define EDP_PSR_STATUS_SENDING_TP1 (1 << 4) 2238 #define EDP_PSR_STATUS_IDLE_MASK 0xf 2239 2240 #define _SRD_PERF_CNT_A 0x60844 2241 #define _SRD_PERF_CNT_EDP 0x6f844 2242 #define EDP_PSR_PERF_CNT(tran) _MMIO(_TRANS2(tran, _SRD_PERF_CNT_A)) 2243 #define EDP_PSR_PERF_CNT_MASK 0xffffff 2244 2245 /* PSR_MASK on SKL+ */ 2246 #define _SRD_DEBUG_A 0x60860 2247 #define _SRD_DEBUG_EDP 0x6f860 2248 #define EDP_PSR_DEBUG(tran) _MMIO(_TRANS2(tran, _SRD_DEBUG_A)) 2249 #define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28) 2250 #define EDP_PSR_DEBUG_MASK_LPSP (1 << 27) 2251 #define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26) 2252 #define EDP_PSR_DEBUG_MASK_HPD (1 << 25) 2253 #define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (1 << 16) /* Reserved in ICL+ */ 2254 #define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */ 2255 2256 #define _PSR2_CTL_A 0x60900 2257 #define _PSR2_CTL_EDP 0x6f900 2258 #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) 2259 #define EDP_PSR2_ENABLE (1 << 31) 2260 #define EDP_SU_TRACK_ENABLE (1 << 30) /* up to adl-p */ 2261 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) 2262 #define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) 2263 #define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */ 2264 #define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */ 2265 #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) 2266 #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) 2267 #define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8 2268 #define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13) 2269 #define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13) 2270 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 2271 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT 13 2272 #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT) 2273 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13) 2274 #define EDP_PSR2_FAST_WAKE_MAX_LINES 8 2275 #define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11) 2276 #define EDP_PSR2_FAST_WAKE_MASK (3 << 11) 2277 #define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5 2278 #define TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT 10 2279 #define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT) 2280 #define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10) 2281 #define EDP_PSR2_TP2_TIME_500us (0 << 8) 2282 #define EDP_PSR2_TP2_TIME_100us (1 << 8) 2283 #define EDP_PSR2_TP2_TIME_2500us (2 << 8) 2284 #define EDP_PSR2_TP2_TIME_50us (3 << 8) 2285 #define EDP_PSR2_TP2_TIME_MASK (3 << 8) 2286 #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4 2287 #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf << 4) 2288 #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a) << 4) 2289 #define EDP_PSR2_IDLE_FRAME_MASK 0xf 2290 #define EDP_PSR2_IDLE_FRAME_SHIFT 0 2291 2292 #define _PSR_EVENT_TRANS_A 0x60848 2293 #define _PSR_EVENT_TRANS_B 0x61848 2294 #define _PSR_EVENT_TRANS_C 0x62848 2295 #define _PSR_EVENT_TRANS_D 0x63848 2296 #define _PSR_EVENT_TRANS_EDP 0x6f848 2297 #define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A) 2298 #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17) 2299 #define PSR_EVENT_PSR2_DISABLED (1 << 16) 2300 #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15) 2301 #define PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14) 2302 #define PSR_EVENT_GRAPHICS_RESET (1 << 12) 2303 #define PSR_EVENT_PCH_INTERRUPT (1 << 11) 2304 #define PSR_EVENT_MEMORY_UP (1 << 10) 2305 #define PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9) 2306 #define PSR_EVENT_WD_TIMER_EXPIRE (1 << 8) 2307 #define PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6) 2308 #define PSR_EVENT_REGISTER_UPDATE (1 << 5) /* Reserved in ICL+ */ 2309 #define PSR_EVENT_HDCP_ENABLE (1 << 4) 2310 #define PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3) 2311 #define PSR_EVENT_VBI_ENABLE (1 << 2) 2312 #define PSR_EVENT_LPSP_MODE_EXIT (1 << 1) 2313 #define PSR_EVENT_PSR_DISABLE (1 << 0) 2314 2315 #define _PSR2_STATUS_A 0x60940 2316 #define _PSR2_STATUS_EDP 0x6f940 2317 #define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A) 2318 #define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28) 2319 #define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8) 2320 2321 #define _PSR2_SU_STATUS_A 0x60914 2322 #define _PSR2_SU_STATUS_EDP 0x6f914 2323 #define _PSR2_SU_STATUS(tran, index) _MMIO(_TRANS2(tran, _PSR2_SU_STATUS_A) + (index) * 4) 2324 #define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3)) 2325 #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10) 2326 #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)) 2327 #define PSR2_SU_STATUS_FRAMES 8 2328 2329 #define _PSR2_MAN_TRK_CTL_A 0x60910 2330 #define _PSR2_MAN_TRK_CTL_EDP 0x6f910 2331 #define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A) 2332 #define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) 2333 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21) 2334 #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 2335 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11) 2336 #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 2337 #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3) 2338 #define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2) 2339 #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1) 2340 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16) 2341 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 2342 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0) 2343 #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 2344 #define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31) 2345 #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14) 2346 #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13) 2347 2348 /* Icelake DSC Rate Control Range Parameter Registers */ 2349 #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240) 2350 #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4) 2351 #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40) 2352 #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4) 2353 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208) 2354 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4) 2355 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308) 2356 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4) 2357 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408) 2358 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4) 2359 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508) 2360 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4) 2361 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2362 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \ 2363 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC) 2364 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2365 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \ 2366 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC) 2367 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2368 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \ 2369 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC) 2370 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2371 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \ 2372 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC) 2373 #define RC_BPG_OFFSET_SHIFT 10 2374 #define RC_MAX_QP_SHIFT 5 2375 #define RC_MIN_QP_SHIFT 0 2376 2377 #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248) 2378 #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4) 2379 #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48) 2380 #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4) 2381 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210) 2382 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4) 2383 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310) 2384 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4) 2385 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410) 2386 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4) 2387 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510) 2388 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4) 2389 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2390 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \ 2391 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC) 2392 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2393 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \ 2394 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC) 2395 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2396 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \ 2397 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC) 2398 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2399 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \ 2400 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC) 2401 2402 #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250) 2403 #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4) 2404 #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50) 2405 #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4) 2406 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218) 2407 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4) 2408 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318) 2409 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4) 2410 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418) 2411 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4) 2412 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518) 2413 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4) 2414 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2415 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \ 2416 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC) 2417 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2418 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \ 2419 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC) 2420 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2421 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \ 2422 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC) 2423 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2424 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \ 2425 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC) 2426 2427 #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258) 2428 #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4) 2429 #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58) 2430 #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4) 2431 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220) 2432 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4) 2433 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320) 2434 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4) 2435 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420) 2436 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4) 2437 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520) 2438 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4) 2439 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2440 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \ 2441 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC) 2442 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2443 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \ 2444 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC) 2445 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2446 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \ 2447 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC) 2448 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 2449 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \ 2450 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC) 2451 2452 /* VGA port control */ 2453 #define ADPA _MMIO(0x61100) 2454 #define PCH_ADPA _MMIO(0xe1100) 2455 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 2456 2457 #define ADPA_DAC_ENABLE (1 << 31) 2458 #define ADPA_DAC_DISABLE 0 2459 #define ADPA_PIPE_SEL_SHIFT 30 2460 #define ADPA_PIPE_SEL_MASK (1 << 30) 2461 #define ADPA_PIPE_SEL(pipe) ((pipe) << 30) 2462 #define ADPA_PIPE_SEL_SHIFT_CPT 29 2463 #define ADPA_PIPE_SEL_MASK_CPT (3 << 29) 2464 #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2465 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 2466 #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24) 2467 #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24) 2468 #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24) 2469 #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24) 2470 #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23) 2471 #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22) 2472 #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22) 2473 #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21) 2474 #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21) 2475 #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20) 2476 #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20) 2477 #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18) 2478 #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18) 2479 #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18) 2480 #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18) 2481 #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17) 2482 #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17) 2483 #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16) 2484 #define ADPA_USE_VGA_HVPOLARITY (1 << 15) 2485 #define ADPA_SETS_HVPOLARITY 0 2486 #define ADPA_VSYNC_CNTL_DISABLE (1 << 10) 2487 #define ADPA_VSYNC_CNTL_ENABLE 0 2488 #define ADPA_HSYNC_CNTL_DISABLE (1 << 11) 2489 #define ADPA_HSYNC_CNTL_ENABLE 0 2490 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) 2491 #define ADPA_VSYNC_ACTIVE_LOW 0 2492 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) 2493 #define ADPA_HSYNC_ACTIVE_LOW 0 2494 #define ADPA_DPMS_MASK (~(3 << 10)) 2495 #define ADPA_DPMS_ON (0 << 10) 2496 #define ADPA_DPMS_SUSPEND (1 << 10) 2497 #define ADPA_DPMS_STANDBY (2 << 10) 2498 #define ADPA_DPMS_OFF (3 << 10) 2499 2500 2501 /* Hotplug control (945+ only) */ 2502 #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) 2503 #define PORTB_HOTPLUG_INT_EN (1 << 29) 2504 #define PORTC_HOTPLUG_INT_EN (1 << 28) 2505 #define PORTD_HOTPLUG_INT_EN (1 << 27) 2506 #define SDVOB_HOTPLUG_INT_EN (1 << 26) 2507 #define SDVOC_HOTPLUG_INT_EN (1 << 25) 2508 #define TV_HOTPLUG_INT_EN (1 << 18) 2509 #define CRT_HOTPLUG_INT_EN (1 << 9) 2510 #define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 2511 PORTC_HOTPLUG_INT_EN | \ 2512 PORTD_HOTPLUG_INT_EN | \ 2513 SDVOC_HOTPLUG_INT_EN | \ 2514 SDVOB_HOTPLUG_INT_EN | \ 2515 CRT_HOTPLUG_INT_EN) 2516 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 2517 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 2518 /* must use period 64 on GM45 according to docs */ 2519 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 2520 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 2521 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 2522 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 2523 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 2524 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 2525 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 2526 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 2527 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 2528 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 2529 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 2530 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 2531 2532 #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) 2533 /* 2534 * HDMI/DP bits are g4x+ 2535 * 2536 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 2537 * Please check the detailed lore in the commit message for for experimental 2538 * evidence. 2539 */ 2540 /* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */ 2541 #define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29) 2542 #define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28) 2543 #define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27) 2544 /* G4X/VLV/CHV DP/HDMI bits again match Bspec */ 2545 #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 2546 #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 2547 #define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 2548 #define PORTD_HOTPLUG_INT_STATUS (3 << 21) 2549 #define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 2550 #define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 2551 #define PORTC_HOTPLUG_INT_STATUS (3 << 19) 2552 #define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 2553 #define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 2554 #define PORTB_HOTPLUG_INT_STATUS (3 << 17) 2555 #define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 2556 #define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 2557 /* CRT/TV common between gen3+ */ 2558 #define CRT_HOTPLUG_INT_STATUS (1 << 11) 2559 #define TV_HOTPLUG_INT_STATUS (1 << 10) 2560 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 2561 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 2562 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 2563 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 2564 #define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 2565 #define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 2566 #define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 2567 #define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 2568 2569 /* SDVO is different across gen3/4 */ 2570 #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 2571 #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 2572 /* 2573 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 2574 * since reality corrobates that they're the same as on gen3. But keep these 2575 * bits here (and the comment!) to help any other lost wanderers back onto the 2576 * right tracks. 2577 */ 2578 #define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 2579 #define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 2580 #define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 2581 #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 2582 #define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 2583 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 2584 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 2585 PORTB_HOTPLUG_INT_STATUS | \ 2586 PORTC_HOTPLUG_INT_STATUS | \ 2587 PORTD_HOTPLUG_INT_STATUS) 2588 2589 #define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 2590 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 2591 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 2592 PORTB_HOTPLUG_INT_STATUS | \ 2593 PORTC_HOTPLUG_INT_STATUS | \ 2594 PORTD_HOTPLUG_INT_STATUS) 2595 2596 /* SDVO and HDMI port control. 2597 * The same register may be used for SDVO or HDMI */ 2598 #define _GEN3_SDVOB 0x61140 2599 #define _GEN3_SDVOC 0x61160 2600 #define GEN3_SDVOB _MMIO(_GEN3_SDVOB) 2601 #define GEN3_SDVOC _MMIO(_GEN3_SDVOC) 2602 #define GEN4_HDMIB GEN3_SDVOB 2603 #define GEN4_HDMIC GEN3_SDVOC 2604 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140) 2605 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160) 2606 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C) 2607 #define PCH_SDVOB _MMIO(0xe1140) 2608 #define PCH_HDMIB PCH_SDVOB 2609 #define PCH_HDMIC _MMIO(0xe1150) 2610 #define PCH_HDMID _MMIO(0xe1160) 2611 2612 #define PORT_DFT_I9XX _MMIO(0x61150) 2613 #define DC_BALANCE_RESET (1 << 25) 2614 #define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) 2615 #define DC_BALANCE_RESET_VLV (1 << 31) 2616 #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) 2617 #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */ 2618 #define PIPE_B_SCRAMBLE_RESET REG_BIT(1) 2619 #define PIPE_A_SCRAMBLE_RESET REG_BIT(0) 2620 2621 /* Gen 3 SDVO bits: */ 2622 #define SDVO_ENABLE (1 << 31) 2623 #define SDVO_PIPE_SEL_SHIFT 30 2624 #define SDVO_PIPE_SEL_MASK (1 << 30) 2625 #define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 2626 #define SDVO_STALL_SELECT (1 << 29) 2627 #define SDVO_INTERRUPT_ENABLE (1 << 26) 2628 /* 2629 * 915G/GM SDVO pixel multiplier. 2630 * Programmed value is multiplier - 1, up to 5x. 2631 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 2632 */ 2633 #define SDVO_PORT_MULTIPLY_MASK (7 << 23) 2634 #define SDVO_PORT_MULTIPLY_SHIFT 23 2635 #define SDVO_PHASE_SELECT_MASK (15 << 19) 2636 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 2637 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 2638 #define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 2639 #define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 2640 #define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 2641 #define SDVO_DETECTED (1 << 2) 2642 /* Bits to be preserved when writing */ 2643 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 2644 SDVO_INTERRUPT_ENABLE) 2645 #define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 2646 2647 /* Gen 4 SDVO/HDMI bits: */ 2648 #define SDVO_COLOR_FORMAT_8bpc (0 << 26) 2649 #define SDVO_COLOR_FORMAT_MASK (7 << 26) 2650 #define SDVO_ENCODING_SDVO (0 << 10) 2651 #define SDVO_ENCODING_HDMI (2 << 10) 2652 #define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 2653 #define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 2654 #define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 2655 #define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */ 2656 /* VSYNC/HSYNC bits new with 965, default is to be set */ 2657 #define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 2658 #define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 2659 2660 /* Gen 5 (IBX) SDVO/HDMI bits: */ 2661 #define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 2662 #define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 2663 2664 /* Gen 6 (CPT) SDVO/HDMI bits: */ 2665 #define SDVO_PIPE_SEL_SHIFT_CPT 29 2666 #define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 2667 #define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2668 2669 /* CHV SDVO/HDMI bits: */ 2670 #define SDVO_PIPE_SEL_SHIFT_CHV 24 2671 #define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 2672 #define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 2673 2674 2675 /* DVO port control */ 2676 #define _DVOA 0x61120 2677 #define DVOA _MMIO(_DVOA) 2678 #define _DVOB 0x61140 2679 #define DVOB _MMIO(_DVOB) 2680 #define _DVOC 0x61160 2681 #define DVOC _MMIO(_DVOC) 2682 #define DVO_ENABLE (1 << 31) 2683 #define DVO_PIPE_SEL_SHIFT 30 2684 #define DVO_PIPE_SEL_MASK (1 << 30) 2685 #define DVO_PIPE_SEL(pipe) ((pipe) << 30) 2686 #define DVO_PIPE_STALL_UNUSED (0 << 28) 2687 #define DVO_PIPE_STALL (1 << 28) 2688 #define DVO_PIPE_STALL_TV (2 << 28) 2689 #define DVO_PIPE_STALL_MASK (3 << 28) 2690 #define DVO_USE_VGA_SYNC (1 << 15) 2691 #define DVO_DATA_ORDER_I740 (0 << 14) 2692 #define DVO_DATA_ORDER_FP (1 << 14) 2693 #define DVO_VSYNC_DISABLE (1 << 11) 2694 #define DVO_HSYNC_DISABLE (1 << 10) 2695 #define DVO_VSYNC_TRISTATE (1 << 9) 2696 #define DVO_HSYNC_TRISTATE (1 << 8) 2697 #define DVO_BORDER_ENABLE (1 << 7) 2698 #define DVO_DATA_ORDER_GBRG (1 << 6) 2699 #define DVO_DATA_ORDER_RGGB (0 << 6) 2700 #define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 2701 #define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 2702 #define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 2703 #define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 2704 #define DVO_BLANK_ACTIVE_HIGH (1 << 2) 2705 #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 2706 #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 2707 #define DVO_PRESERVE_MASK (0x7 << 24) 2708 #define DVOA_SRCDIM _MMIO(0x61124) 2709 #define DVOB_SRCDIM _MMIO(0x61144) 2710 #define DVOC_SRCDIM _MMIO(0x61164) 2711 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12 2712 #define DVO_SRCDIM_VERTICAL_SHIFT 0 2713 2714 /* LVDS port control */ 2715 #define LVDS _MMIO(0x61180) 2716 /* 2717 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 2718 * the DPLL semantics change when the LVDS is assigned to that pipe. 2719 */ 2720 #define LVDS_PORT_EN (1 << 31) 2721 /* Selects pipe B for LVDS data. Must be set on pre-965. */ 2722 #define LVDS_PIPE_SEL_SHIFT 30 2723 #define LVDS_PIPE_SEL_MASK (1 << 30) 2724 #define LVDS_PIPE_SEL(pipe) ((pipe) << 30) 2725 #define LVDS_PIPE_SEL_SHIFT_CPT 29 2726 #define LVDS_PIPE_SEL_MASK_CPT (3 << 29) 2727 #define LVDS_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2728 /* LVDS dithering flag on 965/g4x platform */ 2729 #define LVDS_ENABLE_DITHER (1 << 25) 2730 /* LVDS sync polarity flags. Set to invert (i.e. negative) */ 2731 #define LVDS_VSYNC_POLARITY (1 << 21) 2732 #define LVDS_HSYNC_POLARITY (1 << 20) 2733 2734 /* Enable border for unscaled (or aspect-scaled) display */ 2735 #define LVDS_BORDER_ENABLE (1 << 15) 2736 /* 2737 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 2738 * pixel. 2739 */ 2740 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 2741 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 2742 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 2743 /* 2744 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 2745 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 2746 * on. 2747 */ 2748 #define LVDS_A3_POWER_MASK (3 << 6) 2749 #define LVDS_A3_POWER_DOWN (0 << 6) 2750 #define LVDS_A3_POWER_UP (3 << 6) 2751 /* 2752 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 2753 * is set. 2754 */ 2755 #define LVDS_CLKB_POWER_MASK (3 << 4) 2756 #define LVDS_CLKB_POWER_DOWN (0 << 4) 2757 #define LVDS_CLKB_POWER_UP (3 << 4) 2758 /* 2759 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 2760 * setting for whether we are in dual-channel mode. The B3 pair will 2761 * additionally only be powered up when LVDS_A3_POWER_UP is set. 2762 */ 2763 #define LVDS_B0B3_POWER_MASK (3 << 2) 2764 #define LVDS_B0B3_POWER_DOWN (0 << 2) 2765 #define LVDS_B0B3_POWER_UP (3 << 2) 2766 2767 /* Video Data Island Packet control */ 2768 #define VIDEO_DIP_DATA _MMIO(0x61178) 2769 /* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC 2770 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 2771 * of the infoframe structure specified by CEA-861. */ 2772 #define VIDEO_DIP_DATA_SIZE 32 2773 #define VIDEO_DIP_GMP_DATA_SIZE 36 2774 #define VIDEO_DIP_VSC_DATA_SIZE 36 2775 #define VIDEO_DIP_PPS_DATA_SIZE 132 2776 #define VIDEO_DIP_CTL _MMIO(0x61170) 2777 /* Pre HSW: */ 2778 #define VIDEO_DIP_ENABLE (1 << 31) 2779 #define VIDEO_DIP_PORT(port) ((port) << 29) 2780 #define VIDEO_DIP_PORT_MASK (3 << 29) 2781 #define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */ 2782 #define VIDEO_DIP_ENABLE_AVI (1 << 21) 2783 #define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 2784 #define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */ 2785 #define VIDEO_DIP_ENABLE_SPD (8 << 21) 2786 #define VIDEO_DIP_SELECT_AVI (0 << 19) 2787 #define VIDEO_DIP_SELECT_VENDOR (1 << 19) 2788 #define VIDEO_DIP_SELECT_GAMUT (2 << 19) 2789 #define VIDEO_DIP_SELECT_SPD (3 << 19) 2790 #define VIDEO_DIP_SELECT_MASK (3 << 19) 2791 #define VIDEO_DIP_FREQ_ONCE (0 << 16) 2792 #define VIDEO_DIP_FREQ_VSYNC (1 << 16) 2793 #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 2794 #define VIDEO_DIP_FREQ_MASK (3 << 16) 2795 /* HSW and later: */ 2796 #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) 2797 #define PSR_VSC_BIT_7_SET (1 << 27) 2798 #define VSC_SELECT_MASK (0x3 << 25) 2799 #define VSC_SELECT_SHIFT 25 2800 #define VSC_DIP_HW_HEA_DATA (0 << 25) 2801 #define VSC_DIP_HW_HEA_SW_DATA (1 << 25) 2802 #define VSC_DIP_HW_DATA_SW_HEA (2 << 25) 2803 #define VSC_DIP_SW_HEA_DATA (3 << 25) 2804 #define VDIP_ENABLE_PPS (1 << 24) 2805 #define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 2806 #define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 2807 #define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 2808 #define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 2809 #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 2810 #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 2811 2812 /* Panel power sequencing */ 2813 #define PPS_BASE 0x61200 2814 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) 2815 #define PCH_PPS_BASE 0xC7200 2816 2817 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \ 2818 PPS_BASE + (reg) + \ 2819 (pps_idx) * 0x100) 2820 2821 #define _PP_STATUS 0x61200 2822 #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) 2823 #define PP_ON REG_BIT(31) 2824 /* 2825 * Indicates that all dependencies of the panel are on: 2826 * 2827 * - PLL enabled 2828 * - pipe enabled 2829 * - LVDS/DVOB/DVOC on 2830 */ 2831 #define PP_READY REG_BIT(30) 2832 #define PP_SEQUENCE_MASK REG_GENMASK(29, 28) 2833 #define PP_SEQUENCE_NONE REG_FIELD_PREP(PP_SEQUENCE_MASK, 0) 2834 #define PP_SEQUENCE_POWER_UP REG_FIELD_PREP(PP_SEQUENCE_MASK, 1) 2835 #define PP_SEQUENCE_POWER_DOWN REG_FIELD_PREP(PP_SEQUENCE_MASK, 2) 2836 #define PP_CYCLE_DELAY_ACTIVE REG_BIT(27) 2837 #define PP_SEQUENCE_STATE_MASK REG_GENMASK(3, 0) 2838 #define PP_SEQUENCE_STATE_OFF_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x0) 2839 #define PP_SEQUENCE_STATE_OFF_S0_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x1) 2840 #define PP_SEQUENCE_STATE_OFF_S0_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x2) 2841 #define PP_SEQUENCE_STATE_OFF_S0_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x3) 2842 #define PP_SEQUENCE_STATE_ON_IDLE REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x8) 2843 #define PP_SEQUENCE_STATE_ON_S1_1 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0x9) 2844 #define PP_SEQUENCE_STATE_ON_S1_2 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xa) 2845 #define PP_SEQUENCE_STATE_ON_S1_3 REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xb) 2846 #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf) 2847 2848 #define _PP_CONTROL 0x61204 2849 #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) 2850 #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16) 2851 #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd) 2852 #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) 2853 #define EDP_FORCE_VDD REG_BIT(3) 2854 #define EDP_BLC_ENABLE REG_BIT(2) 2855 #define PANEL_POWER_RESET REG_BIT(1) 2856 #define PANEL_POWER_ON REG_BIT(0) 2857 2858 #define _PP_ON_DELAYS 0x61208 2859 #define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) 2860 #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30) 2861 #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0) 2862 #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1) 2863 #define PANEL_PORT_SELECT_DPC REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 2) 2864 #define PANEL_PORT_SELECT_DPD REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 3) 2865 #define PANEL_PORT_SELECT_VLV(port) REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, port) 2866 #define PANEL_POWER_UP_DELAY_MASK REG_GENMASK(28, 16) 2867 #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0) 2868 2869 #define _PP_OFF_DELAYS 0x6120C 2870 #define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS) 2871 #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16) 2872 #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0) 2873 2874 #define _PP_DIVISOR 0x61210 2875 #define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR) 2876 #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8) 2877 #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) 2878 2879 /* Panel fitting */ 2880 #define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) 2881 #define PFIT_ENABLE (1 << 31) 2882 #define PFIT_PIPE_MASK (3 << 29) 2883 #define PFIT_PIPE_SHIFT 29 2884 #define PFIT_PIPE(pipe) ((pipe) << 29) 2885 #define VERT_INTERP_DISABLE (0 << 10) 2886 #define VERT_INTERP_BILINEAR (1 << 10) 2887 #define VERT_INTERP_MASK (3 << 10) 2888 #define VERT_AUTO_SCALE (1 << 9) 2889 #define HORIZ_INTERP_DISABLE (0 << 6) 2890 #define HORIZ_INTERP_BILINEAR (1 << 6) 2891 #define HORIZ_INTERP_MASK (3 << 6) 2892 #define HORIZ_AUTO_SCALE (1 << 5) 2893 #define PANEL_8TO6_DITHER_ENABLE (1 << 3) 2894 #define PFIT_FILTER_FUZZY (0 << 24) 2895 #define PFIT_SCALING_AUTO (0 << 26) 2896 #define PFIT_SCALING_PROGRAMMED (1 << 26) 2897 #define PFIT_SCALING_PILLAR (2 << 26) 2898 #define PFIT_SCALING_LETTER (3 << 26) 2899 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) 2900 /* Pre-965 */ 2901 #define PFIT_VERT_SCALE_SHIFT 20 2902 #define PFIT_VERT_SCALE_MASK 0xfff00000 2903 #define PFIT_HORIZ_SCALE_SHIFT 4 2904 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0 2905 /* 965+ */ 2906 #define PFIT_VERT_SCALE_SHIFT_965 16 2907 #define PFIT_VERT_SCALE_MASK_965 0x1fff0000 2908 #define PFIT_HORIZ_SCALE_SHIFT_965 0 2909 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 2910 2911 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) 2912 2913 #define _VLV_BLC_PWM_CTL2_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61250) 2914 #define _VLV_BLC_PWM_CTL2_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61350) 2915 #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ 2916 _VLV_BLC_PWM_CTL2_B) 2917 2918 #define _VLV_BLC_PWM_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61254) 2919 #define _VLV_BLC_PWM_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61354) 2920 #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ 2921 _VLV_BLC_PWM_CTL_B) 2922 2923 #define _VLV_BLC_HIST_CTL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x61260) 2924 #define _VLV_BLC_HIST_CTL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x61360) 2925 #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ 2926 _VLV_BLC_HIST_CTL_B) 2927 2928 /* Backlight control */ 2929 #define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */ 2930 #define BLM_PWM_ENABLE (1 << 31) 2931 #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ 2932 #define BLM_PIPE_SELECT (1 << 29) 2933 #define BLM_PIPE_SELECT_IVB (3 << 29) 2934 #define BLM_PIPE_A (0 << 29) 2935 #define BLM_PIPE_B (1 << 29) 2936 #define BLM_PIPE_C (2 << 29) /* ivb + */ 2937 #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ 2938 #define BLM_TRANSCODER_B BLM_PIPE_B 2939 #define BLM_TRANSCODER_C BLM_PIPE_C 2940 #define BLM_TRANSCODER_EDP (3 << 29) 2941 #define BLM_PIPE(pipe) ((pipe) << 29) 2942 #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ 2943 #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) 2944 #define BLM_PHASE_IN_ENABLE (1 << 25) 2945 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) 2946 #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) 2947 #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) 2948 #define BLM_PHASE_IN_COUNT_SHIFT (8) 2949 #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) 2950 #define BLM_PHASE_IN_INCR_SHIFT (0) 2951 #define BLM_PHASE_IN_INCR_MASK (0xff << 0) 2952 #define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254) 2953 /* 2954 * This is the most significant 15 bits of the number of backlight cycles in a 2955 * complete cycle of the modulated backlight control. 2956 * 2957 * The actual value is this field multiplied by two. 2958 */ 2959 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 2960 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 2961 #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ 2962 /* 2963 * This is the number of cycles out of the backlight modulation cycle for which 2964 * the backlight is on. 2965 * 2966 * This field must be no greater than the number of cycles in the complete 2967 * backlight modulation cycle. 2968 */ 2969 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 2970 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 2971 #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) 2972 #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ 2973 2974 #define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260) 2975 #define BLM_HISTOGRAM_ENABLE (1 << 31) 2976 2977 /* New registers for PCH-split platforms. Safe where new bits show up, the 2978 * register layout machtes with gen4 BLC_PWM_CTL[12]. */ 2979 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250) 2980 #define BLC_PWM_CPU_CTL _MMIO(0x48254) 2981 2982 #define HSW_BLC_PWM2_CTL _MMIO(0x48350) 2983 2984 /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is 2985 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ 2986 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250) 2987 #define BLM_PCH_PWM_ENABLE (1 << 31) 2988 #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) 2989 #define BLM_PCH_POLARITY (1 << 29) 2990 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254) 2991 2992 #define UTIL_PIN_CTL _MMIO(0x48400) 2993 #define UTIL_PIN_ENABLE (1 << 31) 2994 #define UTIL_PIN_PIPE_MASK (3 << 29) 2995 #define UTIL_PIN_PIPE(x) ((x) << 29) 2996 #define UTIL_PIN_MODE_MASK (0xf << 24) 2997 #define UTIL_PIN_MODE_DATA (0 << 24) 2998 #define UTIL_PIN_MODE_PWM (1 << 24) 2999 #define UTIL_PIN_MODE_VBLANK (4 << 24) 3000 #define UTIL_PIN_MODE_VSYNC (5 << 24) 3001 #define UTIL_PIN_MODE_EYE_LEVEL (8 << 24) 3002 #define UTIL_PIN_OUTPUT_DATA (1 << 23) 3003 #define UTIL_PIN_POLARITY (1 << 22) 3004 #define UTIL_PIN_DIRECTION_INPUT (1 << 19) 3005 #define UTIL_PIN_INPUT_DATA (1 << 16) 3006 3007 /* BXT backlight register definition. */ 3008 #define _BXT_BLC_PWM_CTL1 0xC8250 3009 #define BXT_BLC_PWM_ENABLE (1 << 31) 3010 #define BXT_BLC_PWM_POLARITY (1 << 29) 3011 #define _BXT_BLC_PWM_FREQ1 0xC8254 3012 #define _BXT_BLC_PWM_DUTY1 0xC8258 3013 3014 #define _BXT_BLC_PWM_CTL2 0xC8350 3015 #define _BXT_BLC_PWM_FREQ2 0xC8354 3016 #define _BXT_BLC_PWM_DUTY2 0xC8358 3017 3018 #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \ 3019 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2) 3020 #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \ 3021 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2) 3022 #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \ 3023 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2) 3024 3025 #define PCH_GTC_CTL _MMIO(0xe7000) 3026 #define PCH_GTC_ENABLE (1 << 31) 3027 3028 /* TV port control */ 3029 #define TV_CTL _MMIO(0x68000) 3030 /* Enables the TV encoder */ 3031 # define TV_ENC_ENABLE (1 << 31) 3032 /* Sources the TV encoder input from pipe B instead of A. */ 3033 # define TV_ENC_PIPE_SEL_SHIFT 30 3034 # define TV_ENC_PIPE_SEL_MASK (1 << 30) 3035 # define TV_ENC_PIPE_SEL(pipe) ((pipe) << 30) 3036 /* Outputs composite video (DAC A only) */ 3037 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 3038 /* Outputs SVideo video (DAC B/C) */ 3039 # define TV_ENC_OUTPUT_SVIDEO (1 << 28) 3040 /* Outputs Component video (DAC A/B/C) */ 3041 # define TV_ENC_OUTPUT_COMPONENT (2 << 28) 3042 /* Outputs Composite and SVideo (DAC A/B/C) */ 3043 # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 3044 # define TV_TRILEVEL_SYNC (1 << 21) 3045 /* Enables slow sync generation (945GM only) */ 3046 # define TV_SLOW_SYNC (1 << 20) 3047 /* Selects 4x oversampling for 480i and 576p */ 3048 # define TV_OVERSAMPLE_4X (0 << 18) 3049 /* Selects 2x oversampling for 720p and 1080i */ 3050 # define TV_OVERSAMPLE_2X (1 << 18) 3051 /* Selects no oversampling for 1080p */ 3052 # define TV_OVERSAMPLE_NONE (2 << 18) 3053 /* Selects 8x oversampling */ 3054 # define TV_OVERSAMPLE_8X (3 << 18) 3055 # define TV_OVERSAMPLE_MASK (3 << 18) 3056 /* Selects progressive mode rather than interlaced */ 3057 # define TV_PROGRESSIVE (1 << 17) 3058 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 3059 # define TV_PAL_BURST (1 << 16) 3060 /* Field for setting delay of Y compared to C */ 3061 # define TV_YC_SKEW_MASK (7 << 12) 3062 /* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 3063 # define TV_ENC_SDP_FIX (1 << 11) 3064 /* 3065 * Enables a fix for the 915GM only. 3066 * 3067 * Not sure what it does. 3068 */ 3069 # define TV_ENC_C0_FIX (1 << 10) 3070 /* Bits that must be preserved by software */ 3071 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 3072 # define TV_FUSE_STATE_MASK (3 << 4) 3073 /* Read-only state that reports all features enabled */ 3074 # define TV_FUSE_STATE_ENABLED (0 << 4) 3075 /* Read-only state that reports that Macrovision is disabled in hardware*/ 3076 # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 3077 /* Read-only state that reports that TV-out is disabled in hardware. */ 3078 # define TV_FUSE_STATE_DISABLED (2 << 4) 3079 /* Normal operation */ 3080 # define TV_TEST_MODE_NORMAL (0 << 0) 3081 /* Encoder test pattern 1 - combo pattern */ 3082 # define TV_TEST_MODE_PATTERN_1 (1 << 0) 3083 /* Encoder test pattern 2 - full screen vertical 75% color bars */ 3084 # define TV_TEST_MODE_PATTERN_2 (2 << 0) 3085 /* Encoder test pattern 3 - full screen horizontal 75% color bars */ 3086 # define TV_TEST_MODE_PATTERN_3 (3 << 0) 3087 /* Encoder test pattern 4 - random noise */ 3088 # define TV_TEST_MODE_PATTERN_4 (4 << 0) 3089 /* Encoder test pattern 5 - linear color ramps */ 3090 # define TV_TEST_MODE_PATTERN_5 (5 << 0) 3091 /* 3092 * This test mode forces the DACs to 50% of full output. 3093 * 3094 * This is used for load detection in combination with TVDAC_SENSE_MASK 3095 */ 3096 # define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 3097 # define TV_TEST_MODE_MASK (7 << 0) 3098 3099 #define TV_DAC _MMIO(0x68004) 3100 # define TV_DAC_SAVE 0x00ffff00 3101 /* 3102 * Reports that DAC state change logic has reported change (RO). 3103 * 3104 * This gets cleared when TV_DAC_STATE_EN is cleared 3105 */ 3106 # define TVDAC_STATE_CHG (1 << 31) 3107 # define TVDAC_SENSE_MASK (7 << 28) 3108 /* Reports that DAC A voltage is above the detect threshold */ 3109 # define TVDAC_A_SENSE (1 << 30) 3110 /* Reports that DAC B voltage is above the detect threshold */ 3111 # define TVDAC_B_SENSE (1 << 29) 3112 /* Reports that DAC C voltage is above the detect threshold */ 3113 # define TVDAC_C_SENSE (1 << 28) 3114 /* 3115 * Enables DAC state detection logic, for load-based TV detection. 3116 * 3117 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 3118 * to off, for load detection to work. 3119 */ 3120 # define TVDAC_STATE_CHG_EN (1 << 27) 3121 /* Sets the DAC A sense value to high */ 3122 # define TVDAC_A_SENSE_CTL (1 << 26) 3123 /* Sets the DAC B sense value to high */ 3124 # define TVDAC_B_SENSE_CTL (1 << 25) 3125 /* Sets the DAC C sense value to high */ 3126 # define TVDAC_C_SENSE_CTL (1 << 24) 3127 /* Overrides the ENC_ENABLE and DAC voltage levels */ 3128 # define DAC_CTL_OVERRIDE (1 << 7) 3129 /* Sets the slew rate. Must be preserved in software */ 3130 # define ENC_TVDAC_SLEW_FAST (1 << 6) 3131 # define DAC_A_1_3_V (0 << 4) 3132 # define DAC_A_1_1_V (1 << 4) 3133 # define DAC_A_0_7_V (2 << 4) 3134 # define DAC_A_MASK (3 << 4) 3135 # define DAC_B_1_3_V (0 << 2) 3136 # define DAC_B_1_1_V (1 << 2) 3137 # define DAC_B_0_7_V (2 << 2) 3138 # define DAC_B_MASK (3 << 2) 3139 # define DAC_C_1_3_V (0 << 0) 3140 # define DAC_C_1_1_V (1 << 0) 3141 # define DAC_C_0_7_V (2 << 0) 3142 # define DAC_C_MASK (3 << 0) 3143 3144 /* 3145 * CSC coefficients are stored in a floating point format with 9 bits of 3146 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 3147 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 3148 * -1 (0x3) being the only legal negative value. 3149 */ 3150 #define TV_CSC_Y _MMIO(0x68010) 3151 # define TV_RY_MASK 0x07ff0000 3152 # define TV_RY_SHIFT 16 3153 # define TV_GY_MASK 0x00000fff 3154 # define TV_GY_SHIFT 0 3155 3156 #define TV_CSC_Y2 _MMIO(0x68014) 3157 # define TV_BY_MASK 0x07ff0000 3158 # define TV_BY_SHIFT 16 3159 /* 3160 * Y attenuation for component video. 3161 * 3162 * Stored in 1.9 fixed point. 3163 */ 3164 # define TV_AY_MASK 0x000003ff 3165 # define TV_AY_SHIFT 0 3166 3167 #define TV_CSC_U _MMIO(0x68018) 3168 # define TV_RU_MASK 0x07ff0000 3169 # define TV_RU_SHIFT 16 3170 # define TV_GU_MASK 0x000007ff 3171 # define TV_GU_SHIFT 0 3172 3173 #define TV_CSC_U2 _MMIO(0x6801c) 3174 # define TV_BU_MASK 0x07ff0000 3175 # define TV_BU_SHIFT 16 3176 /* 3177 * U attenuation for component video. 3178 * 3179 * Stored in 1.9 fixed point. 3180 */ 3181 # define TV_AU_MASK 0x000003ff 3182 # define TV_AU_SHIFT 0 3183 3184 #define TV_CSC_V _MMIO(0x68020) 3185 # define TV_RV_MASK 0x0fff0000 3186 # define TV_RV_SHIFT 16 3187 # define TV_GV_MASK 0x000007ff 3188 # define TV_GV_SHIFT 0 3189 3190 #define TV_CSC_V2 _MMIO(0x68024) 3191 # define TV_BV_MASK 0x07ff0000 3192 # define TV_BV_SHIFT 16 3193 /* 3194 * V attenuation for component video. 3195 * 3196 * Stored in 1.9 fixed point. 3197 */ 3198 # define TV_AV_MASK 0x000007ff 3199 # define TV_AV_SHIFT 0 3200 3201 #define TV_CLR_KNOBS _MMIO(0x68028) 3202 /* 2s-complement brightness adjustment */ 3203 # define TV_BRIGHTNESS_MASK 0xff000000 3204 # define TV_BRIGHTNESS_SHIFT 24 3205 /* Contrast adjustment, as a 2.6 unsigned floating point number */ 3206 # define TV_CONTRAST_MASK 0x00ff0000 3207 # define TV_CONTRAST_SHIFT 16 3208 /* Saturation adjustment, as a 2.6 unsigned floating point number */ 3209 # define TV_SATURATION_MASK 0x0000ff00 3210 # define TV_SATURATION_SHIFT 8 3211 /* Hue adjustment, as an integer phase angle in degrees */ 3212 # define TV_HUE_MASK 0x000000ff 3213 # define TV_HUE_SHIFT 0 3214 3215 #define TV_CLR_LEVEL _MMIO(0x6802c) 3216 /* Controls the DAC level for black */ 3217 # define TV_BLACK_LEVEL_MASK 0x01ff0000 3218 # define TV_BLACK_LEVEL_SHIFT 16 3219 /* Controls the DAC level for blanking */ 3220 # define TV_BLANK_LEVEL_MASK 0x000001ff 3221 # define TV_BLANK_LEVEL_SHIFT 0 3222 3223 #define TV_H_CTL_1 _MMIO(0x68030) 3224 /* Number of pixels in the hsync. */ 3225 # define TV_HSYNC_END_MASK 0x1fff0000 3226 # define TV_HSYNC_END_SHIFT 16 3227 /* Total number of pixels minus one in the line (display and blanking). */ 3228 # define TV_HTOTAL_MASK 0x00001fff 3229 # define TV_HTOTAL_SHIFT 0 3230 3231 #define TV_H_CTL_2 _MMIO(0x68034) 3232 /* Enables the colorburst (needed for non-component color) */ 3233 # define TV_BURST_ENA (1 << 31) 3234 /* Offset of the colorburst from the start of hsync, in pixels minus one. */ 3235 # define TV_HBURST_START_SHIFT 16 3236 # define TV_HBURST_START_MASK 0x1fff0000 3237 /* Length of the colorburst */ 3238 # define TV_HBURST_LEN_SHIFT 0 3239 # define TV_HBURST_LEN_MASK 0x0001fff 3240 3241 #define TV_H_CTL_3 _MMIO(0x68038) 3242 /* End of hblank, measured in pixels minus one from start of hsync */ 3243 # define TV_HBLANK_END_SHIFT 16 3244 # define TV_HBLANK_END_MASK 0x1fff0000 3245 /* Start of hblank, measured in pixels minus one from start of hsync */ 3246 # define TV_HBLANK_START_SHIFT 0 3247 # define TV_HBLANK_START_MASK 0x0001fff 3248 3249 #define TV_V_CTL_1 _MMIO(0x6803c) 3250 /* XXX */ 3251 # define TV_NBR_END_SHIFT 16 3252 # define TV_NBR_END_MASK 0x07ff0000 3253 /* XXX */ 3254 # define TV_VI_END_F1_SHIFT 8 3255 # define TV_VI_END_F1_MASK 0x00003f00 3256 /* XXX */ 3257 # define TV_VI_END_F2_SHIFT 0 3258 # define TV_VI_END_F2_MASK 0x0000003f 3259 3260 #define TV_V_CTL_2 _MMIO(0x68040) 3261 /* Length of vsync, in half lines */ 3262 # define TV_VSYNC_LEN_MASK 0x07ff0000 3263 # define TV_VSYNC_LEN_SHIFT 16 3264 /* Offset of the start of vsync in field 1, measured in one less than the 3265 * number of half lines. 3266 */ 3267 # define TV_VSYNC_START_F1_MASK 0x00007f00 3268 # define TV_VSYNC_START_F1_SHIFT 8 3269 /* 3270 * Offset of the start of vsync in field 2, measured in one less than the 3271 * number of half lines. 3272 */ 3273 # define TV_VSYNC_START_F2_MASK 0x0000007f 3274 # define TV_VSYNC_START_F2_SHIFT 0 3275 3276 #define TV_V_CTL_3 _MMIO(0x68044) 3277 /* Enables generation of the equalization signal */ 3278 # define TV_EQUAL_ENA (1 << 31) 3279 /* Length of vsync, in half lines */ 3280 # define TV_VEQ_LEN_MASK 0x007f0000 3281 # define TV_VEQ_LEN_SHIFT 16 3282 /* Offset of the start of equalization in field 1, measured in one less than 3283 * the number of half lines. 3284 */ 3285 # define TV_VEQ_START_F1_MASK 0x0007f00 3286 # define TV_VEQ_START_F1_SHIFT 8 3287 /* 3288 * Offset of the start of equalization in field 2, measured in one less than 3289 * the number of half lines. 3290 */ 3291 # define TV_VEQ_START_F2_MASK 0x000007f 3292 # define TV_VEQ_START_F2_SHIFT 0 3293 3294 #define TV_V_CTL_4 _MMIO(0x68048) 3295 /* 3296 * Offset to start of vertical colorburst, measured in one less than the 3297 * number of lines from vertical start. 3298 */ 3299 # define TV_VBURST_START_F1_MASK 0x003f0000 3300 # define TV_VBURST_START_F1_SHIFT 16 3301 /* 3302 * Offset to the end of vertical colorburst, measured in one less than the 3303 * number of lines from the start of NBR. 3304 */ 3305 # define TV_VBURST_END_F1_MASK 0x000000ff 3306 # define TV_VBURST_END_F1_SHIFT 0 3307 3308 #define TV_V_CTL_5 _MMIO(0x6804c) 3309 /* 3310 * Offset to start of vertical colorburst, measured in one less than the 3311 * number of lines from vertical start. 3312 */ 3313 # define TV_VBURST_START_F2_MASK 0x003f0000 3314 # define TV_VBURST_START_F2_SHIFT 16 3315 /* 3316 * Offset to the end of vertical colorburst, measured in one less than the 3317 * number of lines from the start of NBR. 3318 */ 3319 # define TV_VBURST_END_F2_MASK 0x000000ff 3320 # define TV_VBURST_END_F2_SHIFT 0 3321 3322 #define TV_V_CTL_6 _MMIO(0x68050) 3323 /* 3324 * Offset to start of vertical colorburst, measured in one less than the 3325 * number of lines from vertical start. 3326 */ 3327 # define TV_VBURST_START_F3_MASK 0x003f0000 3328 # define TV_VBURST_START_F3_SHIFT 16 3329 /* 3330 * Offset to the end of vertical colorburst, measured in one less than the 3331 * number of lines from the start of NBR. 3332 */ 3333 # define TV_VBURST_END_F3_MASK 0x000000ff 3334 # define TV_VBURST_END_F3_SHIFT 0 3335 3336 #define TV_V_CTL_7 _MMIO(0x68054) 3337 /* 3338 * Offset to start of vertical colorburst, measured in one less than the 3339 * number of lines from vertical start. 3340 */ 3341 # define TV_VBURST_START_F4_MASK 0x003f0000 3342 # define TV_VBURST_START_F4_SHIFT 16 3343 /* 3344 * Offset to the end of vertical colorburst, measured in one less than the 3345 * number of lines from the start of NBR. 3346 */ 3347 # define TV_VBURST_END_F4_MASK 0x000000ff 3348 # define TV_VBURST_END_F4_SHIFT 0 3349 3350 #define TV_SC_CTL_1 _MMIO(0x68060) 3351 /* Turns on the first subcarrier phase generation DDA */ 3352 # define TV_SC_DDA1_EN (1 << 31) 3353 /* Turns on the first subcarrier phase generation DDA */ 3354 # define TV_SC_DDA2_EN (1 << 30) 3355 /* Turns on the first subcarrier phase generation DDA */ 3356 # define TV_SC_DDA3_EN (1 << 29) 3357 /* Sets the subcarrier DDA to reset frequency every other field */ 3358 # define TV_SC_RESET_EVERY_2 (0 << 24) 3359 /* Sets the subcarrier DDA to reset frequency every fourth field */ 3360 # define TV_SC_RESET_EVERY_4 (1 << 24) 3361 /* Sets the subcarrier DDA to reset frequency every eighth field */ 3362 # define TV_SC_RESET_EVERY_8 (2 << 24) 3363 /* Sets the subcarrier DDA to never reset the frequency */ 3364 # define TV_SC_RESET_NEVER (3 << 24) 3365 /* Sets the peak amplitude of the colorburst.*/ 3366 # define TV_BURST_LEVEL_MASK 0x00ff0000 3367 # define TV_BURST_LEVEL_SHIFT 16 3368 /* Sets the increment of the first subcarrier phase generation DDA */ 3369 # define TV_SCDDA1_INC_MASK 0x00000fff 3370 # define TV_SCDDA1_INC_SHIFT 0 3371 3372 #define TV_SC_CTL_2 _MMIO(0x68064) 3373 /* Sets the rollover for the second subcarrier phase generation DDA */ 3374 # define TV_SCDDA2_SIZE_MASK 0x7fff0000 3375 # define TV_SCDDA2_SIZE_SHIFT 16 3376 /* Sets the increent of the second subcarrier phase generation DDA */ 3377 # define TV_SCDDA2_INC_MASK 0x00007fff 3378 # define TV_SCDDA2_INC_SHIFT 0 3379 3380 #define TV_SC_CTL_3 _MMIO(0x68068) 3381 /* Sets the rollover for the third subcarrier phase generation DDA */ 3382 # define TV_SCDDA3_SIZE_MASK 0x7fff0000 3383 # define TV_SCDDA3_SIZE_SHIFT 16 3384 /* Sets the increent of the third subcarrier phase generation DDA */ 3385 # define TV_SCDDA3_INC_MASK 0x00007fff 3386 # define TV_SCDDA3_INC_SHIFT 0 3387 3388 #define TV_WIN_POS _MMIO(0x68070) 3389 /* X coordinate of the display from the start of horizontal active */ 3390 # define TV_XPOS_MASK 0x1fff0000 3391 # define TV_XPOS_SHIFT 16 3392 /* Y coordinate of the display from the start of vertical active (NBR) */ 3393 # define TV_YPOS_MASK 0x00000fff 3394 # define TV_YPOS_SHIFT 0 3395 3396 #define TV_WIN_SIZE _MMIO(0x68074) 3397 /* Horizontal size of the display window, measured in pixels*/ 3398 # define TV_XSIZE_MASK 0x1fff0000 3399 # define TV_XSIZE_SHIFT 16 3400 /* 3401 * Vertical size of the display window, measured in pixels. 3402 * 3403 * Must be even for interlaced modes. 3404 */ 3405 # define TV_YSIZE_MASK 0x00000fff 3406 # define TV_YSIZE_SHIFT 0 3407 3408 #define TV_FILTER_CTL_1 _MMIO(0x68080) 3409 /* 3410 * Enables automatic scaling calculation. 3411 * 3412 * If set, the rest of the registers are ignored, and the calculated values can 3413 * be read back from the register. 3414 */ 3415 # define TV_AUTO_SCALE (1 << 31) 3416 /* 3417 * Disables the vertical filter. 3418 * 3419 * This is required on modes more than 1024 pixels wide */ 3420 # define TV_V_FILTER_BYPASS (1 << 29) 3421 /* Enables adaptive vertical filtering */ 3422 # define TV_VADAPT (1 << 28) 3423 # define TV_VADAPT_MODE_MASK (3 << 26) 3424 /* Selects the least adaptive vertical filtering mode */ 3425 # define TV_VADAPT_MODE_LEAST (0 << 26) 3426 /* Selects the moderately adaptive vertical filtering mode */ 3427 # define TV_VADAPT_MODE_MODERATE (1 << 26) 3428 /* Selects the most adaptive vertical filtering mode */ 3429 # define TV_VADAPT_MODE_MOST (3 << 26) 3430 /* 3431 * Sets the horizontal scaling factor. 3432 * 3433 * This should be the fractional part of the horizontal scaling factor divided 3434 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 3435 * 3436 * (src width - 1) / ((oversample * dest width) - 1) 3437 */ 3438 # define TV_HSCALE_FRAC_MASK 0x00003fff 3439 # define TV_HSCALE_FRAC_SHIFT 0 3440 3441 #define TV_FILTER_CTL_2 _MMIO(0x68084) 3442 /* 3443 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3444 * 3445 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 3446 */ 3447 # define TV_VSCALE_INT_MASK 0x00038000 3448 # define TV_VSCALE_INT_SHIFT 15 3449 /* 3450 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3451 * 3452 * \sa TV_VSCALE_INT_MASK 3453 */ 3454 # define TV_VSCALE_FRAC_MASK 0x00007fff 3455 # define TV_VSCALE_FRAC_SHIFT 0 3456 3457 #define TV_FILTER_CTL_3 _MMIO(0x68088) 3458 /* 3459 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3460 * 3461 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 3462 * 3463 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3464 */ 3465 # define TV_VSCALE_IP_INT_MASK 0x00038000 3466 # define TV_VSCALE_IP_INT_SHIFT 15 3467 /* 3468 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3469 * 3470 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3471 * 3472 * \sa TV_VSCALE_IP_INT_MASK 3473 */ 3474 # define TV_VSCALE_IP_FRAC_MASK 0x00007fff 3475 # define TV_VSCALE_IP_FRAC_SHIFT 0 3476 3477 #define TV_CC_CONTROL _MMIO(0x68090) 3478 # define TV_CC_ENABLE (1 << 31) 3479 /* 3480 * Specifies which field to send the CC data in. 3481 * 3482 * CC data is usually sent in field 0. 3483 */ 3484 # define TV_CC_FID_MASK (1 << 27) 3485 # define TV_CC_FID_SHIFT 27 3486 /* Sets the horizontal position of the CC data. Usually 135. */ 3487 # define TV_CC_HOFF_MASK 0x03ff0000 3488 # define TV_CC_HOFF_SHIFT 16 3489 /* Sets the vertical position of the CC data. Usually 21 */ 3490 # define TV_CC_LINE_MASK 0x0000003f 3491 # define TV_CC_LINE_SHIFT 0 3492 3493 #define TV_CC_DATA _MMIO(0x68094) 3494 # define TV_CC_RDY (1 << 31) 3495 /* Second word of CC data to be transmitted. */ 3496 # define TV_CC_DATA_2_MASK 0x007f0000 3497 # define TV_CC_DATA_2_SHIFT 16 3498 /* First word of CC data to be transmitted. */ 3499 # define TV_CC_DATA_1_MASK 0x0000007f 3500 # define TV_CC_DATA_1_SHIFT 0 3501 3502 #define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */ 3503 #define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */ 3504 #define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */ 3505 #define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */ 3506 3507 /* Display Port */ 3508 #define DP_A _MMIO(0x64000) /* eDP */ 3509 #define DP_B _MMIO(0x64100) 3510 #define DP_C _MMIO(0x64200) 3511 #define DP_D _MMIO(0x64300) 3512 3513 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100) 3514 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200) 3515 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300) 3516 3517 #define DP_PORT_EN (1 << 31) 3518 #define DP_PIPE_SEL_SHIFT 30 3519 #define DP_PIPE_SEL_MASK (1 << 30) 3520 #define DP_PIPE_SEL(pipe) ((pipe) << 30) 3521 #define DP_PIPE_SEL_SHIFT_IVB 29 3522 #define DP_PIPE_SEL_MASK_IVB (3 << 29) 3523 #define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29) 3524 #define DP_PIPE_SEL_SHIFT_CHV 16 3525 #define DP_PIPE_SEL_MASK_CHV (3 << 16) 3526 #define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16) 3527 3528 /* Link training mode - select a suitable mode for each stage */ 3529 #define DP_LINK_TRAIN_PAT_1 (0 << 28) 3530 #define DP_LINK_TRAIN_PAT_2 (1 << 28) 3531 #define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 3532 #define DP_LINK_TRAIN_OFF (3 << 28) 3533 #define DP_LINK_TRAIN_MASK (3 << 28) 3534 #define DP_LINK_TRAIN_SHIFT 28 3535 3536 /* CPT Link training mode */ 3537 #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 3538 #define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 3539 #define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 3540 #define DP_LINK_TRAIN_OFF_CPT (3 << 8) 3541 #define DP_LINK_TRAIN_MASK_CPT (7 << 8) 3542 #define DP_LINK_TRAIN_SHIFT_CPT 8 3543 3544 /* Signal voltages. These are mostly controlled by the other end */ 3545 #define DP_VOLTAGE_0_4 (0 << 25) 3546 #define DP_VOLTAGE_0_6 (1 << 25) 3547 #define DP_VOLTAGE_0_8 (2 << 25) 3548 #define DP_VOLTAGE_1_2 (3 << 25) 3549 #define DP_VOLTAGE_MASK (7 << 25) 3550 #define DP_VOLTAGE_SHIFT 25 3551 3552 /* Signal pre-emphasis levels, like voltages, the other end tells us what 3553 * they want 3554 */ 3555 #define DP_PRE_EMPHASIS_0 (0 << 22) 3556 #define DP_PRE_EMPHASIS_3_5 (1 << 22) 3557 #define DP_PRE_EMPHASIS_6 (2 << 22) 3558 #define DP_PRE_EMPHASIS_9_5 (3 << 22) 3559 #define DP_PRE_EMPHASIS_MASK (7 << 22) 3560 #define DP_PRE_EMPHASIS_SHIFT 22 3561 3562 /* How many wires to use. I guess 3 was too hard */ 3563 #define DP_PORT_WIDTH(width) (((width) - 1) << 19) 3564 #define DP_PORT_WIDTH_MASK (7 << 19) 3565 #define DP_PORT_WIDTH_SHIFT 19 3566 3567 /* Mystic DPCD version 1.1 special mode */ 3568 #define DP_ENHANCED_FRAMING (1 << 18) 3569 3570 /* eDP */ 3571 #define DP_PLL_FREQ_270MHZ (0 << 16) 3572 #define DP_PLL_FREQ_162MHZ (1 << 16) 3573 #define DP_PLL_FREQ_MASK (3 << 16) 3574 3575 /* locked once port is enabled */ 3576 #define DP_PORT_REVERSAL (1 << 15) 3577 3578 /* eDP */ 3579 #define DP_PLL_ENABLE (1 << 14) 3580 3581 /* sends the clock on lane 15 of the PEG for debug */ 3582 #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 3583 3584 #define DP_SCRAMBLING_DISABLE (1 << 12) 3585 #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 3586 3587 /* limit RGB values to avoid confusing TVs */ 3588 #define DP_COLOR_RANGE_16_235 (1 << 8) 3589 3590 /* Turn on the audio link */ 3591 #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 3592 3593 /* vs and hs sync polarity */ 3594 #define DP_SYNC_VS_HIGH (1 << 4) 3595 #define DP_SYNC_HS_HIGH (1 << 3) 3596 3597 /* A fantasy */ 3598 #define DP_DETECTED (1 << 2) 3599 3600 /* The aux channel provides a way to talk to the 3601 * signal sink for DDC etc. Max packet size supported 3602 * is 20 bytes in each direction, hence the 5 fixed 3603 * data registers 3604 */ 3605 #define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010) 3606 #define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014) 3607 3608 #define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110) 3609 #define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114) 3610 3611 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) 3612 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 3613 3614 #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 3615 #define DP_AUX_CH_CTL_DONE (1 << 30) 3616 #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 3617 #define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 3618 #define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 3619 #define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 3620 #define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 3621 #define DP_AUX_CH_CTL_TIME_OUT_MAX (3 << 26) /* Varies per platform */ 3622 #define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 3623 #define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 3624 #define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 3625 #define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 3626 #define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 3627 #define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 3628 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 3629 #define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 3630 #define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 3631 #define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 3632 #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 3633 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 3634 #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 3635 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14) 3636 #define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13) 3637 #define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12) 3638 #define DP_AUX_CH_CTL_TBT_IO (1 << 11) 3639 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5) 3640 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) 3641 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 3642 3643 /* 3644 * Computing GMCH M and N values for the Display Port link 3645 * 3646 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 3647 * 3648 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 3649 * 3650 * The GMCH value is used internally 3651 * 3652 * bytes_per_pixel is the number of bytes coming out of the plane, 3653 * which is after the LUTs, so we want the bytes for our color format. 3654 * For our current usage, this is always 3, one byte for R, G and B. 3655 */ 3656 #define _PIPEA_DATA_M_G4X 0x70050 3657 #define _PIPEB_DATA_M_G4X 0x71050 3658 3659 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 3660 #define TU_SIZE_MASK REG_GENMASK(30, 25) 3661 #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */ 3662 3663 #define DATA_LINK_M_N_MASK REG_GENMASK(23, 0) 3664 #define DATA_LINK_N_MAX (0x800000) 3665 3666 #define _PIPEA_DATA_N_G4X 0x70054 3667 #define _PIPEB_DATA_N_G4X 0x71054 3668 3669 /* 3670 * Computing Link M and N values for the Display Port link 3671 * 3672 * Link M / N = pixel_clock / ls_clk 3673 * 3674 * (the DP spec calls pixel_clock the 'strm_clk') 3675 * 3676 * The Link value is transmitted in the Main Stream 3677 * Attributes and VB-ID. 3678 */ 3679 3680 #define _PIPEA_LINK_M_G4X 0x70060 3681 #define _PIPEB_LINK_M_G4X 0x71060 3682 #define _PIPEA_LINK_N_G4X 0x70064 3683 #define _PIPEB_LINK_N_G4X 0x71064 3684 3685 #define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 3686 #define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 3687 #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 3688 #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 3689 3690 /* Display & cursor control */ 3691 3692 /* Pipe A */ 3693 #define _PIPEADSL 0x70000 3694 #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */ 3695 #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0) 3696 #define _PIPEACONF 0x70008 3697 #define PIPECONF_ENABLE REG_BIT(31) 3698 #define PIPECONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */ 3699 #define PIPECONF_STATE_ENABLE REG_BIT(30) /* i965+ */ 3700 #define PIPECONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */ 3701 #define PIPECONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */ 3702 #define PIPECONF_FRAME_START_DELAY(x) REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */ 3703 #define PIPECONF_PIPE_LOCKED REG_BIT(25) 3704 #define PIPECONF_FORCE_BORDER REG_BIT(25) 3705 #define PIPECONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */ 3706 #define PIPECONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */ 3707 #define PIPECONF_GAMMA_MODE_8BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 0) 3708 #define PIPECONF_GAMMA_MODE_10BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 1) 3709 #define PIPECONF_GAMMA_MODE_12BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */ 3710 #define PIPECONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */ 3711 #define PIPECONF_GAMMA_MODE(x) REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */ 3712 #define PIPECONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */ 3713 #define PIPECONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 0) 3714 #define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 only */ 3715 #define PIPECONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */ 3716 #define PIPECONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 6) 3717 #define PIPECONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */ 3718 /* 3719 * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display, 3720 * DBL=power saving pixel doubling, PF-ID* requires panel fitter 3721 */ 3722 #define PIPECONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */ 3723 #define PIPECONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */ 3724 #define PIPECONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 0) 3725 #define PIPECONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 1) 3726 #define PIPECONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 3) 3727 #define PIPECONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */ 3728 #define PIPECONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */ 3729 #define PIPECONF_REFRESH_RATE_ALT_ILK REG_BIT(20) 3730 #define PIPECONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */ 3731 #define PIPECONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(PIPECONF_MSA_TIMING_DELAY_MASK, (x)) 3732 #define PIPECONF_CXSR_DOWNCLOCK REG_BIT(16) 3733 #define PIPECONF_REFRESH_RATE_ALT_VLV REG_BIT(14) 3734 #define PIPECONF_COLOR_RANGE_SELECT REG_BIT(13) 3735 #define PIPECONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */ 3736 #define PIPECONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */ 3737 #define PIPECONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */ 3738 #define PIPECONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */ 3739 #define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */ 3740 #define PIPECONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */ 3741 #define PIPECONF_BPC_8 REG_FIELD_PREP(PIPECONF_BPC_MASK, 0) 3742 #define PIPECONF_BPC_10 REG_FIELD_PREP(PIPECONF_BPC_MASK, 1) 3743 #define PIPECONF_BPC_6 REG_FIELD_PREP(PIPECONF_BPC_MASK, 2) 3744 #define PIPECONF_BPC_12 REG_FIELD_PREP(PIPECONF_BPC_MASK, 3) 3745 #define PIPECONF_DITHER_EN REG_BIT(4) 3746 #define PIPECONF_DITHER_TYPE_MASK REG_GENMASK(3, 2) 3747 #define PIPECONF_DITHER_TYPE_SP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 0) 3748 #define PIPECONF_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 1) 3749 #define PIPECONF_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 2) 3750 #define PIPECONF_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 3) 3751 #define _PIPEASTAT 0x70024 3752 #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31) 3753 #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30) 3754 #define PIPE_CRC_ERROR_ENABLE (1UL << 29) 3755 #define PIPE_CRC_DONE_ENABLE (1UL << 28) 3756 #define PERF_COUNTER2_INTERRUPT_EN (1UL << 27) 3757 #define PIPE_GMBUS_EVENT_ENABLE (1UL << 27) 3758 #define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26) 3759 #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) 3760 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) 3761 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) 3762 #define PIPE_DPST_EVENT_ENABLE (1UL << 23) 3763 #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) 3764 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) 3765 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) 3766 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20) 3767 #define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19) 3768 #define PERF_COUNTER_INTERRUPT_EN (1UL << 19) 3769 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */ 3770 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */ 3771 #define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17) 3772 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) 3773 #define PIPEA_HBLANK_INT_EN_VLV (1UL << 16) 3774 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16) 3775 #define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15) 3776 #define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14) 3777 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13) 3778 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12) 3779 #define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11) 3780 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11) 3781 #define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10) 3782 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) 3783 #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) 3784 #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) 3785 #define PIPE_DPST_EVENT_STATUS (1UL << 7) 3786 #define PIPE_A_PSR_STATUS_VLV (1UL << 6) 3787 #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) 3788 #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) 3789 #define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4) 3790 #define PIPE_B_PSR_STATUS_VLV (1UL << 3) 3791 #define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3) 3792 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */ 3793 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */ 3794 #define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1) 3795 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) 3796 #define PIPE_HBLANK_INT_STATUS (1UL << 0) 3797 #define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0) 3798 3799 #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 3800 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff 3801 3802 #define PIPE_A_OFFSET 0x70000 3803 #define PIPE_B_OFFSET 0x71000 3804 #define PIPE_C_OFFSET 0x72000 3805 #define PIPE_D_OFFSET 0x73000 3806 #define CHV_PIPE_C_OFFSET 0x74000 3807 /* 3808 * There's actually no pipe EDP. Some pipe registers have 3809 * simply shifted from the pipe to the transcoder, while 3810 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 3811 * to access such registers in transcoder EDP. 3812 */ 3813 #define PIPE_EDP_OFFSET 0x7f000 3814 3815 /* ICL DSI 0 and 1 */ 3816 #define PIPE_DSI0_OFFSET 0x7b000 3817 #define PIPE_DSI1_OFFSET 0x7b800 3818 3819 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) 3820 #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) 3821 #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) 3822 #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) 3823 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) 3824 3825 #define _PIPEAGCMAX 0x70010 3826 #define _PIPEBGCMAX 0x71010 3827 #define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4) 3828 3829 #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ 3830 #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A) 3831 #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13) 3832 3833 #define _PIPE_MISC_A 0x70030 3834 #define _PIPE_MISC_B 0x71030 3835 #define PIPEMISC_YUV420_ENABLE REG_BIT(27) /* glk+ */ 3836 #define PIPEMISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */ 3837 #define PIPEMISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */ 3838 #define PIPEMISC_OUTPUT_COLORSPACE_YUV REG_BIT(11) 3839 #define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ 3840 /* 3841 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with 3842 * valid values of: 6, 8, 10 BPC. 3843 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of: 3844 * 6, 8, 10, 12 BPC. 3845 */ 3846 #define PIPEMISC_BPC_MASK REG_GENMASK(7, 5) 3847 #define PIPEMISC_BPC_8 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0) 3848 #define PIPEMISC_BPC_10 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1) 3849 #define PIPEMISC_BPC_6 REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2) 3850 #define PIPEMISC_BPC_12_ADLP REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */ 3851 #define PIPEMISC_DITHER_ENABLE REG_BIT(4) 3852 #define PIPEMISC_DITHER_TYPE_MASK REG_GENMASK(3, 2) 3853 #define PIPEMISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0) 3854 #define PIPEMISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1) 3855 #define PIPEMISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2) 3856 #define PIPEMISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3) 3857 #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) 3858 3859 #define _PIPE_MISC2_A 0x7002C 3860 #define _PIPE_MISC2_B 0x7102C 3861 #define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24) 3862 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80) 3863 #define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20) 3864 #define PIPE_MISC2(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC2_A) 3865 3866 /* Skylake+ pipe bottom (background) color */ 3867 #define _SKL_BOTTOM_COLOR_A 0x70034 3868 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31) 3869 #define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30) 3870 #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A) 3871 3872 #define _ICL_PIPE_A_STATUS 0x70058 3873 #define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS) 3874 #define PIPE_STATUS_UNDERRUN REG_BIT(31) 3875 #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28) 3876 #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27) 3877 #define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26) 3878 3879 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) 3880 #define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29) 3881 #define PIPEB_HLINE_INT_EN REG_BIT(28) 3882 #define PIPEB_VBLANK_INT_EN REG_BIT(27) 3883 #define SPRITED_FLIP_DONE_INT_EN REG_BIT(26) 3884 #define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25) 3885 #define PLANEB_FLIP_DONE_INT_EN REG_BIT(24) 3886 #define PIPE_PSR_INT_EN REG_BIT(22) 3887 #define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21) 3888 #define PIPEA_HLINE_INT_EN REG_BIT(20) 3889 #define PIPEA_VBLANK_INT_EN REG_BIT(19) 3890 #define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18) 3891 #define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17) 3892 #define PLANEA_FLIPDONE_INT_EN REG_BIT(16) 3893 #define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13) 3894 #define PIPEC_HLINE_INT_EN REG_BIT(12) 3895 #define PIPEC_VBLANK_INT_EN REG_BIT(11) 3896 #define SPRITEF_FLIPDONE_INT_EN REG_BIT(10) 3897 #define SPRITEE_FLIPDONE_INT_EN REG_BIT(9) 3898 #define PLANEC_FLIPDONE_INT_EN REG_BIT(8) 3899 3900 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 3901 #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16) 3902 #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16) 3903 #define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27) 3904 #define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26) 3905 #define PLANEC_INVALID_GTT_INT_EN REG_BIT(25) 3906 #define CURSORC_INVALID_GTT_INT_EN REG_BIT(24) 3907 #define CURSORB_INVALID_GTT_INT_EN REG_BIT(23) 3908 #define CURSORA_INVALID_GTT_INT_EN REG_BIT(22) 3909 #define SPRITED_INVALID_GTT_INT_EN REG_BIT(21) 3910 #define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20) 3911 #define PLANEB_INVALID_GTT_INT_EN REG_BIT(19) 3912 #define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18) 3913 #define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17) 3914 #define PLANEA_INVALID_GTT_INT_EN REG_BIT(16) 3915 #define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0) 3916 #define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0) 3917 #define SPRITEF_INVALID_GTT_STATUS REG_BIT(11) 3918 #define SPRITEE_INVALID_GTT_STATUS REG_BIT(10) 3919 #define PLANEC_INVALID_GTT_STATUS REG_BIT(9) 3920 #define CURSORC_INVALID_GTT_STATUS REG_BIT(8) 3921 #define CURSORB_INVALID_GTT_STATUS REG_BIT(7) 3922 #define CURSORA_INVALID_GTT_STATUS REG_BIT(6) 3923 #define SPRITED_INVALID_GTT_STATUS REG_BIT(5) 3924 #define SPRITEC_INVALID_GTT_STATUS REG_BIT(4) 3925 #define PLANEB_INVALID_GTT_STATUS REG_BIT(3) 3926 #define SPRITEB_INVALID_GTT_STATUS REG_BIT(2) 3927 #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1) 3928 #define PLANEA_INVALID_GTT_STATUS REG_BIT(0) 3929 3930 #define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) 3931 #define DSPARB_CSTART_MASK (0x7f << 7) 3932 #define DSPARB_CSTART_SHIFT 7 3933 #define DSPARB_BSTART_MASK (0x7f) 3934 #define DSPARB_BSTART_SHIFT 0 3935 #define DSPARB_BEND_SHIFT 9 /* on 855 */ 3936 #define DSPARB_AEND_SHIFT 0 3937 #define DSPARB_SPRITEA_SHIFT_VLV 0 3938 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0) 3939 #define DSPARB_SPRITEB_SHIFT_VLV 8 3940 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8) 3941 #define DSPARB_SPRITEC_SHIFT_VLV 16 3942 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16) 3943 #define DSPARB_SPRITED_SHIFT_VLV 24 3944 #define DSPARB_SPRITED_MASK_VLV (0xff << 24) 3945 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */ 3946 #define DSPARB_SPRITEA_HI_SHIFT_VLV 0 3947 #define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0) 3948 #define DSPARB_SPRITEB_HI_SHIFT_VLV 4 3949 #define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4) 3950 #define DSPARB_SPRITEC_HI_SHIFT_VLV 8 3951 #define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8) 3952 #define DSPARB_SPRITED_HI_SHIFT_VLV 12 3953 #define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12) 3954 #define DSPARB_SPRITEE_HI_SHIFT_VLV 16 3955 #define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16) 3956 #define DSPARB_SPRITEF_HI_SHIFT_VLV 20 3957 #define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20) 3958 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */ 3959 #define DSPARB_SPRITEE_SHIFT_VLV 0 3960 #define DSPARB_SPRITEE_MASK_VLV (0xff << 0) 3961 #define DSPARB_SPRITEF_SHIFT_VLV 8 3962 #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) 3963 3964 /* pnv/gen4/g4x/vlv/chv */ 3965 #define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) 3966 #define DSPFW_SR_SHIFT 23 3967 #define DSPFW_SR_MASK (0x1ff << 23) 3968 #define DSPFW_CURSORB_SHIFT 16 3969 #define DSPFW_CURSORB_MASK (0x3f << 16) 3970 #define DSPFW_PLANEB_SHIFT 8 3971 #define DSPFW_PLANEB_MASK (0x7f << 8) 3972 #define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */ 3973 #define DSPFW_PLANEA_SHIFT 0 3974 #define DSPFW_PLANEA_MASK (0x7f << 0) 3975 #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ 3976 #define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) 3977 #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ 3978 #define DSPFW_FBC_SR_SHIFT 28 3979 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ 3980 #define DSPFW_FBC_HPLL_SR_SHIFT 24 3981 #define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */ 3982 #define DSPFW_SPRITEB_SHIFT (16) 3983 #define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */ 3984 #define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */ 3985 #define DSPFW_CURSORA_SHIFT 8 3986 #define DSPFW_CURSORA_MASK (0x3f << 8) 3987 #define DSPFW_PLANEC_OLD_SHIFT 0 3988 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */ 3989 #define DSPFW_SPRITEA_SHIFT 0 3990 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ 3991 #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ 3992 #define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) 3993 #define DSPFW_HPLL_SR_EN (1 << 31) 3994 #define PINEVIEW_SELF_REFRESH_EN (1 << 30) 3995 #define DSPFW_CURSOR_SR_SHIFT 24 3996 #define DSPFW_CURSOR_SR_MASK (0x3f << 24) 3997 #define DSPFW_HPLL_CURSOR_SHIFT 16 3998 #define DSPFW_HPLL_CURSOR_MASK (0x3f << 16) 3999 #define DSPFW_HPLL_SR_SHIFT 0 4000 #define DSPFW_HPLL_SR_MASK (0x1ff << 0) 4001 4002 /* vlv/chv */ 4003 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070) 4004 #define DSPFW_SPRITEB_WM1_SHIFT 16 4005 #define DSPFW_SPRITEB_WM1_MASK (0xff << 16) 4006 #define DSPFW_CURSORA_WM1_SHIFT 8 4007 #define DSPFW_CURSORA_WM1_MASK (0x3f << 8) 4008 #define DSPFW_SPRITEA_WM1_SHIFT 0 4009 #define DSPFW_SPRITEA_WM1_MASK (0xff << 0) 4010 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074) 4011 #define DSPFW_PLANEB_WM1_SHIFT 24 4012 #define DSPFW_PLANEB_WM1_MASK (0xff << 24) 4013 #define DSPFW_PLANEA_WM1_SHIFT 16 4014 #define DSPFW_PLANEA_WM1_MASK (0xff << 16) 4015 #define DSPFW_CURSORB_WM1_SHIFT 8 4016 #define DSPFW_CURSORB_WM1_MASK (0x3f << 8) 4017 #define DSPFW_CURSOR_SR_WM1_SHIFT 0 4018 #define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0) 4019 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078) 4020 #define DSPFW_SR_WM1_SHIFT 0 4021 #define DSPFW_SR_WM1_MASK (0x1ff << 0) 4022 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c) 4023 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 4024 #define DSPFW_SPRITED_WM1_SHIFT 24 4025 #define DSPFW_SPRITED_WM1_MASK (0xff << 24) 4026 #define DSPFW_SPRITED_SHIFT 16 4027 #define DSPFW_SPRITED_MASK_VLV (0xff << 16) 4028 #define DSPFW_SPRITEC_WM1_SHIFT 8 4029 #define DSPFW_SPRITEC_WM1_MASK (0xff << 8) 4030 #define DSPFW_SPRITEC_SHIFT 0 4031 #define DSPFW_SPRITEC_MASK_VLV (0xff << 0) 4032 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8) 4033 #define DSPFW_SPRITEF_WM1_SHIFT 24 4034 #define DSPFW_SPRITEF_WM1_MASK (0xff << 24) 4035 #define DSPFW_SPRITEF_SHIFT 16 4036 #define DSPFW_SPRITEF_MASK_VLV (0xff << 16) 4037 #define DSPFW_SPRITEE_WM1_SHIFT 8 4038 #define DSPFW_SPRITEE_WM1_MASK (0xff << 8) 4039 #define DSPFW_SPRITEE_SHIFT 0 4040 #define DSPFW_SPRITEE_MASK_VLV (0xff << 0) 4041 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 4042 #define DSPFW_PLANEC_WM1_SHIFT 24 4043 #define DSPFW_PLANEC_WM1_MASK (0xff << 24) 4044 #define DSPFW_PLANEC_SHIFT 16 4045 #define DSPFW_PLANEC_MASK_VLV (0xff << 16) 4046 #define DSPFW_CURSORC_WM1_SHIFT 8 4047 #define DSPFW_CURSORC_WM1_MASK (0x3f << 16) 4048 #define DSPFW_CURSORC_SHIFT 0 4049 #define DSPFW_CURSORC_MASK (0x3f << 0) 4050 4051 /* vlv/chv high order bits */ 4052 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064) 4053 #define DSPFW_SR_HI_SHIFT 24 4054 #define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 4055 #define DSPFW_SPRITEF_HI_SHIFT 23 4056 #define DSPFW_SPRITEF_HI_MASK (1 << 23) 4057 #define DSPFW_SPRITEE_HI_SHIFT 22 4058 #define DSPFW_SPRITEE_HI_MASK (1 << 22) 4059 #define DSPFW_PLANEC_HI_SHIFT 21 4060 #define DSPFW_PLANEC_HI_MASK (1 << 21) 4061 #define DSPFW_SPRITED_HI_SHIFT 20 4062 #define DSPFW_SPRITED_HI_MASK (1 << 20) 4063 #define DSPFW_SPRITEC_HI_SHIFT 16 4064 #define DSPFW_SPRITEC_HI_MASK (1 << 16) 4065 #define DSPFW_PLANEB_HI_SHIFT 12 4066 #define DSPFW_PLANEB_HI_MASK (1 << 12) 4067 #define DSPFW_SPRITEB_HI_SHIFT 8 4068 #define DSPFW_SPRITEB_HI_MASK (1 << 8) 4069 #define DSPFW_SPRITEA_HI_SHIFT 4 4070 #define DSPFW_SPRITEA_HI_MASK (1 << 4) 4071 #define DSPFW_PLANEA_HI_SHIFT 0 4072 #define DSPFW_PLANEA_HI_MASK (1 << 0) 4073 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068) 4074 #define DSPFW_SR_WM1_HI_SHIFT 24 4075 #define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */ 4076 #define DSPFW_SPRITEF_WM1_HI_SHIFT 23 4077 #define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23) 4078 #define DSPFW_SPRITEE_WM1_HI_SHIFT 22 4079 #define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22) 4080 #define DSPFW_PLANEC_WM1_HI_SHIFT 21 4081 #define DSPFW_PLANEC_WM1_HI_MASK (1 << 21) 4082 #define DSPFW_SPRITED_WM1_HI_SHIFT 20 4083 #define DSPFW_SPRITED_WM1_HI_MASK (1 << 20) 4084 #define DSPFW_SPRITEC_WM1_HI_SHIFT 16 4085 #define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16) 4086 #define DSPFW_PLANEB_WM1_HI_SHIFT 12 4087 #define DSPFW_PLANEB_WM1_HI_MASK (1 << 12) 4088 #define DSPFW_SPRITEB_WM1_HI_SHIFT 8 4089 #define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8) 4090 #define DSPFW_SPRITEA_WM1_HI_SHIFT 4 4091 #define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4) 4092 #define DSPFW_PLANEA_WM1_HI_SHIFT 0 4093 #define DSPFW_PLANEA_WM1_HI_MASK (1 << 0) 4094 4095 /* drain latency register values*/ 4096 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 4097 #define DDL_CURSOR_SHIFT 24 4098 #define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite)) 4099 #define DDL_PLANE_SHIFT 0 4100 #define DDL_PRECISION_HIGH (1 << 7) 4101 #define DDL_PRECISION_LOW (0 << 7) 4102 #define DRAIN_LATENCY_MASK 0x7f 4103 4104 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400) 4105 #define CBR_PND_DEADLINE_DISABLE (1 << 31) 4106 #define CBR_PWM_CLOCK_MUX_SELECT (1 << 30) 4107 4108 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450) 4109 #define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */ 4110 4111 /* FIFO watermark sizes etc */ 4112 #define G4X_FIFO_LINE_SIZE 64 4113 #define I915_FIFO_LINE_SIZE 64 4114 #define I830_FIFO_LINE_SIZE 32 4115 4116 #define VALLEYVIEW_FIFO_SIZE 255 4117 #define G4X_FIFO_SIZE 127 4118 #define I965_FIFO_SIZE 512 4119 #define I945_FIFO_SIZE 127 4120 #define I915_FIFO_SIZE 95 4121 #define I855GM_FIFO_SIZE 127 /* In cachelines */ 4122 #define I830_FIFO_SIZE 95 4123 4124 #define VALLEYVIEW_MAX_WM 0xff 4125 #define G4X_MAX_WM 0x3f 4126 #define I915_MAX_WM 0x3f 4127 4128 #define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 4129 #define PINEVIEW_FIFO_LINE_SIZE 64 4130 #define PINEVIEW_MAX_WM 0x1ff 4131 #define PINEVIEW_DFT_WM 0x3f 4132 #define PINEVIEW_DFT_HPLLOFF_WM 0 4133 #define PINEVIEW_GUARD_WM 10 4134 #define PINEVIEW_CURSOR_FIFO 64 4135 #define PINEVIEW_CURSOR_MAX_WM 0x3f 4136 #define PINEVIEW_CURSOR_DFT_WM 0 4137 #define PINEVIEW_CURSOR_GUARD_WM 5 4138 4139 #define VALLEYVIEW_CURSOR_MAX_WM 64 4140 #define I965_CURSOR_FIFO 64 4141 #define I965_CURSOR_MAX_WM 32 4142 #define I965_CURSOR_DFT_WM 8 4143 4144 /* Watermark register definitions for SKL */ 4145 #define _CUR_WM_A_0 0x70140 4146 #define _CUR_WM_B_0 0x71140 4147 #define _CUR_WM_SAGV_A 0x70158 4148 #define _CUR_WM_SAGV_B 0x71158 4149 #define _CUR_WM_SAGV_TRANS_A 0x7015C 4150 #define _CUR_WM_SAGV_TRANS_B 0x7115C 4151 #define _CUR_WM_TRANS_A 0x70168 4152 #define _CUR_WM_TRANS_B 0x71168 4153 #define _PLANE_WM_1_A_0 0x70240 4154 #define _PLANE_WM_1_B_0 0x71240 4155 #define _PLANE_WM_2_A_0 0x70340 4156 #define _PLANE_WM_2_B_0 0x71340 4157 #define _PLANE_WM_SAGV_1_A 0x70258 4158 #define _PLANE_WM_SAGV_1_B 0x71258 4159 #define _PLANE_WM_SAGV_2_A 0x70358 4160 #define _PLANE_WM_SAGV_2_B 0x71358 4161 #define _PLANE_WM_SAGV_TRANS_1_A 0x7025C 4162 #define _PLANE_WM_SAGV_TRANS_1_B 0x7125C 4163 #define _PLANE_WM_SAGV_TRANS_2_A 0x7035C 4164 #define _PLANE_WM_SAGV_TRANS_2_B 0x7135C 4165 #define _PLANE_WM_TRANS_1_A 0x70268 4166 #define _PLANE_WM_TRANS_1_B 0x71268 4167 #define _PLANE_WM_TRANS_2_A 0x70368 4168 #define _PLANE_WM_TRANS_2_B 0x71368 4169 #define PLANE_WM_EN (1 << 31) 4170 #define PLANE_WM_IGNORE_LINES (1 << 30) 4171 #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) 4172 #define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) 4173 4174 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) 4175 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) 4176 #define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B) 4177 #define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B) 4178 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B) 4179 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) 4180 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) 4181 #define _PLANE_WM_BASE(pipe, plane) \ 4182 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) 4183 #define PLANE_WM(pipe, plane, level) \ 4184 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) 4185 #define _PLANE_WM_SAGV_1(pipe) \ 4186 _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B) 4187 #define _PLANE_WM_SAGV_2(pipe) \ 4188 _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B) 4189 #define PLANE_WM_SAGV(pipe, plane) \ 4190 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe))) 4191 #define _PLANE_WM_SAGV_TRANS_1(pipe) \ 4192 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B) 4193 #define _PLANE_WM_SAGV_TRANS_2(pipe) \ 4194 _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B) 4195 #define PLANE_WM_SAGV_TRANS(pipe, plane) \ 4196 _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe))) 4197 #define _PLANE_WM_TRANS_1(pipe) \ 4198 _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B) 4199 #define _PLANE_WM_TRANS_2(pipe) \ 4200 _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B) 4201 #define PLANE_WM_TRANS(pipe, plane) \ 4202 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) 4203 4204 /* define the Watermark register on Ironlake */ 4205 #define _WM0_PIPEA_ILK 0x45100 4206 #define _WM0_PIPEB_ILK 0x45104 4207 #define _WM0_PIPEC_IVB 0x45200 4208 #define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \ 4209 _WM0_PIPEB_ILK, _WM0_PIPEC_IVB) 4210 #define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16) 4211 #define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8) 4212 #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0) 4213 #define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x)) 4214 #define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x)) 4215 #define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x)) 4216 #define WM1_LP_ILK _MMIO(0x45108) 4217 #define WM2_LP_ILK _MMIO(0x4510c) 4218 #define WM3_LP_ILK _MMIO(0x45110) 4219 #define WM_LP_ENABLE REG_BIT(31) 4220 #define WM_LP_LATENCY_MASK REG_GENMASK(30, 24) 4221 #define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19) 4222 #define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20) 4223 #define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8) 4224 #define WM_LP_CURSOR_MASK REG_GENMASK(7, 0) 4225 #define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x)) 4226 #define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x)) 4227 #define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x)) 4228 #define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x)) 4229 #define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x)) 4230 #define WM1S_LP_ILK _MMIO(0x45120) 4231 #define WM2S_LP_IVB _MMIO(0x45124) 4232 #define WM3S_LP_IVB _MMIO(0x45128) 4233 #define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */ 4234 #define WM_LP_SPRITE_MASK REG_GENMASK(10, 0) 4235 #define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x)) 4236 4237 /* 4238 * The two pipe frame counter registers are not synchronized, so 4239 * reading a stable value is somewhat tricky. The following code 4240 * should work: 4241 * 4242 * do { 4243 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4244 * PIPE_FRAME_HIGH_SHIFT; 4245 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 4246 * PIPE_FRAME_LOW_SHIFT); 4247 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4248 * PIPE_FRAME_HIGH_SHIFT); 4249 * } while (high1 != high2); 4250 * frame = (high1 << 8) | low1; 4251 */ 4252 #define _PIPEAFRAMEHIGH 0x70040 4253 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 4254 #define PIPE_FRAME_HIGH_SHIFT 0 4255 #define _PIPEAFRAMEPIXEL 0x70044 4256 #define PIPE_FRAME_LOW_MASK 0xff000000 4257 #define PIPE_FRAME_LOW_SHIFT 24 4258 #define PIPE_PIXEL_MASK 0x00ffffff 4259 #define PIPE_PIXEL_SHIFT 0 4260 /* GM45+ just has to be different */ 4261 #define _PIPEA_FRMCOUNT_G4X 0x70040 4262 #define _PIPEA_FLIPCOUNT_G4X 0x70044 4263 #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) 4264 #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) 4265 4266 /* Cursor A & B regs */ 4267 #define _CURACNTR 0x70080 4268 /* Old style CUR*CNTR flags (desktop 8xx) */ 4269 #define CURSOR_ENABLE REG_BIT(31) 4270 #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) 4271 #define CURSOR_STRIDE_MASK REG_GENMASK(29, 28) 4272 #define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */ 4273 #define CURSOR_FORMAT_MASK REG_GENMASK(26, 24) 4274 #define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0) 4275 #define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1) 4276 #define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2) 4277 #define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4) 4278 #define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5) 4279 /* New style CUR*CNTR flags */ 4280 #define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 4281 #define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */ 4282 #define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28) 4283 #define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe)) 4284 #define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26) 4285 #define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 4286 #define MCURSOR_ROTATE_180 REG_BIT(15) 4287 #define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14) 4288 #define MCURSOR_MODE_MASK 0x27 4289 #define MCURSOR_MODE_DISABLE 0x00 4290 #define MCURSOR_MODE_128_32B_AX 0x02 4291 #define MCURSOR_MODE_256_32B_AX 0x03 4292 #define MCURSOR_MODE_64_32B_AX 0x07 4293 #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) 4294 #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) 4295 #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX) 4296 #define _CURABASE 0x70084 4297 #define _CURAPOS 0x70088 4298 #define CURSOR_POS_Y_SIGN REG_BIT(31) 4299 #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16) 4300 #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) 4301 #define CURSOR_POS_X_SIGN REG_BIT(15) 4302 #define CURSOR_POS_X_MASK REG_GENMASK(14, 0) 4303 #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) 4304 #define _CURASIZE 0x700a0 /* 845/865 */ 4305 #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) 4306 #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) 4307 #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0) 4308 #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) 4309 #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ 4310 #define CUR_FBC_EN REG_BIT(31) 4311 #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0) 4312 #define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) 4313 #define _CURASURFLIVE 0x700ac /* g4x+ */ 4314 #define _CURBCNTR 0x700c0 4315 #define _CURBBASE 0x700c4 4316 #define _CURBPOS 0x700c8 4317 4318 #define _CURBCNTR_IVB 0x71080 4319 #define _CURBBASE_IVB 0x71084 4320 #define _CURBPOS_IVB 0x71088 4321 4322 #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) 4323 #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) 4324 #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) 4325 #define CURSIZE(pipe) _CURSOR2(pipe, _CURASIZE) 4326 #define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A) 4327 #define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE) 4328 4329 #define CURSOR_A_OFFSET 0x70080 4330 #define CURSOR_B_OFFSET 0x700c0 4331 #define CHV_CURSOR_C_OFFSET 0x700e0 4332 #define IVB_CURSOR_B_OFFSET 0x71080 4333 #define IVB_CURSOR_C_OFFSET 0x72080 4334 #define TGL_CURSOR_D_OFFSET 0x73080 4335 4336 /* Display A control */ 4337 #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ 4338 #define _DSPACNTR 0x70180 4339 #define DISP_ENABLE REG_BIT(31) 4340 #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) 4341 #define DISP_FORMAT_MASK REG_GENMASK(29, 26) 4342 #define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2) 4343 #define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3) 4344 #define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4) 4345 #define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5) 4346 #define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6) 4347 #define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7) 4348 #define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8) 4349 #define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9) 4350 #define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10) 4351 #define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11) 4352 #define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12) 4353 #define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14) 4354 #define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15) 4355 #define DISP_STEREO_ENABLE REG_BIT(25) 4356 #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ 4357 #define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24) 4358 #define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe)) 4359 #define DISP_SRC_KEY_ENABLE REG_BIT(22) 4360 #define DISP_LINE_DOUBLE REG_BIT(20) 4361 #define DISP_STEREO_POLARITY_SECOND REG_BIT(18) 4362 #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ 4363 #define DISP_ROTATE_180 REG_BIT(15) 4364 #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ 4365 #define DISP_TILED REG_BIT(10) 4366 #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ 4367 #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ 4368 #define _DSPAADDR 0x70184 4369 #define _DSPASTRIDE 0x70188 4370 #define _DSPAPOS 0x7018C /* reserved */ 4371 #define DISP_POS_Y_MASK REG_GENMASK(31, 16) 4372 #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) 4373 #define DISP_POS_X_MASK REG_GENMASK(15, 0) 4374 #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) 4375 #define _DSPASIZE 0x70190 4376 #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) 4377 #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) 4378 #define DISP_WIDTH_MASK REG_GENMASK(15, 0) 4379 #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) 4380 #define _DSPASURF 0x7019C /* 965+ only */ 4381 #define DISP_ADDR_MASK REG_GENMASK(31, 12) 4382 #define _DSPATILEOFF 0x701A4 /* 965+ only */ 4383 #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) 4384 #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) 4385 #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) 4386 #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) 4387 #define _DSPAOFFSET 0x701A4 /* HSW */ 4388 #define _DSPASURFLIVE 0x701AC 4389 #define _DSPAGAMC 0x701E0 4390 4391 #define DSPADDR_VLV(plane) _MMIO_PIPE2(plane, _DSPAADDR_VLV) 4392 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) 4393 #define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) 4394 #define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) 4395 #define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) 4396 #define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) 4397 #define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) 4398 #define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) 4399 #define DSPLINOFF(plane) DSPADDR(plane) 4400 #define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) 4401 #define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) 4402 #define DSPGAMC(plane, i) _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ 4403 4404 /* CHV pipe B blender and primary plane */ 4405 #define _CHV_BLEND_A 0x60a00 4406 #define CHV_BLEND_MASK REG_GENMASK(31, 30) 4407 #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0) 4408 #define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1) 4409 #define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2) 4410 #define _CHV_CANVAS_A 0x60a04 4411 #define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20) 4412 #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10) 4413 #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0) 4414 #define _PRIMPOS_A 0x60a08 4415 #define PRIM_POS_Y_MASK REG_GENMASK(31, 16) 4416 #define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) 4417 #define PRIM_POS_X_MASK REG_GENMASK(15, 0) 4418 #define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x)) 4419 #define _PRIMSIZE_A 0x60a0c 4420 #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16) 4421 #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h)) 4422 #define PRIM_WIDTH_MASK REG_GENMASK(15, 0) 4423 #define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w)) 4424 #define _PRIMCNSTALPHA_A 0x60a10 4425 #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31) 4426 #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0) 4427 #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha)) 4428 4429 #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) 4430 #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) 4431 #define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) 4432 #define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) 4433 #define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) 4434 4435 /* Display/Sprite base address macros */ 4436 #define DISP_BASEADDR_MASK (0xfffff000) 4437 #define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK) 4438 #define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK) 4439 4440 /* 4441 * VBIOS flags 4442 * gen2: 4443 * [00:06] alm,mgm 4444 * [10:16] all 4445 * [30:32] alm,mgm 4446 * gen3+: 4447 * [00:0f] all 4448 * [10:1f] all 4449 * [30:32] all 4450 */ 4451 #define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) 4452 #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) 4453 #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) 4454 #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) 4455 4456 /* Pipe B */ 4457 #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) 4458 #define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) 4459 #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) 4460 #define _PIPEBFRAMEHIGH 0x71040 4461 #define _PIPEBFRAMEPIXEL 0x71044 4462 #define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) 4463 #define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) 4464 4465 4466 /* Display B control */ 4467 #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) 4468 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) 4469 #define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0) 4470 #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) 4471 #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) 4472 #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) 4473 #define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) 4474 #define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) 4475 #define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 4476 #define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) 4477 #define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) 4478 4479 /* ICL DSI 0 and 1 */ 4480 #define _PIPEDSI0CONF 0x7b008 4481 #define _PIPEDSI1CONF 0x7b808 4482 4483 /* Sprite A control */ 4484 #define _DVSACNTR 0x72180 4485 #define DVS_ENABLE REG_BIT(31) 4486 #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30) 4487 #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27) 4488 #define DVS_FORMAT_MASK REG_GENMASK(26, 25) 4489 #define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0) 4490 #define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1) 4491 #define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2) 4492 #define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3) 4493 #define DVS_PIPE_CSC_ENABLE REG_BIT(24) 4494 #define DVS_SOURCE_KEY REG_BIT(22) 4495 #define DVS_RGB_ORDER_XBGR REG_BIT(20) 4496 #define DVS_YUV_FORMAT_BT709 REG_BIT(18) 4497 #define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16) 4498 #define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0) 4499 #define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1) 4500 #define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2) 4501 #define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3) 4502 #define DVS_ROTATE_180 REG_BIT(15) 4503 #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14) 4504 #define DVS_TILED REG_BIT(10) 4505 #define DVS_DEST_KEY REG_BIT(2) 4506 #define _DVSALINOFF 0x72184 4507 #define _DVSASTRIDE 0x72188 4508 #define _DVSAPOS 0x7218c 4509 #define DVS_POS_Y_MASK REG_GENMASK(31, 16) 4510 #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y)) 4511 #define DVS_POS_X_MASK REG_GENMASK(15, 0) 4512 #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x)) 4513 #define _DVSASIZE 0x72190 4514 #define DVS_HEIGHT_MASK REG_GENMASK(31, 16) 4515 #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h)) 4516 #define DVS_WIDTH_MASK REG_GENMASK(15, 0) 4517 #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w)) 4518 #define _DVSAKEYVAL 0x72194 4519 #define _DVSAKEYMSK 0x72198 4520 #define _DVSASURF 0x7219c 4521 #define DVS_ADDR_MASK REG_GENMASK(31, 12) 4522 #define _DVSAKEYMAXVAL 0x721a0 4523 #define _DVSATILEOFF 0x721a4 4524 #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16) 4525 #define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y)) 4526 #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0) 4527 #define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x)) 4528 #define _DVSASURFLIVE 0x721ac 4529 #define _DVSAGAMC_G4X 0x721e0 /* g4x */ 4530 #define _DVSASCALE 0x72204 4531 #define DVS_SCALE_ENABLE REG_BIT(31) 4532 #define DVS_FILTER_MASK REG_GENMASK(30, 29) 4533 #define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0) 4534 #define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1) 4535 #define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2) 4536 #define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ 4537 #define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27) 4538 #define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16) 4539 #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w)) 4540 #define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0) 4541 #define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h)) 4542 #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */ 4543 #define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */ 4544 4545 #define _DVSBCNTR 0x73180 4546 #define _DVSBLINOFF 0x73184 4547 #define _DVSBSTRIDE 0x73188 4548 #define _DVSBPOS 0x7318c 4549 #define _DVSBSIZE 0x73190 4550 #define _DVSBKEYVAL 0x73194 4551 #define _DVSBKEYMSK 0x73198 4552 #define _DVSBSURF 0x7319c 4553 #define _DVSBKEYMAXVAL 0x731a0 4554 #define _DVSBTILEOFF 0x731a4 4555 #define _DVSBSURFLIVE 0x731ac 4556 #define _DVSBGAMC_G4X 0x731e0 /* g4x */ 4557 #define _DVSBSCALE 0x73204 4558 #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */ 4559 #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ 4560 4561 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) 4562 #define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 4563 #define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 4564 #define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) 4565 #define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) 4566 #define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 4567 #define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) 4568 #define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) 4569 #define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 4570 #define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 4571 #define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 4572 #define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 4573 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ 4574 #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */ 4575 #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ 4576 4577 #define _SPRA_CTL 0x70280 4578 #define SPRITE_ENABLE REG_BIT(31) 4579 #define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30) 4580 #define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 4581 #define SPRITE_FORMAT_MASK REG_GENMASK(27, 25) 4582 #define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0) 4583 #define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1) 4584 #define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2) 4585 #define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3) 4586 #define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4) 4587 #define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */ 4588 #define SPRITE_PIPE_CSC_ENABLE REG_BIT(24) 4589 #define SPRITE_SOURCE_KEY REG_BIT(22) 4590 #define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */ 4591 #define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19) 4592 #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */ 4593 #define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16) 4594 #define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0) 4595 #define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1) 4596 #define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2) 4597 #define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3) 4598 #define SPRITE_ROTATE_180 REG_BIT(15) 4599 #define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14) 4600 #define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13) 4601 #define SPRITE_TILED REG_BIT(10) 4602 #define SPRITE_DEST_KEY REG_BIT(2) 4603 #define _SPRA_LINOFF 0x70284 4604 #define _SPRA_STRIDE 0x70288 4605 #define _SPRA_POS 0x7028c 4606 #define SPRITE_POS_Y_MASK REG_GENMASK(31, 16) 4607 #define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y)) 4608 #define SPRITE_POS_X_MASK REG_GENMASK(15, 0) 4609 #define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x)) 4610 #define _SPRA_SIZE 0x70290 4611 #define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16) 4612 #define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h)) 4613 #define SPRITE_WIDTH_MASK REG_GENMASK(15, 0) 4614 #define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w)) 4615 #define _SPRA_KEYVAL 0x70294 4616 #define _SPRA_KEYMSK 0x70298 4617 #define _SPRA_SURF 0x7029c 4618 #define SPRITE_ADDR_MASK REG_GENMASK(31, 12) 4619 #define _SPRA_KEYMAX 0x702a0 4620 #define _SPRA_TILEOFF 0x702a4 4621 #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16) 4622 #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y)) 4623 #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0) 4624 #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x)) 4625 #define _SPRA_OFFSET 0x702a4 4626 #define _SPRA_SURFLIVE 0x702ac 4627 #define _SPRA_SCALE 0x70304 4628 #define SPRITE_SCALE_ENABLE REG_BIT(31) 4629 #define SPRITE_FILTER_MASK REG_GENMASK(30, 29) 4630 #define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0) 4631 #define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1) 4632 #define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2) 4633 #define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ 4634 #define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27) 4635 #define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16) 4636 #define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w)) 4637 #define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0) 4638 #define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h)) 4639 #define _SPRA_GAMC 0x70400 4640 #define _SPRA_GAMC16 0x70440 4641 #define _SPRA_GAMC17 0x7044c 4642 4643 #define _SPRB_CTL 0x71280 4644 #define _SPRB_LINOFF 0x71284 4645 #define _SPRB_STRIDE 0x71288 4646 #define _SPRB_POS 0x7128c 4647 #define _SPRB_SIZE 0x71290 4648 #define _SPRB_KEYVAL 0x71294 4649 #define _SPRB_KEYMSK 0x71298 4650 #define _SPRB_SURF 0x7129c 4651 #define _SPRB_KEYMAX 0x712a0 4652 #define _SPRB_TILEOFF 0x712a4 4653 #define _SPRB_OFFSET 0x712a4 4654 #define _SPRB_SURFLIVE 0x712ac 4655 #define _SPRB_SCALE 0x71304 4656 #define _SPRB_GAMC 0x71400 4657 #define _SPRB_GAMC16 0x71440 4658 #define _SPRB_GAMC17 0x7144c 4659 4660 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 4661 #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 4662 #define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 4663 #define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) 4664 #define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 4665 #define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 4666 #define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 4667 #define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 4668 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 4669 #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 4670 #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 4671 #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 4672 #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */ 4673 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */ 4674 #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */ 4675 #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 4676 4677 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 4678 #define SP_ENABLE REG_BIT(31) 4679 #define SP_PIPE_GAMMA_ENABLE REG_BIT(30) 4680 #define SP_FORMAT_MASK REG_GENMASK(29, 26) 4681 #define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0) 4682 #define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2) 4683 #define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5) 4684 #define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6) 4685 #define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7) 4686 #define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8) 4687 #define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9) 4688 #define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */ 4689 #define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */ 4690 #define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14) 4691 #define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15) 4692 #define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */ 4693 #define SP_SOURCE_KEY REG_BIT(22) 4694 #define SP_YUV_FORMAT_BT709 REG_BIT(18) 4695 #define SP_YUV_ORDER_MASK REG_GENMASK(17, 16) 4696 #define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0) 4697 #define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1) 4698 #define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2) 4699 #define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3) 4700 #define SP_ROTATE_180 REG_BIT(15) 4701 #define SP_TILED REG_BIT(10) 4702 #define SP_MIRROR REG_BIT(8) /* CHV pipe B */ 4703 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 4704 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 4705 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 4706 #define SP_POS_Y_MASK REG_GENMASK(31, 16) 4707 #define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y)) 4708 #define SP_POS_X_MASK REG_GENMASK(15, 0) 4709 #define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x)) 4710 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 4711 #define SP_HEIGHT_MASK REG_GENMASK(31, 16) 4712 #define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h)) 4713 #define SP_WIDTH_MASK REG_GENMASK(15, 0) 4714 #define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w)) 4715 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 4716 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 4717 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 4718 #define SP_ADDR_MASK REG_GENMASK(31, 12) 4719 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 4720 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 4721 #define SP_OFFSET_Y_MASK REG_GENMASK(31, 16) 4722 #define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y)) 4723 #define SP_OFFSET_X_MASK REG_GENMASK(15, 0) 4724 #define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x)) 4725 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 4726 #define SP_CONST_ALPHA_ENABLE REG_BIT(31) 4727 #define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0) 4728 #define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha)) 4729 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0) 4730 #define SP_CONTRAST_MASK REG_GENMASK(26, 18) 4731 #define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */ 4732 #define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0) 4733 #define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */ 4734 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4) 4735 #define SP_SH_SIN_MASK REG_GENMASK(26, 16) 4736 #define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */ 4737 #define SP_SH_COS_MASK REG_GENMASK(9, 0) 4738 #define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */ 4739 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0) 4740 4741 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 4742 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 4743 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 4744 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 4745 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 4746 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 4747 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 4748 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 4749 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 4750 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 4751 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 4752 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) 4753 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4) 4754 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0) 4755 4756 #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 4757 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) 4758 #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ 4759 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b))) 4760 4761 #define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) 4762 #define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) 4763 #define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) 4764 #define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) 4765 #define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) 4766 #define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) 4767 #define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) 4768 #define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) 4769 #define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) 4770 #define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) 4771 #define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) 4772 #define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) 4773 #define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1) 4774 #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */ 4775 4776 /* 4777 * CHV pipe B sprite CSC 4778 * 4779 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| 4780 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| 4781 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| 4782 */ 4783 #define _MMIO_CHV_SPCSC(plane_id, reg) \ 4784 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) 4785 4786 #define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) 4787 #define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) 4788 #define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) 4789 #define SPCSC_OOFF_MASK REG_GENMASK(26, 16) 4790 #define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */ 4791 #define SPCSC_IOFF_MASK REG_GENMASK(10, 0) 4792 #define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */ 4793 4794 #define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) 4795 #define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) 4796 #define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) 4797 #define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) 4798 #define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) 4799 #define SPCSC_C1_MASK REG_GENMASK(30, 16) 4800 #define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */ 4801 #define SPCSC_C0_MASK REG_GENMASK(14, 0) 4802 #define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */ 4803 4804 #define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) 4805 #define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) 4806 #define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928) 4807 #define SPCSC_IMAX_MASK REG_GENMASK(26, 16) 4808 #define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */ 4809 #define SPCSC_IMIN_MASK REG_GENMASK(10, 0) 4810 #define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */ 4811 4812 #define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c) 4813 #define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930) 4814 #define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934) 4815 #define SPCSC_OMAX_MASK REG_GENMASK(25, 16) 4816 #define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */ 4817 #define SPCSC_OMIN_MASK REG_GENMASK(9, 0) 4818 #define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */ 4819 4820 /* Skylake plane registers */ 4821 4822 #define _PLANE_CTL_1_A 0x70180 4823 #define _PLANE_CTL_2_A 0x70280 4824 #define _PLANE_CTL_3_A 0x70380 4825 #define PLANE_CTL_ENABLE REG_BIT(31) 4826 #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ 4827 #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ 4828 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */ 4829 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 4830 /* 4831 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition 4832 * expanded to include bit 23 as well. However, the shift-24 based values 4833 * correctly map to the same formats in ICL, as long as bit 23 is set to 0 4834 */ 4835 #define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */ 4836 #define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */ 4837 #define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0) 4838 #define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1) 4839 #define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2) 4840 #define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3) 4841 #define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4) 4842 #define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5) 4843 #define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6) 4844 #define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7) 4845 #define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8) 4846 #define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12) 4847 #define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14) 4848 #define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1) 4849 #define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3) 4850 #define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5) 4851 #define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7) 4852 #define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9) 4853 #define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11) 4854 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */ 4855 #define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21) 4856 #define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1) 4857 #define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2) 4858 #define PLANE_CTL_ORDER_RGBX REG_BIT(20) 4859 #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19) 4860 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) 4861 #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16) 4862 #define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0) 4863 #define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1) 4864 #define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2) 4865 #define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3) 4866 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15) 4867 #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14) 4868 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */ 4869 #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */ 4870 #define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10) 4871 #define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0) 4872 #define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1) 4873 #define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4) 4874 #define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) 4875 #define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) 4876 #define PLANE_CTL_ASYNC_FLIP REG_BIT(9) 4877 #define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8) 4878 #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */ 4879 #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */ 4880 #define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0) 4881 #define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2) 4882 #define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3) 4883 #define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0) 4884 #define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0) 4885 #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) 4886 #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) 4887 #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) 4888 #define _PLANE_STRIDE_1_A 0x70188 4889 #define _PLANE_STRIDE_2_A 0x70288 4890 #define _PLANE_STRIDE_3_A 0x70388 4891 #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) 4892 #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) 4893 #define _PLANE_POS_1_A 0x7018c 4894 #define _PLANE_POS_2_A 0x7028c 4895 #define _PLANE_POS_3_A 0x7038c 4896 #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) 4897 #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) 4898 #define PLANE_POS_X_MASK REG_GENMASK(15, 0) 4899 #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) 4900 #define _PLANE_SIZE_1_A 0x70190 4901 #define _PLANE_SIZE_2_A 0x70290 4902 #define _PLANE_SIZE_3_A 0x70390 4903 #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) 4904 #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) 4905 #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) 4906 #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) 4907 #define _PLANE_SURF_1_A 0x7019c 4908 #define _PLANE_SURF_2_A 0x7029c 4909 #define _PLANE_SURF_3_A 0x7039c 4910 #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) 4911 #define PLANE_SURF_DECRYPT REG_BIT(2) 4912 #define _PLANE_OFFSET_1_A 0x701a4 4913 #define _PLANE_OFFSET_2_A 0x702a4 4914 #define _PLANE_OFFSET_3_A 0x703a4 4915 #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16) 4916 #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y)) 4917 #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0) 4918 #define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x)) 4919 #define _PLANE_KEYVAL_1_A 0x70194 4920 #define _PLANE_KEYVAL_2_A 0x70294 4921 #define _PLANE_KEYMSK_1_A 0x70198 4922 #define _PLANE_KEYMSK_2_A 0x70298 4923 #define PLANE_KEYMSK_ALPHA_ENABLE (1 << 31) 4924 #define _PLANE_KEYMAX_1_A 0x701a0 4925 #define _PLANE_KEYMAX_2_A 0x702a0 4926 #define PLANE_KEYMAX_ALPHA(a) ((a) << 24) 4927 #define _PLANE_CC_VAL_1_A 0x701b4 4928 #define _PLANE_CC_VAL_2_A 0x702b4 4929 #define _PLANE_AUX_DIST_1_A 0x701c0 4930 #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12) 4931 #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0) 4932 #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride)) 4933 #define _PLANE_AUX_DIST_2_A 0x702c0 4934 #define _PLANE_AUX_OFFSET_1_A 0x701c4 4935 #define _PLANE_AUX_OFFSET_2_A 0x702c4 4936 #define _PLANE_CUS_CTL_1_A 0x701c8 4937 #define _PLANE_CUS_CTL_2_A 0x702c8 4938 #define PLANE_CUS_ENABLE REG_BIT(31) 4939 #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) 4940 #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 4941 #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 4942 #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) 4943 #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) 4944 #define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) 4945 #define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16) 4946 #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0) 4947 #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1) 4948 #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2) 4949 #define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) 4950 #define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12) 4951 #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) 4952 #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) 4953 #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2) 4954 #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ 4955 #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ 4956 #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ 4957 #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */ 4958 #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) 4959 #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */ 4960 #define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */ 4961 #define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */ 4962 #define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17) 4963 #define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0) 4964 #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1) 4965 #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2) 4966 #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3) 4967 #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4) 4968 #define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13) 4969 #define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4) 4970 #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0) 4971 #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2) 4972 #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3) 4973 #define _PLANE_BUF_CFG_1_A 0x7027c 4974 #define _PLANE_BUF_CFG_2_A 0x7037c 4975 #define _PLANE_NV12_BUF_CFG_1_A 0x70278 4976 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 4977 4978 #define _PLANE_CC_VAL_1_B 0x711b4 4979 #define _PLANE_CC_VAL_2_B 0x712b4 4980 #define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4) 4981 #define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4) 4982 #define PLANE_CC_VAL(pipe, plane, dw) \ 4983 _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) 4984 4985 /* Input CSC Register Definitions */ 4986 #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 4987 #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 4988 4989 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0 4990 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0 4991 4992 #define _PLANE_INPUT_CSC_RY_GY_1(pipe) \ 4993 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \ 4994 _PLANE_INPUT_CSC_RY_GY_1_B) 4995 #define _PLANE_INPUT_CSC_RY_GY_2(pipe) \ 4996 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ 4997 _PLANE_INPUT_CSC_RY_GY_2_B) 4998 4999 #define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ 5000 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ 5001 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) 5002 5003 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8 5004 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8 5005 5006 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8 5007 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8 5008 5009 #define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \ 5010 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \ 5011 _PLANE_INPUT_CSC_PREOFF_HI_1_B) 5012 #define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \ 5013 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \ 5014 _PLANE_INPUT_CSC_PREOFF_HI_2_B) 5015 #define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ 5016 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ 5017 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) 5018 5019 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 5020 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 5021 5022 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 5023 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 5024 5025 #define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \ 5026 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \ 5027 _PLANE_INPUT_CSC_POSTOFF_HI_1_B) 5028 #define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \ 5029 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \ 5030 _PLANE_INPUT_CSC_POSTOFF_HI_2_B) 5031 #define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ 5032 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ 5033 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) 5034 5035 #define _PLANE_CTL_1_B 0x71180 5036 #define _PLANE_CTL_2_B 0x71280 5037 #define _PLANE_CTL_3_B 0x71380 5038 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) 5039 #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) 5040 #define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) 5041 #define PLANE_CTL(pipe, plane) \ 5042 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) 5043 5044 #define _PLANE_STRIDE_1_B 0x71188 5045 #define _PLANE_STRIDE_2_B 0x71288 5046 #define _PLANE_STRIDE_3_B 0x71388 5047 #define _PLANE_STRIDE_1(pipe) \ 5048 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) 5049 #define _PLANE_STRIDE_2(pipe) \ 5050 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) 5051 #define _PLANE_STRIDE_3(pipe) \ 5052 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) 5053 #define PLANE_STRIDE(pipe, plane) \ 5054 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) 5055 5056 #define _PLANE_POS_1_B 0x7118c 5057 #define _PLANE_POS_2_B 0x7128c 5058 #define _PLANE_POS_3_B 0x7138c 5059 #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) 5060 #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) 5061 #define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) 5062 #define PLANE_POS(pipe, plane) \ 5063 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) 5064 5065 #define _PLANE_SIZE_1_B 0x71190 5066 #define _PLANE_SIZE_2_B 0x71290 5067 #define _PLANE_SIZE_3_B 0x71390 5068 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) 5069 #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) 5070 #define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) 5071 #define PLANE_SIZE(pipe, plane) \ 5072 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) 5073 5074 #define _PLANE_SURF_1_B 0x7119c 5075 #define _PLANE_SURF_2_B 0x7129c 5076 #define _PLANE_SURF_3_B 0x7139c 5077 #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) 5078 #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) 5079 #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) 5080 #define PLANE_SURF(pipe, plane) \ 5081 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) 5082 5083 #define _PLANE_OFFSET_1_B 0x711a4 5084 #define _PLANE_OFFSET_2_B 0x712a4 5085 #define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) 5086 #define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) 5087 #define PLANE_OFFSET(pipe, plane) \ 5088 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) 5089 5090 #define _PLANE_KEYVAL_1_B 0x71194 5091 #define _PLANE_KEYVAL_2_B 0x71294 5092 #define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) 5093 #define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) 5094 #define PLANE_KEYVAL(pipe, plane) \ 5095 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) 5096 5097 #define _PLANE_KEYMSK_1_B 0x71198 5098 #define _PLANE_KEYMSK_2_B 0x71298 5099 #define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) 5100 #define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) 5101 #define PLANE_KEYMSK(pipe, plane) \ 5102 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) 5103 5104 #define _PLANE_KEYMAX_1_B 0x711a0 5105 #define _PLANE_KEYMAX_2_B 0x712a0 5106 #define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) 5107 #define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) 5108 #define PLANE_KEYMAX(pipe, plane) \ 5109 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) 5110 5111 #define _PLANE_BUF_CFG_1_B 0x7127c 5112 #define _PLANE_BUF_CFG_2_B 0x7137c 5113 /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ 5114 #define PLANE_BUF_END_MASK REG_GENMASK(27, 16) 5115 #define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) 5116 #define PLANE_BUF_START_MASK REG_GENMASK(11, 0) 5117 #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) 5118 #define _PLANE_BUF_CFG_1(pipe) \ 5119 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) 5120 #define _PLANE_BUF_CFG_2(pipe) \ 5121 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) 5122 #define PLANE_BUF_CFG(pipe, plane) \ 5123 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) 5124 5125 #define _PLANE_NV12_BUF_CFG_1_B 0x71278 5126 #define _PLANE_NV12_BUF_CFG_2_B 0x71378 5127 #define _PLANE_NV12_BUF_CFG_1(pipe) \ 5128 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) 5129 #define _PLANE_NV12_BUF_CFG_2(pipe) \ 5130 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) 5131 #define PLANE_NV12_BUF_CFG(pipe, plane) \ 5132 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) 5133 5134 #define _PLANE_AUX_DIST_1_B 0x711c0 5135 #define _PLANE_AUX_DIST_2_B 0x712c0 5136 #define _PLANE_AUX_DIST_1(pipe) \ 5137 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) 5138 #define _PLANE_AUX_DIST_2(pipe) \ 5139 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) 5140 #define PLANE_AUX_DIST(pipe, plane) \ 5141 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) 5142 5143 #define _PLANE_AUX_OFFSET_1_B 0x711c4 5144 #define _PLANE_AUX_OFFSET_2_B 0x712c4 5145 #define _PLANE_AUX_OFFSET_1(pipe) \ 5146 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) 5147 #define _PLANE_AUX_OFFSET_2(pipe) \ 5148 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) 5149 #define PLANE_AUX_OFFSET(pipe, plane) \ 5150 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) 5151 5152 #define _PLANE_CUS_CTL_1_B 0x711c8 5153 #define _PLANE_CUS_CTL_2_B 0x712c8 5154 #define _PLANE_CUS_CTL_1(pipe) \ 5155 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) 5156 #define _PLANE_CUS_CTL_2(pipe) \ 5157 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) 5158 #define PLANE_CUS_CTL(pipe, plane) \ 5159 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) 5160 5161 #define _PLANE_COLOR_CTL_1_B 0x711CC 5162 #define _PLANE_COLOR_CTL_2_B 0x712CC 5163 #define _PLANE_COLOR_CTL_3_B 0x713CC 5164 #define _PLANE_COLOR_CTL_1(pipe) \ 5165 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) 5166 #define _PLANE_COLOR_CTL_2(pipe) \ 5167 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) 5168 #define PLANE_COLOR_CTL(pipe, plane) \ 5169 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) 5170 5171 #define _SEL_FETCH_PLANE_BASE_1_A 0x70890 5172 #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 5173 #define _SEL_FETCH_PLANE_BASE_3_A 0x708D0 5174 #define _SEL_FETCH_PLANE_BASE_4_A 0x708F0 5175 #define _SEL_FETCH_PLANE_BASE_5_A 0x70920 5176 #define _SEL_FETCH_PLANE_BASE_6_A 0x70940 5177 #define _SEL_FETCH_PLANE_BASE_7_A 0x70960 5178 #define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880 5179 #define _SEL_FETCH_PLANE_BASE_1_B 0x71890 5180 5181 #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \ 5182 _SEL_FETCH_PLANE_BASE_1_A, \ 5183 _SEL_FETCH_PLANE_BASE_2_A, \ 5184 _SEL_FETCH_PLANE_BASE_3_A, \ 5185 _SEL_FETCH_PLANE_BASE_4_A, \ 5186 _SEL_FETCH_PLANE_BASE_5_A, \ 5187 _SEL_FETCH_PLANE_BASE_6_A, \ 5188 _SEL_FETCH_PLANE_BASE_7_A, \ 5189 _SEL_FETCH_PLANE_BASE_CUR_A) 5190 #define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B) 5191 #define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \ 5192 _SEL_FETCH_PLANE_BASE_1_A + \ 5193 _SEL_FETCH_PLANE_BASE_A(plane)) 5194 5195 #define _SEL_FETCH_PLANE_CTL_1_A 0x70890 5196 #define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5197 _SEL_FETCH_PLANE_CTL_1_A - \ 5198 _SEL_FETCH_PLANE_BASE_1_A) 5199 #define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31) 5200 5201 #define _SEL_FETCH_PLANE_POS_1_A 0x70894 5202 #define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5203 _SEL_FETCH_PLANE_POS_1_A - \ 5204 _SEL_FETCH_PLANE_BASE_1_A) 5205 5206 #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 5207 #define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5208 _SEL_FETCH_PLANE_SIZE_1_A - \ 5209 _SEL_FETCH_PLANE_BASE_1_A) 5210 5211 #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C 5212 #define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 5213 _SEL_FETCH_PLANE_OFFSET_1_A - \ 5214 _SEL_FETCH_PLANE_BASE_1_A) 5215 5216 /* SKL new cursor registers */ 5217 #define _CUR_BUF_CFG_A 0x7017c 5218 #define _CUR_BUF_CFG_B 0x7117c 5219 #define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) 5220 5221 /* VBIOS regs */ 5222 #define VGACNTRL _MMIO(0x71400) 5223 # define VGA_DISP_DISABLE (1 << 31) 5224 # define VGA_2X_MODE (1 << 30) 5225 # define VGA_PIPE_B_SELECT (1 << 29) 5226 5227 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400) 5228 5229 /* Ironlake */ 5230 5231 #define CPU_VGACNTRL _MMIO(0x41000) 5232 5233 #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) 5234 #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 5235 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ 5236 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */ 5237 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */ 5238 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */ 5239 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */ 5240 #define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0) 5241 #define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0) 5242 #define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0) 5243 #define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0) 5244 5245 /* refresh rate hardware control */ 5246 #define RR_HW_CTL _MMIO(0x45300) 5247 #define RR_HW_LOW_POWER_FRAMES_MASK 0xff 5248 #define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 5249 5250 #define FDI_PLL_BIOS_0 _MMIO(0x46000) 5251 #define FDI_PLL_FB_CLOCK_MASK 0xff 5252 #define FDI_PLL_BIOS_1 _MMIO(0x46004) 5253 #define FDI_PLL_BIOS_2 _MMIO(0x46008) 5254 #define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c) 5255 #define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010) 5256 #define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014) 5257 5258 #define PCH_3DCGDIS0 _MMIO(0x46020) 5259 # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 5260 # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 5261 5262 #define PCH_3DCGDIS1 _MMIO(0x46024) 5263 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 5264 5265 #define FDI_PLL_FREQ_CTL _MMIO(0x46030) 5266 #define FDI_PLL_FREQ_CHANGE_REQUEST (1 << 24) 5267 #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 5268 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 5269 5270 5271 #define _PIPEA_DATA_M1 0x60030 5272 #define _PIPEA_DATA_N1 0x60034 5273 #define _PIPEA_DATA_M2 0x60038 5274 #define _PIPEA_DATA_N2 0x6003c 5275 #define _PIPEA_LINK_M1 0x60040 5276 #define _PIPEA_LINK_N1 0x60044 5277 #define _PIPEA_LINK_M2 0x60048 5278 #define _PIPEA_LINK_N2 0x6004c 5279 5280 /* PIPEB timing regs are same start from 0x61000 */ 5281 5282 #define _PIPEB_DATA_M1 0x61030 5283 #define _PIPEB_DATA_N1 0x61034 5284 #define _PIPEB_DATA_M2 0x61038 5285 #define _PIPEB_DATA_N2 0x6103c 5286 #define _PIPEB_LINK_M1 0x61040 5287 #define _PIPEB_LINK_N1 0x61044 5288 #define _PIPEB_LINK_M2 0x61048 5289 #define _PIPEB_LINK_N2 0x6104c 5290 5291 #define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) 5292 #define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) 5293 #define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) 5294 #define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) 5295 #define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) 5296 #define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) 5297 #define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) 5298 #define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) 5299 5300 /* CPU panel fitter */ 5301 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 5302 #define _PFA_CTL_1 0x68080 5303 #define _PFB_CTL_1 0x68880 5304 #define PF_ENABLE (1 << 31) 5305 #define PF_PIPE_SEL_MASK_IVB (3 << 29) 5306 #define PF_PIPE_SEL_IVB(pipe) ((pipe) << 29) 5307 #define PF_FILTER_MASK (3 << 23) 5308 #define PF_FILTER_PROGRAMMED (0 << 23) 5309 #define PF_FILTER_MED_3x3 (1 << 23) 5310 #define PF_FILTER_EDGE_ENHANCE (2 << 23) 5311 #define PF_FILTER_EDGE_SOFTEN (3 << 23) 5312 #define _PFA_WIN_SZ 0x68074 5313 #define _PFB_WIN_SZ 0x68874 5314 #define _PFA_WIN_POS 0x68070 5315 #define _PFB_WIN_POS 0x68870 5316 #define _PFA_VSCALE 0x68084 5317 #define _PFB_VSCALE 0x68884 5318 #define _PFA_HSCALE 0x68090 5319 #define _PFB_HSCALE 0x68890 5320 5321 #define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 5322 #define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 5323 #define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 5324 #define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 5325 #define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 5326 5327 #define _PSA_CTL 0x68180 5328 #define _PSB_CTL 0x68980 5329 #define PS_ENABLE (1 << 31) 5330 #define _PSA_WIN_SZ 0x68174 5331 #define _PSB_WIN_SZ 0x68974 5332 #define _PSA_WIN_POS 0x68170 5333 #define _PSB_WIN_POS 0x68970 5334 5335 #define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL) 5336 #define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ) 5337 #define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS) 5338 5339 /* 5340 * Skylake scalers 5341 */ 5342 #define _PS_1A_CTRL 0x68180 5343 #define _PS_2A_CTRL 0x68280 5344 #define _PS_1B_CTRL 0x68980 5345 #define _PS_2B_CTRL 0x68A80 5346 #define _PS_1C_CTRL 0x69180 5347 #define PS_SCALER_EN (1 << 31) 5348 #define SKL_PS_SCALER_MODE_MASK (3 << 28) 5349 #define SKL_PS_SCALER_MODE_DYN (0 << 28) 5350 #define SKL_PS_SCALER_MODE_HQ (1 << 28) 5351 #define SKL_PS_SCALER_MODE_NV12 (2 << 28) 5352 #define PS_SCALER_MODE_PLANAR (1 << 29) 5353 #define PS_SCALER_MODE_NORMAL (0 << 29) 5354 #define PS_PLANE_SEL_MASK (7 << 25) 5355 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25) 5356 #define PS_FILTER_MASK (3 << 23) 5357 #define PS_FILTER_MEDIUM (0 << 23) 5358 #define PS_FILTER_PROGRAMMED (1 << 23) 5359 #define PS_FILTER_EDGE_ENHANCE (2 << 23) 5360 #define PS_FILTER_BILINEAR (3 << 23) 5361 #define PS_VERT3TAP (1 << 21) 5362 #define PS_VERT_INT_INVERT_FIELD1 (0 << 20) 5363 #define PS_VERT_INT_INVERT_FIELD0 (1 << 20) 5364 #define PS_PWRUP_PROGRESS (1 << 17) 5365 #define PS_V_FILTER_BYPASS (1 << 8) 5366 #define PS_VADAPT_EN (1 << 7) 5367 #define PS_VADAPT_MODE_MASK (3 << 5) 5368 #define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5) 5369 #define PS_VADAPT_MODE_MOD_ADAPT (1 << 5) 5370 #define PS_VADAPT_MODE_MOST_ADAPT (3 << 5) 5371 #define PS_PLANE_Y_SEL_MASK (7 << 5) 5372 #define PS_PLANE_Y_SEL(plane) (((plane) + 1) << 5) 5373 #define PS_Y_VERT_FILTER_SELECT(set) ((set) << 4) 5374 #define PS_Y_HORZ_FILTER_SELECT(set) ((set) << 3) 5375 #define PS_UV_VERT_FILTER_SELECT(set) ((set) << 2) 5376 #define PS_UV_HORZ_FILTER_SELECT(set) ((set) << 1) 5377 5378 #define _PS_PWR_GATE_1A 0x68160 5379 #define _PS_PWR_GATE_2A 0x68260 5380 #define _PS_PWR_GATE_1B 0x68960 5381 #define _PS_PWR_GATE_2B 0x68A60 5382 #define _PS_PWR_GATE_1C 0x69160 5383 #define PS_PWR_GATE_DIS_OVERRIDE (1 << 31) 5384 #define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3) 5385 #define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3) 5386 #define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3) 5387 #define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3) 5388 #define PS_PWR_GATE_SLPEN_8 0 5389 #define PS_PWR_GATE_SLPEN_16 1 5390 #define PS_PWR_GATE_SLPEN_24 2 5391 #define PS_PWR_GATE_SLPEN_32 3 5392 5393 #define _PS_WIN_POS_1A 0x68170 5394 #define _PS_WIN_POS_2A 0x68270 5395 #define _PS_WIN_POS_1B 0x68970 5396 #define _PS_WIN_POS_2B 0x68A70 5397 #define _PS_WIN_POS_1C 0x69170 5398 5399 #define _PS_WIN_SZ_1A 0x68174 5400 #define _PS_WIN_SZ_2A 0x68274 5401 #define _PS_WIN_SZ_1B 0x68974 5402 #define _PS_WIN_SZ_2B 0x68A74 5403 #define _PS_WIN_SZ_1C 0x69174 5404 5405 #define _PS_VSCALE_1A 0x68184 5406 #define _PS_VSCALE_2A 0x68284 5407 #define _PS_VSCALE_1B 0x68984 5408 #define _PS_VSCALE_2B 0x68A84 5409 #define _PS_VSCALE_1C 0x69184 5410 5411 #define _PS_HSCALE_1A 0x68190 5412 #define _PS_HSCALE_2A 0x68290 5413 #define _PS_HSCALE_1B 0x68990 5414 #define _PS_HSCALE_2B 0x68A90 5415 #define _PS_HSCALE_1C 0x69190 5416 5417 #define _PS_VPHASE_1A 0x68188 5418 #define _PS_VPHASE_2A 0x68288 5419 #define _PS_VPHASE_1B 0x68988 5420 #define _PS_VPHASE_2B 0x68A88 5421 #define _PS_VPHASE_1C 0x69188 5422 #define PS_Y_PHASE(x) ((x) << 16) 5423 #define PS_UV_RGB_PHASE(x) ((x) << 0) 5424 #define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */ 5425 #define PS_PHASE_TRIP (1 << 0) 5426 5427 #define _PS_HPHASE_1A 0x68194 5428 #define _PS_HPHASE_2A 0x68294 5429 #define _PS_HPHASE_1B 0x68994 5430 #define _PS_HPHASE_2B 0x68A94 5431 #define _PS_HPHASE_1C 0x69194 5432 5433 #define _PS_ECC_STAT_1A 0x681D0 5434 #define _PS_ECC_STAT_2A 0x682D0 5435 #define _PS_ECC_STAT_1B 0x689D0 5436 #define _PS_ECC_STAT_2B 0x68AD0 5437 #define _PS_ECC_STAT_1C 0x691D0 5438 5439 #define _PS_COEF_SET0_INDEX_1A 0x68198 5440 #define _PS_COEF_SET0_INDEX_2A 0x68298 5441 #define _PS_COEF_SET0_INDEX_1B 0x68998 5442 #define _PS_COEF_SET0_INDEX_2B 0x68A98 5443 #define PS_COEE_INDEX_AUTO_INC (1 << 10) 5444 5445 #define _PS_COEF_SET0_DATA_1A 0x6819C 5446 #define _PS_COEF_SET0_DATA_2A 0x6829C 5447 #define _PS_COEF_SET0_DATA_1B 0x6899C 5448 #define _PS_COEF_SET0_DATA_2B 0x68A9C 5449 5450 #define _ID(id, a, b) _PICK_EVEN(id, a, b) 5451 #define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \ 5452 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \ 5453 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL)) 5454 #define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \ 5455 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \ 5456 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B)) 5457 #define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \ 5458 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \ 5459 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B)) 5460 #define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \ 5461 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \ 5462 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B)) 5463 #define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \ 5464 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \ 5465 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B)) 5466 #define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \ 5467 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \ 5468 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B)) 5469 #define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \ 5470 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \ 5471 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B)) 5472 #define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \ 5473 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \ 5474 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B)) 5475 #define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \ 5476 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \ 5477 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B)) 5478 #define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 5479 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \ 5480 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8) 5481 5482 #define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \ 5483 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \ 5484 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8) 5485 /* legacy palette */ 5486 #define _LGC_PALETTE_A 0x4a000 5487 #define _LGC_PALETTE_B 0x4a800 5488 #define LGC_PALETTE_RED_MASK REG_GENMASK(23, 16) 5489 #define LGC_PALETTE_GREEN_MASK REG_GENMASK(15, 8) 5490 #define LGC_PALETTE_BLUE_MASK REG_GENMASK(7, 0) 5491 #define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4) 5492 5493 /* ilk/snb precision palette */ 5494 #define _PREC_PALETTE_A 0x4b000 5495 #define _PREC_PALETTE_B 0x4c000 5496 #define PREC_PALETTE_RED_MASK REG_GENMASK(29, 20) 5497 #define PREC_PALETTE_GREEN_MASK REG_GENMASK(19, 10) 5498 #define PREC_PALETTE_BLUE_MASK REG_GENMASK(9, 0) 5499 #define PREC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _PREC_PALETTE_A, _PREC_PALETTE_B) + (i) * 4) 5500 5501 #define _PREC_PIPEAGCMAX 0x4d000 5502 #define _PREC_PIPEBGCMAX 0x4d010 5503 #define PREC_PIPEGCMAX(pipe, i) _MMIO(_PIPE(pipe, _PIPEAGCMAX, _PIPEBGCMAX) + (i) * 4) 5504 5505 #define _GAMMA_MODE_A 0x4a480 5506 #define _GAMMA_MODE_B 0x4ac80 5507 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 5508 #define PRE_CSC_GAMMA_ENABLE (1 << 31) 5509 #define POST_CSC_GAMMA_ENABLE (1 << 30) 5510 #define GAMMA_MODE_MODE_MASK (3 << 0) 5511 #define GAMMA_MODE_MODE_8BIT (0 << 0) 5512 #define GAMMA_MODE_MODE_10BIT (1 << 0) 5513 #define GAMMA_MODE_MODE_12BIT (2 << 0) 5514 #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */ 5515 #define GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED (3 << 0) /* icl + */ 5516 5517 /* Display Internal Timeout Register */ 5518 #define RM_TIMEOUT _MMIO(0x42060) 5519 #define MMIO_TIMEOUT_US(us) ((us) << 0) 5520 5521 /* interrupts */ 5522 #define DE_MASTER_IRQ_CONTROL (1 << 31) 5523 #define DE_SPRITEB_FLIP_DONE (1 << 29) 5524 #define DE_SPRITEA_FLIP_DONE (1 << 28) 5525 #define DE_PLANEB_FLIP_DONE (1 << 27) 5526 #define DE_PLANEA_FLIP_DONE (1 << 26) 5527 #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 5528 #define DE_PCU_EVENT (1 << 25) 5529 #define DE_GTT_FAULT (1 << 24) 5530 #define DE_POISON (1 << 23) 5531 #define DE_PERFORM_COUNTER (1 << 22) 5532 #define DE_PCH_EVENT (1 << 21) 5533 #define DE_AUX_CHANNEL_A (1 << 20) 5534 #define DE_DP_A_HOTPLUG (1 << 19) 5535 #define DE_GSE (1 << 18) 5536 #define DE_PIPEB_VBLANK (1 << 15) 5537 #define DE_PIPEB_EVEN_FIELD (1 << 14) 5538 #define DE_PIPEB_ODD_FIELD (1 << 13) 5539 #define DE_PIPEB_LINE_COMPARE (1 << 12) 5540 #define DE_PIPEB_VSYNC (1 << 11) 5541 #define DE_PIPEB_CRC_DONE (1 << 10) 5542 #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 5543 #define DE_PIPEA_VBLANK (1 << 7) 5544 #define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe))) 5545 #define DE_PIPEA_EVEN_FIELD (1 << 6) 5546 #define DE_PIPEA_ODD_FIELD (1 << 5) 5547 #define DE_PIPEA_LINE_COMPARE (1 << 4) 5548 #define DE_PIPEA_VSYNC (1 << 3) 5549 #define DE_PIPEA_CRC_DONE (1 << 2) 5550 #define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe))) 5551 #define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 5552 #define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe))) 5553 5554 /* More Ivybridge lolz */ 5555 #define DE_ERR_INT_IVB (1 << 30) 5556 #define DE_GSE_IVB (1 << 29) 5557 #define DE_PCH_EVENT_IVB (1 << 28) 5558 #define DE_DP_A_HOTPLUG_IVB (1 << 27) 5559 #define DE_AUX_CHANNEL_A_IVB (1 << 26) 5560 #define DE_EDP_PSR_INT_HSW (1 << 19) 5561 #define DE_SPRITEC_FLIP_DONE_IVB (1 << 14) 5562 #define DE_PLANEC_FLIP_DONE_IVB (1 << 13) 5563 #define DE_PIPEC_VBLANK_IVB (1 << 10) 5564 #define DE_SPRITEB_FLIP_DONE_IVB (1 << 9) 5565 #define DE_PLANEB_FLIP_DONE_IVB (1 << 8) 5566 #define DE_PIPEB_VBLANK_IVB (1 << 5) 5567 #define DE_SPRITEA_FLIP_DONE_IVB (1 << 4) 5568 #define DE_PLANEA_FLIP_DONE_IVB (1 << 3) 5569 #define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane))) 5570 #define DE_PIPEA_VBLANK_IVB (1 << 0) 5571 #define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5)) 5572 5573 #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ 5574 #define MASTER_INTERRUPT_ENABLE (1 << 31) 5575 5576 #define DEISR _MMIO(0x44000) 5577 #define DEIMR _MMIO(0x44004) 5578 #define DEIIR _MMIO(0x44008) 5579 #define DEIER _MMIO(0x4400c) 5580 5581 #define GTISR _MMIO(0x44010) 5582 #define GTIMR _MMIO(0x44014) 5583 #define GTIIR _MMIO(0x44018) 5584 #define GTIER _MMIO(0x4401c) 5585 5586 #define GEN8_MASTER_IRQ _MMIO(0x44200) 5587 #define GEN8_MASTER_IRQ_CONTROL (1 << 31) 5588 #define GEN8_PCU_IRQ (1 << 30) 5589 #define GEN8_DE_PCH_IRQ (1 << 23) 5590 #define GEN8_DE_MISC_IRQ (1 << 22) 5591 #define GEN8_DE_PORT_IRQ (1 << 20) 5592 #define GEN8_DE_PIPE_C_IRQ (1 << 18) 5593 #define GEN8_DE_PIPE_B_IRQ (1 << 17) 5594 #define GEN8_DE_PIPE_A_IRQ (1 << 16) 5595 #define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe))) 5596 #define GEN8_GT_VECS_IRQ (1 << 6) 5597 #define GEN8_GT_GUC_IRQ (1 << 5) 5598 #define GEN8_GT_PM_IRQ (1 << 4) 5599 #define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */ 5600 #define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */ 5601 #define GEN8_GT_BCS_IRQ (1 << 1) 5602 #define GEN8_GT_RCS_IRQ (1 << 0) 5603 5604 #define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c) 5605 5606 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which))) 5607 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which))) 5608 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which))) 5609 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which))) 5610 5611 #define GEN8_RCS_IRQ_SHIFT 0 5612 #define GEN8_BCS_IRQ_SHIFT 16 5613 #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */ 5614 #define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */ 5615 #define GEN8_VECS_IRQ_SHIFT 0 5616 #define GEN8_WD_IRQ_SHIFT 16 5617 5618 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe))) 5619 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe))) 5620 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe))) 5621 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe))) 5622 #define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 5623 #define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 5624 #define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 5625 #define XELPD_PIPE_SOFT_UNDERRUN (1 << 22) 5626 #define XELPD_PIPE_HARD_UNDERRUN (1 << 21) 5627 #define GEN8_PIPE_CURSOR_FAULT (1 << 10) 5628 #define GEN8_PIPE_SPRITE_FAULT (1 << 9) 5629 #define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 5630 #define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 5631 #define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 5632 #define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 5633 #define GEN8_PIPE_VSYNC (1 << 1) 5634 #define GEN8_PIPE_VBLANK (1 << 0) 5635 #define GEN9_PIPE_CURSOR_FAULT (1 << 11) 5636 #define GEN11_PIPE_PLANE7_FAULT (1 << 22) 5637 #define GEN11_PIPE_PLANE6_FAULT (1 << 21) 5638 #define GEN11_PIPE_PLANE5_FAULT (1 << 20) 5639 #define GEN9_PIPE_PLANE4_FAULT (1 << 10) 5640 #define GEN9_PIPE_PLANE3_FAULT (1 << 9) 5641 #define GEN9_PIPE_PLANE2_FAULT (1 << 8) 5642 #define GEN9_PIPE_PLANE1_FAULT (1 << 7) 5643 #define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6) 5644 #define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5) 5645 #define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4) 5646 #define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3) 5647 #define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p))) 5648 #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 5649 (GEN8_PIPE_CURSOR_FAULT | \ 5650 GEN8_PIPE_SPRITE_FAULT | \ 5651 GEN8_PIPE_PRIMARY_FAULT) 5652 #define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \ 5653 (GEN9_PIPE_CURSOR_FAULT | \ 5654 GEN9_PIPE_PLANE4_FAULT | \ 5655 GEN9_PIPE_PLANE3_FAULT | \ 5656 GEN9_PIPE_PLANE2_FAULT | \ 5657 GEN9_PIPE_PLANE1_FAULT) 5658 #define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \ 5659 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 5660 GEN11_PIPE_PLANE7_FAULT | \ 5661 GEN11_PIPE_PLANE6_FAULT | \ 5662 GEN11_PIPE_PLANE5_FAULT) 5663 #define RKL_DE_PIPE_IRQ_FAULT_ERRORS \ 5664 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \ 5665 GEN11_PIPE_PLANE5_FAULT) 5666 5667 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) 5668 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1) 5669 5670 #define GEN8_DE_PORT_ISR _MMIO(0x44440) 5671 #define GEN8_DE_PORT_IMR _MMIO(0x44444) 5672 #define GEN8_DE_PORT_IIR _MMIO(0x44448) 5673 #define GEN8_DE_PORT_IER _MMIO(0x4444c) 5674 #define DSI1_NON_TE (1 << 31) 5675 #define DSI0_NON_TE (1 << 30) 5676 #define ICL_AUX_CHANNEL_E (1 << 29) 5677 #define ICL_AUX_CHANNEL_F (1 << 28) 5678 #define GEN9_AUX_CHANNEL_D (1 << 27) 5679 #define GEN9_AUX_CHANNEL_C (1 << 26) 5680 #define GEN9_AUX_CHANNEL_B (1 << 25) 5681 #define DSI1_TE (1 << 24) 5682 #define DSI0_TE (1 << 23) 5683 #define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin)) 5684 #define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \ 5685 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \ 5686 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) 5687 #define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) 5688 #define BXT_DE_PORT_GMBUS (1 << 1) 5689 #define GEN8_AUX_CHANNEL_A (1 << 0) 5690 #define TGL_DE_PORT_AUX_USBC6 REG_BIT(13) 5691 #define XELPD_DE_PORT_AUX_DDIE REG_BIT(13) 5692 #define TGL_DE_PORT_AUX_USBC5 REG_BIT(12) 5693 #define XELPD_DE_PORT_AUX_DDID REG_BIT(12) 5694 #define TGL_DE_PORT_AUX_USBC4 REG_BIT(11) 5695 #define TGL_DE_PORT_AUX_USBC3 REG_BIT(10) 5696 #define TGL_DE_PORT_AUX_USBC2 REG_BIT(9) 5697 #define TGL_DE_PORT_AUX_USBC1 REG_BIT(8) 5698 #define TGL_DE_PORT_AUX_DDIC REG_BIT(2) 5699 #define TGL_DE_PORT_AUX_DDIB REG_BIT(1) 5700 #define TGL_DE_PORT_AUX_DDIA REG_BIT(0) 5701 5702 #define GEN8_DE_MISC_ISR _MMIO(0x44460) 5703 #define GEN8_DE_MISC_IMR _MMIO(0x44464) 5704 #define GEN8_DE_MISC_IIR _MMIO(0x44468) 5705 #define GEN8_DE_MISC_IER _MMIO(0x4446c) 5706 #define GEN8_DE_MISC_GSE (1 << 27) 5707 #define GEN8_DE_EDP_PSR (1 << 19) 5708 5709 #define GEN8_PCU_ISR _MMIO(0x444e0) 5710 #define GEN8_PCU_IMR _MMIO(0x444e4) 5711 #define GEN8_PCU_IIR _MMIO(0x444e8) 5712 #define GEN8_PCU_IER _MMIO(0x444ec) 5713 5714 #define GEN11_GU_MISC_ISR _MMIO(0x444f0) 5715 #define GEN11_GU_MISC_IMR _MMIO(0x444f4) 5716 #define GEN11_GU_MISC_IIR _MMIO(0x444f8) 5717 #define GEN11_GU_MISC_IER _MMIO(0x444fc) 5718 #define GEN11_GU_MISC_GSE (1 << 27) 5719 5720 #define GEN11_GFX_MSTR_IRQ _MMIO(0x190010) 5721 #define GEN11_MASTER_IRQ (1 << 31) 5722 #define GEN11_PCU_IRQ (1 << 30) 5723 #define GEN11_GU_MISC_IRQ (1 << 29) 5724 #define GEN11_DISPLAY_IRQ (1 << 16) 5725 #define GEN11_GT_DW_IRQ(x) (1 << (x)) 5726 #define GEN11_GT_DW1_IRQ (1 << 1) 5727 #define GEN11_GT_DW0_IRQ (1 << 0) 5728 5729 #define DG1_MSTR_TILE_INTR _MMIO(0x190008) 5730 #define DG1_MSTR_IRQ REG_BIT(31) 5731 #define DG1_MSTR_TILE(t) REG_BIT(t) 5732 5733 #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) 5734 #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) 5735 #define GEN11_AUDIO_CODEC_IRQ (1 << 24) 5736 #define GEN11_DE_PCH_IRQ (1 << 23) 5737 #define GEN11_DE_MISC_IRQ (1 << 22) 5738 #define GEN11_DE_HPD_IRQ (1 << 21) 5739 #define GEN11_DE_PORT_IRQ (1 << 20) 5740 #define GEN11_DE_PIPE_C (1 << 18) 5741 #define GEN11_DE_PIPE_B (1 << 17) 5742 #define GEN11_DE_PIPE_A (1 << 16) 5743 5744 #define GEN11_DE_HPD_ISR _MMIO(0x44470) 5745 #define GEN11_DE_HPD_IMR _MMIO(0x44474) 5746 #define GEN11_DE_HPD_IIR _MMIO(0x44478) 5747 #define GEN11_DE_HPD_IER _MMIO(0x4447c) 5748 #define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin)) 5749 #define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \ 5750 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \ 5751 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \ 5752 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \ 5753 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \ 5754 GEN11_TC_HOTPLUG(HPD_PORT_TC1)) 5755 #define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) 5756 #define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \ 5757 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \ 5758 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \ 5759 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \ 5760 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \ 5761 GEN11_TBT_HOTPLUG(HPD_PORT_TC1)) 5762 5763 #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) 5764 #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) 5765 #define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 5766 #define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 5767 #define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 5768 #define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4)) 5769 5770 #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) 5771 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ 5772 #define ILK_ELPIN_409_SELECT (1 << 25) 5773 #define ILK_DPARB_GATE (1 << 22) 5774 #define ILK_VSDPFD_FULL (1 << 21) 5775 #define FUSE_STRAP _MMIO(0x42014) 5776 #define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) 5777 #define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) 5778 #define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) 5779 #define IVB_PIPE_C_DISABLE (1 << 28) 5780 #define ILK_HDCP_DISABLE (1 << 25) 5781 #define ILK_eDP_A_DISABLE (1 << 24) 5782 #define HSW_CDCLK_LIMIT (1 << 24) 5783 #define ILK_DESKTOP (1 << 23) 5784 #define HSW_CPU_SSC_ENABLE (1 << 21) 5785 5786 #define FUSE_STRAP3 _MMIO(0x42020) 5787 #define HSW_REF_CLK_SELECT (1 << 1) 5788 5789 #define ILK_DSPCLK_GATE_D _MMIO(0x42020) 5790 #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 5791 #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 5792 #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 5793 #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 5794 #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 5795 5796 #define IVB_CHICKEN3 _MMIO(0x4200c) 5797 # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 5798 # define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 5799 5800 #define CHICKEN_PAR1_1 _MMIO(0x42080) 5801 #define IGNORE_KVMR_PIPE_A REG_BIT(23) 5802 #define KBL_ARB_FILL_SPARE_22 REG_BIT(22) 5803 #define DIS_RAM_BYPASS_PSR2_MAN_TRACK (1 << 16) 5804 #define SKL_DE_COMPRESSED_HASH_MODE (1 << 15) 5805 #define DPA_MASK_VBLANK_SRD (1 << 15) 5806 #define FORCE_ARB_IDLE_PLANES (1 << 14) 5807 #define SKL_EDP_PSR_FIX_RDWRAP (1 << 3) 5808 #define IGNORE_PSR2_HW_TRACKING (1 << 1) 5809 5810 #define CHICKEN_PAR2_1 _MMIO(0x42090) 5811 #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT (1 << 14) 5812 5813 #define CHICKEN_MISC_2 _MMIO(0x42084) 5814 #define KBL_ARB_FILL_SPARE_14 REG_BIT(14) 5815 #define KBL_ARB_FILL_SPARE_13 REG_BIT(13) 5816 #define GLK_CL2_PWR_DOWN (1 << 12) 5817 #define GLK_CL1_PWR_DOWN (1 << 11) 5818 #define GLK_CL0_PWR_DOWN (1 << 10) 5819 5820 #define CHICKEN_MISC_4 _MMIO(0x4208c) 5821 #define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13) 5822 #define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0) 5823 #define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x)) 5824 5825 #define _CHICKEN_PIPESL_1_A 0x420b0 5826 #define _CHICKEN_PIPESL_1_B 0x420b4 5827 #define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27) 5828 #define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0) 5829 #define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1) 5830 #define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2) 5831 #define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3) 5832 #define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25) 5833 #define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0) 5834 #define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1) 5835 #define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2) 5836 #define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3) 5837 #define HSW_FBCQ_DIS (1 << 22) 5838 #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 5839 #define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0) 5840 #define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0) 5841 #define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1) 5842 #define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2) 5843 #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) 5844 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 5845 5846 #define _CHICKEN_TRANS_A 0x420c0 5847 #define _CHICKEN_TRANS_B 0x420c4 5848 #define _CHICKEN_TRANS_C 0x420c8 5849 #define _CHICKEN_TRANS_EDP 0x420cc 5850 #define _CHICKEN_TRANS_D 0x420d8 5851 #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ 5852 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ 5853 [TRANSCODER_A] = _CHICKEN_TRANS_A, \ 5854 [TRANSCODER_B] = _CHICKEN_TRANS_B, \ 5855 [TRANSCODER_C] = _CHICKEN_TRANS_C, \ 5856 [TRANSCODER_D] = _CHICKEN_TRANS_D)) 5857 #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) 5858 #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x) 5859 #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */ 5860 #define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23) 5861 #define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19) 5862 #define ADLP_1_BASED_X_GRANULARITY REG_BIT(18) 5863 #define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18) 5864 #define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */ 5865 #define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */ 5866 #define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15) 5867 #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) 5868 5869 #define DISP_ARB_CTL _MMIO(0x45000) 5870 #define DISP_FBC_MEMORY_WAKE (1 << 31) 5871 #define DISP_TILE_SURFACE_SWIZZLING (1 << 13) 5872 #define DISP_FBC_WM_DIS (1 << 15) 5873 #define DISP_ARB_CTL2 _MMIO(0x45004) 5874 #define DISP_DATA_PARTITION_5_6 (1 << 6) 5875 #define DISP_IPC_ENABLE (1 << 3) 5876 5877 /* 5878 * The below are numbered starting from "S1" on gen11/gen12, but starting 5879 * with display 13, the bspec switches to a 0-based numbering scheme 5880 * (although the addresses stay the same so new S0 = old S1, new S1 = old S2). 5881 * We'll just use the 0-based numbering here for all platforms since it's the 5882 * way things will be named by the hardware team going forward, plus it's more 5883 * consistent with how most of the rest of our registers are named. 5884 */ 5885 #define _DBUF_CTL_S0 0x45008 5886 #define _DBUF_CTL_S1 0x44FE8 5887 #define _DBUF_CTL_S2 0x44300 5888 #define _DBUF_CTL_S3 0x44304 5889 #define DBUF_CTL_S(slice) _MMIO(_PICK(slice, \ 5890 _DBUF_CTL_S0, \ 5891 _DBUF_CTL_S1, \ 5892 _DBUF_CTL_S2, \ 5893 _DBUF_CTL_S3)) 5894 #define DBUF_POWER_REQUEST REG_BIT(31) 5895 #define DBUF_POWER_STATE REG_BIT(30) 5896 #define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19) 5897 #define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x) 5898 #define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */ 5899 #define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */ 5900 5901 #define GEN7_MSG_CTL _MMIO(0x45010) 5902 #define WAIT_FOR_PCH_RESET_ACK (1 << 1) 5903 #define WAIT_FOR_PCH_FLR_ACK (1 << 0) 5904 5905 #define _BW_BUDDY0_CTL 0x45130 5906 #define _BW_BUDDY1_CTL 0x45140 5907 #define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \ 5908 _BW_BUDDY0_CTL, \ 5909 _BW_BUDDY1_CTL)) 5910 #define BW_BUDDY_DISABLE REG_BIT(31) 5911 #define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16) 5912 #define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x) 5913 5914 #define _BW_BUDDY0_PAGE_MASK 0x45134 5915 #define _BW_BUDDY1_PAGE_MASK 0x45144 5916 #define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \ 5917 _BW_BUDDY0_PAGE_MASK, \ 5918 _BW_BUDDY1_PAGE_MASK)) 5919 5920 #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) 5921 #define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) 5922 5923 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 5924 #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) 5925 #define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25) 5926 #define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24) 5927 #define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23) 5928 #define ICL_DELAY_PMRSP REG_BIT(22) 5929 #define DISABLE_FLR_SRC REG_BIT(15) 5930 #define MASK_WAKEMEM REG_BIT(13) 5931 #define DDI_CLOCK_REG_ACCESS REG_BIT(7) 5932 5933 #define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434) 5934 #define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27) 5935 #define DCPR_MASK_LPMODE REG_BIT(26) 5936 #define DCPR_SEND_RESP_IMM REG_BIT(25) 5937 #define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24) 5938 5939 #define SKL_DFSM _MMIO(0x51000) 5940 #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27) 5941 #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25) 5942 #define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23) 5943 #define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23) 5944 #define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23) 5945 #define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23) 5946 #define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23) 5947 #define ICL_DFSM_DMC_DISABLE (1 << 23) 5948 #define SKL_DFSM_PIPE_A_DISABLE (1 << 30) 5949 #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) 5950 #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) 5951 #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) 5952 #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7) 5953 5954 #define SKL_DSSM _MMIO(0x51004) 5955 #define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29) 5956 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29) 5957 #define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29) 5958 #define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29) 5959 5960 /*GEN11 chicken */ 5961 #define _PIPEA_CHICKEN 0x70038 5962 #define _PIPEB_CHICKEN 0x71038 5963 #define _PIPEC_CHICKEN 0x72038 5964 #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\ 5965 _PIPEB_CHICKEN) 5966 #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30) 5967 #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30) 5968 #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15) 5969 #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12) 5970 #define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7) 5971 5972 /* PCH */ 5973 5974 #define PCH_DISPLAY_BASE 0xc0000u 5975 5976 /* south display engine interrupt: IBX */ 5977 #define SDE_AUDIO_POWER_D (1 << 27) 5978 #define SDE_AUDIO_POWER_C (1 << 26) 5979 #define SDE_AUDIO_POWER_B (1 << 25) 5980 #define SDE_AUDIO_POWER_SHIFT (25) 5981 #define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 5982 #define SDE_GMBUS (1 << 24) 5983 #define SDE_AUDIO_HDCP_TRANSB (1 << 23) 5984 #define SDE_AUDIO_HDCP_TRANSA (1 << 22) 5985 #define SDE_AUDIO_HDCP_MASK (3 << 22) 5986 #define SDE_AUDIO_TRANSB (1 << 21) 5987 #define SDE_AUDIO_TRANSA (1 << 20) 5988 #define SDE_AUDIO_TRANS_MASK (3 << 20) 5989 #define SDE_POISON (1 << 19) 5990 /* 18 reserved */ 5991 #define SDE_FDI_RXB (1 << 17) 5992 #define SDE_FDI_RXA (1 << 16) 5993 #define SDE_FDI_MASK (3 << 16) 5994 #define SDE_AUXD (1 << 15) 5995 #define SDE_AUXC (1 << 14) 5996 #define SDE_AUXB (1 << 13) 5997 #define SDE_AUX_MASK (7 << 13) 5998 /* 12 reserved */ 5999 #define SDE_CRT_HOTPLUG (1 << 11) 6000 #define SDE_PORTD_HOTPLUG (1 << 10) 6001 #define SDE_PORTC_HOTPLUG (1 << 9) 6002 #define SDE_PORTB_HOTPLUG (1 << 8) 6003 #define SDE_SDVOB_HOTPLUG (1 << 6) 6004 #define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 6005 SDE_SDVOB_HOTPLUG | \ 6006 SDE_PORTB_HOTPLUG | \ 6007 SDE_PORTC_HOTPLUG | \ 6008 SDE_PORTD_HOTPLUG) 6009 #define SDE_TRANSB_CRC_DONE (1 << 5) 6010 #define SDE_TRANSB_CRC_ERR (1 << 4) 6011 #define SDE_TRANSB_FIFO_UNDER (1 << 3) 6012 #define SDE_TRANSA_CRC_DONE (1 << 2) 6013 #define SDE_TRANSA_CRC_ERR (1 << 1) 6014 #define SDE_TRANSA_FIFO_UNDER (1 << 0) 6015 #define SDE_TRANS_MASK (0x3f) 6016 6017 /* south display engine interrupt: CPT - CNP */ 6018 #define SDE_AUDIO_POWER_D_CPT (1 << 31) 6019 #define SDE_AUDIO_POWER_C_CPT (1 << 30) 6020 #define SDE_AUDIO_POWER_B_CPT (1 << 29) 6021 #define SDE_AUDIO_POWER_SHIFT_CPT 29 6022 #define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 6023 #define SDE_AUXD_CPT (1 << 27) 6024 #define SDE_AUXC_CPT (1 << 26) 6025 #define SDE_AUXB_CPT (1 << 25) 6026 #define SDE_AUX_MASK_CPT (7 << 25) 6027 #define SDE_PORTE_HOTPLUG_SPT (1 << 25) 6028 #define SDE_PORTA_HOTPLUG_SPT (1 << 24) 6029 #define SDE_PORTD_HOTPLUG_CPT (1 << 23) 6030 #define SDE_PORTC_HOTPLUG_CPT (1 << 22) 6031 #define SDE_PORTB_HOTPLUG_CPT (1 << 21) 6032 #define SDE_CRT_HOTPLUG_CPT (1 << 19) 6033 #define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 6034 #define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 6035 SDE_SDVOB_HOTPLUG_CPT | \ 6036 SDE_PORTD_HOTPLUG_CPT | \ 6037 SDE_PORTC_HOTPLUG_CPT | \ 6038 SDE_PORTB_HOTPLUG_CPT) 6039 #define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \ 6040 SDE_PORTD_HOTPLUG_CPT | \ 6041 SDE_PORTC_HOTPLUG_CPT | \ 6042 SDE_PORTB_HOTPLUG_CPT | \ 6043 SDE_PORTA_HOTPLUG_SPT) 6044 #define SDE_GMBUS_CPT (1 << 17) 6045 #define SDE_ERROR_CPT (1 << 16) 6046 #define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 6047 #define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 6048 #define SDE_FDI_RXC_CPT (1 << 8) 6049 #define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 6050 #define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 6051 #define SDE_FDI_RXB_CPT (1 << 4) 6052 #define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 6053 #define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 6054 #define SDE_FDI_RXA_CPT (1 << 0) 6055 #define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 6056 SDE_AUDIO_CP_REQ_B_CPT | \ 6057 SDE_AUDIO_CP_REQ_A_CPT) 6058 #define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 6059 SDE_AUDIO_CP_CHG_B_CPT | \ 6060 SDE_AUDIO_CP_CHG_A_CPT) 6061 #define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 6062 SDE_FDI_RXB_CPT | \ 6063 SDE_FDI_RXA_CPT) 6064 6065 /* south display engine interrupt: ICP/TGP */ 6066 #define SDE_GMBUS_ICP (1 << 23) 6067 #define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin)) 6068 #define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */ 6069 #define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin)) 6070 #define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \ 6071 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \ 6072 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \ 6073 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A)) 6074 #define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \ 6075 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \ 6076 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \ 6077 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \ 6078 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \ 6079 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1)) 6080 6081 #define SDEISR _MMIO(0xc4000) 6082 #define SDEIMR _MMIO(0xc4004) 6083 #define SDEIIR _MMIO(0xc4008) 6084 #define SDEIER _MMIO(0xc400c) 6085 6086 #define SERR_INT _MMIO(0xc4040) 6087 #define SERR_INT_POISON (1 << 31) 6088 #define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) 6089 6090 /* digital port hotplug */ 6091 #define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */ 6092 #define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */ 6093 #define BXT_DDIA_HPD_INVERT (1 << 27) 6094 #define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */ 6095 #define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */ 6096 #define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */ 6097 #define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */ 6098 #define PORTD_HOTPLUG_ENABLE (1 << 20) 6099 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */ 6100 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */ 6101 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */ 6102 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */ 6103 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */ 6104 #define PORTD_HOTPLUG_STATUS_MASK (3 << 16) 6105 #define PORTD_HOTPLUG_NO_DETECT (0 << 16) 6106 #define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 6107 #define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 6108 #define PORTC_HOTPLUG_ENABLE (1 << 12) 6109 #define BXT_DDIC_HPD_INVERT (1 << 11) 6110 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */ 6111 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */ 6112 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */ 6113 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */ 6114 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */ 6115 #define PORTC_HOTPLUG_STATUS_MASK (3 << 8) 6116 #define PORTC_HOTPLUG_NO_DETECT (0 << 8) 6117 #define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 6118 #define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 6119 #define PORTB_HOTPLUG_ENABLE (1 << 4) 6120 #define BXT_DDIB_HPD_INVERT (1 << 3) 6121 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */ 6122 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */ 6123 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */ 6124 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */ 6125 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */ 6126 #define PORTB_HOTPLUG_STATUS_MASK (3 << 0) 6127 #define PORTB_HOTPLUG_NO_DETECT (0 << 0) 6128 #define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 6129 #define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 6130 #define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ 6131 BXT_DDIB_HPD_INVERT | \ 6132 BXT_DDIC_HPD_INVERT) 6133 6134 #define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */ 6135 #define PORTE_HOTPLUG_ENABLE (1 << 4) 6136 #define PORTE_HOTPLUG_STATUS_MASK (3 << 0) 6137 #define PORTE_HOTPLUG_NO_DETECT (0 << 0) 6138 #define PORTE_HOTPLUG_SHORT_DETECT (1 << 0) 6139 #define PORTE_HOTPLUG_LONG_DETECT (2 << 0) 6140 6141 /* This register is a reuse of PCH_PORT_HOTPLUG register. The 6142 * functionality covered in PCH_PORT_HOTPLUG is split into 6143 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC. 6144 */ 6145 6146 #define SHOTPLUG_CTL_DDI _MMIO(0xc4030) 6147 #define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6148 #define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6149 #define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6150 #define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6151 #define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6152 #define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4)) 6153 6154 #define SHOTPLUG_CTL_TC _MMIO(0xc4034) 6155 #define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4)) 6156 #define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4)) 6157 #define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4)) 6158 6159 #define SHPD_FILTER_CNT _MMIO(0xc4038) 6160 #define SHPD_FILTER_CNT_500_ADJ 0x001D9 6161 6162 #define _PCH_DPLL_A 0xc6014 6163 #define _PCH_DPLL_B 0xc6018 6164 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 6165 6166 #define _PCH_FPA0 0xc6040 6167 #define FP_CB_TUNE (0x3 << 22) 6168 #define _PCH_FPA1 0xc6044 6169 #define _PCH_FPB0 0xc6048 6170 #define _PCH_FPB1 0xc604c 6171 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0) 6172 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1) 6173 6174 #define PCH_DPLL_TEST _MMIO(0xc606c) 6175 6176 #define PCH_DREF_CONTROL _MMIO(0xC6200) 6177 #define DREF_CONTROL_MASK 0x7fc3 6178 #define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13) 6179 #define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13) 6180 #define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13) 6181 #define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13) 6182 #define DREF_SSC_SOURCE_DISABLE (0 << 11) 6183 #define DREF_SSC_SOURCE_ENABLE (2 << 11) 6184 #define DREF_SSC_SOURCE_MASK (3 << 11) 6185 #define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9) 6186 #define DREF_NONSPREAD_CK505_ENABLE (1 << 9) 6187 #define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9) 6188 #define DREF_NONSPREAD_SOURCE_MASK (3 << 9) 6189 #define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7) 6190 #define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7) 6191 #define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7) 6192 #define DREF_SSC4_DOWNSPREAD (0 << 6) 6193 #define DREF_SSC4_CENTERSPREAD (1 << 6) 6194 #define DREF_SSC1_DISABLE (0 << 1) 6195 #define DREF_SSC1_ENABLE (1 << 1) 6196 #define DREF_SSC4_DISABLE (0) 6197 #define DREF_SSC4_ENABLE (1) 6198 6199 #define PCH_RAWCLK_FREQ _MMIO(0xc6204) 6200 #define FDL_TP1_TIMER_SHIFT 12 6201 #define FDL_TP1_TIMER_MASK (3 << 12) 6202 #define FDL_TP2_TIMER_SHIFT 10 6203 #define FDL_TP2_TIMER_MASK (3 << 10) 6204 #define RAWCLK_FREQ_MASK 0x3ff 6205 #define CNP_RAWCLK_DIV_MASK (0x3ff << 16) 6206 #define CNP_RAWCLK_DIV(div) ((div) << 16) 6207 #define CNP_RAWCLK_FRAC_MASK (0xf << 26) 6208 #define CNP_RAWCLK_DEN(den) ((den) << 26) 6209 #define ICP_RAWCLK_NUM(num) ((num) << 11) 6210 6211 #define PCH_DPLL_TMR_CFG _MMIO(0xc6208) 6212 6213 #define PCH_SSC4_PARMS _MMIO(0xc6210) 6214 #define PCH_SSC4_AUX_PARMS _MMIO(0xc6214) 6215 6216 #define PCH_DPLL_SEL _MMIO(0xc7000) 6217 #define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4)) 6218 #define TRANS_DPLLA_SEL(pipe) 0 6219 #define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3)) 6220 6221 /* transcoder */ 6222 6223 #define _PCH_TRANS_HTOTAL_A 0xe0000 6224 #define TRANS_HTOTAL_SHIFT 16 6225 #define TRANS_HACTIVE_SHIFT 0 6226 #define _PCH_TRANS_HBLANK_A 0xe0004 6227 #define TRANS_HBLANK_END_SHIFT 16 6228 #define TRANS_HBLANK_START_SHIFT 0 6229 #define _PCH_TRANS_HSYNC_A 0xe0008 6230 #define TRANS_HSYNC_END_SHIFT 16 6231 #define TRANS_HSYNC_START_SHIFT 0 6232 #define _PCH_TRANS_VTOTAL_A 0xe000c 6233 #define TRANS_VTOTAL_SHIFT 16 6234 #define TRANS_VACTIVE_SHIFT 0 6235 #define _PCH_TRANS_VBLANK_A 0xe0010 6236 #define TRANS_VBLANK_END_SHIFT 16 6237 #define TRANS_VBLANK_START_SHIFT 0 6238 #define _PCH_TRANS_VSYNC_A 0xe0014 6239 #define TRANS_VSYNC_END_SHIFT 16 6240 #define TRANS_VSYNC_START_SHIFT 0 6241 #define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 6242 6243 #define _PCH_TRANSA_DATA_M1 0xe0030 6244 #define _PCH_TRANSA_DATA_N1 0xe0034 6245 #define _PCH_TRANSA_DATA_M2 0xe0038 6246 #define _PCH_TRANSA_DATA_N2 0xe003c 6247 #define _PCH_TRANSA_LINK_M1 0xe0040 6248 #define _PCH_TRANSA_LINK_N1 0xe0044 6249 #define _PCH_TRANSA_LINK_M2 0xe0048 6250 #define _PCH_TRANSA_LINK_N2 0xe004c 6251 6252 /* Per-transcoder DIP controls (PCH) */ 6253 #define _VIDEO_DIP_CTL_A 0xe0200 6254 #define _VIDEO_DIP_DATA_A 0xe0208 6255 #define _VIDEO_DIP_GCP_A 0xe0210 6256 #define GCP_COLOR_INDICATION (1 << 2) 6257 #define GCP_DEFAULT_PHASE_ENABLE (1 << 1) 6258 #define GCP_AV_MUTE (1 << 0) 6259 6260 #define _VIDEO_DIP_CTL_B 0xe1200 6261 #define _VIDEO_DIP_DATA_B 0xe1208 6262 #define _VIDEO_DIP_GCP_B 0xe1210 6263 6264 #define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 6265 #define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 6266 #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 6267 6268 /* Per-transcoder DIP controls (VLV) */ 6269 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 6270 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 6271 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 6272 6273 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 6274 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 6275 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 6276 6277 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) 6278 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) 6279 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) 6280 6281 #define VLV_TVIDEO_DIP_CTL(pipe) \ 6282 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ 6283 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) 6284 #define VLV_TVIDEO_DIP_DATA(pipe) \ 6285 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ 6286 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) 6287 #define VLV_TVIDEO_DIP_GCP(pipe) \ 6288 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 6289 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 6290 6291 /* Haswell DIP controls */ 6292 6293 #define _HSW_VIDEO_DIP_CTL_A 0x60200 6294 #define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220 6295 #define _HSW_VIDEO_DIP_VS_DATA_A 0x60260 6296 #define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 6297 #define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 6298 #define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320 6299 #define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440 6300 #define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240 6301 #define _HSW_VIDEO_DIP_VS_ECC_A 0x60280 6302 #define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 6303 #define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300 6304 #define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344 6305 #define _HSW_VIDEO_DIP_GCP_A 0x60210 6306 6307 #define _HSW_VIDEO_DIP_CTL_B 0x61200 6308 #define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220 6309 #define _HSW_VIDEO_DIP_VS_DATA_B 0x61260 6310 #define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 6311 #define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 6312 #define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320 6313 #define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440 6314 #define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240 6315 #define _HSW_VIDEO_DIP_VS_ECC_B 0x61280 6316 #define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 6317 #define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300 6318 #define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344 6319 #define _HSW_VIDEO_DIP_GCP_B 0x61210 6320 6321 /* Icelake PPS_DATA and _ECC DIP Registers. 6322 * These are available for transcoders B,C and eDP. 6323 * Adding the _A so as to reuse the _MMIO_TRANS2 6324 * definition, with which it offsets to the right location. 6325 */ 6326 6327 #define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350 6328 #define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350 6329 #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 6330 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 6331 6332 #define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) 6333 #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) 6334 #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) 6335 #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) 6336 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) 6337 #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) 6338 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) 6339 #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) 6340 #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) 6341 #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) 6342 6343 #define _HSW_STEREO_3D_CTL_A 0x70020 6344 #define S3D_ENABLE (1 << 31) 6345 #define _HSW_STEREO_3D_CTL_B 0x71020 6346 6347 #define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) 6348 6349 #define _PCH_TRANS_HTOTAL_B 0xe1000 6350 #define _PCH_TRANS_HBLANK_B 0xe1004 6351 #define _PCH_TRANS_HSYNC_B 0xe1008 6352 #define _PCH_TRANS_VTOTAL_B 0xe100c 6353 #define _PCH_TRANS_VBLANK_B 0xe1010 6354 #define _PCH_TRANS_VSYNC_B 0xe1014 6355 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 6356 6357 #define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 6358 #define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 6359 #define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 6360 #define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 6361 #define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 6362 #define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 6363 #define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B) 6364 6365 #define _PCH_TRANSB_DATA_M1 0xe1030 6366 #define _PCH_TRANSB_DATA_N1 0xe1034 6367 #define _PCH_TRANSB_DATA_M2 0xe1038 6368 #define _PCH_TRANSB_DATA_N2 0xe103c 6369 #define _PCH_TRANSB_LINK_M1 0xe1040 6370 #define _PCH_TRANSB_LINK_N1 0xe1044 6371 #define _PCH_TRANSB_LINK_M2 0xe1048 6372 #define _PCH_TRANSB_LINK_N2 0xe104c 6373 6374 #define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 6375 #define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 6376 #define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 6377 #define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 6378 #define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 6379 #define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 6380 #define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 6381 #define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 6382 6383 #define _PCH_TRANSACONF 0xf0008 6384 #define _PCH_TRANSBCONF 0xf1008 6385 #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 6386 #define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */ 6387 #define TRANS_ENABLE REG_BIT(31) 6388 #define TRANS_STATE_ENABLE REG_BIT(30) 6389 #define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */ 6390 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */ 6391 #define TRANS_INTERLACE_MASK REG_GENMASK(23, 21) 6392 #define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0) 6393 #define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */ 6394 #define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3) 6395 #define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */ 6396 #define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0) 6397 #define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1) 6398 #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2) 6399 #define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3) 6400 #define _TRANSA_CHICKEN1 0xf0060 6401 #define _TRANSB_CHICKEN1 0xf1060 6402 #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 6403 #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1 << 10) 6404 #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1 << 4) 6405 #define _TRANSA_CHICKEN2 0xf0064 6406 #define _TRANSB_CHICKEN2 0xf1064 6407 #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 6408 #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31) 6409 #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29) 6410 #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27) 6411 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */ 6412 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26) 6413 #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25) 6414 6415 #define SOUTH_CHICKEN1 _MMIO(0xc2000) 6416 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 6417 #define FDIA_PHASE_SYNC_SHIFT_EN 18 6418 #define INVERT_DDID_HPD (1 << 18) 6419 #define INVERT_DDIC_HPD (1 << 17) 6420 #define INVERT_DDIB_HPD (1 << 16) 6421 #define INVERT_DDIA_HPD (1 << 15) 6422 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 6423 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 6424 #define FDI_BC_BIFURCATION_SELECT (1 << 12) 6425 #define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8) 6426 #define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8) 6427 #define SBCLK_RUN_REFCLK_DIS (1 << 7) 6428 #define SPT_PWM_GRANULARITY (1 << 0) 6429 #define SOUTH_CHICKEN2 _MMIO(0xc2004) 6430 #define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13) 6431 #define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12) 6432 #define LPT_PWM_GRANULARITY (1 << 5) 6433 #define DPLS_EDP_PPS_FIX_DIS (1 << 0) 6434 6435 #define _FDI_RXA_CHICKEN 0xc200c 6436 #define _FDI_RXB_CHICKEN 0xc2010 6437 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1 << 1) 6438 #define FDI_RX_PHASE_SYNC_POINTER_EN (1 << 0) 6439 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 6440 6441 #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020) 6442 #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) 6443 #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) 6444 #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) 6445 #define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15) 6446 #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) 6447 #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) 6448 #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) 6449 6450 /* CPU: FDI_TX */ 6451 #define _FDI_TXA_CTL 0x60100 6452 #define _FDI_TXB_CTL 0x61100 6453 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 6454 #define FDI_TX_DISABLE (0 << 31) 6455 #define FDI_TX_ENABLE (1 << 31) 6456 #define FDI_LINK_TRAIN_PATTERN_1 (0 << 28) 6457 #define FDI_LINK_TRAIN_PATTERN_2 (1 << 28) 6458 #define FDI_LINK_TRAIN_PATTERN_IDLE (2 << 28) 6459 #define FDI_LINK_TRAIN_NONE (3 << 28) 6460 #define FDI_LINK_TRAIN_VOLTAGE_0_4V (0 << 25) 6461 #define FDI_LINK_TRAIN_VOLTAGE_0_6V (1 << 25) 6462 #define FDI_LINK_TRAIN_VOLTAGE_0_8V (2 << 25) 6463 #define FDI_LINK_TRAIN_VOLTAGE_1_2V (3 << 25) 6464 #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22) 6465 #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1 << 22) 6466 #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) 6467 #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) 6468 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 6469 SNB has different settings. */ 6470 /* SNB A-stepping */ 6471 #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 6472 #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 6473 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 6474 #define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 6475 /* SNB B-stepping */ 6476 #define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0 << 22) 6477 #define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a << 22) 6478 #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39 << 22) 6479 #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38 << 22) 6480 #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f << 22) 6481 #define FDI_DP_PORT_WIDTH_SHIFT 19 6482 #define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 6483 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 6484 #define FDI_TX_ENHANCE_FRAME_ENABLE (1 << 18) 6485 /* Ironlake: hardwired to 1 */ 6486 #define FDI_TX_PLL_ENABLE (1 << 14) 6487 6488 /* Ivybridge has different bits for lolz */ 6489 #define FDI_LINK_TRAIN_PATTERN_1_IVB (0 << 8) 6490 #define FDI_LINK_TRAIN_PATTERN_2_IVB (1 << 8) 6491 #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2 << 8) 6492 #define FDI_LINK_TRAIN_NONE_IVB (3 << 8) 6493 6494 /* both Tx and Rx */ 6495 #define FDI_COMPOSITE_SYNC (1 << 11) 6496 #define FDI_LINK_TRAIN_AUTO (1 << 10) 6497 #define FDI_SCRAMBLING_ENABLE (0 << 7) 6498 #define FDI_SCRAMBLING_DISABLE (1 << 7) 6499 6500 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 6501 #define _FDI_RXA_CTL 0xf000c 6502 #define _FDI_RXB_CTL 0xf100c 6503 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 6504 #define FDI_RX_ENABLE (1 << 31) 6505 /* train, dp width same as FDI_TX */ 6506 #define FDI_FS_ERRC_ENABLE (1 << 27) 6507 #define FDI_FE_ERRC_ENABLE (1 << 26) 6508 #define FDI_RX_POLARITY_REVERSED_LPT (1 << 16) 6509 #define FDI_8BPC (0 << 16) 6510 #define FDI_10BPC (1 << 16) 6511 #define FDI_6BPC (2 << 16) 6512 #define FDI_12BPC (3 << 16) 6513 #define FDI_RX_LINK_REVERSAL_OVERRIDE (1 << 15) 6514 #define FDI_DMI_LINK_REVERSE_MASK (1 << 14) 6515 #define FDI_RX_PLL_ENABLE (1 << 13) 6516 #define FDI_FS_ERR_CORRECT_ENABLE (1 << 11) 6517 #define FDI_FE_ERR_CORRECT_ENABLE (1 << 10) 6518 #define FDI_FS_ERR_REPORT_ENABLE (1 << 9) 6519 #define FDI_FE_ERR_REPORT_ENABLE (1 << 8) 6520 #define FDI_RX_ENHANCE_FRAME_ENABLE (1 << 6) 6521 #define FDI_PCDCLK (1 << 4) 6522 /* CPT */ 6523 #define FDI_AUTO_TRAINING (1 << 10) 6524 #define FDI_LINK_TRAIN_PATTERN_1_CPT (0 << 8) 6525 #define FDI_LINK_TRAIN_PATTERN_2_CPT (1 << 8) 6526 #define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2 << 8) 6527 #define FDI_LINK_TRAIN_NORMAL_CPT (3 << 8) 6528 #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3 << 8) 6529 6530 #define _FDI_RXA_MISC 0xf0010 6531 #define _FDI_RXB_MISC 0xf1010 6532 #define FDI_RX_PWRDN_LANE1_MASK (3 << 26) 6533 #define FDI_RX_PWRDN_LANE1_VAL(x) ((x) << 26) 6534 #define FDI_RX_PWRDN_LANE0_MASK (3 << 24) 6535 #define FDI_RX_PWRDN_LANE0_VAL(x) ((x) << 24) 6536 #define FDI_RX_TP1_TO_TP2_48 (2 << 20) 6537 #define FDI_RX_TP1_TO_TP2_64 (3 << 20) 6538 #define FDI_RX_FDI_DELAY_90 (0x90 << 0) 6539 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 6540 6541 #define _FDI_RXA_TUSIZE1 0xf0030 6542 #define _FDI_RXA_TUSIZE2 0xf0038 6543 #define _FDI_RXB_TUSIZE1 0xf1030 6544 #define _FDI_RXB_TUSIZE2 0xf1038 6545 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 6546 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 6547 6548 /* FDI_RX interrupt register format */ 6549 #define FDI_RX_INTER_LANE_ALIGN (1 << 10) 6550 #define FDI_RX_SYMBOL_LOCK (1 << 9) /* train 2 */ 6551 #define FDI_RX_BIT_LOCK (1 << 8) /* train 1 */ 6552 #define FDI_RX_TRAIN_PATTERN_2_FAIL (1 << 7) 6553 #define FDI_RX_FS_CODE_ERR (1 << 6) 6554 #define FDI_RX_FE_CODE_ERR (1 << 5) 6555 #define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1 << 4) 6556 #define FDI_RX_HDCP_LINK_FAIL (1 << 3) 6557 #define FDI_RX_PIXEL_FIFO_OVERFLOW (1 << 2) 6558 #define FDI_RX_CROSS_CLOCK_OVERFLOW (1 << 1) 6559 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1 << 0) 6560 6561 #define _FDI_RXA_IIR 0xf0014 6562 #define _FDI_RXA_IMR 0xf0018 6563 #define _FDI_RXB_IIR 0xf1014 6564 #define _FDI_RXB_IMR 0xf1018 6565 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 6566 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 6567 6568 #define FDI_PLL_CTL_1 _MMIO(0xfe000) 6569 #define FDI_PLL_CTL_2 _MMIO(0xfe004) 6570 6571 #define PCH_LVDS _MMIO(0xe1180) 6572 #define LVDS_DETECTED (1 << 1) 6573 6574 #define _PCH_DP_B 0xe4100 6575 #define PCH_DP_B _MMIO(_PCH_DP_B) 6576 #define _PCH_DPB_AUX_CH_CTL 0xe4110 6577 #define _PCH_DPB_AUX_CH_DATA1 0xe4114 6578 #define _PCH_DPB_AUX_CH_DATA2 0xe4118 6579 #define _PCH_DPB_AUX_CH_DATA3 0xe411c 6580 #define _PCH_DPB_AUX_CH_DATA4 0xe4120 6581 #define _PCH_DPB_AUX_CH_DATA5 0xe4124 6582 6583 #define _PCH_DP_C 0xe4200 6584 #define PCH_DP_C _MMIO(_PCH_DP_C) 6585 #define _PCH_DPC_AUX_CH_CTL 0xe4210 6586 #define _PCH_DPC_AUX_CH_DATA1 0xe4214 6587 #define _PCH_DPC_AUX_CH_DATA2 0xe4218 6588 #define _PCH_DPC_AUX_CH_DATA3 0xe421c 6589 #define _PCH_DPC_AUX_CH_DATA4 0xe4220 6590 #define _PCH_DPC_AUX_CH_DATA5 0xe4224 6591 6592 #define _PCH_DP_D 0xe4300 6593 #define PCH_DP_D _MMIO(_PCH_DP_D) 6594 #define _PCH_DPD_AUX_CH_CTL 0xe4310 6595 #define _PCH_DPD_AUX_CH_DATA1 0xe4314 6596 #define _PCH_DPD_AUX_CH_DATA2 0xe4318 6597 #define _PCH_DPD_AUX_CH_DATA3 0xe431c 6598 #define _PCH_DPD_AUX_CH_DATA4 0xe4320 6599 #define _PCH_DPD_AUX_CH_DATA5 0xe4324 6600 6601 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) 6602 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ 6603 6604 /* CPT */ 6605 #define _TRANS_DP_CTL_A 0xe0300 6606 #define _TRANS_DP_CTL_B 0xe1300 6607 #define _TRANS_DP_CTL_C 0xe2300 6608 #define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B) 6609 #define TRANS_DP_OUTPUT_ENABLE REG_BIT(31) 6610 #define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29) 6611 #define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3) 6612 #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B) 6613 #define TRANS_DP_AUDIO_ONLY REG_BIT(26) 6614 #define TRANS_DP_ENH_FRAMING REG_BIT(18) 6615 #define TRANS_DP_BPC_MASK REG_GENMASK(10, 9) 6616 #define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0) 6617 #define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1) 6618 #define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2) 6619 #define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3) 6620 #define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4) 6621 #define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3) 6622 6623 #define _TRANS_DP2_CTL_A 0x600a0 6624 #define _TRANS_DP2_CTL_B 0x610a0 6625 #define _TRANS_DP2_CTL_C 0x620a0 6626 #define _TRANS_DP2_CTL_D 0x630a0 6627 #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B) 6628 #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31) 6629 #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30) 6630 #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23) 6631 6632 #define _TRANS_DP2_VFREQHIGH_A 0x600a4 6633 #define _TRANS_DP2_VFREQHIGH_B 0x610a4 6634 #define _TRANS_DP2_VFREQHIGH_C 0x620a4 6635 #define _TRANS_DP2_VFREQHIGH_D 0x630a4 6636 #define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B) 6637 #define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8) 6638 #define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz)) 6639 6640 #define _TRANS_DP2_VFREQLOW_A 0x600a8 6641 #define _TRANS_DP2_VFREQLOW_B 0x610a8 6642 #define _TRANS_DP2_VFREQLOW_C 0x620a8 6643 #define _TRANS_DP2_VFREQLOW_D 0x630a8 6644 #define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B) 6645 6646 /* SNB eDP training params */ 6647 /* SNB A-stepping */ 6648 #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) 6649 #define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) 6650 #define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22) 6651 #define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22) 6652 /* SNB B-stepping */ 6653 #define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22) 6654 #define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22) 6655 #define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22) 6656 #define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22) 6657 #define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22) 6658 #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22) 6659 6660 /* IVB */ 6661 #define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22) 6662 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22) 6663 #define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22) 6664 #define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22) 6665 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22) 6666 #define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22) 6667 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22) 6668 6669 /* legacy values */ 6670 #define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22) 6671 #define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22) 6672 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22) 6673 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22) 6674 #define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22) 6675 6676 #define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22) 6677 6678 #define VLV_PMWGICZ _MMIO(0x1300a4) 6679 6680 #define HSW_EDRAM_CAP _MMIO(0x120010) 6681 #define EDRAM_ENABLED 0x1 6682 #define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf) 6683 #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) 6684 #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) 6685 6686 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C) 6687 #define PIXEL_OVERLAP_CNT_MASK (3 << 30) 6688 #define PIXEL_OVERLAP_CNT_SHIFT 30 6689 6690 #define GEN6_PCODE_MAILBOX _MMIO(0x138124) 6691 #define GEN6_PCODE_READY (1 << 31) 6692 #define GEN6_PCODE_ERROR_MASK 0xFF 6693 #define GEN6_PCODE_SUCCESS 0x0 6694 #define GEN6_PCODE_ILLEGAL_CMD 0x1 6695 #define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2 6696 #define GEN6_PCODE_TIMEOUT 0x3 6697 #define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF 6698 #define GEN7_PCODE_TIMEOUT 0x2 6699 #define GEN7_PCODE_ILLEGAL_DATA 0x3 6700 #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4 6701 #define GEN11_PCODE_LOCKED 0x6 6702 #define GEN11_PCODE_REJECTED 0x11 6703 #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10 6704 #define GEN6_PCODE_WRITE_RC6VIDS 0x4 6705 #define GEN6_PCODE_READ_RC6VIDS 0x5 6706 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 6707 #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 6708 #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18 6709 #define GEN9_PCODE_READ_MEM_LATENCY 0x6 6710 #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF 6711 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 6712 #define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16 6713 #define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24 6714 #define SKL_PCODE_LOAD_HDCP_KEYS 0x5 6715 #define SKL_PCODE_CDCLK_CONTROL 0x7 6716 #define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3 6717 #define SKL_CDCLK_READY_FOR_CHANGE 0x1 6718 #define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 6719 #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 6720 #define GEN6_READ_OC_PARAMS 0xc 6721 #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd 6722 #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8) 6723 #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) 6724 #define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8)) 6725 #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe 6726 #define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0) 6727 #define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0) 6728 #define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1) 6729 #define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2) 6730 #define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2) 6731 #define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0) 6732 #define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1) 6733 #define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2) 6734 #define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0) 6735 #define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x)) 6736 #define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8) 6737 #define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x)) 6738 #define GEN6_PCODE_READ_D_COMP 0x10 6739 #define GEN6_PCODE_WRITE_D_COMP 0x11 6740 #define ICL_PCODE_EXIT_TCCOLD 0x12 6741 #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17 6742 #define DISPLAY_IPS_CONTROL 0x19 6743 #define TGL_PCODE_TCCOLD 0x26 6744 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0) 6745 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0 6746 #define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0) 6747 /* See also IPS_CTL */ 6748 #define IPS_PCODE_CONTROL (1 << 30) 6749 #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A 6750 #define GEN9_PCODE_SAGV_CONTROL 0x21 6751 #define GEN9_SAGV_DISABLE 0x0 6752 #define GEN9_SAGV_IS_DISABLED 0x1 6753 #define GEN9_SAGV_ENABLE 0x3 6754 #define DG1_PCODE_STATUS 0x7E 6755 #define DG1_UNCORE_GET_INIT_STATUS 0x0 6756 #define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1 6757 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23 6758 #define GEN6_PCODE_DATA _MMIO(0x138128) 6759 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 6760 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 6761 #define GEN6_PCODE_DATA1 _MMIO(0x13812C) 6762 6763 /* IVYBRIDGE DPF */ 6764 #define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */ 6765 #define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14) 6766 #define GEN7_PARITY_ERROR_VALID (1 << 13) 6767 #define GEN7_L3CDERRST1_BANK_MASK (3 << 11) 6768 #define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8) 6769 #define GEN7_PARITY_ERROR_ROW(reg) \ 6770 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14) 6771 #define GEN7_PARITY_ERROR_BANK(reg) \ 6772 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11) 6773 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ 6774 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 6775 #define GEN7_L3CDERRST1_ENABLE (1 << 7) 6776 6777 /* Audio */ 6778 #define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020) 6779 #define INTEL_AUDIO_DEVCL 0x808629FB 6780 #define INTEL_AUDIO_DEVBLC 0x80862801 6781 #define INTEL_AUDIO_DEVCTG 0x80862802 6782 6783 #define G4X_AUD_CNTL_ST _MMIO(0x620B4) 6784 #define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 6785 #define G4X_ELDV_DEVCTG (1 << 14) 6786 #define G4X_ELD_ADDR_MASK (0xf << 5) 6787 #define G4X_ELD_ACK (1 << 4) 6788 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C) 6789 6790 #define _IBX_HDMIW_HDMIEDID_A 0xE2050 6791 #define _IBX_HDMIW_HDMIEDID_B 0xE2150 6792 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ 6793 _IBX_HDMIW_HDMIEDID_B) 6794 #define _IBX_AUD_CNTL_ST_A 0xE20B4 6795 #define _IBX_AUD_CNTL_ST_B 0xE21B4 6796 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ 6797 _IBX_AUD_CNTL_ST_B) 6798 #define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10) 6799 #define IBX_ELD_ADDRESS_MASK (0x1f << 5) 6800 #define IBX_ELD_ACK (1 << 4) 6801 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0) 6802 #define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4)) 6803 #define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4)) 6804 6805 #define _CPT_HDMIW_HDMIEDID_A 0xE5050 6806 #define _CPT_HDMIW_HDMIEDID_B 0xE5150 6807 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) 6808 #define _CPT_AUD_CNTL_ST_A 0xE50B4 6809 #define _CPT_AUD_CNTL_ST_B 0xE51B4 6810 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) 6811 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0) 6812 6813 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) 6814 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) 6815 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) 6816 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) 6817 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) 6818 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) 6819 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0) 6820 6821 /* These are the 4 32-bit write offset registers for each stream 6822 * output buffer. It determines the offset from the 6823 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 6824 */ 6825 #define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4) 6826 6827 #define _IBX_AUD_CONFIG_A 0xe2000 6828 #define _IBX_AUD_CONFIG_B 0xe2100 6829 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) 6830 #define _CPT_AUD_CONFIG_A 0xe5000 6831 #define _CPT_AUD_CONFIG_B 0xe5100 6832 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) 6833 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) 6834 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) 6835 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) 6836 6837 #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 6838 #define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 6839 #define AUD_CONFIG_UPPER_N_SHIFT 20 6840 #define AUD_CONFIG_UPPER_N_MASK (0xff << 20) 6841 #define AUD_CONFIG_LOWER_N_SHIFT 4 6842 #define AUD_CONFIG_LOWER_N_MASK (0xfff << 4) 6843 #define AUD_CONFIG_N_MASK (AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK) 6844 #define AUD_CONFIG_N(n) \ 6845 (((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) | \ 6846 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT)) 6847 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 6848 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) 6849 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) 6850 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) 6851 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) 6852 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) 6853 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) 6854 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) 6855 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) 6856 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) 6857 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) 6858 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) 6859 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 (10 << 16) 6860 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 (11 << 16) 6861 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 (12 << 16) 6862 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 (13 << 16) 6863 #define AUD_CONFIG_DISABLE_NCTS (1 << 3) 6864 6865 /* HSW Audio */ 6866 #define _HSW_AUD_CONFIG_A 0x65000 6867 #define _HSW_AUD_CONFIG_B 0x65100 6868 #define HSW_AUD_CFG(trans) _MMIO_TRANS(trans, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B) 6869 6870 #define _HSW_AUD_MISC_CTRL_A 0x65010 6871 #define _HSW_AUD_MISC_CTRL_B 0x65110 6872 #define HSW_AUD_MISC_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B) 6873 6874 #define _HSW_AUD_M_CTS_ENABLE_A 0x65028 6875 #define _HSW_AUD_M_CTS_ENABLE_B 0x65128 6876 #define HSW_AUD_M_CTS_ENABLE(trans) _MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B) 6877 #define AUD_M_CTS_M_VALUE_INDEX (1 << 21) 6878 #define AUD_M_CTS_M_PROG_ENABLE (1 << 20) 6879 #define AUD_CONFIG_M_MASK 0xfffff 6880 6881 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 6882 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 6883 #define HSW_AUD_DIP_ELD_CTRL(trans) _MMIO_TRANS(trans, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B) 6884 6885 /* Audio Digital Converter */ 6886 #define _HSW_AUD_DIG_CNVT_1 0x65080 6887 #define _HSW_AUD_DIG_CNVT_2 0x65180 6888 #define AUD_DIG_CNVT(trans) _MMIO_TRANS(trans, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2) 6889 #define DIP_PORT_SEL_MASK 0x3 6890 6891 #define _HSW_AUD_EDID_DATA_A 0x65050 6892 #define _HSW_AUD_EDID_DATA_B 0x65150 6893 #define HSW_AUD_EDID_DATA(trans) _MMIO_TRANS(trans, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B) 6894 6895 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c) 6896 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0) 6897 #define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4)) 6898 #define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4)) 6899 #define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4)) 6900 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4)) 6901 6902 #define _AUD_TCA_DP_2DOT0_CTRL 0x650bc 6903 #define _AUD_TCB_DP_2DOT0_CTRL 0x651bc 6904 #define AUD_DP_2DOT0_CTRL(trans) _MMIO_TRANS(trans, _AUD_TCA_DP_2DOT0_CTRL, _AUD_TCB_DP_2DOT0_CTRL) 6905 #define AUD_ENABLE_SDP_SPLIT REG_BIT(31) 6906 6907 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10) 6908 #define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15) 6909 6910 #define AUD_FREQ_CNTRL _MMIO(0x65900) 6911 #define AUD_PIN_BUF_CTL _MMIO(0x48414) 6912 #define AUD_PIN_BUF_ENABLE REG_BIT(31) 6913 6914 #define AUD_TS_CDCLK_M _MMIO(0x65ea0) 6915 #define AUD_TS_CDCLK_M_EN REG_BIT(31) 6916 #define AUD_TS_CDCLK_N _MMIO(0x65ea4) 6917 6918 /* Display Audio Config Reg */ 6919 #define AUD_CONFIG_BE _MMIO(0x65ef0) 6920 #define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe))) 6921 #define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe))) 6922 #define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6))) 6923 #define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6)) 6924 #define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6)) 6925 #define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6)) 6926 6927 #define HBLANK_START_COUNT_8 0 6928 #define HBLANK_START_COUNT_16 1 6929 #define HBLANK_START_COUNT_32 2 6930 #define HBLANK_START_COUNT_64 3 6931 #define HBLANK_START_COUNT_96 4 6932 #define HBLANK_START_COUNT_128 5 6933 6934 /* 6935 * HSW - ICL power wells 6936 * 6937 * Platforms have up to 3 power well control register sets, each set 6938 * controlling up to 16 power wells via a request/status HW flag tuple: 6939 * - main (HSW_PWR_WELL_CTL[1-4]) 6940 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4]) 6941 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4]) 6942 * Each control register set consists of up to 4 registers used by different 6943 * sources that can request a power well to be enabled: 6944 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1) 6945 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2) 6946 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set) 6947 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4) 6948 */ 6949 #define HSW_PWR_WELL_CTL1 _MMIO(0x45400) 6950 #define HSW_PWR_WELL_CTL2 _MMIO(0x45404) 6951 #define HSW_PWR_WELL_CTL3 _MMIO(0x45408) 6952 #define HSW_PWR_WELL_CTL4 _MMIO(0x4540C) 6953 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) 6954 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) 6955 6956 /* HSW/BDW power well */ 6957 #define HSW_PW_CTL_IDX_GLOBAL 15 6958 6959 /* SKL/BXT/GLK power wells */ 6960 #define SKL_PW_CTL_IDX_PW_2 15 6961 #define SKL_PW_CTL_IDX_PW_1 14 6962 #define GLK_PW_CTL_IDX_AUX_C 10 6963 #define GLK_PW_CTL_IDX_AUX_B 9 6964 #define GLK_PW_CTL_IDX_AUX_A 8 6965 #define SKL_PW_CTL_IDX_DDI_D 4 6966 #define SKL_PW_CTL_IDX_DDI_C 3 6967 #define SKL_PW_CTL_IDX_DDI_B 2 6968 #define SKL_PW_CTL_IDX_DDI_A_E 1 6969 #define GLK_PW_CTL_IDX_DDI_A 1 6970 #define SKL_PW_CTL_IDX_MISC_IO 0 6971 6972 /* ICL/TGL - power wells */ 6973 #define TGL_PW_CTL_IDX_PW_5 4 6974 #define ICL_PW_CTL_IDX_PW_4 3 6975 #define ICL_PW_CTL_IDX_PW_3 2 6976 #define ICL_PW_CTL_IDX_PW_2 1 6977 #define ICL_PW_CTL_IDX_PW_1 0 6978 6979 /* XE_LPD - power wells */ 6980 #define XELPD_PW_CTL_IDX_PW_D 8 6981 #define XELPD_PW_CTL_IDX_PW_C 7 6982 #define XELPD_PW_CTL_IDX_PW_B 6 6983 #define XELPD_PW_CTL_IDX_PW_A 5 6984 6985 #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440) 6986 #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444) 6987 #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C) 6988 #define TGL_PW_CTL_IDX_AUX_TBT6 14 6989 #define TGL_PW_CTL_IDX_AUX_TBT5 13 6990 #define TGL_PW_CTL_IDX_AUX_TBT4 12 6991 #define ICL_PW_CTL_IDX_AUX_TBT4 11 6992 #define TGL_PW_CTL_IDX_AUX_TBT3 11 6993 #define ICL_PW_CTL_IDX_AUX_TBT3 10 6994 #define TGL_PW_CTL_IDX_AUX_TBT2 10 6995 #define ICL_PW_CTL_IDX_AUX_TBT2 9 6996 #define TGL_PW_CTL_IDX_AUX_TBT1 9 6997 #define ICL_PW_CTL_IDX_AUX_TBT1 8 6998 #define TGL_PW_CTL_IDX_AUX_TC6 8 6999 #define XELPD_PW_CTL_IDX_AUX_E 8 7000 #define TGL_PW_CTL_IDX_AUX_TC5 7 7001 #define XELPD_PW_CTL_IDX_AUX_D 7 7002 #define TGL_PW_CTL_IDX_AUX_TC4 6 7003 #define ICL_PW_CTL_IDX_AUX_F 5 7004 #define TGL_PW_CTL_IDX_AUX_TC3 5 7005 #define ICL_PW_CTL_IDX_AUX_E 4 7006 #define TGL_PW_CTL_IDX_AUX_TC2 4 7007 #define ICL_PW_CTL_IDX_AUX_D 3 7008 #define TGL_PW_CTL_IDX_AUX_TC1 3 7009 #define ICL_PW_CTL_IDX_AUX_C 2 7010 #define ICL_PW_CTL_IDX_AUX_B 1 7011 #define ICL_PW_CTL_IDX_AUX_A 0 7012 7013 #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450) 7014 #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454) 7015 #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C) 7016 #define XELPD_PW_CTL_IDX_DDI_E 8 7017 #define TGL_PW_CTL_IDX_DDI_TC6 8 7018 #define XELPD_PW_CTL_IDX_DDI_D 7 7019 #define TGL_PW_CTL_IDX_DDI_TC5 7 7020 #define TGL_PW_CTL_IDX_DDI_TC4 6 7021 #define ICL_PW_CTL_IDX_DDI_F 5 7022 #define TGL_PW_CTL_IDX_DDI_TC3 5 7023 #define ICL_PW_CTL_IDX_DDI_E 4 7024 #define TGL_PW_CTL_IDX_DDI_TC2 4 7025 #define ICL_PW_CTL_IDX_DDI_D 3 7026 #define TGL_PW_CTL_IDX_DDI_TC1 3 7027 #define ICL_PW_CTL_IDX_DDI_C 2 7028 #define ICL_PW_CTL_IDX_DDI_B 1 7029 #define ICL_PW_CTL_IDX_DDI_A 0 7030 7031 /* HSW - power well misc debug registers */ 7032 #define HSW_PWR_WELL_CTL5 _MMIO(0x45410) 7033 #define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31) 7034 #define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20) 7035 #define HSW_PWR_WELL_FORCE_ON (1 << 19) 7036 #define HSW_PWR_WELL_CTL6 _MMIO(0x45414) 7037 7038 /* SKL Fuse Status */ 7039 enum skl_power_gate { 7040 SKL_PG0, 7041 SKL_PG1, 7042 SKL_PG2, 7043 ICL_PG3, 7044 ICL_PG4, 7045 }; 7046 7047 #define SKL_FUSE_STATUS _MMIO(0x42000) 7048 #define SKL_FUSE_DOWNLOAD_STATUS (1 << 31) 7049 /* 7050 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 7051 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2 7052 */ 7053 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ 7054 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) 7055 /* 7056 * PG0 is HW controlled, so doesn't have a corresponding power well control knob 7057 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4 7058 */ 7059 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ 7060 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) 7061 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg))) 7062 7063 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) 7064 #define _ICL_AUX_ANAOVRD1_A 0x162398 7065 #define _ICL_AUX_ANAOVRD1_B 0x6C398 7066 #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \ 7067 _ICL_AUX_ANAOVRD1_A, \ 7068 _ICL_AUX_ANAOVRD1_B)) 7069 #define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7) 7070 #define ICL_AUX_ANAOVRD1_ENABLE (1 << 0) 7071 7072 /* HDCP Key Registers */ 7073 #define HDCP_KEY_CONF _MMIO(0x66c00) 7074 #define HDCP_AKSV_SEND_TRIGGER BIT(31) 7075 #define HDCP_CLEAR_KEYS_TRIGGER BIT(30) 7076 #define HDCP_KEY_LOAD_TRIGGER BIT(8) 7077 #define HDCP_KEY_STATUS _MMIO(0x66c04) 7078 #define HDCP_FUSE_IN_PROGRESS BIT(7) 7079 #define HDCP_FUSE_ERROR BIT(6) 7080 #define HDCP_FUSE_DONE BIT(5) 7081 #define HDCP_KEY_LOAD_STATUS BIT(1) 7082 #define HDCP_KEY_LOAD_DONE BIT(0) 7083 #define HDCP_AKSV_LO _MMIO(0x66c10) 7084 #define HDCP_AKSV_HI _MMIO(0x66c14) 7085 7086 /* HDCP Repeater Registers */ 7087 #define HDCP_REP_CTL _MMIO(0x66d00) 7088 #define HDCP_TRANSA_REP_PRESENT BIT(31) 7089 #define HDCP_TRANSB_REP_PRESENT BIT(30) 7090 #define HDCP_TRANSC_REP_PRESENT BIT(29) 7091 #define HDCP_TRANSD_REP_PRESENT BIT(28) 7092 #define HDCP_DDIB_REP_PRESENT BIT(30) 7093 #define HDCP_DDIA_REP_PRESENT BIT(29) 7094 #define HDCP_DDIC_REP_PRESENT BIT(28) 7095 #define HDCP_DDID_REP_PRESENT BIT(27) 7096 #define HDCP_DDIF_REP_PRESENT BIT(26) 7097 #define HDCP_DDIE_REP_PRESENT BIT(25) 7098 #define HDCP_TRANSA_SHA1_M0 (1 << 20) 7099 #define HDCP_TRANSB_SHA1_M0 (2 << 20) 7100 #define HDCP_TRANSC_SHA1_M0 (3 << 20) 7101 #define HDCP_TRANSD_SHA1_M0 (4 << 20) 7102 #define HDCP_DDIB_SHA1_M0 (1 << 20) 7103 #define HDCP_DDIA_SHA1_M0 (2 << 20) 7104 #define HDCP_DDIC_SHA1_M0 (3 << 20) 7105 #define HDCP_DDID_SHA1_M0 (4 << 20) 7106 #define HDCP_DDIF_SHA1_M0 (5 << 20) 7107 #define HDCP_DDIE_SHA1_M0 (6 << 20) /* Bspec says 5? */ 7108 #define HDCP_SHA1_BUSY BIT(16) 7109 #define HDCP_SHA1_READY BIT(17) 7110 #define HDCP_SHA1_COMPLETE BIT(18) 7111 #define HDCP_SHA1_V_MATCH BIT(19) 7112 #define HDCP_SHA1_TEXT_32 (1 << 1) 7113 #define HDCP_SHA1_COMPLETE_HASH (2 << 1) 7114 #define HDCP_SHA1_TEXT_24 (4 << 1) 7115 #define HDCP_SHA1_TEXT_16 (5 << 1) 7116 #define HDCP_SHA1_TEXT_8 (6 << 1) 7117 #define HDCP_SHA1_TEXT_0 (7 << 1) 7118 #define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04) 7119 #define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08) 7120 #define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C) 7121 #define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10) 7122 #define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14) 7123 #define HDCP_SHA_V_PRIME(h) _MMIO((0x66d04 + (h) * 4)) 7124 #define HDCP_SHA_TEXT _MMIO(0x66d18) 7125 7126 /* HDCP Auth Registers */ 7127 #define _PORTA_HDCP_AUTHENC 0x66800 7128 #define _PORTB_HDCP_AUTHENC 0x66500 7129 #define _PORTC_HDCP_AUTHENC 0x66600 7130 #define _PORTD_HDCP_AUTHENC 0x66700 7131 #define _PORTE_HDCP_AUTHENC 0x66A00 7132 #define _PORTF_HDCP_AUTHENC 0x66900 7133 #define _PORT_HDCP_AUTHENC(port, x) _MMIO(_PICK(port, \ 7134 _PORTA_HDCP_AUTHENC, \ 7135 _PORTB_HDCP_AUTHENC, \ 7136 _PORTC_HDCP_AUTHENC, \ 7137 _PORTD_HDCP_AUTHENC, \ 7138 _PORTE_HDCP_AUTHENC, \ 7139 _PORTF_HDCP_AUTHENC) + (x)) 7140 #define PORT_HDCP_CONF(port) _PORT_HDCP_AUTHENC(port, 0x0) 7141 #define _TRANSA_HDCP_CONF 0x66400 7142 #define _TRANSB_HDCP_CONF 0x66500 7143 #define TRANS_HDCP_CONF(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_CONF, \ 7144 _TRANSB_HDCP_CONF) 7145 #define HDCP_CONF(dev_priv, trans, port) \ 7146 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7147 TRANS_HDCP_CONF(trans) : \ 7148 PORT_HDCP_CONF(port)) 7149 7150 #define HDCP_CONF_CAPTURE_AN BIT(0) 7151 #define HDCP_CONF_AUTH_AND_ENC (BIT(1) | BIT(0)) 7152 #define PORT_HDCP_ANINIT(port) _PORT_HDCP_AUTHENC(port, 0x4) 7153 #define _TRANSA_HDCP_ANINIT 0x66404 7154 #define _TRANSB_HDCP_ANINIT 0x66504 7155 #define TRANS_HDCP_ANINIT(trans) _MMIO_TRANS(trans, \ 7156 _TRANSA_HDCP_ANINIT, \ 7157 _TRANSB_HDCP_ANINIT) 7158 #define HDCP_ANINIT(dev_priv, trans, port) \ 7159 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7160 TRANS_HDCP_ANINIT(trans) : \ 7161 PORT_HDCP_ANINIT(port)) 7162 7163 #define PORT_HDCP_ANLO(port) _PORT_HDCP_AUTHENC(port, 0x8) 7164 #define _TRANSA_HDCP_ANLO 0x66408 7165 #define _TRANSB_HDCP_ANLO 0x66508 7166 #define TRANS_HDCP_ANLO(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANLO, \ 7167 _TRANSB_HDCP_ANLO) 7168 #define HDCP_ANLO(dev_priv, trans, port) \ 7169 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7170 TRANS_HDCP_ANLO(trans) : \ 7171 PORT_HDCP_ANLO(port)) 7172 7173 #define PORT_HDCP_ANHI(port) _PORT_HDCP_AUTHENC(port, 0xC) 7174 #define _TRANSA_HDCP_ANHI 0x6640C 7175 #define _TRANSB_HDCP_ANHI 0x6650C 7176 #define TRANS_HDCP_ANHI(trans) _MMIO_TRANS(trans, _TRANSA_HDCP_ANHI, \ 7177 _TRANSB_HDCP_ANHI) 7178 #define HDCP_ANHI(dev_priv, trans, port) \ 7179 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7180 TRANS_HDCP_ANHI(trans) : \ 7181 PORT_HDCP_ANHI(port)) 7182 7183 #define PORT_HDCP_BKSVLO(port) _PORT_HDCP_AUTHENC(port, 0x10) 7184 #define _TRANSA_HDCP_BKSVLO 0x66410 7185 #define _TRANSB_HDCP_BKSVLO 0x66510 7186 #define TRANS_HDCP_BKSVLO(trans) _MMIO_TRANS(trans, \ 7187 _TRANSA_HDCP_BKSVLO, \ 7188 _TRANSB_HDCP_BKSVLO) 7189 #define HDCP_BKSVLO(dev_priv, trans, port) \ 7190 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7191 TRANS_HDCP_BKSVLO(trans) : \ 7192 PORT_HDCP_BKSVLO(port)) 7193 7194 #define PORT_HDCP_BKSVHI(port) _PORT_HDCP_AUTHENC(port, 0x14) 7195 #define _TRANSA_HDCP_BKSVHI 0x66414 7196 #define _TRANSB_HDCP_BKSVHI 0x66514 7197 #define TRANS_HDCP_BKSVHI(trans) _MMIO_TRANS(trans, \ 7198 _TRANSA_HDCP_BKSVHI, \ 7199 _TRANSB_HDCP_BKSVHI) 7200 #define HDCP_BKSVHI(dev_priv, trans, port) \ 7201 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7202 TRANS_HDCP_BKSVHI(trans) : \ 7203 PORT_HDCP_BKSVHI(port)) 7204 7205 #define PORT_HDCP_RPRIME(port) _PORT_HDCP_AUTHENC(port, 0x18) 7206 #define _TRANSA_HDCP_RPRIME 0x66418 7207 #define _TRANSB_HDCP_RPRIME 0x66518 7208 #define TRANS_HDCP_RPRIME(trans) _MMIO_TRANS(trans, \ 7209 _TRANSA_HDCP_RPRIME, \ 7210 _TRANSB_HDCP_RPRIME) 7211 #define HDCP_RPRIME(dev_priv, trans, port) \ 7212 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7213 TRANS_HDCP_RPRIME(trans) : \ 7214 PORT_HDCP_RPRIME(port)) 7215 7216 #define PORT_HDCP_STATUS(port) _PORT_HDCP_AUTHENC(port, 0x1C) 7217 #define _TRANSA_HDCP_STATUS 0x6641C 7218 #define _TRANSB_HDCP_STATUS 0x6651C 7219 #define TRANS_HDCP_STATUS(trans) _MMIO_TRANS(trans, \ 7220 _TRANSA_HDCP_STATUS, \ 7221 _TRANSB_HDCP_STATUS) 7222 #define HDCP_STATUS(dev_priv, trans, port) \ 7223 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7224 TRANS_HDCP_STATUS(trans) : \ 7225 PORT_HDCP_STATUS(port)) 7226 7227 #define HDCP_STATUS_STREAM_A_ENC BIT(31) 7228 #define HDCP_STATUS_STREAM_B_ENC BIT(30) 7229 #define HDCP_STATUS_STREAM_C_ENC BIT(29) 7230 #define HDCP_STATUS_STREAM_D_ENC BIT(28) 7231 #define HDCP_STATUS_AUTH BIT(21) 7232 #define HDCP_STATUS_ENC BIT(20) 7233 #define HDCP_STATUS_RI_MATCH BIT(19) 7234 #define HDCP_STATUS_R0_READY BIT(18) 7235 #define HDCP_STATUS_AN_READY BIT(17) 7236 #define HDCP_STATUS_CIPHER BIT(16) 7237 #define HDCP_STATUS_FRAME_CNT(x) (((x) >> 8) & 0xff) 7238 7239 /* HDCP2.2 Registers */ 7240 #define _PORTA_HDCP2_BASE 0x66800 7241 #define _PORTB_HDCP2_BASE 0x66500 7242 #define _PORTC_HDCP2_BASE 0x66600 7243 #define _PORTD_HDCP2_BASE 0x66700 7244 #define _PORTE_HDCP2_BASE 0x66A00 7245 #define _PORTF_HDCP2_BASE 0x66900 7246 #define _PORT_HDCP2_BASE(port, x) _MMIO(_PICK((port), \ 7247 _PORTA_HDCP2_BASE, \ 7248 _PORTB_HDCP2_BASE, \ 7249 _PORTC_HDCP2_BASE, \ 7250 _PORTD_HDCP2_BASE, \ 7251 _PORTE_HDCP2_BASE, \ 7252 _PORTF_HDCP2_BASE) + (x)) 7253 7254 #define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98) 7255 #define _TRANSA_HDCP2_AUTH 0x66498 7256 #define _TRANSB_HDCP2_AUTH 0x66598 7257 #define TRANS_HDCP2_AUTH(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_AUTH, \ 7258 _TRANSB_HDCP2_AUTH) 7259 #define AUTH_LINK_AUTHENTICATED BIT(31) 7260 #define AUTH_LINK_TYPE BIT(30) 7261 #define AUTH_FORCE_CLR_INPUTCTR BIT(19) 7262 #define AUTH_CLR_KEYS BIT(18) 7263 #define HDCP2_AUTH(dev_priv, trans, port) \ 7264 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7265 TRANS_HDCP2_AUTH(trans) : \ 7266 PORT_HDCP2_AUTH(port)) 7267 7268 #define PORT_HDCP2_CTL(port) _PORT_HDCP2_BASE(port, 0xB0) 7269 #define _TRANSA_HDCP2_CTL 0x664B0 7270 #define _TRANSB_HDCP2_CTL 0x665B0 7271 #define TRANS_HDCP2_CTL(trans) _MMIO_TRANS(trans, _TRANSA_HDCP2_CTL, \ 7272 _TRANSB_HDCP2_CTL) 7273 #define CTL_LINK_ENCRYPTION_REQ BIT(31) 7274 #define HDCP2_CTL(dev_priv, trans, port) \ 7275 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7276 TRANS_HDCP2_CTL(trans) : \ 7277 PORT_HDCP2_CTL(port)) 7278 7279 #define PORT_HDCP2_STATUS(port) _PORT_HDCP2_BASE(port, 0xB4) 7280 #define _TRANSA_HDCP2_STATUS 0x664B4 7281 #define _TRANSB_HDCP2_STATUS 0x665B4 7282 #define TRANS_HDCP2_STATUS(trans) _MMIO_TRANS(trans, \ 7283 _TRANSA_HDCP2_STATUS, \ 7284 _TRANSB_HDCP2_STATUS) 7285 #define LINK_TYPE_STATUS BIT(22) 7286 #define LINK_AUTH_STATUS BIT(21) 7287 #define LINK_ENCRYPTION_STATUS BIT(20) 7288 #define HDCP2_STATUS(dev_priv, trans, port) \ 7289 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7290 TRANS_HDCP2_STATUS(trans) : \ 7291 PORT_HDCP2_STATUS(port)) 7292 7293 #define _PIPEA_HDCP2_STREAM_STATUS 0x668C0 7294 #define _PIPEB_HDCP2_STREAM_STATUS 0x665C0 7295 #define _PIPEC_HDCP2_STREAM_STATUS 0x666C0 7296 #define _PIPED_HDCP2_STREAM_STATUS 0x667C0 7297 #define PIPE_HDCP2_STREAM_STATUS(pipe) _MMIO(_PICK((pipe), \ 7298 _PIPEA_HDCP2_STREAM_STATUS, \ 7299 _PIPEB_HDCP2_STREAM_STATUS, \ 7300 _PIPEC_HDCP2_STREAM_STATUS, \ 7301 _PIPED_HDCP2_STREAM_STATUS)) 7302 7303 #define _TRANSA_HDCP2_STREAM_STATUS 0x664C0 7304 #define _TRANSB_HDCP2_STREAM_STATUS 0x665C0 7305 #define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \ 7306 _TRANSA_HDCP2_STREAM_STATUS, \ 7307 _TRANSB_HDCP2_STREAM_STATUS) 7308 #define STREAM_ENCRYPTION_STATUS BIT(31) 7309 #define STREAM_TYPE_STATUS BIT(30) 7310 #define HDCP2_STREAM_STATUS(dev_priv, trans, port) \ 7311 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7312 TRANS_HDCP2_STREAM_STATUS(trans) : \ 7313 PIPE_HDCP2_STREAM_STATUS(pipe)) 7314 7315 #define _PORTA_HDCP2_AUTH_STREAM 0x66F00 7316 #define _PORTB_HDCP2_AUTH_STREAM 0x66F04 7317 #define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \ 7318 _PORTA_HDCP2_AUTH_STREAM, \ 7319 _PORTB_HDCP2_AUTH_STREAM) 7320 #define _TRANSA_HDCP2_AUTH_STREAM 0x66F00 7321 #define _TRANSB_HDCP2_AUTH_STREAM 0x66F04 7322 #define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \ 7323 _TRANSA_HDCP2_AUTH_STREAM, \ 7324 _TRANSB_HDCP2_AUTH_STREAM) 7325 #define AUTH_STREAM_TYPE BIT(31) 7326 #define HDCP2_AUTH_STREAM(dev_priv, trans, port) \ 7327 (GRAPHICS_VER(dev_priv) >= 12 ? \ 7328 TRANS_HDCP2_AUTH_STREAM(trans) : \ 7329 PORT_HDCP2_AUTH_STREAM(port)) 7330 7331 /* Per-pipe DDI Function Control */ 7332 #define _TRANS_DDI_FUNC_CTL_A 0x60400 7333 #define _TRANS_DDI_FUNC_CTL_B 0x61400 7334 #define _TRANS_DDI_FUNC_CTL_C 0x62400 7335 #define _TRANS_DDI_FUNC_CTL_D 0x63400 7336 #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 7337 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 7338 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 7339 #define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) 7340 7341 #define TRANS_DDI_FUNC_ENABLE (1 << 31) 7342 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 7343 #define TRANS_DDI_PORT_SHIFT 28 7344 #define TGL_TRANS_DDI_PORT_SHIFT 27 7345 #define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT) 7346 #define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT) 7347 #define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT) 7348 #define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT) 7349 #define TRANS_DDI_MODE_SELECT_MASK (7 << 24) 7350 #define TRANS_DDI_MODE_SELECT_HDMI (0 << 24) 7351 #define TRANS_DDI_MODE_SELECT_DVI (1 << 24) 7352 #define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24) 7353 #define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24) 7354 #define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24) 7355 #define TRANS_DDI_BPC_MASK (7 << 20) 7356 #define TRANS_DDI_BPC_8 (0 << 20) 7357 #define TRANS_DDI_BPC_10 (1 << 20) 7358 #define TRANS_DDI_BPC_6 (2 << 20) 7359 #define TRANS_DDI_BPC_12 (3 << 20) 7360 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18) 7361 #define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x)) 7362 #define TRANS_DDI_PVSYNC (1 << 17) 7363 #define TRANS_DDI_PHSYNC (1 << 16) 7364 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) 7365 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) 7366 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) 7367 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) 7368 #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) 7369 #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) 7370 #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) 7371 #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) 7372 #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ 7373 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans) 7374 #define TRANS_DDI_HDCP_SIGNALLING (1 << 9) 7375 #define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8) 7376 #define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7) 7377 #define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6) 7378 #define TRANS_DDI_HDCP_SELECT REG_BIT(5) 7379 #define TRANS_DDI_BFI_ENABLE (1 << 4) 7380 #define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4) 7381 #define TRANS_DDI_HDMI_SCRAMBLING (1 << 0) 7382 #define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \ 7383 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \ 7384 | TRANS_DDI_HDMI_SCRAMBLING) 7385 7386 #define _TRANS_DDI_FUNC_CTL2_A 0x60404 7387 #define _TRANS_DDI_FUNC_CTL2_B 0x61404 7388 #define _TRANS_DDI_FUNC_CTL2_C 0x62404 7389 #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 7390 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 7391 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 7392 #define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A) 7393 #define PORT_SYNC_MODE_ENABLE REG_BIT(4) 7394 #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0) 7395 #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x)) 7396 7397 #define TRANS_CMTG_CHICKEN _MMIO(0x6fa90) 7398 #define DISABLE_DPT_CLK_GATING REG_BIT(1) 7399 7400 /* DisplayPort Transport Control */ 7401 #define _DP_TP_CTL_A 0x64040 7402 #define _DP_TP_CTL_B 0x64140 7403 #define _TGL_DP_TP_CTL_A 0x60540 7404 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 7405 #define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A) 7406 #define DP_TP_CTL_ENABLE (1 << 31) 7407 #define DP_TP_CTL_FEC_ENABLE (1 << 30) 7408 #define DP_TP_CTL_MODE_SST (0 << 27) 7409 #define DP_TP_CTL_MODE_MST (1 << 27) 7410 #define DP_TP_CTL_FORCE_ACT (1 << 25) 7411 #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) 7412 #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) 7413 #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) 7414 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) 7415 #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8) 7416 #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8) 7417 #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8) 7418 #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8) 7419 #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8) 7420 #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7) 7421 7422 /* DisplayPort Transport Status */ 7423 #define _DP_TP_STATUS_A 0x64044 7424 #define _DP_TP_STATUS_B 0x64144 7425 #define _TGL_DP_TP_STATUS_A 0x60544 7426 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 7427 #define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A) 7428 #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) 7429 #define DP_TP_STATUS_IDLE_DONE (1 << 25) 7430 #define DP_TP_STATUS_ACT_SENT (1 << 24) 7431 #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) 7432 #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12) 7433 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 7434 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 7435 #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 7436 7437 /* DDI Buffer Control */ 7438 #define _DDI_BUF_CTL_A 0x64000 7439 #define _DDI_BUF_CTL_B 0x64100 7440 #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) 7441 #define DDI_BUF_CTL_ENABLE (1 << 31) 7442 #define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 7443 #define DDI_BUF_EMP_MASK (0xf << 24) 7444 #define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20) 7445 #define DDI_BUF_PORT_REVERSAL (1 << 16) 7446 #define DDI_BUF_IS_IDLE (1 << 7) 7447 #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) 7448 #define DDI_A_4_LANES (1 << 4) 7449 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 7450 #define DDI_PORT_WIDTH_MASK (7 << 1) 7451 #define DDI_PORT_WIDTH_SHIFT 1 7452 #define DDI_INIT_DISPLAY_DETECTED (1 << 0) 7453 7454 /* DDI Buffer Translations */ 7455 #define _DDI_BUF_TRANS_A 0x64E00 7456 #define _DDI_BUF_TRANS_B 0x64E60 7457 #define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8) 7458 #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) 7459 #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) 7460 7461 /* DDI DP Compliance Control */ 7462 #define _DDI_DP_COMP_CTL_A 0x605F0 7463 #define _DDI_DP_COMP_CTL_B 0x615F0 7464 #define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B) 7465 #define DDI_DP_COMP_CTL_ENABLE (1 << 31) 7466 #define DDI_DP_COMP_CTL_D10_2 (0 << 28) 7467 #define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28) 7468 #define DDI_DP_COMP_CTL_PRBS7 (2 << 28) 7469 #define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28) 7470 #define DDI_DP_COMP_CTL_HBR2 (4 << 28) 7471 #define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28) 7472 #define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0) 7473 7474 /* DDI DP Compliance Pattern */ 7475 #define _DDI_DP_COMP_PAT_A 0x605F4 7476 #define _DDI_DP_COMP_PAT_B 0x615F4 7477 #define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4) 7478 7479 /* Sideband Interface (SBI) is programmed indirectly, via 7480 * SBI_ADDR, which contains the register offset; and SBI_DATA, 7481 * which contains the payload */ 7482 #define SBI_ADDR _MMIO(0xC6000) 7483 #define SBI_DATA _MMIO(0xC6004) 7484 #define SBI_CTL_STAT _MMIO(0xC6008) 7485 #define SBI_CTL_DEST_ICLK (0x0 << 16) 7486 #define SBI_CTL_DEST_MPHY (0x1 << 16) 7487 #define SBI_CTL_OP_IORD (0x2 << 8) 7488 #define SBI_CTL_OP_IOWR (0x3 << 8) 7489 #define SBI_CTL_OP_CRRD (0x6 << 8) 7490 #define SBI_CTL_OP_CRWR (0x7 << 8) 7491 #define SBI_RESPONSE_FAIL (0x1 << 1) 7492 #define SBI_RESPONSE_SUCCESS (0x0 << 1) 7493 #define SBI_BUSY (0x1 << 0) 7494 #define SBI_READY (0x0 << 0) 7495 7496 /* SBI offsets */ 7497 #define SBI_SSCDIVINTPHASE 0x0200 7498 #define SBI_SSCDIVINTPHASE6 0x0600 7499 #define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 7500 #define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1) 7501 #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1) 7502 #define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 7503 #define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8) 7504 #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8) 7505 #define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15) 7506 #define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0) 7507 #define SBI_SSCDITHPHASE 0x0204 7508 #define SBI_SSCCTL 0x020c 7509 #define SBI_SSCCTL6 0x060C 7510 #define SBI_SSCCTL_PATHALT (1 << 3) 7511 #define SBI_SSCCTL_DISABLE (1 << 0) 7512 #define SBI_SSCAUXDIV6 0x0610 7513 #define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 7514 #define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4) 7515 #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4) 7516 #define SBI_DBUFF0 0x2a00 7517 #define SBI_GEN0 0x1f00 7518 #define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0) 7519 7520 /* LPT PIXCLK_GATE */ 7521 #define PIXCLK_GATE _MMIO(0xC6020) 7522 #define PIXCLK_GATE_UNGATE (1 << 0) 7523 #define PIXCLK_GATE_GATE (0 << 0) 7524 7525 /* SPLL */ 7526 #define SPLL_CTL _MMIO(0x46020) 7527 #define SPLL_PLL_ENABLE (1 << 31) 7528 #define SPLL_REF_BCLK (0 << 28) 7529 #define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 7530 #define SPLL_REF_NON_SSC_HSW (2 << 28) 7531 #define SPLL_REF_PCH_SSC_BDW (2 << 28) 7532 #define SPLL_REF_LCPLL (3 << 28) 7533 #define SPLL_REF_MASK (3 << 28) 7534 #define SPLL_FREQ_810MHz (0 << 26) 7535 #define SPLL_FREQ_1350MHz (1 << 26) 7536 #define SPLL_FREQ_2700MHz (2 << 26) 7537 #define SPLL_FREQ_MASK (3 << 26) 7538 7539 /* WRPLL */ 7540 #define _WRPLL_CTL1 0x46040 7541 #define _WRPLL_CTL2 0x46060 7542 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) 7543 #define WRPLL_PLL_ENABLE (1 << 31) 7544 #define WRPLL_REF_BCLK (0 << 28) 7545 #define WRPLL_REF_PCH_SSC (1 << 28) 7546 #define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */ 7547 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */ 7548 #define WRPLL_REF_LCPLL (3 << 28) 7549 #define WRPLL_REF_MASK (3 << 28) 7550 /* WRPLL divider programming */ 7551 #define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0) 7552 #define WRPLL_DIVIDER_REF_MASK (0xff) 7553 #define WRPLL_DIVIDER_POST(x) ((x) << 8) 7554 #define WRPLL_DIVIDER_POST_MASK (0x3f << 8) 7555 #define WRPLL_DIVIDER_POST_SHIFT 8 7556 #define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16) 7557 #define WRPLL_DIVIDER_FB_SHIFT 16 7558 #define WRPLL_DIVIDER_FB_MASK (0xff << 16) 7559 7560 /* Port clock selection */ 7561 #define _PORT_CLK_SEL_A 0x46100 7562 #define _PORT_CLK_SEL_B 0x46104 7563 #define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B) 7564 #define PORT_CLK_SEL_MASK REG_GENMASK(31, 29) 7565 #define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0) 7566 #define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1) 7567 #define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2) 7568 #define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3) 7569 #define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll)) 7570 #define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4) 7571 #define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5) 7572 #define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7) 7573 7574 /* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */ 7575 #define DDI_CLK_SEL(port) PORT_CLK_SEL(port) 7576 #define DDI_CLK_SEL_MASK REG_GENMASK(31, 28) 7577 #define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0) 7578 #define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8) 7579 #define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC) 7580 #define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD) 7581 #define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE) 7582 #define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF) 7583 7584 /* Transcoder clock selection */ 7585 #define _TRANS_CLK_SEL_A 0x46140 7586 #define _TRANS_CLK_SEL_B 0x46144 7587 #define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B) 7588 /* For each transcoder, we need to select the corresponding port clock */ 7589 #define TRANS_CLK_SEL_DISABLED (0x0 << 29) 7590 #define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29) 7591 #define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28) 7592 #define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28) 7593 7594 7595 #define CDCLK_FREQ _MMIO(0x46200) 7596 7597 #define _TRANSA_MSA_MISC 0x60410 7598 #define _TRANSB_MSA_MISC 0x61410 7599 #define _TRANSC_MSA_MISC 0x62410 7600 #define _TRANS_EDP_MSA_MISC 0x6f410 7601 #define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) 7602 /* See DP_MSA_MISC_* for the bit definitions */ 7603 7604 #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C 7605 #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C 7606 #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C 7607 #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C 7608 #define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY) 7609 #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0) 7610 #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x)) 7611 7612 /* LCPLL Control */ 7613 #define LCPLL_CTL _MMIO(0x130040) 7614 #define LCPLL_PLL_DISABLE (1 << 31) 7615 #define LCPLL_PLL_LOCK (1 << 30) 7616 #define LCPLL_REF_NON_SSC (0 << 28) 7617 #define LCPLL_REF_BCLK (2 << 28) 7618 #define LCPLL_REF_PCH_SSC (3 << 28) 7619 #define LCPLL_REF_MASK (3 << 28) 7620 #define LCPLL_CLK_FREQ_MASK (3 << 26) 7621 #define LCPLL_CLK_FREQ_450 (0 << 26) 7622 #define LCPLL_CLK_FREQ_54O_BDW (1 << 26) 7623 #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) 7624 #define LCPLL_CLK_FREQ_675_BDW (3 << 26) 7625 #define LCPLL_CD_CLOCK_DISABLE (1 << 25) 7626 #define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24) 7627 #define LCPLL_CD2X_CLOCK_DISABLE (1 << 23) 7628 #define LCPLL_POWER_DOWN_ALLOW (1 << 22) 7629 #define LCPLL_CD_SOURCE_FCLK (1 << 21) 7630 #define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19) 7631 7632 /* 7633 * SKL Clocks 7634 */ 7635 7636 /* CDCLK_CTL */ 7637 #define CDCLK_CTL _MMIO(0x46000) 7638 #define CDCLK_FREQ_SEL_MASK (3 << 26) 7639 #define CDCLK_FREQ_450_432 (0 << 26) 7640 #define CDCLK_FREQ_540 (1 << 26) 7641 #define CDCLK_FREQ_337_308 (2 << 26) 7642 #define CDCLK_FREQ_675_617 (3 << 26) 7643 #define BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22) 7644 #define BXT_CDCLK_CD2X_DIV_SEL_1 (0 << 22) 7645 #define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1 << 22) 7646 #define BXT_CDCLK_CD2X_DIV_SEL_2 (2 << 22) 7647 #define BXT_CDCLK_CD2X_DIV_SEL_4 (3 << 22) 7648 #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20) 7649 #define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19) 7650 #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) 7651 #define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19) 7652 #define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19) 7653 #define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe) 7654 #define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE 7655 #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16) 7656 #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) 7657 7658 /* CDCLK_SQUASH_CTL */ 7659 #define CDCLK_SQUASH_CTL _MMIO(0x46008) 7660 #define CDCLK_SQUASH_ENABLE REG_BIT(31) 7661 #define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24) 7662 #define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x)) 7663 #define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0) 7664 #define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x)) 7665 7666 /* LCPLL_CTL */ 7667 #define LCPLL1_CTL _MMIO(0x46010) 7668 #define LCPLL2_CTL _MMIO(0x46014) 7669 #define LCPLL_PLL_ENABLE (1 << 31) 7670 7671 /* DPLL control1 */ 7672 #define DPLL_CTRL1 _MMIO(0x6C058) 7673 #define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5)) 7674 #define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4)) 7675 #define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1)) 7676 #define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1) 7677 #define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1)) 7678 #define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6)) 7679 #define DPLL_CTRL1_LINK_RATE_2700 0 7680 #define DPLL_CTRL1_LINK_RATE_1350 1 7681 #define DPLL_CTRL1_LINK_RATE_810 2 7682 #define DPLL_CTRL1_LINK_RATE_1620 3 7683 #define DPLL_CTRL1_LINK_RATE_1080 4 7684 #define DPLL_CTRL1_LINK_RATE_2160 5 7685 7686 /* DPLL control2 */ 7687 #define DPLL_CTRL2 _MMIO(0x6C05C) 7688 #define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15)) 7689 #define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1)) 7690 #define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1) 7691 #define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1)) 7692 #define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3)) 7693 7694 /* DPLL Status */ 7695 #define DPLL_STATUS _MMIO(0x6C060) 7696 #define DPLL_LOCK(id) (1 << ((id) * 8)) 7697 7698 /* DPLL cfg */ 7699 #define _DPLL1_CFGCR1 0x6C040 7700 #define _DPLL2_CFGCR1 0x6C048 7701 #define _DPLL3_CFGCR1 0x6C050 7702 #define DPLL_CFGCR1_FREQ_ENABLE (1 << 31) 7703 #define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9) 7704 #define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9) 7705 #define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff) 7706 7707 #define _DPLL1_CFGCR2 0x6C044 7708 #define _DPLL2_CFGCR2 0x6C04C 7709 #define _DPLL3_CFGCR2 0x6C054 7710 #define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8) 7711 #define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8) 7712 #define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7) 7713 #define DPLL_CFGCR2_KDIV_MASK (3 << 5) 7714 #define DPLL_CFGCR2_KDIV(x) ((x) << 5) 7715 #define DPLL_CFGCR2_KDIV_5 (0 << 5) 7716 #define DPLL_CFGCR2_KDIV_2 (1 << 5) 7717 #define DPLL_CFGCR2_KDIV_3 (2 << 5) 7718 #define DPLL_CFGCR2_KDIV_1 (3 << 5) 7719 #define DPLL_CFGCR2_PDIV_MASK (7 << 2) 7720 #define DPLL_CFGCR2_PDIV(x) ((x) << 2) 7721 #define DPLL_CFGCR2_PDIV_1 (0 << 2) 7722 #define DPLL_CFGCR2_PDIV_2 (1 << 2) 7723 #define DPLL_CFGCR2_PDIV_3 (2 << 2) 7724 #define DPLL_CFGCR2_PDIV_7 (4 << 2) 7725 #define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2) 7726 #define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3) 7727 7728 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1) 7729 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2) 7730 7731 /* ICL Clocks */ 7732 #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280) 7733 #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5)) 7734 #define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10) 7735 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ 7736 (tc_port) + 12 : \ 7737 (tc_port) - TC_PORT_4 + 21)) 7738 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2) 7739 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7740 #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7741 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27) 7742 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \ 7743 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7744 #define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \ 7745 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7746 7747 /* 7748 * DG1 Clocks 7749 * First registers controls the first A and B, while the second register 7750 * controls the phy C and D. The bits on these registers are the 7751 * same, but refer to different phys 7752 */ 7753 #define _DG1_DPCLKA_CFGCR0 0x164280 7754 #define _DG1_DPCLKA1_CFGCR0 0x16C280 7755 #define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2) 7756 #define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2) 7757 #define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \ 7758 _DG1_DPCLKA_CFGCR0, \ 7759 _DG1_DPCLKA1_CFGCR0) 7760 #define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10) 7761 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2) 7762 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7763 #define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)) 7764 7765 /* ADLS Clocks */ 7766 #define _ADLS_DPCLKA_CFGCR0 0x164280 7767 #define _ADLS_DPCLKA_CFGCR1 0x1642BC 7768 #define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \ 7769 _ADLS_DPCLKA_CFGCR0, \ 7770 _ADLS_DPCLKA_CFGCR1) 7771 #define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2) 7772 /* ADLS DPCLKA_CFGCR0 DDI mask */ 7773 #define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4) 7774 #define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2) 7775 #define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0) 7776 /* ADLS DPCLKA_CFGCR1 DDI mask */ 7777 #define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2) 7778 #define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0) 7779 #define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \ 7780 ADLS_DPCLKA_DDIA_SEL_MASK, \ 7781 ADLS_DPCLKA_DDIB_SEL_MASK, \ 7782 ADLS_DPCLKA_DDII_SEL_MASK, \ 7783 ADLS_DPCLKA_DDIJ_SEL_MASK, \ 7784 ADLS_DPCLKA_DDIK_SEL_MASK) 7785 7786 /* ICL PLL */ 7787 #define DPLL0_ENABLE 0x46010 7788 #define DPLL1_ENABLE 0x46014 7789 #define _ADLS_DPLL2_ENABLE 0x46018 7790 #define _ADLS_DPLL3_ENABLE 0x46030 7791 #define PLL_ENABLE (1 << 31) 7792 #define PLL_LOCK (1 << 30) 7793 #define PLL_POWER_ENABLE (1 << 27) 7794 #define PLL_POWER_STATE (1 << 26) 7795 #define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ 7796 _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE) 7797 7798 #define _DG2_PLL3_ENABLE 0x4601C 7799 7800 #define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ 7801 _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE) 7802 7803 #define TBT_PLL_ENABLE _MMIO(0x46020) 7804 7805 #define _MG_PLL1_ENABLE 0x46030 7806 #define _MG_PLL2_ENABLE 0x46034 7807 #define _MG_PLL3_ENABLE 0x46038 7808 #define _MG_PLL4_ENABLE 0x4603C 7809 /* Bits are the same as DPLL0_ENABLE */ 7810 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ 7811 _MG_PLL2_ENABLE) 7812 7813 /* DG1 PLL */ 7814 #define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \ 7815 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE) 7816 7817 /* ADL-P Type C PLL */ 7818 #define PORTTC1_PLL_ENABLE 0x46038 7819 #define PORTTC2_PLL_ENABLE 0x46040 7820 7821 #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \ 7822 PORTTC1_PLL_ENABLE, \ 7823 PORTTC2_PLL_ENABLE) 7824 7825 #define _ICL_DPLL0_CFGCR0 0x164000 7826 #define _ICL_DPLL1_CFGCR0 0x164080 7827 #define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \ 7828 _ICL_DPLL1_CFGCR0) 7829 #define DPLL_CFGCR0_HDMI_MODE (1 << 30) 7830 #define DPLL_CFGCR0_SSC_ENABLE (1 << 29) 7831 #define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25) 7832 #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25) 7833 #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25) 7834 #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25) 7835 #define DPLL_CFGCR0_LINK_RATE_810 (2 << 25) 7836 #define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25) 7837 #define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25) 7838 #define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25) 7839 #define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25) 7840 #define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25) 7841 #define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10) 7842 #define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10) 7843 #define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10) 7844 #define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff) 7845 7846 #define _ICL_DPLL0_CFGCR1 0x164004 7847 #define _ICL_DPLL1_CFGCR1 0x164084 7848 #define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \ 7849 _ICL_DPLL1_CFGCR1) 7850 #define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10) 7851 #define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10) 7852 #define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10) 7853 #define DPLL_CFGCR1_QDIV_MODE_SHIFT (9) 7854 #define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9) 7855 #define DPLL_CFGCR1_KDIV_MASK (7 << 6) 7856 #define DPLL_CFGCR1_KDIV_SHIFT (6) 7857 #define DPLL_CFGCR1_KDIV(x) ((x) << 6) 7858 #define DPLL_CFGCR1_KDIV_1 (1 << 6) 7859 #define DPLL_CFGCR1_KDIV_2 (2 << 6) 7860 #define DPLL_CFGCR1_KDIV_3 (4 << 6) 7861 #define DPLL_CFGCR1_PDIV_MASK (0xf << 2) 7862 #define DPLL_CFGCR1_PDIV_SHIFT (2) 7863 #define DPLL_CFGCR1_PDIV(x) ((x) << 2) 7864 #define DPLL_CFGCR1_PDIV_2 (1 << 2) 7865 #define DPLL_CFGCR1_PDIV_3 (2 << 2) 7866 #define DPLL_CFGCR1_PDIV_5 (4 << 2) 7867 #define DPLL_CFGCR1_PDIV_7 (8 << 2) 7868 #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0) 7869 #define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0) 7870 #define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0) 7871 7872 #define _TGL_DPLL0_CFGCR0 0x164284 7873 #define _TGL_DPLL1_CFGCR0 0x16428C 7874 #define _TGL_TBTPLL_CFGCR0 0x16429C 7875 #define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 7876 _TGL_DPLL1_CFGCR0, \ 7877 _TGL_TBTPLL_CFGCR0) 7878 #define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \ 7879 _TGL_DPLL1_CFGCR0) 7880 7881 #define _TGL_DPLL0_DIV0 0x164B00 7882 #define _TGL_DPLL1_DIV0 0x164C00 7883 #define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0) 7884 #define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) 7885 #define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val)) 7886 7887 #define _TGL_DPLL0_CFGCR1 0x164288 7888 #define _TGL_DPLL1_CFGCR1 0x164290 7889 #define _TGL_TBTPLL_CFGCR1 0x1642A0 7890 #define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 7891 _TGL_DPLL1_CFGCR1, \ 7892 _TGL_TBTPLL_CFGCR1) 7893 #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \ 7894 _TGL_DPLL1_CFGCR1) 7895 7896 #define _DG1_DPLL2_CFGCR0 0x16C284 7897 #define _DG1_DPLL3_CFGCR0 0x16C28C 7898 #define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 7899 _TGL_DPLL1_CFGCR0, \ 7900 _DG1_DPLL2_CFGCR0, \ 7901 _DG1_DPLL3_CFGCR0) 7902 7903 #define _DG1_DPLL2_CFGCR1 0x16C288 7904 #define _DG1_DPLL3_CFGCR1 0x16C290 7905 #define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 7906 _TGL_DPLL1_CFGCR1, \ 7907 _DG1_DPLL2_CFGCR1, \ 7908 _DG1_DPLL3_CFGCR1) 7909 7910 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */ 7911 #define _ADLS_DPLL3_CFGCR0 0x1642C0 7912 #define _ADLS_DPLL4_CFGCR0 0x164294 7913 #define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \ 7914 _TGL_DPLL1_CFGCR0, \ 7915 _ADLS_DPLL4_CFGCR0, \ 7916 _ADLS_DPLL3_CFGCR0) 7917 7918 #define _ADLS_DPLL3_CFGCR1 0x1642C4 7919 #define _ADLS_DPLL4_CFGCR1 0x164298 7920 #define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \ 7921 _TGL_DPLL1_CFGCR1, \ 7922 _ADLS_DPLL4_CFGCR1, \ 7923 _ADLS_DPLL3_CFGCR1) 7924 7925 #define _DKL_PHY1_BASE 0x168000 7926 #define _DKL_PHY2_BASE 0x169000 7927 #define _DKL_PHY3_BASE 0x16A000 7928 #define _DKL_PHY4_BASE 0x16B000 7929 #define _DKL_PHY5_BASE 0x16C000 7930 #define _DKL_PHY6_BASE 0x16D000 7931 7932 /* DEKEL PHY MMIO Address = Phy base + (internal address & ~index_mask) */ 7933 #define _DKL_PCS_DW5 0x14 7934 #define DKL_PCS_DW5(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 7935 _DKL_PHY2_BASE) + \ 7936 _DKL_PCS_DW5) 7937 #define DKL_PCS_DW5_CORE_SOFTRESET REG_BIT(11) 7938 7939 #define _DKL_PLL_DIV0 0x200 7940 #define DKL_PLL_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25) 7941 #define DKL_PLL_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val)) 7942 #define DKL_PLL_DIV0_INTEG_COEFF(x) ((x) << 16) 7943 #define DKL_PLL_DIV0_INTEG_COEFF_MASK (0x1F << 16) 7944 #define DKL_PLL_DIV0_PROP_COEFF(x) ((x) << 12) 7945 #define DKL_PLL_DIV0_PROP_COEFF_MASK (0xF << 12) 7946 #define DKL_PLL_DIV0_FBPREDIV_SHIFT (8) 7947 #define DKL_PLL_DIV0_FBPREDIV(x) ((x) << DKL_PLL_DIV0_FBPREDIV_SHIFT) 7948 #define DKL_PLL_DIV0_FBPREDIV_MASK (0xF << DKL_PLL_DIV0_FBPREDIV_SHIFT) 7949 #define DKL_PLL_DIV0_FBDIV_INT(x) ((x) << 0) 7950 #define DKL_PLL_DIV0_FBDIV_INT_MASK (0xFF << 0) 7951 #define DKL_PLL_DIV0_MASK (DKL_PLL_DIV0_INTEG_COEFF_MASK | \ 7952 DKL_PLL_DIV0_PROP_COEFF_MASK | \ 7953 DKL_PLL_DIV0_FBPREDIV_MASK | \ 7954 DKL_PLL_DIV0_FBDIV_INT_MASK) 7955 #define DKL_PLL_DIV0(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 7956 _DKL_PHY2_BASE) + \ 7957 _DKL_PLL_DIV0) 7958 7959 #define _DKL_PLL_DIV1 0x204 7960 #define DKL_PLL_DIV1_IREF_TRIM(x) ((x) << 16) 7961 #define DKL_PLL_DIV1_IREF_TRIM_MASK (0x1F << 16) 7962 #define DKL_PLL_DIV1_TDC_TARGET_CNT(x) ((x) << 0) 7963 #define DKL_PLL_DIV1_TDC_TARGET_CNT_MASK (0xFF << 0) 7964 #define DKL_PLL_DIV1(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 7965 _DKL_PHY2_BASE) + \ 7966 _DKL_PLL_DIV1) 7967 7968 #define _DKL_PLL_SSC 0x210 7969 #define DKL_PLL_SSC_IREF_NDIV_RATIO(x) ((x) << 29) 7970 #define DKL_PLL_SSC_IREF_NDIV_RATIO_MASK (0x7 << 29) 7971 #define DKL_PLL_SSC_STEP_LEN(x) ((x) << 16) 7972 #define DKL_PLL_SSC_STEP_LEN_MASK (0xFF << 16) 7973 #define DKL_PLL_SSC_STEP_NUM(x) ((x) << 11) 7974 #define DKL_PLL_SSC_STEP_NUM_MASK (0x7 << 11) 7975 #define DKL_PLL_SSC_EN (1 << 9) 7976 #define DKL_PLL_SSC(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 7977 _DKL_PHY2_BASE) + \ 7978 _DKL_PLL_SSC) 7979 7980 #define _DKL_PLL_BIAS 0x214 7981 #define DKL_PLL_BIAS_FRAC_EN_H (1 << 30) 7982 #define DKL_PLL_BIAS_FBDIV_SHIFT (8) 7983 #define DKL_PLL_BIAS_FBDIV_FRAC(x) ((x) << DKL_PLL_BIAS_FBDIV_SHIFT) 7984 #define DKL_PLL_BIAS_FBDIV_FRAC_MASK (0x3FFFFF << DKL_PLL_BIAS_FBDIV_SHIFT) 7985 #define DKL_PLL_BIAS(tc_port) _MMIO(_PORT(tc_port, _DKL_PHY1_BASE, \ 7986 _DKL_PHY2_BASE) + \ 7987 _DKL_PLL_BIAS) 7988 7989 #define _DKL_PLL_TDC_COLDST_BIAS 0x218 7990 #define DKL_PLL_TDC_SSC_STEP_SIZE(x) ((x) << 8) 7991 #define DKL_PLL_TDC_SSC_STEP_SIZE_MASK (0xFF << 8) 7992 #define DKL_PLL_TDC_FEED_FWD_GAIN(x) ((x) << 0) 7993 #define DKL_PLL_TDC_FEED_FWD_GAIN_MASK (0xFF << 0) 7994 #define DKL_PLL_TDC_COLDST_BIAS(tc_port) _MMIO(_PORT(tc_port, \ 7995 _DKL_PHY1_BASE, \ 7996 _DKL_PHY2_BASE) + \ 7997 _DKL_PLL_TDC_COLDST_BIAS) 7998 7999 #define _DKL_REFCLKIN_CTL 0x12C 8000 /* Bits are the same as MG_REFCLKIN_CTL */ 8001 #define DKL_REFCLKIN_CTL(tc_port) _MMIO(_PORT(tc_port, \ 8002 _DKL_PHY1_BASE, \ 8003 _DKL_PHY2_BASE) + \ 8004 _DKL_REFCLKIN_CTL) 8005 8006 #define _DKL_CLKTOP2_HSCLKCTL 0xD4 8007 /* Bits are the same as MG_CLKTOP2_HSCLKCTL */ 8008 #define DKL_CLKTOP2_HSCLKCTL(tc_port) _MMIO(_PORT(tc_port, \ 8009 _DKL_PHY1_BASE, \ 8010 _DKL_PHY2_BASE) + \ 8011 _DKL_CLKTOP2_HSCLKCTL) 8012 8013 #define _DKL_CLKTOP2_CORECLKCTL1 0xD8 8014 /* Bits are the same as MG_CLKTOP2_CORECLKCTL1 */ 8015 #define DKL_CLKTOP2_CORECLKCTL1(tc_port) _MMIO(_PORT(tc_port, \ 8016 _DKL_PHY1_BASE, \ 8017 _DKL_PHY2_BASE) + \ 8018 _DKL_CLKTOP2_CORECLKCTL1) 8019 8020 #define _DKL_TX_DPCNTL0 0x2C0 8021 #define DKL_TX_PRESHOOT_COEFF(x) ((x) << 13) 8022 #define DKL_TX_PRESHOOT_COEFF_MASK (0x1f << 13) 8023 #define DKL_TX_DE_EMPHASIS_COEFF(x) ((x) << 8) 8024 #define DKL_TX_DE_EMPAHSIS_COEFF_MASK (0x1f << 8) 8025 #define DKL_TX_VSWING_CONTROL(x) ((x) << 0) 8026 #define DKL_TX_VSWING_CONTROL_MASK (0x7 << 0) 8027 #define DKL_TX_DPCNTL0(tc_port) _MMIO(_PORT(tc_port, \ 8028 _DKL_PHY1_BASE, \ 8029 _DKL_PHY2_BASE) + \ 8030 _DKL_TX_DPCNTL0) 8031 8032 #define _DKL_TX_DPCNTL1 0x2C4 8033 /* Bits are the same as DKL_TX_DPCNTRL0 */ 8034 #define DKL_TX_DPCNTL1(tc_port) _MMIO(_PORT(tc_port, \ 8035 _DKL_PHY1_BASE, \ 8036 _DKL_PHY2_BASE) + \ 8037 _DKL_TX_DPCNTL1) 8038 8039 #define _DKL_TX_DPCNTL2 0x2C8 8040 #define DKL_TX_DP20BITMODE REG_BIT(2) 8041 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK REG_GENMASK(4, 3) 8042 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK, (val)) 8043 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK REG_GENMASK(6, 5) 8044 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, (val)) 8045 #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \ 8046 _DKL_PHY1_BASE, \ 8047 _DKL_PHY2_BASE) + \ 8048 _DKL_TX_DPCNTL2) 8049 8050 #define _DKL_TX_FW_CALIB 0x2F8 8051 #define DKL_TX_CFG_DISABLE_WAIT_INIT (1 << 7) 8052 #define DKL_TX_FW_CALIB(tc_port) _MMIO(_PORT(tc_port, \ 8053 _DKL_PHY1_BASE, \ 8054 _DKL_PHY2_BASE) + \ 8055 _DKL_TX_FW_CALIB) 8056 8057 #define _DKL_TX_PMD_LANE_SUS 0xD00 8058 #define DKL_TX_PMD_LANE_SUS(tc_port) _MMIO(_PORT(tc_port, \ 8059 _DKL_PHY1_BASE, \ 8060 _DKL_PHY2_BASE) + \ 8061 _DKL_TX_PMD_LANE_SUS) 8062 8063 #define _DKL_TX_DW17 0xDC4 8064 #define DKL_TX_DW17(tc_port) _MMIO(_PORT(tc_port, \ 8065 _DKL_PHY1_BASE, \ 8066 _DKL_PHY2_BASE) + \ 8067 _DKL_TX_DW17) 8068 8069 #define _DKL_TX_DW18 0xDC8 8070 #define DKL_TX_DW18(tc_port) _MMIO(_PORT(tc_port, \ 8071 _DKL_PHY1_BASE, \ 8072 _DKL_PHY2_BASE) + \ 8073 _DKL_TX_DW18) 8074 8075 #define _DKL_DP_MODE 0xA0 8076 #define DKL_DP_MODE(tc_port) _MMIO(_PORT(tc_port, \ 8077 _DKL_PHY1_BASE, \ 8078 _DKL_PHY2_BASE) + \ 8079 _DKL_DP_MODE) 8080 8081 #define _DKL_CMN_UC_DW27 0x36C 8082 #define DKL_CMN_UC_DW27_UC_HEALTH (0x1 << 15) 8083 #define DKL_CMN_UC_DW_27(tc_port) _MMIO(_PORT(tc_port, \ 8084 _DKL_PHY1_BASE, \ 8085 _DKL_PHY2_BASE) + \ 8086 _DKL_CMN_UC_DW27) 8087 8088 /* 8089 * Each Dekel PHY is addressed through a 4KB aperture. Each PHY has more than 8090 * 4KB of register space, so a separate index is programmed in HIP_INDEX_REG0 8091 * or HIP_INDEX_REG1, based on the port number, to set the upper 2 address 8092 * bits that point the 4KB window into the full PHY register space. 8093 */ 8094 #define _HIP_INDEX_REG0 0x1010A0 8095 #define _HIP_INDEX_REG1 0x1010A4 8096 #define HIP_INDEX_REG(tc_port) _MMIO((tc_port) < 4 ? _HIP_INDEX_REG0 \ 8097 : _HIP_INDEX_REG1) 8098 #define _HIP_INDEX_SHIFT(tc_port) (8 * ((tc_port) % 4)) 8099 #define HIP_INDEX_VAL(tc_port, val) ((val) << _HIP_INDEX_SHIFT(tc_port)) 8100 8101 /* BXT display engine PLL */ 8102 #define BXT_DE_PLL_CTL _MMIO(0x6d000) 8103 #define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */ 8104 #define BXT_DE_PLL_RATIO_MASK 0xff 8105 8106 #define BXT_DE_PLL_ENABLE _MMIO(0x46070) 8107 #define BXT_DE_PLL_PLL_ENABLE (1 << 31) 8108 #define BXT_DE_PLL_LOCK (1 << 30) 8109 #define BXT_DE_PLL_FREQ_REQ (1 << 23) 8110 #define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22) 8111 #define ICL_CDCLK_PLL_RATIO(x) (x) 8112 #define ICL_CDCLK_PLL_RATIO_MASK 0xff 8113 8114 /* GEN9 DC */ 8115 #define DC_STATE_EN _MMIO(0x45504) 8116 #define DC_STATE_DISABLE 0 8117 #define DC_STATE_EN_DC3CO REG_BIT(30) 8118 #define DC_STATE_DC3CO_STATUS REG_BIT(29) 8119 #define DC_STATE_EN_UPTO_DC5 (1 << 0) 8120 #define DC_STATE_EN_DC9 (1 << 3) 8121 #define DC_STATE_EN_UPTO_DC6 (2 << 0) 8122 #define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3 8123 8124 #define DC_STATE_DEBUG _MMIO(0x45520) 8125 #define DC_STATE_DEBUG_MASK_CORES (1 << 0) 8126 #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) 8127 8128 #define D_COMP_BDW _MMIO(0x138144) 8129 8130 /* Pipe WM_LINETIME - watermark line time */ 8131 #define _WM_LINETIME_A 0x45270 8132 #define _WM_LINETIME_B 0x45274 8133 #define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B) 8134 #define HSW_LINETIME_MASK REG_GENMASK(8, 0) 8135 #define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x)) 8136 #define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16) 8137 #define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x)) 8138 8139 /* SFUSE_STRAP */ 8140 #define SFUSE_STRAP _MMIO(0xc2014) 8141 #define SFUSE_STRAP_FUSE_LOCK (1 << 13) 8142 #define SFUSE_STRAP_RAW_FREQUENCY (1 << 8) 8143 #define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7) 8144 #define SFUSE_STRAP_CRT_DISABLED (1 << 6) 8145 #define SFUSE_STRAP_DDIF_DETECTED (1 << 3) 8146 #define SFUSE_STRAP_DDIB_DETECTED (1 << 2) 8147 #define SFUSE_STRAP_DDIC_DETECTED (1 << 1) 8148 #define SFUSE_STRAP_DDID_DETECTED (1 << 0) 8149 8150 #define WM_MISC _MMIO(0x45260) 8151 #define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 8152 8153 #define WM_DBG _MMIO(0x45280) 8154 #define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0) 8155 #define WM_DBG_DISALLOW_MAXFIFO (1 << 1) 8156 #define WM_DBG_DISALLOW_SPRITE (1 << 2) 8157 8158 /* pipe CSC */ 8159 #define _PIPE_A_CSC_COEFF_RY_GY 0x49010 8160 #define _PIPE_A_CSC_COEFF_BY 0x49014 8161 #define _PIPE_A_CSC_COEFF_RU_GU 0x49018 8162 #define _PIPE_A_CSC_COEFF_BU 0x4901c 8163 #define _PIPE_A_CSC_COEFF_RV_GV 0x49020 8164 #define _PIPE_A_CSC_COEFF_BV 0x49024 8165 8166 #define _PIPE_A_CSC_MODE 0x49028 8167 #define ICL_CSC_ENABLE (1 << 31) /* icl+ */ 8168 #define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */ 8169 #define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */ 8170 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */ 8171 #define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */ 8172 8173 #define _PIPE_A_CSC_PREOFF_HI 0x49030 8174 #define _PIPE_A_CSC_PREOFF_ME 0x49034 8175 #define _PIPE_A_CSC_PREOFF_LO 0x49038 8176 #define _PIPE_A_CSC_POSTOFF_HI 0x49040 8177 #define _PIPE_A_CSC_POSTOFF_ME 0x49044 8178 #define _PIPE_A_CSC_POSTOFF_LO 0x49048 8179 8180 #define _PIPE_B_CSC_COEFF_RY_GY 0x49110 8181 #define _PIPE_B_CSC_COEFF_BY 0x49114 8182 #define _PIPE_B_CSC_COEFF_RU_GU 0x49118 8183 #define _PIPE_B_CSC_COEFF_BU 0x4911c 8184 #define _PIPE_B_CSC_COEFF_RV_GV 0x49120 8185 #define _PIPE_B_CSC_COEFF_BV 0x49124 8186 #define _PIPE_B_CSC_MODE 0x49128 8187 #define _PIPE_B_CSC_PREOFF_HI 0x49130 8188 #define _PIPE_B_CSC_PREOFF_ME 0x49134 8189 #define _PIPE_B_CSC_PREOFF_LO 0x49138 8190 #define _PIPE_B_CSC_POSTOFF_HI 0x49140 8191 #define _PIPE_B_CSC_POSTOFF_ME 0x49144 8192 #define _PIPE_B_CSC_POSTOFF_LO 0x49148 8193 8194 #define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 8195 #define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 8196 #define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 8197 #define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 8198 #define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 8199 #define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 8200 #define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 8201 #define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 8202 #define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 8203 #define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 8204 #define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 8205 #define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 8206 #define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 8207 8208 /* Pipe Output CSC */ 8209 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY 0x49050 8210 #define _PIPE_A_OUTPUT_CSC_COEFF_BY 0x49054 8211 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU 0x49058 8212 #define _PIPE_A_OUTPUT_CSC_COEFF_BU 0x4905c 8213 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV 0x49060 8214 #define _PIPE_A_OUTPUT_CSC_COEFF_BV 0x49064 8215 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI 0x49068 8216 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME 0x4906c 8217 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO 0x49070 8218 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI 0x49074 8219 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME 0x49078 8220 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO 0x4907c 8221 8222 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY 0x49150 8223 #define _PIPE_B_OUTPUT_CSC_COEFF_BY 0x49154 8224 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU 0x49158 8225 #define _PIPE_B_OUTPUT_CSC_COEFF_BU 0x4915c 8226 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV 0x49160 8227 #define _PIPE_B_OUTPUT_CSC_COEFF_BV 0x49164 8228 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI 0x49168 8229 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME 0x4916c 8230 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO 0x49170 8231 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI 0x49174 8232 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME 0x49178 8233 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO 0x4917c 8234 8235 #define PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe,\ 8236 _PIPE_A_OUTPUT_CSC_COEFF_RY_GY,\ 8237 _PIPE_B_OUTPUT_CSC_COEFF_RY_GY) 8238 #define PIPE_CSC_OUTPUT_COEFF_BY(pipe) _MMIO_PIPE(pipe, \ 8239 _PIPE_A_OUTPUT_CSC_COEFF_BY, \ 8240 _PIPE_B_OUTPUT_CSC_COEFF_BY) 8241 #define PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, \ 8242 _PIPE_A_OUTPUT_CSC_COEFF_RU_GU, \ 8243 _PIPE_B_OUTPUT_CSC_COEFF_RU_GU) 8244 #define PIPE_CSC_OUTPUT_COEFF_BU(pipe) _MMIO_PIPE(pipe, \ 8245 _PIPE_A_OUTPUT_CSC_COEFF_BU, \ 8246 _PIPE_B_OUTPUT_CSC_COEFF_BU) 8247 #define PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, \ 8248 _PIPE_A_OUTPUT_CSC_COEFF_RV_GV, \ 8249 _PIPE_B_OUTPUT_CSC_COEFF_RV_GV) 8250 #define PIPE_CSC_OUTPUT_COEFF_BV(pipe) _MMIO_PIPE(pipe, \ 8251 _PIPE_A_OUTPUT_CSC_COEFF_BV, \ 8252 _PIPE_B_OUTPUT_CSC_COEFF_BV) 8253 #define PIPE_CSC_OUTPUT_PREOFF_HI(pipe) _MMIO_PIPE(pipe, \ 8254 _PIPE_A_OUTPUT_CSC_PREOFF_HI, \ 8255 _PIPE_B_OUTPUT_CSC_PREOFF_HI) 8256 #define PIPE_CSC_OUTPUT_PREOFF_ME(pipe) _MMIO_PIPE(pipe, \ 8257 _PIPE_A_OUTPUT_CSC_PREOFF_ME, \ 8258 _PIPE_B_OUTPUT_CSC_PREOFF_ME) 8259 #define PIPE_CSC_OUTPUT_PREOFF_LO(pipe) _MMIO_PIPE(pipe, \ 8260 _PIPE_A_OUTPUT_CSC_PREOFF_LO, \ 8261 _PIPE_B_OUTPUT_CSC_PREOFF_LO) 8262 #define PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, \ 8263 _PIPE_A_OUTPUT_CSC_POSTOFF_HI, \ 8264 _PIPE_B_OUTPUT_CSC_POSTOFF_HI) 8265 #define PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, \ 8266 _PIPE_A_OUTPUT_CSC_POSTOFF_ME, \ 8267 _PIPE_B_OUTPUT_CSC_POSTOFF_ME) 8268 #define PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, \ 8269 _PIPE_A_OUTPUT_CSC_POSTOFF_LO, \ 8270 _PIPE_B_OUTPUT_CSC_POSTOFF_LO) 8271 8272 /* pipe degamma/gamma LUTs on IVB+ */ 8273 #define _PAL_PREC_INDEX_A 0x4A400 8274 #define _PAL_PREC_INDEX_B 0x4AC00 8275 #define _PAL_PREC_INDEX_C 0x4B400 8276 #define PAL_PREC_10_12_BIT (0 << 31) 8277 #define PAL_PREC_SPLIT_MODE (1 << 31) 8278 #define PAL_PREC_AUTO_INCREMENT (1 << 15) 8279 #define PAL_PREC_INDEX_VALUE_MASK (0x3ff << 0) 8280 #define PAL_PREC_INDEX_VALUE(x) ((x) << 0) 8281 #define _PAL_PREC_DATA_A 0x4A404 8282 #define _PAL_PREC_DATA_B 0x4AC04 8283 #define _PAL_PREC_DATA_C 0x4B404 8284 #define _PAL_PREC_GC_MAX_A 0x4A410 8285 #define _PAL_PREC_GC_MAX_B 0x4AC10 8286 #define _PAL_PREC_GC_MAX_C 0x4B410 8287 #define PREC_PAL_DATA_RED_MASK REG_GENMASK(29, 20) 8288 #define PREC_PAL_DATA_GREEN_MASK REG_GENMASK(19, 10) 8289 #define PREC_PAL_DATA_BLUE_MASK REG_GENMASK(9, 0) 8290 #define _PAL_PREC_EXT_GC_MAX_A 0x4A420 8291 #define _PAL_PREC_EXT_GC_MAX_B 0x4AC20 8292 #define _PAL_PREC_EXT_GC_MAX_C 0x4B420 8293 #define _PAL_PREC_EXT2_GC_MAX_A 0x4A430 8294 #define _PAL_PREC_EXT2_GC_MAX_B 0x4AC30 8295 #define _PAL_PREC_EXT2_GC_MAX_C 0x4B430 8296 8297 #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B) 8298 #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B) 8299 #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) 8300 #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) 8301 #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) 8302 8303 #define _PRE_CSC_GAMC_INDEX_A 0x4A484 8304 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84 8305 #define _PRE_CSC_GAMC_INDEX_C 0x4B484 8306 #define PRE_CSC_GAMC_AUTO_INCREMENT (1 << 10) 8307 #define _PRE_CSC_GAMC_DATA_A 0x4A488 8308 #define _PRE_CSC_GAMC_DATA_B 0x4AC88 8309 #define _PRE_CSC_GAMC_DATA_C 0x4B488 8310 8311 #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) 8312 #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) 8313 8314 /* ICL Multi segmented gamma */ 8315 #define _PAL_PREC_MULTI_SEG_INDEX_A 0x4A408 8316 #define _PAL_PREC_MULTI_SEG_INDEX_B 0x4AC08 8317 #define PAL_PREC_MULTI_SEGMENT_AUTO_INCREMENT REG_BIT(15) 8318 #define PAL_PREC_MULTI_SEGMENT_INDEX_VALUE_MASK REG_GENMASK(4, 0) 8319 8320 #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C 8321 #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C 8322 #define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24) 8323 #define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20) 8324 #define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14) 8325 #define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10) 8326 #define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4) 8327 #define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0) 8328 8329 #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \ 8330 _PAL_PREC_MULTI_SEG_INDEX_A, \ 8331 _PAL_PREC_MULTI_SEG_INDEX_B) 8332 #define PREC_PAL_MULTI_SEG_DATA(pipe) _MMIO_PIPE(pipe, \ 8333 _PAL_PREC_MULTI_SEG_DATA_A, \ 8334 _PAL_PREC_MULTI_SEG_DATA_B) 8335 8336 #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) 8337 8338 /* Plane CSC Registers */ 8339 #define _PLANE_CSC_RY_GY_1_A 0x70210 8340 #define _PLANE_CSC_RY_GY_2_A 0x70310 8341 8342 #define _PLANE_CSC_RY_GY_1_B 0x71210 8343 #define _PLANE_CSC_RY_GY_2_B 0x71310 8344 8345 #define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \ 8346 _PLANE_CSC_RY_GY_1_B) 8347 #define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ 8348 _PLANE_INPUT_CSC_RY_GY_2_B) 8349 #define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \ 8350 _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ 8351 _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) 8352 8353 #define _PLANE_CSC_PREOFF_HI_1_A 0x70228 8354 #define _PLANE_CSC_PREOFF_HI_2_A 0x70328 8355 8356 #define _PLANE_CSC_PREOFF_HI_1_B 0x71228 8357 #define _PLANE_CSC_PREOFF_HI_2_B 0x71328 8358 8359 #define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \ 8360 _PLANE_CSC_PREOFF_HI_1_B) 8361 #define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \ 8362 _PLANE_CSC_PREOFF_HI_2_B) 8363 #define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \ 8364 (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \ 8365 (index) * 4) 8366 8367 #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234 8368 #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334 8369 8370 #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234 8371 #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334 8372 8373 #define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \ 8374 _PLANE_CSC_POSTOFF_HI_1_B) 8375 #define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \ 8376 _PLANE_CSC_POSTOFF_HI_2_B) 8377 #define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \ 8378 (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ 8379 (index) * 4) 8380 8381 /* pipe CSC & degamma/gamma LUTs on CHV */ 8382 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) 8383 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) 8384 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908) 8385 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C) 8386 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910) 8387 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) 8388 #define CGM_PIPE_DEGAMMA_RED_MASK REG_GENMASK(13, 0) 8389 #define CGM_PIPE_DEGAMMA_GREEN_MASK REG_GENMASK(29, 16) 8390 #define CGM_PIPE_DEGAMMA_BLUE_MASK REG_GENMASK(13, 0) 8391 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000) 8392 #define CGM_PIPE_GAMMA_RED_MASK REG_GENMASK(9, 0) 8393 #define CGM_PIPE_GAMMA_GREEN_MASK REG_GENMASK(25, 16) 8394 #define CGM_PIPE_GAMMA_BLUE_MASK REG_GENMASK(9, 0) 8395 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00) 8396 #define CGM_PIPE_MODE_GAMMA (1 << 2) 8397 #define CGM_PIPE_MODE_CSC (1 << 1) 8398 #define CGM_PIPE_MODE_DEGAMMA (1 << 0) 8399 8400 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900) 8401 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904) 8402 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908) 8403 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C) 8404 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910) 8405 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) 8406 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000) 8407 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00) 8408 8409 #define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01) 8410 #define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23) 8411 #define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45) 8412 #define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67) 8413 #define CGM_PIPE_CSC_COEFF8(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8) 8414 #define CGM_PIPE_DEGAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, _CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4) 8415 #define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, _CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4) 8416 #define CGM_PIPE_MODE(pipe) _MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, _CGM_PIPE_B_MODE) 8417 8418 /* Gen4+ Timestamp and Pipe Frame time stamp registers */ 8419 #define GEN4_TIMESTAMP _MMIO(0x2358) 8420 #define ILK_TIMESTAMP_HI _MMIO(0x70070) 8421 #define IVB_TIMESTAMP_CTR _MMIO(0x44070) 8422 8423 #define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074) 8424 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 8425 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff 8426 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 8427 #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) 8428 8429 #define _PIPE_FRMTMSTMP_A 0x70048 8430 #define PIPE_FRMTMSTMP(pipe) \ 8431 _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A) 8432 8433 /* Display Stream Splitter Control */ 8434 #define DSS_CTL1 _MMIO(0x67400) 8435 #define SPLITTER_ENABLE (1 << 31) 8436 #define JOINER_ENABLE (1 << 30) 8437 #define DUAL_LINK_MODE_INTERLEAVE (1 << 24) 8438 #define DUAL_LINK_MODE_FRONTBACK (0 << 24) 8439 #define OVERLAP_PIXELS_MASK (0xf << 16) 8440 #define OVERLAP_PIXELS(pixels) ((pixels) << 16) 8441 #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 8442 #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 8443 #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 8444 8445 #define DSS_CTL2 _MMIO(0x67404) 8446 #define LEFT_BRANCH_VDSC_ENABLE (1 << 31) 8447 #define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) 8448 #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 8449 #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 8450 8451 #define _ICL_PIPE_DSS_CTL1_PB 0x78200 8452 #define _ICL_PIPE_DSS_CTL1_PC 0x78400 8453 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8454 _ICL_PIPE_DSS_CTL1_PB, \ 8455 _ICL_PIPE_DSS_CTL1_PC) 8456 #define BIG_JOINER_ENABLE (1 << 29) 8457 #define MASTER_BIG_JOINER_ENABLE (1 << 28) 8458 #define VGA_CENTERING_ENABLE (1 << 27) 8459 #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25) 8460 #define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0) 8461 #define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1) 8462 #define UNCOMPRESSED_JOINER_MASTER (1 << 21) 8463 #define UNCOMPRESSED_JOINER_SLAVE (1 << 20) 8464 8465 #define _ICL_PIPE_DSS_CTL2_PB 0x78204 8466 #define _ICL_PIPE_DSS_CTL2_PC 0x78404 8467 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8468 _ICL_PIPE_DSS_CTL2_PB, \ 8469 _ICL_PIPE_DSS_CTL2_PC) 8470 8471 #define GEN12_GSMBASE _MMIO(0x108100) 8472 #define GEN12_DSMBASE _MMIO(0x1080C0) 8473 8474 #define XEHP_CLOCK_GATE_DIS _MMIO(0x101014) 8475 #define SGSI_SIDECLK_DIS REG_BIT(17) 8476 #define SGGI_DIS REG_BIT(15) 8477 #define SGR_DIS REG_BIT(13) 8478 8479 #define XEHPSDV_TILE0_ADDR_RANGE _MMIO(0x4900) 8480 #define XEHPSDV_TILE_LMEM_RANGE_SHIFT 8 8481 8482 #define XEHPSDV_FLAT_CCS_BASE_ADDR _MMIO(0x4910) 8483 #define XEHPSDV_CCS_BASE_SHIFT 8 8484 8485 /* gamt regs */ 8486 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) 8487 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ 8488 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */ 8489 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */ 8490 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */ 8491 8492 #define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */ 8493 #define MMCD_PCLA (1 << 31) 8494 #define MMCD_HOTSPOT_EN (1 << 27) 8495 8496 #define _ICL_PHY_MISC_A 0x64C00 8497 #define _ICL_PHY_MISC_B 0x64C04 8498 #define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */ 8499 #define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B) 8500 #define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \ 8501 ICL_PHY_MISC(port)) 8502 #define ICL_PHY_MISC_MUX_DDID (1 << 28) 8503 #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23) 8504 #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20) 8505 8506 /* Icelake Display Stream Compression Registers */ 8507 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) 8508 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) 8509 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270 8510 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 8511 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 8512 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570 8513 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8514 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ 8515 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) 8516 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8517 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ 8518 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) 8519 #define DSC_VBR_ENABLE (1 << 19) 8520 #define DSC_422_ENABLE (1 << 18) 8521 #define DSC_COLOR_SPACE_CONVERSION (1 << 17) 8522 #define DSC_BLOCK_PREDICTION (1 << 16) 8523 #define DSC_LINE_BUF_DEPTH_SHIFT 12 8524 #define DSC_BPC_SHIFT 8 8525 #define DSC_VER_MIN_SHIFT 4 8526 #define DSC_VER_MAJ (0x1 << 0) 8527 8528 #define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204) 8529 #define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04) 8530 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274 8531 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374 8532 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474 8533 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574 8534 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8535 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \ 8536 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC) 8537 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8538 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \ 8539 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC) 8540 #define DSC_BPP(bpp) ((bpp) << 0) 8541 8542 #define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208) 8543 #define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08) 8544 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278 8545 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378 8546 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478 8547 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578 8548 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8549 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \ 8550 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC) 8551 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8552 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \ 8553 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC) 8554 #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16) 8555 #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0) 8556 8557 #define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C) 8558 #define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C) 8559 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C 8560 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C 8561 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C 8562 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C 8563 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8564 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \ 8565 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC) 8566 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8567 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \ 8568 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC) 8569 #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16) 8570 #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0) 8571 8572 #define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210) 8573 #define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10) 8574 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280 8575 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380 8576 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480 8577 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580 8578 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8579 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \ 8580 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC) 8581 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8582 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \ 8583 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC) 8584 #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16) 8585 #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0) 8586 8587 #define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214) 8588 #define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14) 8589 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284 8590 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384 8591 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484 8592 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584 8593 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8594 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \ 8595 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC) 8596 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8597 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \ 8598 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC) 8599 #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16) 8600 #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0) 8601 8602 #define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218) 8603 #define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18) 8604 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288 8605 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388 8606 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488 8607 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588 8608 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8609 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \ 8610 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC) 8611 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8612 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \ 8613 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC) 8614 #define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24) 8615 #define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16) 8616 #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8) 8617 #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0) 8618 8619 #define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C) 8620 #define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C) 8621 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C 8622 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C 8623 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C 8624 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C 8625 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8626 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \ 8627 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC) 8628 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8629 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \ 8630 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC) 8631 #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16) 8632 #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0) 8633 8634 #define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220) 8635 #define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20) 8636 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290 8637 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390 8638 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490 8639 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590 8640 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8641 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \ 8642 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC) 8643 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8644 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \ 8645 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC) 8646 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16) 8647 #define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0) 8648 8649 #define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224) 8650 #define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24) 8651 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294 8652 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394 8653 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494 8654 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594 8655 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8656 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \ 8657 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC) 8658 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8659 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \ 8660 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC) 8661 #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16) 8662 #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0) 8663 8664 #define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228) 8665 #define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28) 8666 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298 8667 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398 8668 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498 8669 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598 8670 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8671 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \ 8672 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC) 8673 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8674 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \ 8675 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC) 8676 #define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20) 8677 #define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16) 8678 #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8) 8679 #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0) 8680 8681 #define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C) 8682 #define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C) 8683 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C 8684 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C 8685 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C 8686 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C 8687 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8688 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \ 8689 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC) 8690 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8691 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \ 8692 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC) 8693 8694 #define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260) 8695 #define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60) 8696 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0 8697 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0 8698 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0 8699 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0 8700 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8701 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \ 8702 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC) 8703 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8704 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \ 8705 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC) 8706 8707 #define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264) 8708 #define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64) 8709 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4 8710 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4 8711 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4 8712 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4 8713 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8714 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \ 8715 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC) 8716 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8717 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \ 8718 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC) 8719 8720 #define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268) 8721 #define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68) 8722 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8 8723 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8 8724 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8 8725 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8 8726 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8727 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \ 8728 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC) 8729 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8730 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \ 8731 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC) 8732 8733 #define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C) 8734 #define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C) 8735 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC 8736 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC 8737 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC 8738 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC 8739 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8740 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \ 8741 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC) 8742 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8743 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \ 8744 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC) 8745 8746 #define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270) 8747 #define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70) 8748 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0 8749 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0 8750 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0 8751 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0 8752 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8753 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \ 8754 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC) 8755 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8756 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \ 8757 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC) 8758 #define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20) 8759 #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) 8760 #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0) 8761 8762 /* Icelake Rate Control Buffer Threshold Registers */ 8763 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) 8764 #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4) 8765 #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30) 8766 #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4) 8767 #define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254) 8768 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4) 8769 #define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354) 8770 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4) 8771 #define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454) 8772 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4) 8773 #define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554) 8774 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4) 8775 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8776 _ICL_DSC0_RC_BUF_THRESH_0_PB, \ 8777 _ICL_DSC0_RC_BUF_THRESH_0_PC) 8778 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8779 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \ 8780 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC) 8781 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8782 _ICL_DSC1_RC_BUF_THRESH_0_PB, \ 8783 _ICL_DSC1_RC_BUF_THRESH_0_PC) 8784 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8785 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \ 8786 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC) 8787 8788 #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238) 8789 #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4) 8790 #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38) 8791 #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4) 8792 #define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C) 8793 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4) 8794 #define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C) 8795 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4) 8796 #define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C) 8797 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4) 8798 #define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C) 8799 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4) 8800 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8801 _ICL_DSC0_RC_BUF_THRESH_1_PB, \ 8802 _ICL_DSC0_RC_BUF_THRESH_1_PC) 8803 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8804 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \ 8805 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC) 8806 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8807 _ICL_DSC1_RC_BUF_THRESH_1_PB, \ 8808 _ICL_DSC1_RC_BUF_THRESH_1_PC) 8809 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 8810 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \ 8811 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC) 8812 8813 #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0) 8814 #define MODULAR_FIA_MASK (1 << 4) 8815 #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6)) 8816 #define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5)) 8817 #define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8) 8818 #define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8)) 8819 #define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8)) 8820 8821 #define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890) 8822 #define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx)) 8823 8824 #define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894) 8825 #define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx)) 8826 8827 #define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880) 8828 #define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4) 8829 #define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4)) 8830 #define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4)) 8831 8832 #define _TCSS_DDI_STATUS_1 0x161500 8833 #define _TCSS_DDI_STATUS_2 0x161504 8834 #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \ 8835 _TCSS_DDI_STATUS_1, \ 8836 _TCSS_DDI_STATUS_2)) 8837 #define TCSS_DDI_STATUS_READY REG_BIT(2) 8838 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1) 8839 #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0) 8840 8841 #define PRIMARY_SPI_TRIGGER _MMIO(0x102040) 8842 #define PRIMARY_SPI_ADDRESS _MMIO(0x102080) 8843 #define PRIMARY_SPI_REGIONID _MMIO(0x102084) 8844 #define SPI_STATIC_REGIONS _MMIO(0x102090) 8845 #define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0) 8846 #define OROM_OFFSET _MMIO(0x1020c0) 8847 #define OROM_OFFSET_MASK REG_GENMASK(20, 16) 8848 8849 /* This register controls the Display State Buffer (DSB) engines. */ 8850 #define _DSBSL_INSTANCE_BASE 0x70B00 8851 #define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \ 8852 (pipe) * 0x1000 + (id) * 0x100) 8853 #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0) 8854 #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4) 8855 #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8) 8856 #define DSB_ENABLE (1 << 31) 8857 #define DSB_STATUS (1 << 0) 8858 8859 #define CLKREQ_POLICY _MMIO(0x101038) 8860 #define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1) 8861 8862 #define CLKGATE_DIS_MISC _MMIO(0x46534) 8863 #define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21) 8864 8865 #define GEN12_CULLBIT1 _MMIO(0x6100) 8866 #define GEN12_CULLBIT2 _MMIO(0x7030) 8867 #define GEN12_STATE_ACK_DEBUG _MMIO(0x20BC) 8868 8869 #endif /* _I915_REG_H_ */ 8870