1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 *
27 * Contributors:
28 * Niu Bing <bing.niu@intel.com>
29 * Zhi Wang <zhi.a.wang@intel.com>
30 *
31 */
32
33 #ifndef _GVT_H_
34 #define _GVT_H_
35
36 #include <uapi/linux/pci_regs.h>
37 #include <linux/kvm_host.h>
38 #include <linux/vfio.h>
39
40 #include "i915_drv.h"
41 #include "intel_gvt.h"
42
43 #include "debug.h"
44 #include "mmio.h"
45 #include "reg.h"
46 #include "interrupt.h"
47 #include "gtt.h"
48 #include "display.h"
49 #include "edid.h"
50 #include "execlist.h"
51 #include "scheduler.h"
52 #include "sched_policy.h"
53 #include "mmio_context.h"
54 #include "cmd_parser.h"
55 #include "fb_decoder.h"
56 #include "dmabuf.h"
57 #include "page_track.h"
58
59 #define GVT_MAX_VGPU 8
60
61 /* Describe per-platform limitations. */
62 struct intel_gvt_device_info {
63 u32 max_support_vgpus;
64 u32 cfg_space_size;
65 u32 mmio_size;
66 u32 mmio_bar;
67 unsigned long msi_cap_offset;
68 u32 gtt_start_offset;
69 u32 gtt_entry_size;
70 u32 gtt_entry_size_shift;
71 int gmadr_bytes_in_cmd;
72 u32 max_surface_size;
73 };
74
75 /* GM resources owned by a vGPU */
76 struct intel_vgpu_gm {
77 u64 aperture_sz;
78 u64 hidden_sz;
79 struct drm_mm_node low_gm_node;
80 struct drm_mm_node high_gm_node;
81 };
82
83 #define INTEL_GVT_MAX_NUM_FENCES 32
84
85 /* Fences owned by a vGPU */
86 struct intel_vgpu_fence {
87 struct i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES];
88 u32 base;
89 u32 size;
90 };
91
92 struct intel_vgpu_mmio {
93 void *vreg;
94 };
95
96 #define INTEL_GVT_MAX_BAR_NUM 4
97
98 struct intel_vgpu_pci_bar {
99 u64 size;
100 bool tracked;
101 };
102
103 struct intel_vgpu_cfg_space {
104 unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE];
105 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];
106 u32 pmcsr_off;
107 };
108
109 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
110
111 struct intel_vgpu_irq {
112 bool irq_warn_once[INTEL_GVT_EVENT_MAX];
113 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],
114 INTEL_GVT_EVENT_MAX);
115 };
116
117 struct intel_vgpu_opregion {
118 bool mapped;
119 void *va;
120 u32 gfn[INTEL_GVT_OPREGION_PAGES];
121 };
122
123 #define vgpu_opregion(vgpu) (&(vgpu->opregion))
124
125 struct intel_vgpu_display {
126 struct intel_vgpu_i2c_edid i2c_edid;
127 struct intel_vgpu_port ports[I915_MAX_PORTS];
128 struct intel_vgpu_sbi sbi;
129 enum port port_num;
130 };
131
132 struct vgpu_sched_ctl {
133 int weight;
134 };
135
136 enum {
137 INTEL_VGPU_EXECLIST_SUBMISSION = 1,
138 INTEL_VGPU_GUC_SUBMISSION,
139 };
140
141 struct intel_vgpu_submission_ops {
142 const char *name;
143 int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
144 void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
145 void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
146 };
147
148 struct intel_vgpu_submission {
149 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
150 struct list_head workload_q_head[I915_NUM_ENGINES];
151 struct intel_context *shadow[I915_NUM_ENGINES];
152 struct kmem_cache *workloads;
153 atomic_t running_workload_num;
154 union {
155 u64 i915_context_pml4;
156 u64 i915_context_pdps[GEN8_3LVL_PDPES];
157 };
158 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
159 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
160 void *ring_scan_buffer[I915_NUM_ENGINES];
161 int ring_scan_buffer_size[I915_NUM_ENGINES];
162 const struct intel_vgpu_submission_ops *ops;
163 int virtual_submission_interface;
164 bool active;
165 struct {
166 u32 lrca;
167 bool valid;
168 u64 ring_context_gpa;
169 } last_ctx[I915_NUM_ENGINES];
170 };
171
172 #define KVMGT_DEBUGFS_FILENAME "kvmgt_nr_cache_entries"
173
174 struct intel_vgpu {
175 struct intel_gvt *gvt;
176 struct mutex vgpu_lock;
177 int id;
178 bool active;
179 bool attached;
180 bool pv_notified;
181 bool failsafe;
182 unsigned int resetting_eng;
183
184 /* Both sched_data and sched_ctl can be seen a part of the global gvt
185 * scheduler structure. So below 2 vgpu data are protected
186 * by sched_lock, not vgpu_lock.
187 */
188 void *sched_data;
189 struct vgpu_sched_ctl sched_ctl;
190
191 struct intel_vgpu_fence fence;
192 struct intel_vgpu_gm gm;
193 struct intel_vgpu_cfg_space cfg_space;
194 struct intel_vgpu_mmio mmio;
195 struct intel_vgpu_irq irq;
196 struct intel_vgpu_gtt gtt;
197 struct intel_vgpu_opregion opregion;
198 struct intel_vgpu_display display;
199 struct intel_vgpu_submission submission;
200 struct radix_tree_root page_track_tree;
201 u32 hws_pga[I915_NUM_ENGINES];
202 /* Set on PCI_D3, reset on DMLR, not reflecting the actual PM state */
203 bool d3_entered;
204
205 struct dentry *debugfs;
206
207 struct list_head dmabuf_obj_list_head;
208 struct mutex dmabuf_lock;
209 struct idr object_idr;
210 struct intel_vgpu_vblank_timer vblank_timer;
211
212 u32 scan_nonprivbb;
213
214 struct vfio_device vfio_device;
215 struct vfio_region *region;
216 int num_regions;
217 struct eventfd_ctx *intx_trigger;
218 struct eventfd_ctx *msi_trigger;
219
220 /*
221 * Two caches are used to avoid mapping duplicated pages (eg.
222 * scratch pages). This help to reduce dma setup overhead.
223 */
224 struct rb_root gfn_cache;
225 struct rb_root dma_addr_cache;
226 unsigned long nr_cache_entries;
227 struct mutex cache_lock;
228
229 struct notifier_block iommu_notifier;
230 atomic_t released;
231
232 struct kvm_page_track_notifier_node track_node;
233 #define NR_BKT (1 << 18)
234 struct hlist_head ptable[NR_BKT];
235 #undef NR_BKT
236 };
237
238 /* validating GM healthy status*/
239 #define vgpu_is_vm_unhealthy(ret_val) \
240 (((ret_val) == -EBADRQC) || ((ret_val) == -EFAULT))
241
242 struct intel_gvt_gm {
243 unsigned long vgpu_allocated_low_gm_size;
244 unsigned long vgpu_allocated_high_gm_size;
245 };
246
247 struct intel_gvt_fence {
248 unsigned long vgpu_allocated_fence_num;
249 };
250
251 /* Special MMIO blocks. */
252 struct gvt_mmio_block {
253 unsigned int device;
254 i915_reg_t offset;
255 unsigned int size;
256 gvt_mmio_func read;
257 gvt_mmio_func write;
258 };
259
260 #define INTEL_GVT_MMIO_HASH_BITS 11
261
262 struct intel_gvt_mmio {
263 u16 *mmio_attribute;
264 /* Register contains RO bits */
265 #define F_RO (1 << 0)
266 /* Register contains graphics address */
267 #define F_GMADR (1 << 1)
268 /* Mode mask registers with high 16 bits as the mask bits */
269 #define F_MODE_MASK (1 << 2)
270 /* This reg can be accessed by GPU commands */
271 #define F_CMD_ACCESS (1 << 3)
272 /* This reg has been accessed by a VM */
273 #define F_ACCESSED (1 << 4)
274 /* This reg requires save & restore during host PM suspend/resume */
275 #define F_PM_SAVE (1 << 5)
276 /* This reg could be accessed by unaligned address */
277 #define F_UNALIGN (1 << 6)
278 /* This reg is in GVT's mmio save-restor list and in hardware
279 * logical context image
280 */
281 #define F_SR_IN_CTX (1 << 7)
282 /* Value of command write of this reg needs to be patched */
283 #define F_CMD_WRITE_PATCH (1 << 8)
284
285 struct gvt_mmio_block *mmio_block;
286 unsigned int num_mmio_block;
287
288 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
289 unsigned long num_tracked_mmio;
290 };
291
292 struct intel_gvt_firmware {
293 void *cfg_space;
294 void *mmio;
295 bool firmware_loaded;
296 };
297
298 #define NR_MAX_INTEL_VGPU_TYPES 20
299 struct intel_vgpu_type {
300 char name[16];
301 unsigned int avail_instance;
302 unsigned int low_gm_size;
303 unsigned int high_gm_size;
304 unsigned int fence;
305 unsigned int weight;
306 enum intel_vgpu_edid resolution;
307 };
308
309 struct intel_gvt {
310 /* GVT scope lock, protect GVT itself, and all resource currently
311 * not yet protected by special locks(vgpu and scheduler lock).
312 */
313 struct mutex lock;
314 /* scheduler scope lock, protect gvt and vgpu schedule related data */
315 struct mutex sched_lock;
316
317 struct intel_gt *gt;
318 struct idr vgpu_idr; /* vGPU IDR pool */
319
320 struct intel_gvt_device_info device_info;
321 struct intel_gvt_gm gm;
322 struct intel_gvt_fence fence;
323 struct intel_gvt_mmio mmio;
324 struct intel_gvt_firmware firmware;
325 struct intel_gvt_irq irq;
326 struct intel_gvt_gtt gtt;
327 struct intel_gvt_workload_scheduler scheduler;
328 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES];
329 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS);
330 struct intel_vgpu_type *types;
331 unsigned int num_types;
332 struct intel_vgpu *idle_vgpu;
333
334 struct task_struct *service_thread;
335 wait_queue_head_t service_thread_wq;
336
337 /* service_request is always used in bit operation, we should always
338 * use it with atomic bit ops so that no need to use gvt big lock.
339 */
340 unsigned long service_request;
341
342 struct {
343 struct engine_mmio *mmio;
344 int ctx_mmio_count[I915_NUM_ENGINES];
345 u32 *tlb_mmio_offset_list;
346 u32 tlb_mmio_offset_list_cnt;
347 u32 *mocs_mmio_offset_list;
348 u32 mocs_mmio_offset_list_cnt;
349 } engine_mmio_list;
350 bool is_reg_whitelist_updated;
351
352 struct dentry *debugfs_root;
353 };
354
to_gvt(struct drm_i915_private * i915)355 static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915)
356 {
357 return i915->gvt;
358 }
359
360 enum {
361 /* Scheduling trigger by timer */
362 INTEL_GVT_REQUEST_SCHED = 0,
363
364 /* Scheduling trigger by event */
365 INTEL_GVT_REQUEST_EVENT_SCHED = 1,
366
367 /* per-vGPU vblank emulation request */
368 INTEL_GVT_REQUEST_EMULATE_VBLANK = 2,
369 INTEL_GVT_REQUEST_EMULATE_VBLANK_MAX = INTEL_GVT_REQUEST_EMULATE_VBLANK
370 + GVT_MAX_VGPU,
371 };
372
intel_gvt_request_service(struct intel_gvt * gvt,int service)373 static inline void intel_gvt_request_service(struct intel_gvt *gvt,
374 int service)
375 {
376 set_bit(service, (void *)&gvt->service_request);
377 wake_up(&gvt->service_thread_wq);
378 }
379
380 void intel_gvt_free_firmware(struct intel_gvt *gvt);
381 int intel_gvt_load_firmware(struct intel_gvt *gvt);
382
383 /* Aperture/GM space definitions for GVT device */
384 #define MB_TO_BYTES(mb) ((mb) << 20ULL)
385 #define BYTES_TO_MB(b) ((b) >> 20ULL)
386
387 #define HOST_LOW_GM_SIZE MB_TO_BYTES(128)
388 #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384)
389 #define HOST_FENCE 4
390
391 #define gvt_to_ggtt(gvt) ((gvt)->gt->ggtt)
392
393 /* Aperture/GM space definitions for GVT device */
394 #define gvt_aperture_sz(gvt) gvt_to_ggtt(gvt)->mappable_end
395 #define gvt_aperture_pa_base(gvt) gvt_to_ggtt(gvt)->gmadr.start
396
397 #define gvt_ggtt_gm_sz(gvt) gvt_to_ggtt(gvt)->vm.total
398 #define gvt_ggtt_sz(gvt) (gvt_to_ggtt(gvt)->vm.total >> PAGE_SHIFT << 3)
399 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))
400
401 #define gvt_aperture_gmadr_base(gvt) (0)
402 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \
403 + gvt_aperture_sz(gvt) - 1)
404
405 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \
406 + gvt_aperture_sz(gvt))
407 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \
408 + gvt_hidden_sz(gvt) - 1)
409
410 #define gvt_fence_sz(gvt) (gvt_to_ggtt(gvt)->num_fences)
411
412 /* Aperture/GM space definitions for vGPU */
413 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start)
414 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start)
415 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz)
416 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz)
417
418 #define vgpu_aperture_pa_base(vgpu) \
419 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))
420
421 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz)
422
423 #define vgpu_aperture_pa_end(vgpu) \
424 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
425
426 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu))
427 #define vgpu_aperture_gmadr_end(vgpu) \
428 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
429
430 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu))
431 #define vgpu_hidden_gmadr_end(vgpu) \
432 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
433
434 #define vgpu_fence_base(vgpu) (vgpu->fence.base)
435 #define vgpu_fence_sz(vgpu) (vgpu->fence.size)
436
437 /* ring context size i.e. the first 0x50 dwords*/
438 #define RING_CTX_SIZE 320
439
440 struct intel_vgpu_creation_params {
441 __u64 low_gm_sz; /* in MB */
442 __u64 high_gm_sz; /* in MB */
443 __u64 fence_sz;
444 __u64 resolution;
445 __s32 primary;
446 __u64 vgpu_id;
447
448 __u32 weight;
449 };
450
451 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
452 struct intel_vgpu_creation_params *param);
453 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu);
454 void intel_vgpu_free_resource(struct intel_vgpu *vgpu);
455 void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
456 u32 fence, u64 value);
457
458 /* Macros for easily accessing vGPU virtual/shadow register.
459 Explicitly seperate use for typed MMIO reg or real offset.*/
460 #define vgpu_vreg_t(vgpu, reg) \
461 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
462 #define vgpu_vreg(vgpu, offset) \
463 (*(u32 *)(vgpu->mmio.vreg + (offset)))
464 #define vgpu_vreg64_t(vgpu, reg) \
465 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
466 #define vgpu_vreg64(vgpu, offset) \
467 (*(u64 *)(vgpu->mmio.vreg + (offset)))
468
469 #define for_each_active_vgpu(gvt, vgpu, id) \
470 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
471 for_each_if(vgpu->active)
472
intel_vgpu_write_pci_bar(struct intel_vgpu * vgpu,u32 offset,u32 val,bool low)473 static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,
474 u32 offset, u32 val, bool low)
475 {
476 u32 *pval;
477
478 /* BAR offset should be 32 bits algiend */
479 offset = rounddown(offset, 4);
480 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);
481
482 if (low) {
483 /*
484 * only update bit 31 - bit 4,
485 * leave the bit 3 - bit 0 unchanged.
486 */
487 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));
488 } else {
489 *pval = val;
490 }
491 }
492
493 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt);
494 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt);
495
496 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt);
497 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu);
498 struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
499 struct intel_vgpu_type *type);
500 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu);
501 void intel_gvt_release_vgpu(struct intel_vgpu *vgpu);
502 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
503 intel_engine_mask_t engine_mask);
504 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu);
505 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu);
506 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu);
507
508 int intel_gvt_set_opregion(struct intel_vgpu *vgpu);
509 int intel_gvt_set_edid(struct intel_vgpu *vgpu, int port_num);
510
511 /* validating GM functions */
512 #define vgpu_gmadr_is_aperture(vgpu, gmadr) \
513 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \
514 (gmadr <= vgpu_aperture_gmadr_end(vgpu)))
515
516 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \
517 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \
518 (gmadr <= vgpu_hidden_gmadr_end(vgpu)))
519
520 #define vgpu_gmadr_is_valid(vgpu, gmadr) \
521 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \
522 (vgpu_gmadr_is_hidden(vgpu, gmadr))))
523
524 #define gvt_gmadr_is_aperture(gvt, gmadr) \
525 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \
526 (gmadr <= gvt_aperture_gmadr_end(gvt)))
527
528 #define gvt_gmadr_is_hidden(gvt, gmadr) \
529 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \
530 (gmadr <= gvt_hidden_gmadr_end(gvt)))
531
532 #define gvt_gmadr_is_valid(gvt, gmadr) \
533 (gvt_gmadr_is_aperture(gvt, gmadr) || \
534 gvt_gmadr_is_hidden(gvt, gmadr))
535
536 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);
537 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr);
538 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr);
539 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
540 unsigned long *h_index);
541 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
542 unsigned long *g_index);
543
544 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
545 bool primary);
546 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu);
547
548 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
549 void *p_data, unsigned int bytes);
550
551 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
552 void *p_data, unsigned int bytes);
553
554 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected);
555
intel_vgpu_get_bar_gpa(struct intel_vgpu * vgpu,int bar)556 static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar)
557 {
558 /* We are 64bit bar. */
559 return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &
560 PCI_BASE_ADDRESS_MEM_MASK;
561 }
562
563 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu);
564 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu);
565 int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa);
566
567 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci);
568 void populate_pvinfo_page(struct intel_vgpu *vgpu);
569
570 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload);
571 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason);
572 void intel_vgpu_detach_regions(struct intel_vgpu *vgpu);
573
574 enum {
575 GVT_FAILSAFE_UNSUPPORTED_GUEST,
576 GVT_FAILSAFE_INSUFFICIENT_RESOURCE,
577 GVT_FAILSAFE_GUEST_ERR,
578 };
579
mmio_hw_access_pre(struct intel_gt * gt)580 static inline void mmio_hw_access_pre(struct intel_gt *gt)
581 {
582 intel_runtime_pm_get(gt->uncore->rpm);
583 }
584
mmio_hw_access_post(struct intel_gt * gt)585 static inline void mmio_hw_access_post(struct intel_gt *gt)
586 {
587 intel_runtime_pm_put_unchecked(gt->uncore->rpm);
588 }
589
590 /**
591 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed
592 * @gvt: a GVT device
593 * @offset: register offset
594 *
595 */
intel_gvt_mmio_set_accessed(struct intel_gvt * gvt,unsigned int offset)596 static inline void intel_gvt_mmio_set_accessed(
597 struct intel_gvt *gvt, unsigned int offset)
598 {
599 gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED;
600 }
601
602 /**
603 * intel_gvt_mmio_is_cmd_accessible - if a MMIO could be accessed by command
604 * @gvt: a GVT device
605 * @offset: register offset
606 *
607 * Returns:
608 * True if an MMIO is able to be accessed by GPU commands
609 */
intel_gvt_mmio_is_cmd_accessible(struct intel_gvt * gvt,unsigned int offset)610 static inline bool intel_gvt_mmio_is_cmd_accessible(
611 struct intel_gvt *gvt, unsigned int offset)
612 {
613 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS;
614 }
615
616 /**
617 * intel_gvt_mmio_set_cmd_accessible -
618 * mark a MMIO could be accessible by command
619 * @gvt: a GVT device
620 * @offset: register offset
621 *
622 */
intel_gvt_mmio_set_cmd_accessible(struct intel_gvt * gvt,unsigned int offset)623 static inline void intel_gvt_mmio_set_cmd_accessible(
624 struct intel_gvt *gvt, unsigned int offset)
625 {
626 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESS;
627 }
628
629 /**
630 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned
631 * @gvt: a GVT device
632 * @offset: register offset
633 *
634 */
intel_gvt_mmio_is_unalign(struct intel_gvt * gvt,unsigned int offset)635 static inline bool intel_gvt_mmio_is_unalign(
636 struct intel_gvt *gvt, unsigned int offset)
637 {
638 return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN;
639 }
640
641 /**
642 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask
643 * @gvt: a GVT device
644 * @offset: register offset
645 *
646 * Returns:
647 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't.
648 *
649 */
intel_gvt_mmio_has_mode_mask(struct intel_gvt * gvt,unsigned int offset)650 static inline bool intel_gvt_mmio_has_mode_mask(
651 struct intel_gvt *gvt, unsigned int offset)
652 {
653 return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK;
654 }
655
656 /**
657 * intel_gvt_mmio_is_sr_in_ctx -
658 * check if an MMIO has F_SR_IN_CTX mask
659 * @gvt: a GVT device
660 * @offset: register offset
661 *
662 * Returns:
663 * True if an MMIO has an F_SR_IN_CTX mask, false if it isn't.
664 *
665 */
intel_gvt_mmio_is_sr_in_ctx(struct intel_gvt * gvt,unsigned int offset)666 static inline bool intel_gvt_mmio_is_sr_in_ctx(
667 struct intel_gvt *gvt, unsigned int offset)
668 {
669 return gvt->mmio.mmio_attribute[offset >> 2] & F_SR_IN_CTX;
670 }
671
672 /**
673 * intel_gvt_mmio_set_sr_in_ctx -
674 * mask an MMIO in GVT's mmio save-restore list and also
675 * in hardware logical context image
676 * @gvt: a GVT device
677 * @offset: register offset
678 *
679 */
intel_gvt_mmio_set_sr_in_ctx(struct intel_gvt * gvt,unsigned int offset)680 static inline void intel_gvt_mmio_set_sr_in_ctx(
681 struct intel_gvt *gvt, unsigned int offset)
682 {
683 gvt->mmio.mmio_attribute[offset >> 2] |= F_SR_IN_CTX;
684 }
685
686 void intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu);
687 /**
688 * intel_gvt_mmio_set_cmd_write_patch -
689 * mark an MMIO if its cmd write needs to be
690 * patched
691 * @gvt: a GVT device
692 * @offset: register offset
693 *
694 */
intel_gvt_mmio_set_cmd_write_patch(struct intel_gvt * gvt,unsigned int offset)695 static inline void intel_gvt_mmio_set_cmd_write_patch(
696 struct intel_gvt *gvt, unsigned int offset)
697 {
698 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_WRITE_PATCH;
699 }
700
701 /**
702 * intel_gvt_mmio_is_cmd_write_patch - check if an mmio's cmd access needs to
703 * be patched
704 * @gvt: a GVT device
705 * @offset: register offset
706 *
707 * Returns:
708 * True if GPU commmand write to an MMIO should be patched
709 */
intel_gvt_mmio_is_cmd_write_patch(struct intel_gvt * gvt,unsigned int offset)710 static inline bool intel_gvt_mmio_is_cmd_write_patch(
711 struct intel_gvt *gvt, unsigned int offset)
712 {
713 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_WRITE_PATCH;
714 }
715
716 /**
717 * intel_gvt_read_gpa - copy data from GPA to host data buffer
718 * @vgpu: a vGPU
719 * @gpa: guest physical address
720 * @buf: host data buffer
721 * @len: data length
722 *
723 * Returns:
724 * Zero on success, negative error code if failed.
725 */
intel_gvt_read_gpa(struct intel_vgpu * vgpu,unsigned long gpa,void * buf,unsigned long len)726 static inline int intel_gvt_read_gpa(struct intel_vgpu *vgpu, unsigned long gpa,
727 void *buf, unsigned long len)
728 {
729 if (!vgpu->attached)
730 return -ESRCH;
731 return vfio_dma_rw(&vgpu->vfio_device, gpa, buf, len, false);
732 }
733
734 /**
735 * intel_gvt_write_gpa - copy data from host data buffer to GPA
736 * @vgpu: a vGPU
737 * @gpa: guest physical address
738 * @buf: host data buffer
739 * @len: data length
740 *
741 * Returns:
742 * Zero on success, negative error code if failed.
743 */
intel_gvt_write_gpa(struct intel_vgpu * vgpu,unsigned long gpa,void * buf,unsigned long len)744 static inline int intel_gvt_write_gpa(struct intel_vgpu *vgpu,
745 unsigned long gpa, void *buf, unsigned long len)
746 {
747 if (!vgpu->attached)
748 return -ESRCH;
749 return vfio_dma_rw(&vgpu->vfio_device, gpa, buf, len, true);
750 }
751
752 void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu);
753 void intel_gvt_debugfs_init(struct intel_gvt *gvt);
754 void intel_gvt_debugfs_clean(struct intel_gvt *gvt);
755
756 int intel_gvt_page_track_add(struct intel_vgpu *info, u64 gfn);
757 int intel_gvt_page_track_remove(struct intel_vgpu *info, u64 gfn);
758 int intel_gvt_dma_pin_guest_page(struct intel_vgpu *vgpu, dma_addr_t dma_addr);
759 int intel_gvt_dma_map_guest_page(struct intel_vgpu *vgpu, unsigned long gfn,
760 unsigned long size, dma_addr_t *dma_addr);
761 void intel_gvt_dma_unmap_guest_page(struct intel_vgpu *vgpu,
762 dma_addr_t dma_addr);
763
764 #include "trace.h"
765
766 #endif
767