1 /*
2 * arch/arm/mach-spear13xx/spear1310_clock.c
3 *
4 * SPEAr1310 machine clock framework source file
5 *
6 * Copyright (C) 2012 ST Microelectronics
7 * Viresh Kumar <vireshk@kernel.org>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14 #include <linux/clkdev.h>
15 #include <linux/clk/spear.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/of_platform.h>
19 #include <linux/spinlock_types.h>
20 #include "clk.h"
21
22 /* PLL related registers and bit values */
23 #define SPEAR1310_PLL_CFG (misc_base + 0x210)
24 /* PLL_CFG bit values */
25 #define SPEAR1310_CLCD_SYNT_CLK_MASK 1
26 #define SPEAR1310_CLCD_SYNT_CLK_SHIFT 31
27 #define SPEAR1310_RAS_SYNT2_3_CLK_MASK 2
28 #define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT 29
29 #define SPEAR1310_RAS_SYNT_CLK_MASK 2
30 #define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT 27
31 #define SPEAR1310_PLL_CLK_MASK 2
32 #define SPEAR1310_PLL3_CLK_SHIFT 24
33 #define SPEAR1310_PLL2_CLK_SHIFT 22
34 #define SPEAR1310_PLL1_CLK_SHIFT 20
35
36 #define SPEAR1310_PLL1_CTR (misc_base + 0x214)
37 #define SPEAR1310_PLL1_FRQ (misc_base + 0x218)
38 #define SPEAR1310_PLL2_CTR (misc_base + 0x220)
39 #define SPEAR1310_PLL2_FRQ (misc_base + 0x224)
40 #define SPEAR1310_PLL3_CTR (misc_base + 0x22C)
41 #define SPEAR1310_PLL3_FRQ (misc_base + 0x230)
42 #define SPEAR1310_PLL4_CTR (misc_base + 0x238)
43 #define SPEAR1310_PLL4_FRQ (misc_base + 0x23C)
44 #define SPEAR1310_PERIP_CLK_CFG (misc_base + 0x244)
45 /* PERIP_CLK_CFG bit values */
46 #define SPEAR1310_GPT_OSC24_VAL 0
47 #define SPEAR1310_GPT_APB_VAL 1
48 #define SPEAR1310_GPT_CLK_MASK 1
49 #define SPEAR1310_GPT3_CLK_SHIFT 11
50 #define SPEAR1310_GPT2_CLK_SHIFT 10
51 #define SPEAR1310_GPT1_CLK_SHIFT 9
52 #define SPEAR1310_GPT0_CLK_SHIFT 8
53 #define SPEAR1310_UART_CLK_PLL5_VAL 0
54 #define SPEAR1310_UART_CLK_OSC24_VAL 1
55 #define SPEAR1310_UART_CLK_SYNT_VAL 2
56 #define SPEAR1310_UART_CLK_MASK 2
57 #define SPEAR1310_UART_CLK_SHIFT 4
58
59 #define SPEAR1310_AUX_CLK_PLL5_VAL 0
60 #define SPEAR1310_AUX_CLK_SYNT_VAL 1
61 #define SPEAR1310_CLCD_CLK_MASK 2
62 #define SPEAR1310_CLCD_CLK_SHIFT 2
63 #define SPEAR1310_C3_CLK_MASK 1
64 #define SPEAR1310_C3_CLK_SHIFT 1
65
66 #define SPEAR1310_GMAC_CLK_CFG (misc_base + 0x248)
67 #define SPEAR1310_GMAC_PHY_IF_SEL_MASK 3
68 #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT 4
69 #define SPEAR1310_GMAC_PHY_CLK_MASK 1
70 #define SPEAR1310_GMAC_PHY_CLK_SHIFT 3
71 #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2
72 #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1
73
74 #define SPEAR1310_I2S_CLK_CFG (misc_base + 0x24C)
75 /* I2S_CLK_CFG register mask */
76 #define SPEAR1310_I2S_SCLK_X_MASK 0x1F
77 #define SPEAR1310_I2S_SCLK_X_SHIFT 27
78 #define SPEAR1310_I2S_SCLK_Y_MASK 0x1F
79 #define SPEAR1310_I2S_SCLK_Y_SHIFT 22
80 #define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT 21
81 #define SPEAR1310_I2S_SCLK_SYNTH_ENB 20
82 #define SPEAR1310_I2S_PRS1_CLK_X_MASK 0xFF
83 #define SPEAR1310_I2S_PRS1_CLK_X_SHIFT 12
84 #define SPEAR1310_I2S_PRS1_CLK_Y_MASK 0xFF
85 #define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT 4
86 #define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT 3
87 #define SPEAR1310_I2S_REF_SEL_MASK 1
88 #define SPEAR1310_I2S_REF_SHIFT 2
89 #define SPEAR1310_I2S_SRC_CLK_MASK 2
90 #define SPEAR1310_I2S_SRC_CLK_SHIFT 0
91
92 #define SPEAR1310_C3_CLK_SYNT (misc_base + 0x250)
93 #define SPEAR1310_UART_CLK_SYNT (misc_base + 0x254)
94 #define SPEAR1310_GMAC_CLK_SYNT (misc_base + 0x258)
95 #define SPEAR1310_SDHCI_CLK_SYNT (misc_base + 0x25C)
96 #define SPEAR1310_CFXD_CLK_SYNT (misc_base + 0x260)
97 #define SPEAR1310_ADC_CLK_SYNT (misc_base + 0x264)
98 #define SPEAR1310_AMBA_CLK_SYNT (misc_base + 0x268)
99 #define SPEAR1310_CLCD_CLK_SYNT (misc_base + 0x270)
100 #define SPEAR1310_RAS_CLK_SYNT0 (misc_base + 0x280)
101 #define SPEAR1310_RAS_CLK_SYNT1 (misc_base + 0x288)
102 #define SPEAR1310_RAS_CLK_SYNT2 (misc_base + 0x290)
103 #define SPEAR1310_RAS_CLK_SYNT3 (misc_base + 0x298)
104 /* Check Fractional synthesizer reg masks */
105
106 #define SPEAR1310_PERIP1_CLK_ENB (misc_base + 0x300)
107 /* PERIP1_CLK_ENB register masks */
108 #define SPEAR1310_RTC_CLK_ENB 31
109 #define SPEAR1310_ADC_CLK_ENB 30
110 #define SPEAR1310_C3_CLK_ENB 29
111 #define SPEAR1310_JPEG_CLK_ENB 28
112 #define SPEAR1310_CLCD_CLK_ENB 27
113 #define SPEAR1310_DMA_CLK_ENB 25
114 #define SPEAR1310_GPIO1_CLK_ENB 24
115 #define SPEAR1310_GPIO0_CLK_ENB 23
116 #define SPEAR1310_GPT1_CLK_ENB 22
117 #define SPEAR1310_GPT0_CLK_ENB 21
118 #define SPEAR1310_I2S0_CLK_ENB 20
119 #define SPEAR1310_I2S1_CLK_ENB 19
120 #define SPEAR1310_I2C0_CLK_ENB 18
121 #define SPEAR1310_SSP_CLK_ENB 17
122 #define SPEAR1310_UART_CLK_ENB 15
123 #define SPEAR1310_PCIE_SATA_2_CLK_ENB 14
124 #define SPEAR1310_PCIE_SATA_1_CLK_ENB 13
125 #define SPEAR1310_PCIE_SATA_0_CLK_ENB 12
126 #define SPEAR1310_UOC_CLK_ENB 11
127 #define SPEAR1310_UHC1_CLK_ENB 10
128 #define SPEAR1310_UHC0_CLK_ENB 9
129 #define SPEAR1310_GMAC_CLK_ENB 8
130 #define SPEAR1310_CFXD_CLK_ENB 7
131 #define SPEAR1310_SDHCI_CLK_ENB 6
132 #define SPEAR1310_SMI_CLK_ENB 5
133 #define SPEAR1310_FSMC_CLK_ENB 4
134 #define SPEAR1310_SYSRAM0_CLK_ENB 3
135 #define SPEAR1310_SYSRAM1_CLK_ENB 2
136 #define SPEAR1310_SYSROM_CLK_ENB 1
137 #define SPEAR1310_BUS_CLK_ENB 0
138
139 #define SPEAR1310_PERIP2_CLK_ENB (misc_base + 0x304)
140 /* PERIP2_CLK_ENB register masks */
141 #define SPEAR1310_THSENS_CLK_ENB 8
142 #define SPEAR1310_I2S_REF_PAD_CLK_ENB 7
143 #define SPEAR1310_ACP_CLK_ENB 6
144 #define SPEAR1310_GPT3_CLK_ENB 5
145 #define SPEAR1310_GPT2_CLK_ENB 4
146 #define SPEAR1310_KBD_CLK_ENB 3
147 #define SPEAR1310_CPU_DBG_CLK_ENB 2
148 #define SPEAR1310_DDR_CORE_CLK_ENB 1
149 #define SPEAR1310_DDR_CTRL_CLK_ENB 0
150
151 #define SPEAR1310_RAS_CLK_ENB (misc_base + 0x310)
152 /* RAS_CLK_ENB register masks */
153 #define SPEAR1310_SYNT3_CLK_ENB 17
154 #define SPEAR1310_SYNT2_CLK_ENB 16
155 #define SPEAR1310_SYNT1_CLK_ENB 15
156 #define SPEAR1310_SYNT0_CLK_ENB 14
157 #define SPEAR1310_PCLK3_CLK_ENB 13
158 #define SPEAR1310_PCLK2_CLK_ENB 12
159 #define SPEAR1310_PCLK1_CLK_ENB 11
160 #define SPEAR1310_PCLK0_CLK_ENB 10
161 #define SPEAR1310_PLL3_CLK_ENB 9
162 #define SPEAR1310_PLL2_CLK_ENB 8
163 #define SPEAR1310_C125M_PAD_CLK_ENB 7
164 #define SPEAR1310_C30M_CLK_ENB 6
165 #define SPEAR1310_C48M_CLK_ENB 5
166 #define SPEAR1310_OSC_25M_CLK_ENB 4
167 #define SPEAR1310_OSC_32K_CLK_ENB 3
168 #define SPEAR1310_OSC_24M_CLK_ENB 2
169 #define SPEAR1310_PCLK_CLK_ENB 1
170 #define SPEAR1310_ACLK_CLK_ENB 0
171
172 /* RAS Area Control Register */
173 #define SPEAR1310_RAS_CTRL_REG0 (ras_base + 0x000)
174 #define SPEAR1310_SSP1_CLK_MASK 3
175 #define SPEAR1310_SSP1_CLK_SHIFT 26
176 #define SPEAR1310_TDM_CLK_MASK 1
177 #define SPEAR1310_TDM2_CLK_SHIFT 24
178 #define SPEAR1310_TDM1_CLK_SHIFT 23
179 #define SPEAR1310_I2C_CLK_MASK 1
180 #define SPEAR1310_I2C7_CLK_SHIFT 22
181 #define SPEAR1310_I2C6_CLK_SHIFT 21
182 #define SPEAR1310_I2C5_CLK_SHIFT 20
183 #define SPEAR1310_I2C4_CLK_SHIFT 19
184 #define SPEAR1310_I2C3_CLK_SHIFT 18
185 #define SPEAR1310_I2C2_CLK_SHIFT 17
186 #define SPEAR1310_I2C1_CLK_SHIFT 16
187 #define SPEAR1310_GPT64_CLK_MASK 1
188 #define SPEAR1310_GPT64_CLK_SHIFT 15
189 #define SPEAR1310_RAS_UART_CLK_MASK 1
190 #define SPEAR1310_UART5_CLK_SHIFT 14
191 #define SPEAR1310_UART4_CLK_SHIFT 13
192 #define SPEAR1310_UART3_CLK_SHIFT 12
193 #define SPEAR1310_UART2_CLK_SHIFT 11
194 #define SPEAR1310_UART1_CLK_SHIFT 10
195 #define SPEAR1310_PCI_CLK_MASK 1
196 #define SPEAR1310_PCI_CLK_SHIFT 0
197
198 #define SPEAR1310_RAS_CTRL_REG1 (ras_base + 0x004)
199 #define SPEAR1310_PHY_CLK_MASK 0x3
200 #define SPEAR1310_RMII_PHY_CLK_SHIFT 0
201 #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT 2
202
203 #define SPEAR1310_RAS_SW_CLK_CTRL (ras_base + 0x0148)
204 #define SPEAR1310_CAN1_CLK_ENB 25
205 #define SPEAR1310_CAN0_CLK_ENB 24
206 #define SPEAR1310_GPT64_CLK_ENB 23
207 #define SPEAR1310_SSP1_CLK_ENB 22
208 #define SPEAR1310_I2C7_CLK_ENB 21
209 #define SPEAR1310_I2C6_CLK_ENB 20
210 #define SPEAR1310_I2C5_CLK_ENB 19
211 #define SPEAR1310_I2C4_CLK_ENB 18
212 #define SPEAR1310_I2C3_CLK_ENB 17
213 #define SPEAR1310_I2C2_CLK_ENB 16
214 #define SPEAR1310_I2C1_CLK_ENB 15
215 #define SPEAR1310_UART5_CLK_ENB 14
216 #define SPEAR1310_UART4_CLK_ENB 13
217 #define SPEAR1310_UART3_CLK_ENB 12
218 #define SPEAR1310_UART2_CLK_ENB 11
219 #define SPEAR1310_UART1_CLK_ENB 10
220 #define SPEAR1310_RS485_1_CLK_ENB 9
221 #define SPEAR1310_RS485_0_CLK_ENB 8
222 #define SPEAR1310_TDM2_CLK_ENB 7
223 #define SPEAR1310_TDM1_CLK_ENB 6
224 #define SPEAR1310_PCI_CLK_ENB 5
225 #define SPEAR1310_GMII_CLK_ENB 4
226 #define SPEAR1310_MII2_CLK_ENB 3
227 #define SPEAR1310_MII1_CLK_ENB 2
228 #define SPEAR1310_MII0_CLK_ENB 1
229 #define SPEAR1310_ESRAM_CLK_ENB 0
230
231 static DEFINE_SPINLOCK(_lock);
232
233 /* pll rate configuration table, in ascending order of rates */
234 static struct pll_rate_tbl pll_rtbl[] = {
235 /* PCLK 24MHz */
236 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
237 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
238 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
239 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
240 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
241 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
242 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
243 };
244
245 /* vco-pll4 rate configuration table, in ascending order of rates */
246 static struct pll_rate_tbl pll4_rtbl[] = {
247 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
248 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
249 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
250 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
251 };
252
253 /* aux rate configuration table, in ascending order of rates */
254 static struct aux_rate_tbl aux_rtbl[] = {
255 /* For VCO1div2 = 500 MHz */
256 {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
257 {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
258 {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
259 {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
260 {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
261 {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
262 };
263
264 /* gmac rate configuration table, in ascending order of rates */
265 static struct aux_rate_tbl gmac_rtbl[] = {
266 /* For gmac phy input clk */
267 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
268 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
269 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
270 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
271 };
272
273 /* clcd rate configuration table, in ascending order of rates */
274 static struct frac_rate_tbl clcd_rtbl[] = {
275 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
276 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
277 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
278 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
279 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
280 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
281 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
282 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
283 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
284 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
285 };
286
287 /* i2s prescaler1 masks */
288 static const struct aux_clk_masks i2s_prs1_masks = {
289 .eq_sel_mask = AUX_EQ_SEL_MASK,
290 .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT,
291 .eq1_mask = AUX_EQ1_SEL,
292 .eq2_mask = AUX_EQ2_SEL,
293 .xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK,
294 .xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT,
295 .yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK,
296 .yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT,
297 };
298
299 /* i2s sclk (bit clock) syynthesizers masks */
300 static struct aux_clk_masks i2s_sclk_masks = {
301 .eq_sel_mask = AUX_EQ_SEL_MASK,
302 .eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT,
303 .eq1_mask = AUX_EQ1_SEL,
304 .eq2_mask = AUX_EQ2_SEL,
305 .xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK,
306 .xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT,
307 .yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK,
308 .yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT,
309 .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB,
310 };
311
312 /* i2s prs1 aux rate configuration table, in ascending order of rates */
313 static struct aux_rate_tbl i2s_prs1_rtbl[] = {
314 /* For parent clk = 49.152 MHz */
315 {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
316 {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
317 {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
318 {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
319
320 /*
321 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
322 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
323 */
324 {.xscale = 1, .yscale = 3, .eq = 0},
325
326 /* For parent clk = 49.152 MHz */
327 {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
328
329 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
330 };
331
332 /* i2s sclk aux rate configuration table, in ascending order of rates */
333 static struct aux_rate_tbl i2s_sclk_rtbl[] = {
334 /* For i2s_ref_clk = 12.288MHz */
335 {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */
336 {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
337 };
338
339 /* adc rate configuration table, in ascending order of rates */
340 /* possible adc range is 2.5 MHz to 20 MHz. */
341 static struct aux_rate_tbl adc_rtbl[] = {
342 /* For ahb = 166.67 MHz */
343 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
344 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
345 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
346 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
347 };
348
349 /* General synth rate configuration table, in ascending order of rates */
350 static struct frac_rate_tbl gen_rtbl[] = {
351 /* For vco1div4 = 250 MHz */
352 {.div = 0x14000}, /* 25 MHz */
353 {.div = 0x0A000}, /* 50 MHz */
354 {.div = 0x05000}, /* 100 MHz */
355 {.div = 0x02000}, /* 250 MHz */
356 };
357
358 /* clock parents */
359 static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
360 static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
361 static const char *uart0_parents[] = { "pll5_clk", "uart_syn_gclk", };
362 static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", };
363 static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk",
364 "osc_25m_clk", };
365 static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", };
366 static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
367 static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", };
368 static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk",
369 "i2s_src_pad_clk", };
370 static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", };
371 static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
372 "pll3_clk", };
373 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
374 "pll2_clk", };
375 static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none",
376 "ras_pll2_clk", "ras_syn0_clk", };
377 static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk",
378 "ras_pll2_clk", "ras_syn0_clk", };
379 static const char *uart_parents[] = { "ras_apb_clk", "gen_syn3_clk", };
380 static const char *i2c_parents[] = { "ras_apb_clk", "gen_syn1_clk", };
381 static const char *ssp1_parents[] = { "ras_apb_clk", "gen_syn1_clk",
382 "ras_plclk0_clk", };
383 static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", };
384 static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", };
385
spear1310_clk_init(void __iomem * misc_base,void __iomem * ras_base)386 void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
387 {
388 struct clk *clk, *clk1;
389
390 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
391 clk_register_clkdev(clk, "osc_32k_clk", NULL);
392
393 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000);
394 clk_register_clkdev(clk, "osc_24m_clk", NULL);
395
396 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000);
397 clk_register_clkdev(clk, "osc_25m_clk", NULL);
398
399 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000);
400 clk_register_clkdev(clk, "gmii_pad_clk", NULL);
401
402 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0,
403 12288000);
404 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
405
406 /* clock derived from 32 KHz osc clk */
407 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
408 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0,
409 &_lock);
410 clk_register_clkdev(clk, NULL, "e0580000.rtc");
411
412 /* clock derived from 24 or 25 MHz osc clk */
413 /* vco-pll */
414 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
415 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
416 SPEAR1310_PLL_CFG, SPEAR1310_PLL1_CLK_SHIFT,
417 SPEAR1310_PLL_CLK_MASK, 0, &_lock);
418 clk_register_clkdev(clk, "vco1_mclk", NULL);
419 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk",
420 0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl,
421 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
422 clk_register_clkdev(clk, "vco1_clk", NULL);
423 clk_register_clkdev(clk1, "pll1_clk", NULL);
424
425 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
426 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
427 SPEAR1310_PLL_CFG, SPEAR1310_PLL2_CLK_SHIFT,
428 SPEAR1310_PLL_CLK_MASK, 0, &_lock);
429 clk_register_clkdev(clk, "vco2_mclk", NULL);
430 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk",
431 0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl,
432 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
433 clk_register_clkdev(clk, "vco2_clk", NULL);
434 clk_register_clkdev(clk1, "pll2_clk", NULL);
435
436 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
437 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
438 SPEAR1310_PLL_CFG, SPEAR1310_PLL3_CLK_SHIFT,
439 SPEAR1310_PLL_CLK_MASK, 0, &_lock);
440 clk_register_clkdev(clk, "vco3_mclk", NULL);
441 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk",
442 0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl,
443 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
444 clk_register_clkdev(clk, "vco3_clk", NULL);
445 clk_register_clkdev(clk1, "pll3_clk", NULL);
446
447 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
448 0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl,
449 ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
450 clk_register_clkdev(clk, "vco4_clk", NULL);
451 clk_register_clkdev(clk1, "pll4_clk", NULL);
452
453 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
454 48000000);
455 clk_register_clkdev(clk, "pll5_clk", NULL);
456
457 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
458 25000000);
459 clk_register_clkdev(clk, "pll6_clk", NULL);
460
461 /* vco div n clocks */
462 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
463 2);
464 clk_register_clkdev(clk, "vco1div2_clk", NULL);
465
466 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
467 4);
468 clk_register_clkdev(clk, "vco1div4_clk", NULL);
469
470 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
471 2);
472 clk_register_clkdev(clk, "vco2div2_clk", NULL);
473
474 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
475 2);
476 clk_register_clkdev(clk, "vco3div2_clk", NULL);
477
478 /* peripherals */
479 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
480 128);
481 clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0,
482 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0,
483 &_lock);
484 clk_register_clkdev(clk, NULL, "spear_thermal");
485
486 /* clock derived from pll4 clk */
487 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
488 1);
489 clk_register_clkdev(clk, "ddr_clk", NULL);
490
491 /* clock derived from pll1 clk */
492 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
493 CLK_SET_RATE_PARENT, 1, 2);
494 clk_register_clkdev(clk, "cpu_clk", NULL);
495
496 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
497 2);
498 clk_register_clkdev(clk, NULL, "ec800620.wdt");
499
500 clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
501 2);
502 clk_register_clkdev(clk, NULL, "smp_twd");
503
504 clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
505 6);
506 clk_register_clkdev(clk, "ahb_clk", NULL);
507
508 clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1,
509 12);
510 clk_register_clkdev(clk, "apb_clk", NULL);
511
512 /* gpt clocks */
513 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
514 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
515 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT0_CLK_SHIFT,
516 SPEAR1310_GPT_CLK_MASK, 0, &_lock);
517 clk_register_clkdev(clk, "gpt0_mclk", NULL);
518 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
519 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0,
520 &_lock);
521 clk_register_clkdev(clk, NULL, "gpt0");
522
523 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
524 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
525 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT1_CLK_SHIFT,
526 SPEAR1310_GPT_CLK_MASK, 0, &_lock);
527 clk_register_clkdev(clk, "gpt1_mclk", NULL);
528 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
529 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0,
530 &_lock);
531 clk_register_clkdev(clk, NULL, "gpt1");
532
533 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
534 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
535 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT2_CLK_SHIFT,
536 SPEAR1310_GPT_CLK_MASK, 0, &_lock);
537 clk_register_clkdev(clk, "gpt2_mclk", NULL);
538 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
539 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0,
540 &_lock);
541 clk_register_clkdev(clk, NULL, "gpt2");
542
543 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
544 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
545 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT3_CLK_SHIFT,
546 SPEAR1310_GPT_CLK_MASK, 0, &_lock);
547 clk_register_clkdev(clk, "gpt3_mclk", NULL);
548 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
549 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0,
550 &_lock);
551 clk_register_clkdev(clk, NULL, "gpt3");
552
553 /* others */
554 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk",
555 0, SPEAR1310_UART_CLK_SYNT, NULL, aux_rtbl,
556 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
557 clk_register_clkdev(clk, "uart_syn_clk", NULL);
558 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
559
560 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
561 ARRAY_SIZE(uart0_parents),
562 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
563 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT,
564 SPEAR1310_UART_CLK_MASK, 0, &_lock);
565 clk_register_clkdev(clk, "uart0_mclk", NULL);
566
567 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk",
568 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
569 SPEAR1310_UART_CLK_ENB, 0, &_lock);
570 clk_register_clkdev(clk, NULL, "e0000000.serial");
571
572 clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
573 "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL,
574 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
575 clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
576 clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
577
578 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk",
579 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
580 SPEAR1310_SDHCI_CLK_ENB, 0, &_lock);
581 clk_register_clkdev(clk, NULL, "b3000000.sdhci");
582
583 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
584 0, SPEAR1310_CFXD_CLK_SYNT, NULL, aux_rtbl,
585 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
586 clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
587 clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
588
589 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk",
590 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
591 SPEAR1310_CFXD_CLK_ENB, 0, &_lock);
592 clk_register_clkdev(clk, NULL, "b2800000.cf");
593 clk_register_clkdev(clk, NULL, "arasan_xd");
594
595 clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk",
596 0, SPEAR1310_C3_CLK_SYNT, NULL, aux_rtbl,
597 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
598 clk_register_clkdev(clk, "c3_syn_clk", NULL);
599 clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
600
601 clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
602 ARRAY_SIZE(c3_parents),
603 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
604 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT,
605 SPEAR1310_C3_CLK_MASK, 0, &_lock);
606 clk_register_clkdev(clk, "c3_mclk", NULL);
607
608 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0,
609 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0,
610 &_lock);
611 clk_register_clkdev(clk, NULL, "c3");
612
613 /* gmac */
614 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
615 ARRAY_SIZE(gmac_phy_input_parents),
616 CLK_SET_RATE_NO_REPARENT, SPEAR1310_GMAC_CLK_CFG,
617 SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT,
618 SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
619 clk_register_clkdev(clk, "phy_input_mclk", NULL);
620
621 clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk",
622 0, SPEAR1310_GMAC_CLK_SYNT, NULL, gmac_rtbl,
623 ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
624 clk_register_clkdev(clk, "phy_syn_clk", NULL);
625 clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
626
627 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
628 ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT,
629 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
630 SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
631 clk_register_clkdev(clk, "stmmacphy.0", NULL);
632
633 /* clcd */
634 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
635 ARRAY_SIZE(clcd_synth_parents),
636 CLK_SET_RATE_NO_REPARENT, SPEAR1310_CLCD_CLK_SYNT,
637 SPEAR1310_CLCD_SYNT_CLK_SHIFT,
638 SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock);
639 clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
640
641 clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0,
642 SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl,
643 ARRAY_SIZE(clcd_rtbl), &_lock);
644 clk_register_clkdev(clk, "clcd_syn_clk", NULL);
645
646 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
647 ARRAY_SIZE(clcd_pixel_parents),
648 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
649 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
650 SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
651 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
652
653 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
654 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,
655 &_lock);
656 clk_register_clkdev(clk, NULL, "e1000000.clcd");
657
658 /* i2s */
659 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
660 ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT,
661 SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_SRC_CLK_SHIFT,
662 SPEAR1310_I2S_SRC_CLK_MASK, 0, &_lock);
663 clk_register_clkdev(clk, "i2s_src_mclk", NULL);
664
665 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
666 SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
667 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
668 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
669
670 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
671 ARRAY_SIZE(i2s_ref_parents),
672 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
673 SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT,
674 SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock);
675 clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
676
677 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
678 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB,
679 0, &_lock);
680 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
681
682 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk",
683 "i2s_ref_mclk", 0, SPEAR1310_I2S_CLK_CFG,
684 &i2s_sclk_masks, i2s_sclk_rtbl,
685 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
686 clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
687 clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL);
688
689 /* clock derived from ahb clk */
690 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
691 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0,
692 &_lock);
693 clk_register_clkdev(clk, NULL, "e0280000.i2c");
694
695 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
696 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0,
697 &_lock);
698 clk_register_clkdev(clk, NULL, "ea800000.dma");
699 clk_register_clkdev(clk, NULL, "eb000000.dma");
700
701 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0,
702 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0,
703 &_lock);
704 clk_register_clkdev(clk, NULL, "b2000000.jpeg");
705
706 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
707 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0,
708 &_lock);
709 clk_register_clkdev(clk, NULL, "e2000000.eth");
710
711 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
712 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0,
713 &_lock);
714 clk_register_clkdev(clk, NULL, "b0000000.flash");
715
716 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
717 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0,
718 &_lock);
719 clk_register_clkdev(clk, NULL, "ea000000.flash");
720
721 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
722 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0,
723 &_lock);
724 clk_register_clkdev(clk, NULL, "e4000000.ohci");
725 clk_register_clkdev(clk, NULL, "e4800000.ehci");
726
727 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
728 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0,
729 &_lock);
730 clk_register_clkdev(clk, NULL, "e5000000.ohci");
731 clk_register_clkdev(clk, NULL, "e5800000.ehci");
732
733 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
734 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0,
735 &_lock);
736 clk_register_clkdev(clk, NULL, "e3800000.otg");
737
738 clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
739 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
740 0, &_lock);
741 clk_register_clkdev(clk, NULL, "b1000000.pcie");
742 clk_register_clkdev(clk, NULL, "b1000000.ahci");
743
744 clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
745 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
746 0, &_lock);
747 clk_register_clkdev(clk, NULL, "b1800000.pcie");
748 clk_register_clkdev(clk, NULL, "b1800000.ahci");
749
750 clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
751 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
752 0, &_lock);
753 clk_register_clkdev(clk, NULL, "b4000000.pcie");
754 clk_register_clkdev(clk, NULL, "b4000000.ahci");
755
756 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
757 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0,
758 &_lock);
759 clk_register_clkdev(clk, "sysram0_clk", NULL);
760
761 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
762 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0,
763 &_lock);
764 clk_register_clkdev(clk, "sysram1_clk", NULL);
765
766 clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk",
767 0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl,
768 ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
769 clk_register_clkdev(clk, "adc_syn_clk", NULL);
770 clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
771
772 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk",
773 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
774 SPEAR1310_ADC_CLK_ENB, 0, &_lock);
775 clk_register_clkdev(clk, NULL, "e0080000.adc");
776
777 /* clock derived from apb clk */
778 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0,
779 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0,
780 &_lock);
781 clk_register_clkdev(clk, NULL, "e0100000.spi");
782
783 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
784 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0,
785 &_lock);
786 clk_register_clkdev(clk, NULL, "e0600000.gpio");
787
788 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
789 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0,
790 &_lock);
791 clk_register_clkdev(clk, NULL, "e0680000.gpio");
792
793 clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0,
794 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0,
795 &_lock);
796 clk_register_clkdev(clk, NULL, "e0180000.i2s");
797
798 clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0,
799 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0,
800 &_lock);
801 clk_register_clkdev(clk, NULL, "e0200000.i2s");
802
803 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
804 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0,
805 &_lock);
806 clk_register_clkdev(clk, NULL, "e0300000.kbd");
807
808 /* RAS clks */
809 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
810 ARRAY_SIZE(gen_synth0_1_parents),
811 CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG,
812 SPEAR1310_RAS_SYNT0_1_CLK_SHIFT,
813 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
814 clk_register_clkdev(clk, "gen_syn0_1_clk", NULL);
815
816 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
817 ARRAY_SIZE(gen_synth2_3_parents),
818 CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG,
819 SPEAR1310_RAS_SYNT2_3_CLK_SHIFT,
820 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
821 clk_register_clkdev(clk, "gen_syn2_3_clk", NULL);
822
823 clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0,
824 SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
825 &_lock);
826 clk_register_clkdev(clk, "gen_syn0_clk", NULL);
827
828 clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0,
829 SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
830 &_lock);
831 clk_register_clkdev(clk, "gen_syn1_clk", NULL);
832
833 clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0,
834 SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
835 &_lock);
836 clk_register_clkdev(clk, "gen_syn2_clk", NULL);
837
838 clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0,
839 SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
840 &_lock);
841 clk_register_clkdev(clk, "gen_syn3_clk", NULL);
842
843 clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0,
844 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0,
845 &_lock);
846 clk_register_clkdev(clk, "ras_osc_24m_clk", NULL);
847
848 clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0,
849 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0,
850 &_lock);
851 clk_register_clkdev(clk, "ras_osc_25m_clk", NULL);
852
853 clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0,
854 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0,
855 &_lock);
856 clk_register_clkdev(clk, "ras_osc_32k_clk", NULL);
857
858 clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
859 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0,
860 &_lock);
861 clk_register_clkdev(clk, "ras_pll2_clk", NULL);
862
863 clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
864 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0,
865 &_lock);
866 clk_register_clkdev(clk, "ras_pll3_clk", NULL);
867
868 clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_pad_clk", 0,
869 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0,
870 &_lock);
871 clk_register_clkdev(clk, "ras_tx125_clk", NULL);
872
873 clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0,
874 30000000);
875 clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0,
876 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0,
877 &_lock);
878 clk_register_clkdev(clk, "ras_30m_clk", NULL);
879
880 clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0,
881 48000000);
882 clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0,
883 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0,
884 &_lock);
885 clk_register_clkdev(clk, "ras_48m_clk", NULL);
886
887 clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0,
888 SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0,
889 &_lock);
890 clk_register_clkdev(clk, "ras_ahb_clk", NULL);
891
892 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0,
893 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0,
894 &_lock);
895 clk_register_clkdev(clk, "ras_apb_clk", NULL);
896
897 clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, 0,
898 50000000);
899
900 clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, 0, 50000000);
901
902 clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0,
903 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0,
904 &_lock);
905 clk_register_clkdev(clk, NULL, "c_can_platform.0");
906
907 clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0,
908 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0,
909 &_lock);
910 clk_register_clkdev(clk, NULL, "c_can_platform.1");
911
912 clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0,
913 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0,
914 &_lock);
915 clk_register_clkdev(clk, NULL, "5c400000.eth");
916
917 clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0,
918 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0,
919 &_lock);
920 clk_register_clkdev(clk, NULL, "5c500000.eth");
921
922 clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0,
923 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0,
924 &_lock);
925 clk_register_clkdev(clk, NULL, "5c600000.eth");
926
927 clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0,
928 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0,
929 &_lock);
930 clk_register_clkdev(clk, NULL, "5c700000.eth");
931
932 clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk",
933 smii_rgmii_phy_parents,
934 ARRAY_SIZE(smii_rgmii_phy_parents),
935 CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG1,
936 SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
937 SPEAR1310_PHY_CLK_MASK, 0, &_lock);
938 clk_register_clkdev(clk, "stmmacphy.1", NULL);
939 clk_register_clkdev(clk, "stmmacphy.2", NULL);
940 clk_register_clkdev(clk, "stmmacphy.4", NULL);
941
942 clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents,
943 ARRAY_SIZE(rmii_phy_parents), CLK_SET_RATE_NO_REPARENT,
944 SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
945 SPEAR1310_PHY_CLK_MASK, 0, &_lock);
946 clk_register_clkdev(clk, "stmmacphy.3", NULL);
947
948 clk = clk_register_mux(NULL, "uart1_mclk", uart_parents,
949 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
950 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART1_CLK_SHIFT,
951 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
952 clk_register_clkdev(clk, "uart1_mclk", NULL);
953
954 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
955 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0,
956 &_lock);
957 clk_register_clkdev(clk, NULL, "5c800000.serial");
958
959 clk = clk_register_mux(NULL, "uart2_mclk", uart_parents,
960 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
961 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART2_CLK_SHIFT,
962 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
963 clk_register_clkdev(clk, "uart2_mclk", NULL);
964
965 clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0,
966 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0,
967 &_lock);
968 clk_register_clkdev(clk, NULL, "5c900000.serial");
969
970 clk = clk_register_mux(NULL, "uart3_mclk", uart_parents,
971 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
972 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART3_CLK_SHIFT,
973 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
974 clk_register_clkdev(clk, "uart3_mclk", NULL);
975
976 clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0,
977 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0,
978 &_lock);
979 clk_register_clkdev(clk, NULL, "5ca00000.serial");
980
981 clk = clk_register_mux(NULL, "uart4_mclk", uart_parents,
982 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
983 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART4_CLK_SHIFT,
984 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
985 clk_register_clkdev(clk, "uart4_mclk", NULL);
986
987 clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0,
988 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0,
989 &_lock);
990 clk_register_clkdev(clk, NULL, "5cb00000.serial");
991
992 clk = clk_register_mux(NULL, "uart5_mclk", uart_parents,
993 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
994 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART5_CLK_SHIFT,
995 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
996 clk_register_clkdev(clk, "uart5_mclk", NULL);
997
998 clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0,
999 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0,
1000 &_lock);
1001 clk_register_clkdev(clk, NULL, "5cc00000.serial");
1002
1003 clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents,
1004 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1005 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C1_CLK_SHIFT,
1006 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1007 clk_register_clkdev(clk, "i2c1_mclk", NULL);
1008
1009 clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0,
1010 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0,
1011 &_lock);
1012 clk_register_clkdev(clk, NULL, "5cd00000.i2c");
1013
1014 clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents,
1015 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1016 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C2_CLK_SHIFT,
1017 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1018 clk_register_clkdev(clk, "i2c2_mclk", NULL);
1019
1020 clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0,
1021 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0,
1022 &_lock);
1023 clk_register_clkdev(clk, NULL, "5ce00000.i2c");
1024
1025 clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents,
1026 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1027 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C3_CLK_SHIFT,
1028 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1029 clk_register_clkdev(clk, "i2c3_mclk", NULL);
1030
1031 clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0,
1032 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0,
1033 &_lock);
1034 clk_register_clkdev(clk, NULL, "5cf00000.i2c");
1035
1036 clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents,
1037 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1038 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C4_CLK_SHIFT,
1039 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1040 clk_register_clkdev(clk, "i2c4_mclk", NULL);
1041
1042 clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0,
1043 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0,
1044 &_lock);
1045 clk_register_clkdev(clk, NULL, "5d000000.i2c");
1046
1047 clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents,
1048 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1049 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C5_CLK_SHIFT,
1050 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1051 clk_register_clkdev(clk, "i2c5_mclk", NULL);
1052
1053 clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0,
1054 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0,
1055 &_lock);
1056 clk_register_clkdev(clk, NULL, "5d100000.i2c");
1057
1058 clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents,
1059 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1060 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C6_CLK_SHIFT,
1061 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1062 clk_register_clkdev(clk, "i2c6_mclk", NULL);
1063
1064 clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0,
1065 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0,
1066 &_lock);
1067 clk_register_clkdev(clk, NULL, "5d200000.i2c");
1068
1069 clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents,
1070 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1071 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C7_CLK_SHIFT,
1072 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1073 clk_register_clkdev(clk, "i2c7_mclk", NULL);
1074
1075 clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0,
1076 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0,
1077 &_lock);
1078 clk_register_clkdev(clk, NULL, "5d300000.i2c");
1079
1080 clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents,
1081 ARRAY_SIZE(ssp1_parents), CLK_SET_RATE_NO_REPARENT,
1082 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_SSP1_CLK_SHIFT,
1083 SPEAR1310_SSP1_CLK_MASK, 0, &_lock);
1084 clk_register_clkdev(clk, "ssp1_mclk", NULL);
1085
1086 clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0,
1087 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0,
1088 &_lock);
1089 clk_register_clkdev(clk, NULL, "5d400000.spi");
1090
1091 clk = clk_register_mux(NULL, "pci_mclk", pci_parents,
1092 ARRAY_SIZE(pci_parents), CLK_SET_RATE_NO_REPARENT,
1093 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_PCI_CLK_SHIFT,
1094 SPEAR1310_PCI_CLK_MASK, 0, &_lock);
1095 clk_register_clkdev(clk, "pci_mclk", NULL);
1096
1097 clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0,
1098 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0,
1099 &_lock);
1100 clk_register_clkdev(clk, NULL, "pci");
1101
1102 clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents,
1103 ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT,
1104 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM1_CLK_SHIFT,
1105 SPEAR1310_TDM_CLK_MASK, 0, &_lock);
1106 clk_register_clkdev(clk, "tdm1_mclk", NULL);
1107
1108 clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0,
1109 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0,
1110 &_lock);
1111 clk_register_clkdev(clk, NULL, "tdm_hdlc.0");
1112
1113 clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents,
1114 ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT,
1115 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM2_CLK_SHIFT,
1116 SPEAR1310_TDM_CLK_MASK, 0, &_lock);
1117 clk_register_clkdev(clk, "tdm2_mclk", NULL);
1118
1119 clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0,
1120 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0,
1121 &_lock);
1122 clk_register_clkdev(clk, NULL, "tdm_hdlc.1");
1123 }
1124