1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PLL clock descriptions for TI DM644X
4 *
5 * Copyright (C) 2018 David Lechner <david@lechnology.com>
6 */
7
8 #include <linux/bitops.h>
9 #include <linux/clk/davinci.h>
10 #include <linux/clkdev.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13
14 #include "pll.h"
15
16 static const struct davinci_pll_clk_info dm644x_pll1_info = {
17 .name = "pll1",
18 .pllm_mask = GENMASK(4, 0),
19 .pllm_min = 1,
20 .pllm_max = 32,
21 .pllout_min_rate = 400000000,
22 .pllout_max_rate = 600000000, /* 810MHz @ 1.3V, -810 only */
23 .flags = PLL_HAS_CLKMODE | PLL_HAS_POSTDIV,
24 };
25
26 SYSCLK(1, pll1_sysclk1, pll1_pllen, 4, SYSCLK_FIXED_DIV);
27 SYSCLK(2, pll1_sysclk2, pll1_pllen, 4, SYSCLK_FIXED_DIV);
28 SYSCLK(3, pll1_sysclk3, pll1_pllen, 4, SYSCLK_FIXED_DIV);
29 SYSCLK(5, pll1_sysclk5, pll1_pllen, 4, SYSCLK_FIXED_DIV);
30
dm644x_pll1_init(struct device * dev,void __iomem * base,struct regmap * cfgchip)31 int dm644x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
32 {
33 struct clk *clk;
34
35 davinci_pll_clk_register(dev, &dm644x_pll1_info, "ref_clk", base, cfgchip);
36
37 clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
38 clk_register_clkdev(clk, "pll1_sysclk1", "dm644x-psc");
39
40 clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
41 clk_register_clkdev(clk, "pll1_sysclk2", "dm644x-psc");
42
43 clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
44 clk_register_clkdev(clk, "pll1_sysclk3", "dm644x-psc");
45
46 clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base);
47 clk_register_clkdev(clk, "pll1_sysclk5", "dm644x-psc");
48
49 clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
50 clk_register_clkdev(clk, "pll1_auxclk", "dm644x-psc");
51
52 davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
53
54 return 0;
55 }
56
57 static const struct davinci_pll_clk_info dm644x_pll2_info = {
58 .name = "pll2",
59 .pllm_mask = GENMASK(4, 0),
60 .pllm_min = 1,
61 .pllm_max = 32,
62 .pllout_min_rate = 400000000,
63 .pllout_max_rate = 900000000,
64 .flags = PLL_HAS_POSTDIV | PLL_POSTDIV_FIXED_DIV,
65 };
66
67 SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0);
68 SYSCLK(2, pll2_sysclk2, pll2_pllen, 4, 0);
69
dm644x_pll2_init(struct device * dev,void __iomem * base,struct regmap * cfgchip)70 int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
71 {
72 davinci_pll_clk_register(dev, &dm644x_pll2_info, "oscin", base, cfgchip);
73
74 davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
75
76 davinci_pll_sysclk_register(dev, &pll2_sysclk2, base);
77
78 davinci_pll_sysclkbp_clk_register(dev, "pll2_sysclkbp", base);
79
80 return 0;
81 }
82