1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7  * Copyright (C) 2000 Silicon Graphics, Inc.
8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
12  */
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
15 
16 #include <linux/linkage.h>
17 #include <linux/types.h>
18 #include <asm/hazards.h>
19 #include <asm/isa-rev.h>
20 
21 /*
22  * The following macros are especially useful for __asm__
23  * inline assembler.
24  */
25 #ifndef __STR
26 #define __STR(x) #x
27 #endif
28 #ifndef STR
29 #define STR(x) __STR(x)
30 #endif
31 
32 /*
33  *  Configure language
34  */
35 #ifdef __ASSEMBLY__
36 #define _ULCAST_
37 #define _U64CAST_
38 #else
39 #define _ULCAST_ (unsigned long)
40 #define _U64CAST_ (u64)
41 #endif
42 
43 /*
44  * Coprocessor 0 register names
45  */
46 #define CP0_INDEX $0
47 #define CP0_RANDOM $1
48 #define CP0_ENTRYLO0 $2
49 #define CP0_ENTRYLO1 $3
50 #define CP0_CONF $3
51 #define CP0_GLOBALNUMBER $3, 1
52 #define CP0_CONTEXT $4
53 #define CP0_PAGEMASK $5
54 #define CP0_PAGEGRAIN $5, 1
55 #define CP0_SEGCTL0 $5, 2
56 #define CP0_SEGCTL1 $5, 3
57 #define CP0_SEGCTL2 $5, 4
58 #define CP0_WIRED $6
59 #define CP0_INFO $7
60 #define CP0_HWRENA $7
61 #define CP0_BADVADDR $8
62 #define CP0_BADINSTR $8, 1
63 #define CP0_COUNT $9
64 #define CP0_ENTRYHI $10
65 #define CP0_GUESTCTL1 $10, 4
66 #define CP0_GUESTCTL2 $10, 5
67 #define CP0_GUESTCTL3 $10, 6
68 #define CP0_COMPARE $11
69 #define CP0_GUESTCTL0EXT $11, 4
70 #define CP0_STATUS $12
71 #define CP0_GUESTCTL0 $12, 6
72 #define CP0_GTOFFSET $12, 7
73 #define CP0_CAUSE $13
74 #define CP0_EPC $14
75 #define CP0_PRID $15
76 #define CP0_EBASE $15, 1
77 #define CP0_CMGCRBASE $15, 3
78 #define CP0_CONFIG $16
79 #define CP0_CONFIG3 $16, 3
80 #define CP0_CONFIG5 $16, 5
81 #define CP0_CONFIG6 $16, 6
82 #define CP0_LLADDR $17
83 #define CP0_WATCHLO $18
84 #define CP0_WATCHHI $19
85 #define CP0_XCONTEXT $20
86 #define CP0_FRAMEMASK $21
87 #define CP0_DIAGNOSTIC $22
88 #define CP0_DIAGNOSTIC1 $22, 1
89 #define CP0_DEBUG $23
90 #define CP0_DEPC $24
91 #define CP0_PERFORMANCE $25
92 #define CP0_ECC $26
93 #define CP0_CACHEERR $27
94 #define CP0_TAGLO $28
95 #define CP0_TAGHI $29
96 #define CP0_ERROREPC $30
97 #define CP0_DESAVE $31
98 
99 /*
100  * R4640/R4650 cp0 register names.  These registers are listed
101  * here only for completeness; without MMU these CPUs are not useable
102  * by Linux.  A future ELKS port might take make Linux run on them
103  * though ...
104  */
105 #define CP0_IBASE $0
106 #define CP0_IBOUND $1
107 #define CP0_DBASE $2
108 #define CP0_DBOUND $3
109 #define CP0_CALG $17
110 #define CP0_IWATCH $18
111 #define CP0_DWATCH $19
112 
113 /*
114  * Coprocessor 0 Set 1 register names
115  */
116 #define CP0_S1_DERRADDR0  $26
117 #define CP0_S1_DERRADDR1  $27
118 #define CP0_S1_INTCONTROL $20
119 
120 /*
121  * Coprocessor 0 Set 2 register names
122  */
123 #define CP0_S2_SRSCTL	  $12	/* MIPSR2 */
124 
125 /*
126  * Coprocessor 0 Set 3 register names
127  */
128 #define CP0_S3_SRSMAP	  $12	/* MIPSR2 */
129 
130 /*
131  *  TX39 Series
132  */
133 #define CP0_TX39_CACHE	$7
134 
135 
136 /* Generic EntryLo bit definitions */
137 #define ENTRYLO_G		(_ULCAST_(1) << 0)
138 #define ENTRYLO_V		(_ULCAST_(1) << 1)
139 #define ENTRYLO_D		(_ULCAST_(1) << 2)
140 #define ENTRYLO_C_SHIFT		3
141 #define ENTRYLO_C		(_ULCAST_(7) << ENTRYLO_C_SHIFT)
142 
143 /* R3000 EntryLo bit definitions */
144 #define R3K_ENTRYLO_G		(_ULCAST_(1) << 8)
145 #define R3K_ENTRYLO_V		(_ULCAST_(1) << 9)
146 #define R3K_ENTRYLO_D		(_ULCAST_(1) << 10)
147 #define R3K_ENTRYLO_N		(_ULCAST_(1) << 11)
148 
149 /* MIPS32/64 EntryLo bit definitions */
150 #define MIPS_ENTRYLO_PFN_SHIFT	6
151 #define MIPS_ENTRYLO_XI		(_ULCAST_(1) << (BITS_PER_LONG - 2))
152 #define MIPS_ENTRYLO_RI		(_ULCAST_(1) << (BITS_PER_LONG - 1))
153 
154 /*
155  * MIPSr6+ GlobalNumber register definitions
156  */
157 #define MIPS_GLOBALNUMBER_VP_SHF	0
158 #define MIPS_GLOBALNUMBER_VP		(_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
159 #define MIPS_GLOBALNUMBER_CORE_SHF	8
160 #define MIPS_GLOBALNUMBER_CORE		(_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
161 #define MIPS_GLOBALNUMBER_CLUSTER_SHF	16
162 #define MIPS_GLOBALNUMBER_CLUSTER	(_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
163 
164 /*
165  * Values for PageMask register
166  */
167 #ifdef CONFIG_CPU_VR41XX
168 
169 /* Why doesn't stupidity hurt ... */
170 
171 #define PM_1K		0x00000000
172 #define PM_4K		0x00001800
173 #define PM_16K		0x00007800
174 #define PM_64K		0x0001f800
175 #define PM_256K		0x0007f800
176 
177 #else
178 
179 #define PM_4K		0x00000000
180 #define PM_8K		0x00002000
181 #define PM_16K		0x00006000
182 #define PM_32K		0x0000e000
183 #define PM_64K		0x0001e000
184 #define PM_128K		0x0003e000
185 #define PM_256K		0x0007e000
186 #define PM_512K		0x000fe000
187 #define PM_1M		0x001fe000
188 #define PM_2M		0x003fe000
189 #define PM_4M		0x007fe000
190 #define PM_8M		0x00ffe000
191 #define PM_16M		0x01ffe000
192 #define PM_32M		0x03ffe000
193 #define PM_64M		0x07ffe000
194 #define PM_256M		0x1fffe000
195 #define PM_1G		0x7fffe000
196 
197 #endif
198 
199 /*
200  * Default page size for a given kernel configuration
201  */
202 #ifdef CONFIG_PAGE_SIZE_4KB
203 #define PM_DEFAULT_MASK PM_4K
204 #elif defined(CONFIG_PAGE_SIZE_8KB)
205 #define PM_DEFAULT_MASK PM_8K
206 #elif defined(CONFIG_PAGE_SIZE_16KB)
207 #define PM_DEFAULT_MASK PM_16K
208 #elif defined(CONFIG_PAGE_SIZE_32KB)
209 #define PM_DEFAULT_MASK PM_32K
210 #elif defined(CONFIG_PAGE_SIZE_64KB)
211 #define PM_DEFAULT_MASK PM_64K
212 #else
213 #error Bad page size configuration!
214 #endif
215 
216 /*
217  * Default huge tlb size for a given kernel configuration
218  */
219 #ifdef CONFIG_PAGE_SIZE_4KB
220 #define PM_HUGE_MASK	PM_1M
221 #elif defined(CONFIG_PAGE_SIZE_8KB)
222 #define PM_HUGE_MASK	PM_4M
223 #elif defined(CONFIG_PAGE_SIZE_16KB)
224 #define PM_HUGE_MASK	PM_16M
225 #elif defined(CONFIG_PAGE_SIZE_32KB)
226 #define PM_HUGE_MASK	PM_64M
227 #elif defined(CONFIG_PAGE_SIZE_64KB)
228 #define PM_HUGE_MASK	PM_256M
229 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
230 #error Bad page size configuration for hugetlbfs!
231 #endif
232 
233 /*
234  * Wired register bits
235  */
236 #define MIPSR6_WIRED_LIMIT_SHIFT 16
237 #define MIPSR6_WIRED_LIMIT	(_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
238 #define MIPSR6_WIRED_WIRED_SHIFT 0
239 #define MIPSR6_WIRED_WIRED	(_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
240 
241 /*
242  * Values used for computation of new tlb entries
243  */
244 #define PL_4K		12
245 #define PL_16K		14
246 #define PL_64K		16
247 #define PL_256K		18
248 #define PL_1M		20
249 #define PL_4M		22
250 #define PL_16M		24
251 #define PL_64M		26
252 #define PL_256M		28
253 
254 /*
255  * PageGrain bits
256  */
257 #define PG_RIE		(_ULCAST_(1) <<	 31)
258 #define PG_XIE		(_ULCAST_(1) <<	 30)
259 #define PG_ELPA		(_ULCAST_(1) <<	 29)
260 #define PG_ESP		(_ULCAST_(1) <<	 28)
261 #define PG_IEC		(_ULCAST_(1) <<  27)
262 
263 /* MIPS32/64 EntryHI bit definitions */
264 #define MIPS_ENTRYHI_EHINV	(_ULCAST_(1) << 10)
265 #define MIPS_ENTRYHI_ASIDX	(_ULCAST_(0x3) << 8)
266 #define MIPS_ENTRYHI_ASID	(_ULCAST_(0xff) << 0)
267 
268 /*
269  * R4x00 interrupt enable / cause bits
270  */
271 #define IE_SW0		(_ULCAST_(1) <<	 8)
272 #define IE_SW1		(_ULCAST_(1) <<	 9)
273 #define IE_IRQ0		(_ULCAST_(1) << 10)
274 #define IE_IRQ1		(_ULCAST_(1) << 11)
275 #define IE_IRQ2		(_ULCAST_(1) << 12)
276 #define IE_IRQ3		(_ULCAST_(1) << 13)
277 #define IE_IRQ4		(_ULCAST_(1) << 14)
278 #define IE_IRQ5		(_ULCAST_(1) << 15)
279 
280 /*
281  * R4x00 interrupt cause bits
282  */
283 #define C_SW0		(_ULCAST_(1) <<	 8)
284 #define C_SW1		(_ULCAST_(1) <<	 9)
285 #define C_IRQ0		(_ULCAST_(1) << 10)
286 #define C_IRQ1		(_ULCAST_(1) << 11)
287 #define C_IRQ2		(_ULCAST_(1) << 12)
288 #define C_IRQ3		(_ULCAST_(1) << 13)
289 #define C_IRQ4		(_ULCAST_(1) << 14)
290 #define C_IRQ5		(_ULCAST_(1) << 15)
291 
292 /*
293  * Bitfields in the R4xx0 cp0 status register
294  */
295 #define ST0_IE			0x00000001
296 #define ST0_EXL			0x00000002
297 #define ST0_ERL			0x00000004
298 #define ST0_KSU			0x00000018
299 #  define KSU_USER		0x00000010
300 #  define KSU_SUPERVISOR	0x00000008
301 #  define KSU_KERNEL		0x00000000
302 #define ST0_UX			0x00000020
303 #define ST0_SX			0x00000040
304 #define ST0_KX			0x00000080
305 #define ST0_DE			0x00010000
306 #define ST0_CE			0x00020000
307 
308 /*
309  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
310  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
311  * processors.
312  */
313 #define ST0_CO			0x08000000
314 
315 /*
316  * Bitfields in the R[23]000 cp0 status register.
317  */
318 #define ST0_IEC			0x00000001
319 #define ST0_KUC			0x00000002
320 #define ST0_IEP			0x00000004
321 #define ST0_KUP			0x00000008
322 #define ST0_IEO			0x00000010
323 #define ST0_KUO			0x00000020
324 /* bits 6 & 7 are reserved on R[23]000 */
325 #define ST0_ISC			0x00010000
326 #define ST0_SWC			0x00020000
327 #define ST0_CM			0x00080000
328 
329 /*
330  * Bits specific to the R4640/R4650
331  */
332 #define ST0_UM			(_ULCAST_(1) <<	 4)
333 #define ST0_IL			(_ULCAST_(1) << 23)
334 #define ST0_DL			(_ULCAST_(1) << 24)
335 
336 /*
337  * Enable the MIPS MDMX and DSP ASEs
338  */
339 #define ST0_MX			0x01000000
340 
341 /*
342  * Status register bits available in all MIPS CPUs.
343  */
344 #define ST0_IM			0x0000ff00
345 #define	 STATUSB_IP0		8
346 #define	 STATUSF_IP0		(_ULCAST_(1) <<	 8)
347 #define	 STATUSB_IP1		9
348 #define	 STATUSF_IP1		(_ULCAST_(1) <<	 9)
349 #define	 STATUSB_IP2		10
350 #define	 STATUSF_IP2		(_ULCAST_(1) << 10)
351 #define	 STATUSB_IP3		11
352 #define	 STATUSF_IP3		(_ULCAST_(1) << 11)
353 #define	 STATUSB_IP4		12
354 #define	 STATUSF_IP4		(_ULCAST_(1) << 12)
355 #define	 STATUSB_IP5		13
356 #define	 STATUSF_IP5		(_ULCAST_(1) << 13)
357 #define	 STATUSB_IP6		14
358 #define	 STATUSF_IP6		(_ULCAST_(1) << 14)
359 #define	 STATUSB_IP7		15
360 #define	 STATUSF_IP7		(_ULCAST_(1) << 15)
361 #define	 STATUSB_IP8		0
362 #define	 STATUSF_IP8		(_ULCAST_(1) <<	 0)
363 #define	 STATUSB_IP9		1
364 #define	 STATUSF_IP9		(_ULCAST_(1) <<	 1)
365 #define	 STATUSB_IP10		2
366 #define	 STATUSF_IP10		(_ULCAST_(1) <<	 2)
367 #define	 STATUSB_IP11		3
368 #define	 STATUSF_IP11		(_ULCAST_(1) <<	 3)
369 #define	 STATUSB_IP12		4
370 #define	 STATUSF_IP12		(_ULCAST_(1) <<	 4)
371 #define	 STATUSB_IP13		5
372 #define	 STATUSF_IP13		(_ULCAST_(1) <<	 5)
373 #define	 STATUSB_IP14		6
374 #define	 STATUSF_IP14		(_ULCAST_(1) <<	 6)
375 #define	 STATUSB_IP15		7
376 #define	 STATUSF_IP15		(_ULCAST_(1) <<	 7)
377 #define ST0_CH			0x00040000
378 #define ST0_NMI			0x00080000
379 #define ST0_SR			0x00100000
380 #define ST0_TS			0x00200000
381 #define ST0_BEV			0x00400000
382 #define ST0_RE			0x02000000
383 #define ST0_FR			0x04000000
384 #define ST0_CU			0xf0000000
385 #define ST0_CU0			0x10000000
386 #define ST0_CU1			0x20000000
387 #define ST0_CU2			0x40000000
388 #define ST0_CU3			0x80000000
389 #define ST0_XX			0x80000000	/* MIPS IV naming */
390 
391 /* in-kernel enabled CUs */
392 #ifdef CONFIG_CPU_LOONGSON64
393 #define ST0_KERNEL_CUMASK      (ST0_CU0 | ST0_CU2)
394 #else
395 #define ST0_KERNEL_CUMASK      ST0_CU0
396 #endif
397 
398 /*
399  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
400  */
401 #define INTCTLB_IPFDC		23
402 #define INTCTLF_IPFDC		(_ULCAST_(7) << INTCTLB_IPFDC)
403 #define INTCTLB_IPPCI		26
404 #define INTCTLF_IPPCI		(_ULCAST_(7) << INTCTLB_IPPCI)
405 #define INTCTLB_IPTI		29
406 #define INTCTLF_IPTI		(_ULCAST_(7) << INTCTLB_IPTI)
407 
408 /*
409  * Bitfields and bit numbers in the coprocessor 0 cause register.
410  *
411  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
412  */
413 #define CAUSEB_EXCCODE		2
414 #define CAUSEF_EXCCODE		(_ULCAST_(31)  <<  2)
415 #define CAUSEB_IP		8
416 #define CAUSEF_IP		(_ULCAST_(255) <<  8)
417 #define	 CAUSEB_IP0		8
418 #define	 CAUSEF_IP0		(_ULCAST_(1)   <<  8)
419 #define	 CAUSEB_IP1		9
420 #define	 CAUSEF_IP1		(_ULCAST_(1)   <<  9)
421 #define	 CAUSEB_IP2		10
422 #define	 CAUSEF_IP2		(_ULCAST_(1)   << 10)
423 #define	 CAUSEB_IP3		11
424 #define	 CAUSEF_IP3		(_ULCAST_(1)   << 11)
425 #define	 CAUSEB_IP4		12
426 #define	 CAUSEF_IP4		(_ULCAST_(1)   << 12)
427 #define	 CAUSEB_IP5		13
428 #define	 CAUSEF_IP5		(_ULCAST_(1)   << 13)
429 #define	 CAUSEB_IP6		14
430 #define	 CAUSEF_IP6		(_ULCAST_(1)   << 14)
431 #define	 CAUSEB_IP7		15
432 #define	 CAUSEF_IP7		(_ULCAST_(1)   << 15)
433 #define CAUSEB_FDCI		21
434 #define CAUSEF_FDCI		(_ULCAST_(1)   << 21)
435 #define CAUSEB_WP		22
436 #define CAUSEF_WP		(_ULCAST_(1)   << 22)
437 #define CAUSEB_IV		23
438 #define CAUSEF_IV		(_ULCAST_(1)   << 23)
439 #define CAUSEB_PCI		26
440 #define CAUSEF_PCI		(_ULCAST_(1)   << 26)
441 #define CAUSEB_DC		27
442 #define CAUSEF_DC		(_ULCAST_(1)   << 27)
443 #define CAUSEB_CE		28
444 #define CAUSEF_CE		(_ULCAST_(3)   << 28)
445 #define CAUSEB_TI		30
446 #define CAUSEF_TI		(_ULCAST_(1)   << 30)
447 #define CAUSEB_BD		31
448 #define CAUSEF_BD		(_ULCAST_(1)   << 31)
449 
450 /*
451  * Cause.ExcCode trap codes.
452  */
453 #define EXCCODE_INT		0	/* Interrupt pending */
454 #define EXCCODE_MOD		1	/* TLB modified fault */
455 #define EXCCODE_TLBL		2	/* TLB miss on load or ifetch */
456 #define EXCCODE_TLBS		3	/* TLB miss on a store */
457 #define EXCCODE_ADEL		4	/* Address error on a load or ifetch */
458 #define EXCCODE_ADES		5	/* Address error on a store */
459 #define EXCCODE_IBE		6	/* Bus error on an ifetch */
460 #define EXCCODE_DBE		7	/* Bus error on a load or store */
461 #define EXCCODE_SYS		8	/* System call */
462 #define EXCCODE_BP		9	/* Breakpoint */
463 #define EXCCODE_RI		10	/* Reserved instruction exception */
464 #define EXCCODE_CPU		11	/* Coprocessor unusable */
465 #define EXCCODE_OV		12	/* Arithmetic overflow */
466 #define EXCCODE_TR		13	/* Trap instruction */
467 #define EXCCODE_MSAFPE		14	/* MSA floating point exception */
468 #define EXCCODE_FPE		15	/* Floating point exception */
469 #define EXCCODE_TLBRI		19	/* TLB Read-Inhibit exception */
470 #define EXCCODE_TLBXI		20	/* TLB Execution-Inhibit exception */
471 #define EXCCODE_MSADIS		21	/* MSA disabled exception */
472 #define EXCCODE_MDMX		22	/* MDMX unusable exception */
473 #define EXCCODE_WATCH		23	/* Watch address reference */
474 #define EXCCODE_MCHECK		24	/* Machine check */
475 #define EXCCODE_THREAD		25	/* Thread exceptions (MT) */
476 #define EXCCODE_DSPDIS		26	/* DSP disabled exception */
477 #define EXCCODE_GE		27	/* Virtualized guest exception (VZ) */
478 #define EXCCODE_CACHEERR	30	/* Parity/ECC occured on a core */
479 
480 /* Implementation specific trap codes used by MIPS cores */
481 #define MIPS_EXCCODE_TLBPAR	16	/* TLB parity error exception */
482 
483 /* Implementation specific trap codes used by Loongson cores */
484 #define LOONGSON_EXCCODE_GSEXC	16	/* Loongson-specific exception */
485 
486 /*
487  * Bits in the coprocessor 0 config register.
488  */
489 /* Generic bits.  */
490 #define CONF_CM_CACHABLE_NO_WA		0
491 #define CONF_CM_CACHABLE_WA		1
492 #define CONF_CM_UNCACHED		2
493 #define CONF_CM_CACHABLE_NONCOHERENT	3
494 #define CONF_CM_CACHABLE_CE		4
495 #define CONF_CM_CACHABLE_COW		5
496 #define CONF_CM_CACHABLE_CUW		6
497 #define CONF_CM_CACHABLE_ACCELERATED	7
498 #define CONF_CM_CMASK			7
499 #define CONF_BE			(_ULCAST_(1) << 15)
500 
501 /* Bits common to various processors.  */
502 #define CONF_CU			(_ULCAST_(1) <<	 3)
503 #define CONF_DB			(_ULCAST_(1) <<	 4)
504 #define CONF_IB			(_ULCAST_(1) <<	 5)
505 #define CONF_DC			(_ULCAST_(7) <<	 6)
506 #define CONF_IC			(_ULCAST_(7) <<	 9)
507 #define CONF_EB			(_ULCAST_(1) << 13)
508 #define CONF_EM			(_ULCAST_(1) << 14)
509 #define CONF_SM			(_ULCAST_(1) << 16)
510 #define CONF_SC			(_ULCAST_(1) << 17)
511 #define CONF_EW			(_ULCAST_(3) << 18)
512 #define CONF_EP			(_ULCAST_(15)<< 24)
513 #define CONF_EC			(_ULCAST_(7) << 28)
514 #define CONF_CM			(_ULCAST_(1) << 31)
515 
516 /* Bits specific to the R4xx0.	*/
517 #define R4K_CONF_SW		(_ULCAST_(1) << 20)
518 #define R4K_CONF_SS		(_ULCAST_(1) << 21)
519 #define R4K_CONF_SB		(_ULCAST_(3) << 22)
520 
521 /* Bits specific to the R5000.	*/
522 #define R5K_CONF_SE		(_ULCAST_(1) << 12)
523 #define R5K_CONF_SS		(_ULCAST_(3) << 20)
524 
525 /* Bits specific to the RM7000.	 */
526 #define RM7K_CONF_SE		(_ULCAST_(1) <<	 3)
527 #define RM7K_CONF_TE		(_ULCAST_(1) << 12)
528 #define RM7K_CONF_CLK		(_ULCAST_(1) << 16)
529 #define RM7K_CONF_TC		(_ULCAST_(1) << 17)
530 #define RM7K_CONF_SI		(_ULCAST_(3) << 20)
531 #define RM7K_CONF_SC		(_ULCAST_(1) << 31)
532 
533 /* Bits specific to the R10000.	 */
534 #define R10K_CONF_DN		(_ULCAST_(3) <<	 3)
535 #define R10K_CONF_CT		(_ULCAST_(1) <<	 5)
536 #define R10K_CONF_PE		(_ULCAST_(1) <<	 6)
537 #define R10K_CONF_PM		(_ULCAST_(3) <<	 7)
538 #define R10K_CONF_EC		(_ULCAST_(15)<<	 9)
539 #define R10K_CONF_SB		(_ULCAST_(1) << 13)
540 #define R10K_CONF_SK		(_ULCAST_(1) << 14)
541 #define R10K_CONF_SS		(_ULCAST_(7) << 16)
542 #define R10K_CONF_SC		(_ULCAST_(7) << 19)
543 #define R10K_CONF_DC		(_ULCAST_(7) << 26)
544 #define R10K_CONF_IC		(_ULCAST_(7) << 29)
545 
546 /* Bits specific to the VR41xx.	 */
547 #define VR41_CONF_CS		(_ULCAST_(1) << 12)
548 #define VR41_CONF_P4K		(_ULCAST_(1) << 13)
549 #define VR41_CONF_BP		(_ULCAST_(1) << 16)
550 #define VR41_CONF_M16		(_ULCAST_(1) << 20)
551 #define VR41_CONF_AD		(_ULCAST_(1) << 23)
552 
553 /* Bits specific to the R30xx.	*/
554 #define R30XX_CONF_FDM		(_ULCAST_(1) << 19)
555 #define R30XX_CONF_REV		(_ULCAST_(1) << 22)
556 #define R30XX_CONF_AC		(_ULCAST_(1) << 23)
557 #define R30XX_CONF_RF		(_ULCAST_(1) << 24)
558 #define R30XX_CONF_HALT		(_ULCAST_(1) << 25)
559 #define R30XX_CONF_FPINT	(_ULCAST_(7) << 26)
560 #define R30XX_CONF_DBR		(_ULCAST_(1) << 29)
561 #define R30XX_CONF_SB		(_ULCAST_(1) << 30)
562 #define R30XX_CONF_LOCK		(_ULCAST_(1) << 31)
563 
564 /* Bits specific to the TX49.  */
565 #define TX49_CONF_DC		(_ULCAST_(1) << 16)
566 #define TX49_CONF_IC		(_ULCAST_(1) << 17)  /* conflict with CONF_SC */
567 #define TX49_CONF_HALT		(_ULCAST_(1) << 18)
568 #define TX49_CONF_CWFON		(_ULCAST_(1) << 27)
569 
570 /* Bits specific to the MIPS32/64 PRA.	*/
571 #define MIPS_CONF_VI		(_ULCAST_(1) <<  3)
572 #define MIPS_CONF_MT		(_ULCAST_(7) <<	 7)
573 #define MIPS_CONF_MT_TLB	(_ULCAST_(1) <<  7)
574 #define MIPS_CONF_MT_FTLB	(_ULCAST_(4) <<  7)
575 #define MIPS_CONF_AR		(_ULCAST_(7) << 10)
576 #define MIPS_CONF_AT		(_ULCAST_(3) << 13)
577 #define MIPS_CONF_BE		(_ULCAST_(1) << 15)
578 #define MIPS_CONF_BM		(_ULCAST_(1) << 16)
579 #define MIPS_CONF_MM		(_ULCAST_(3) << 17)
580 #define MIPS_CONF_MM_SYSAD	(_ULCAST_(1) << 17)
581 #define MIPS_CONF_MM_FULL	(_ULCAST_(2) << 17)
582 #define MIPS_CONF_SB		(_ULCAST_(1) << 21)
583 #define MIPS_CONF_UDI		(_ULCAST_(1) << 22)
584 #define MIPS_CONF_DSP		(_ULCAST_(1) << 23)
585 #define MIPS_CONF_ISP		(_ULCAST_(1) << 24)
586 #define MIPS_CONF_KU		(_ULCAST_(3) << 25)
587 #define MIPS_CONF_K23		(_ULCAST_(3) << 28)
588 #define MIPS_CONF_M		(_ULCAST_(1) << 31)
589 
590 /*
591  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
592  */
593 #define MIPS_CONF1_FP		(_ULCAST_(1) <<	 0)
594 #define MIPS_CONF1_EP		(_ULCAST_(1) <<	 1)
595 #define MIPS_CONF1_CA		(_ULCAST_(1) <<	 2)
596 #define MIPS_CONF1_WR		(_ULCAST_(1) <<	 3)
597 #define MIPS_CONF1_PC		(_ULCAST_(1) <<	 4)
598 #define MIPS_CONF1_MD		(_ULCAST_(1) <<	 5)
599 #define MIPS_CONF1_C2		(_ULCAST_(1) <<	 6)
600 #define MIPS_CONF1_DA_SHF	7
601 #define MIPS_CONF1_DA_SZ	3
602 #define MIPS_CONF1_DA		(_ULCAST_(7) <<	 7)
603 #define MIPS_CONF1_DL_SHF	10
604 #define MIPS_CONF1_DL_SZ	3
605 #define MIPS_CONF1_DL		(_ULCAST_(7) << 10)
606 #define MIPS_CONF1_DS_SHF	13
607 #define MIPS_CONF1_DS_SZ	3
608 #define MIPS_CONF1_DS		(_ULCAST_(7) << 13)
609 #define MIPS_CONF1_IA_SHF	16
610 #define MIPS_CONF1_IA_SZ	3
611 #define MIPS_CONF1_IA		(_ULCAST_(7) << 16)
612 #define MIPS_CONF1_IL_SHF	19
613 #define MIPS_CONF1_IL_SZ	3
614 #define MIPS_CONF1_IL		(_ULCAST_(7) << 19)
615 #define MIPS_CONF1_IS_SHF	22
616 #define MIPS_CONF1_IS_SZ	3
617 #define MIPS_CONF1_IS		(_ULCAST_(7) << 22)
618 #define MIPS_CONF1_TLBS_SHIFT   (25)
619 #define MIPS_CONF1_TLBS_SIZE    (6)
620 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
621 
622 #define MIPS_CONF2_SA		(_ULCAST_(15)<<	 0)
623 #define MIPS_CONF2_SL		(_ULCAST_(15)<<	 4)
624 #define MIPS_CONF2_SS		(_ULCAST_(15)<<	 8)
625 #define MIPS_CONF2_SU		(_ULCAST_(15)<< 12)
626 #define MIPS_CONF2_TA		(_ULCAST_(15)<< 16)
627 #define MIPS_CONF2_TL		(_ULCAST_(15)<< 20)
628 #define MIPS_CONF2_TS		(_ULCAST_(15)<< 24)
629 #define MIPS_CONF2_TU		(_ULCAST_(7) << 28)
630 
631 #define MIPS_CONF3_TL		(_ULCAST_(1) <<	 0)
632 #define MIPS_CONF3_SM		(_ULCAST_(1) <<	 1)
633 #define MIPS_CONF3_MT		(_ULCAST_(1) <<	 2)
634 #define MIPS_CONF3_CDMM		(_ULCAST_(1) <<	 3)
635 #define MIPS_CONF3_SP		(_ULCAST_(1) <<	 4)
636 #define MIPS_CONF3_VINT		(_ULCAST_(1) <<	 5)
637 #define MIPS_CONF3_VEIC		(_ULCAST_(1) <<	 6)
638 #define MIPS_CONF3_LPA		(_ULCAST_(1) <<	 7)
639 #define MIPS_CONF3_ITL		(_ULCAST_(1) <<	 8)
640 #define MIPS_CONF3_CTXTC	(_ULCAST_(1) <<	 9)
641 #define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)
642 #define MIPS_CONF3_DSP2P	(_ULCAST_(1) << 11)
643 #define MIPS_CONF3_RXI		(_ULCAST_(1) << 12)
644 #define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)
645 #define MIPS_CONF3_ISA		(_ULCAST_(3) << 14)
646 #define MIPS_CONF3_ISA_OE	(_ULCAST_(1) << 16)
647 #define MIPS_CONF3_MCU		(_ULCAST_(1) << 17)
648 #define MIPS_CONF3_MMAR		(_ULCAST_(7) << 18)
649 #define MIPS_CONF3_IPLW		(_ULCAST_(3) << 21)
650 #define MIPS_CONF3_VZ		(_ULCAST_(1) << 23)
651 #define MIPS_CONF3_PW		(_ULCAST_(1) << 24)
652 #define MIPS_CONF3_SC		(_ULCAST_(1) << 25)
653 #define MIPS_CONF3_BI		(_ULCAST_(1) << 26)
654 #define MIPS_CONF3_BP		(_ULCAST_(1) << 27)
655 #define MIPS_CONF3_MSA		(_ULCAST_(1) << 28)
656 #define MIPS_CONF3_CMGCR	(_ULCAST_(1) << 29)
657 #define MIPS_CONF3_BPG		(_ULCAST_(1) << 30)
658 
659 #define MIPS_CONF4_MMUSIZEEXT_SHIFT	(0)
660 #define MIPS_CONF4_MMUSIZEEXT	(_ULCAST_(255) << 0)
661 #define MIPS_CONF4_FTLBSETS_SHIFT	(0)
662 #define MIPS_CONF4_FTLBSETS	(_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
663 #define MIPS_CONF4_FTLBWAYS_SHIFT	(4)
664 #define MIPS_CONF4_FTLBWAYS	(_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
665 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT	(8)
666 /* bits 10:8 in FTLB-only configurations */
667 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
668 /* bits 12:8 in VTLB-FTLB only configurations */
669 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
670 #define MIPS_CONF4_MMUEXTDEF	(_ULCAST_(3) << 14)
671 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
672 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT	(_ULCAST_(2) << 14)
673 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT	(_ULCAST_(3) << 14)
674 #define MIPS_CONF4_KSCREXIST_SHIFT	(16)
675 #define MIPS_CONF4_KSCREXIST	(_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
676 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT	(24)
677 #define MIPS_CONF4_VTLBSIZEEXT	(_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
678 #define MIPS_CONF4_AE		(_ULCAST_(1) << 28)
679 #define MIPS_CONF4_IE		(_ULCAST_(3) << 29)
680 #define MIPS_CONF4_TLBINV	(_ULCAST_(2) << 29)
681 
682 #define MIPS_CONF5_NF		(_ULCAST_(1) << 0)
683 #define MIPS_CONF5_UFR		(_ULCAST_(1) << 2)
684 #define MIPS_CONF5_MRP		(_ULCAST_(1) << 3)
685 #define MIPS_CONF5_LLB		(_ULCAST_(1) << 4)
686 #define MIPS_CONF5_MVH		(_ULCAST_(1) << 5)
687 #define MIPS_CONF5_VP		(_ULCAST_(1) << 7)
688 #define MIPS_CONF5_SBRI		(_ULCAST_(1) << 6)
689 #define MIPS_CONF5_FRE		(_ULCAST_(1) << 8)
690 #define MIPS_CONF5_UFE		(_ULCAST_(1) << 9)
691 #define MIPS_CONF5_CA2		(_ULCAST_(1) << 14)
692 #define MIPS_CONF5_MI		(_ULCAST_(1) << 17)
693 #define MIPS_CONF5_CRCP		(_ULCAST_(1) << 18)
694 #define MIPS_CONF5_MSAEN	(_ULCAST_(1) << 27)
695 #define MIPS_CONF5_EVA		(_ULCAST_(1) << 28)
696 #define MIPS_CONF5_CV		(_ULCAST_(1) << 29)
697 #define MIPS_CONF5_K		(_ULCAST_(1) << 30)
698 
699 /* Config6 feature bits for proAptiv/P5600 */
700 
701 /* Jump register cache prediction disable */
702 #define MTI_CONF6_JRCD		(_ULCAST_(1) << 0)
703 /* MIPSr6 extensions enable */
704 #define MTI_CONF6_R6		(_ULCAST_(1) << 2)
705 /* IFU Performance Control */
706 #define MTI_CONF6_IFUPERFCTL	(_ULCAST_(3) << 10)
707 #define MTI_CONF6_SYND		(_ULCAST_(1) << 13)
708 /* Sleep state performance counter disable */
709 #define MTI_CONF6_SPCD		(_ULCAST_(1) << 14)
710 /* proAptiv FTLB on/off bit */
711 #define MTI_CONF6_FTLBEN	(_ULCAST_(1) << 15)
712 /* Disable load/store bonding */
713 #define MTI_CONF6_DLSB		(_ULCAST_(1) << 21)
714 /* FTLB probability bits */
715 #define MTI_CONF6_FTLBP_SHIFT	(16)
716 
717 /* Config6 feature bits for Loongson-3 */
718 
719 /* Loongson-3 internal timer bit */
720 #define LOONGSON_CONF6_INTIMER	(_ULCAST_(1) << 6)
721 /* Loongson-3 external timer bit */
722 #define LOONGSON_CONF6_EXTIMER	(_ULCAST_(1) << 7)
723 /* Loongson-3 SFB on/off bit, STFill in manual */
724 #define LOONGSON_CONF6_SFBEN	(_ULCAST_(1) << 8)
725 /* Loongson-3's LL on exclusive cacheline */
726 #define LOONGSON_CONF6_LLEXC	(_ULCAST_(1) << 16)
727 /* Loongson-3's SC has a random delay */
728 #define LOONGSON_CONF6_SCRAND	(_ULCAST_(1) << 17)
729 /* Loongson-3 FTLB on/off bit, VTLBOnly in manual */
730 #define LOONGSON_CONF6_FTLBDIS	(_ULCAST_(1) << 22)
731 
732 #define MIPS_CONF7_WII		(_ULCAST_(1) << 31)
733 
734 #define MIPS_CONF7_RPS		(_ULCAST_(1) << 2)
735 
736 #define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)
737 #define MIPS_CONF7_AR		(_ULCAST_(1) << 16)
738 
739 /* Ingenic HPTLB off bits */
740 #define XBURST_PAGECTRL_HPTLB_DIS 0xa9000000
741 
742 /* Ingenic Config7 bits */
743 #define MIPS_CONF7_BTB_LOOP_EN	(_ULCAST_(1) << 4)
744 
745 /* Config7 Bits specific to MIPS Technologies. */
746 
747 /* Performance counters implemented Per TC */
748 #define MTI_CONF7_PTC		(_ULCAST_(1) << 19)
749 
750 /* WatchLo* register definitions */
751 #define MIPS_WATCHLO_IRW	(_ULCAST_(0x7) << 0)
752 
753 /* WatchHi* register definitions */
754 #define MIPS_WATCHHI_M		(_ULCAST_(1) << 31)
755 #define MIPS_WATCHHI_G		(_ULCAST_(1) << 30)
756 #define MIPS_WATCHHI_WM		(_ULCAST_(0x3) << 28)
757 #define MIPS_WATCHHI_WM_R_RVA	(_ULCAST_(0) << 28)
758 #define MIPS_WATCHHI_WM_R_GPA	(_ULCAST_(1) << 28)
759 #define MIPS_WATCHHI_WM_G_GVA	(_ULCAST_(2) << 28)
760 #define MIPS_WATCHHI_EAS	(_ULCAST_(0x3) << 24)
761 #define MIPS_WATCHHI_ASID	(_ULCAST_(0xff) << 16)
762 #define MIPS_WATCHHI_MASK	(_ULCAST_(0x1ff) << 3)
763 #define MIPS_WATCHHI_I		(_ULCAST_(1) << 2)
764 #define MIPS_WATCHHI_R		(_ULCAST_(1) << 1)
765 #define MIPS_WATCHHI_W		(_ULCAST_(1) << 0)
766 #define MIPS_WATCHHI_IRW	(_ULCAST_(0x7) << 0)
767 
768 /* PerfCnt control register definitions */
769 #define MIPS_PERFCTRL_EXL	(_ULCAST_(1) << 0)
770 #define MIPS_PERFCTRL_K		(_ULCAST_(1) << 1)
771 #define MIPS_PERFCTRL_S		(_ULCAST_(1) << 2)
772 #define MIPS_PERFCTRL_U		(_ULCAST_(1) << 3)
773 #define MIPS_PERFCTRL_IE	(_ULCAST_(1) << 4)
774 #define MIPS_PERFCTRL_EVENT_S	5
775 #define MIPS_PERFCTRL_EVENT	(_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
776 #define MIPS_PERFCTRL_PCTD	(_ULCAST_(1) << 15)
777 #define MIPS_PERFCTRL_EC	(_ULCAST_(0x3) << 23)
778 #define MIPS_PERFCTRL_EC_R	(_ULCAST_(0) << 23)
779 #define MIPS_PERFCTRL_EC_RI	(_ULCAST_(1) << 23)
780 #define MIPS_PERFCTRL_EC_G	(_ULCAST_(2) << 23)
781 #define MIPS_PERFCTRL_EC_GRI	(_ULCAST_(3) << 23)
782 #define MIPS_PERFCTRL_W		(_ULCAST_(1) << 30)
783 #define MIPS_PERFCTRL_M		(_ULCAST_(1) << 31)
784 
785 /* PerfCnt control register MT extensions used by MIPS cores */
786 #define MIPS_PERFCTRL_VPEID_S	16
787 #define MIPS_PERFCTRL_VPEID	(_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
788 #define MIPS_PERFCTRL_TCID_S	22
789 #define MIPS_PERFCTRL_TCID	(_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
790 #define MIPS_PERFCTRL_MT_EN	(_ULCAST_(0x3) << 20)
791 #define MIPS_PERFCTRL_MT_EN_ALL	(_ULCAST_(0) << 20)
792 #define MIPS_PERFCTRL_MT_EN_VPE	(_ULCAST_(1) << 20)
793 #define MIPS_PERFCTRL_MT_EN_TC	(_ULCAST_(2) << 20)
794 
795 /* PerfCnt control register MT extensions used by BMIPS5000 */
796 #define BRCM_PERFCTRL_TC	(_ULCAST_(1) << 30)
797 
798 /* PerfCnt control register MT extensions used by Netlogic XLR */
799 #define XLR_PERFCTRL_ALLTHREADS	(_ULCAST_(1) << 13)
800 
801 /* MAAR bit definitions */
802 #define MIPS_MAAR_VH		(_U64CAST_(1) << 63)
803 #define MIPS_MAAR_ADDR		GENMASK_ULL(55, 12)
804 #define MIPS_MAAR_ADDR_SHIFT	12
805 #define MIPS_MAAR_S		(_ULCAST_(1) << 1)
806 #define MIPS_MAAR_VL		(_ULCAST_(1) << 0)
807 #ifdef CONFIG_XPA
808 #define MIPS_MAAR_V		(MIPS_MAAR_VH | MIPS_MAAR_VL)
809 #else
810 #define MIPS_MAAR_V		MIPS_MAAR_VL
811 #endif
812 #define MIPS_MAARX_VH		(_ULCAST_(1) << 31)
813 #define MIPS_MAARX_ADDR		0xF
814 #define MIPS_MAARX_ADDR_SHIFT	32
815 
816 /* MAARI bit definitions */
817 #define MIPS_MAARI_INDEX	(_ULCAST_(0x3f) << 0)
818 
819 /* EBase bit definitions */
820 #define MIPS_EBASE_CPUNUM_SHIFT	0
821 #define MIPS_EBASE_CPUNUM	(_ULCAST_(0x3ff) << 0)
822 #define MIPS_EBASE_WG_SHIFT	11
823 #define MIPS_EBASE_WG		(_ULCAST_(1) << 11)
824 #define MIPS_EBASE_BASE_SHIFT	12
825 #define MIPS_EBASE_BASE		(~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
826 
827 /* CMGCRBase bit definitions */
828 #define MIPS_CMGCRB_BASE	11
829 #define MIPS_CMGCRF_BASE	(~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
830 
831 /* LLAddr bit definitions */
832 #define MIPS_LLADDR_LLB_SHIFT	0
833 #define MIPS_LLADDR_LLB		(_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
834 
835 /*
836  * Bits in the MIPS32 Memory Segmentation registers.
837  */
838 #define MIPS_SEGCFG_PA_SHIFT	9
839 #define MIPS_SEGCFG_PA		(_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
840 #define MIPS_SEGCFG_AM_SHIFT	4
841 #define MIPS_SEGCFG_AM		(_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
842 #define MIPS_SEGCFG_EU_SHIFT	3
843 #define MIPS_SEGCFG_EU		(_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
844 #define MIPS_SEGCFG_C_SHIFT	0
845 #define MIPS_SEGCFG_C		(_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
846 
847 #define MIPS_SEGCFG_UUSK	_ULCAST_(7)
848 #define MIPS_SEGCFG_USK		_ULCAST_(5)
849 #define MIPS_SEGCFG_MUSUK	_ULCAST_(4)
850 #define MIPS_SEGCFG_MUSK	_ULCAST_(3)
851 #define MIPS_SEGCFG_MSK		_ULCAST_(2)
852 #define MIPS_SEGCFG_MK		_ULCAST_(1)
853 #define MIPS_SEGCFG_UK		_ULCAST_(0)
854 
855 #define MIPS_PWFIELD_GDI_SHIFT	24
856 #define MIPS_PWFIELD_GDI_MASK	0x3f000000
857 #define MIPS_PWFIELD_UDI_SHIFT	18
858 #define MIPS_PWFIELD_UDI_MASK	0x00fc0000
859 #define MIPS_PWFIELD_MDI_SHIFT	12
860 #define MIPS_PWFIELD_MDI_MASK	0x0003f000
861 #define MIPS_PWFIELD_PTI_SHIFT	6
862 #define MIPS_PWFIELD_PTI_MASK	0x00000fc0
863 #define MIPS_PWFIELD_PTEI_SHIFT	0
864 #define MIPS_PWFIELD_PTEI_MASK	0x0000003f
865 
866 #define MIPS_PWSIZE_PS_SHIFT	30
867 #define MIPS_PWSIZE_PS_MASK	0x40000000
868 #define MIPS_PWSIZE_GDW_SHIFT	24
869 #define MIPS_PWSIZE_GDW_MASK	0x3f000000
870 #define MIPS_PWSIZE_UDW_SHIFT	18
871 #define MIPS_PWSIZE_UDW_MASK	0x00fc0000
872 #define MIPS_PWSIZE_MDW_SHIFT	12
873 #define MIPS_PWSIZE_MDW_MASK	0x0003f000
874 #define MIPS_PWSIZE_PTW_SHIFT	6
875 #define MIPS_PWSIZE_PTW_MASK	0x00000fc0
876 #define MIPS_PWSIZE_PTEW_SHIFT	0
877 #define MIPS_PWSIZE_PTEW_MASK	0x0000003f
878 
879 #define MIPS_PWCTL_PWEN_SHIFT	31
880 #define MIPS_PWCTL_PWEN_MASK	0x80000000
881 #define MIPS_PWCTL_XK_SHIFT	28
882 #define MIPS_PWCTL_XK_MASK	0x10000000
883 #define MIPS_PWCTL_XS_SHIFT	27
884 #define MIPS_PWCTL_XS_MASK	0x08000000
885 #define MIPS_PWCTL_XU_SHIFT	26
886 #define MIPS_PWCTL_XU_MASK	0x04000000
887 #define MIPS_PWCTL_DPH_SHIFT	7
888 #define MIPS_PWCTL_DPH_MASK	0x00000080
889 #define MIPS_PWCTL_HUGEPG_SHIFT	6
890 #define MIPS_PWCTL_HUGEPG_MASK	0x00000060
891 #define MIPS_PWCTL_PSN_SHIFT	0
892 #define MIPS_PWCTL_PSN_MASK	0x0000003f
893 
894 /* GuestCtl0 fields */
895 #define MIPS_GCTL0_GM_SHIFT	31
896 #define MIPS_GCTL0_GM		(_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
897 #define MIPS_GCTL0_RI_SHIFT	30
898 #define MIPS_GCTL0_RI		(_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
899 #define MIPS_GCTL0_MC_SHIFT	29
900 #define MIPS_GCTL0_MC		(_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
901 #define MIPS_GCTL0_CP0_SHIFT	28
902 #define MIPS_GCTL0_CP0		(_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
903 #define MIPS_GCTL0_AT_SHIFT	26
904 #define MIPS_GCTL0_AT		(_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
905 #define MIPS_GCTL0_GT_SHIFT	25
906 #define MIPS_GCTL0_GT		(_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
907 #define MIPS_GCTL0_CG_SHIFT	24
908 #define MIPS_GCTL0_CG		(_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
909 #define MIPS_GCTL0_CF_SHIFT	23
910 #define MIPS_GCTL0_CF		(_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
911 #define MIPS_GCTL0_G1_SHIFT	22
912 #define MIPS_GCTL0_G1		(_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
913 #define MIPS_GCTL0_G0E_SHIFT	19
914 #define MIPS_GCTL0_G0E		(_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
915 #define MIPS_GCTL0_PT_SHIFT	18
916 #define MIPS_GCTL0_PT		(_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
917 #define MIPS_GCTL0_RAD_SHIFT	9
918 #define MIPS_GCTL0_RAD		(_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
919 #define MIPS_GCTL0_DRG_SHIFT	8
920 #define MIPS_GCTL0_DRG		(_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
921 #define MIPS_GCTL0_G2_SHIFT	7
922 #define MIPS_GCTL0_G2		(_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
923 #define MIPS_GCTL0_GEXC_SHIFT	2
924 #define MIPS_GCTL0_GEXC		(_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
925 #define MIPS_GCTL0_SFC2_SHIFT	1
926 #define MIPS_GCTL0_SFC2		(_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
927 #define MIPS_GCTL0_SFC1_SHIFT	0
928 #define MIPS_GCTL0_SFC1		(_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
929 
930 /* GuestCtl0.AT Guest address translation control */
931 #define MIPS_GCTL0_AT_ROOT	1  /* Guest MMU under Root control */
932 #define MIPS_GCTL0_AT_GUEST	3  /* Guest MMU under Guest control */
933 
934 /* GuestCtl0.GExcCode Hypervisor exception cause codes */
935 #define MIPS_GCTL0_GEXC_GPSI	0  /* Guest Privileged Sensitive Instruction */
936 #define MIPS_GCTL0_GEXC_GSFC	1  /* Guest Software Field Change */
937 #define MIPS_GCTL0_GEXC_HC	2  /* Hypercall */
938 #define MIPS_GCTL0_GEXC_GRR	3  /* Guest Reserved Instruction Redirect */
939 #define MIPS_GCTL0_GEXC_GVA	8  /* Guest Virtual Address available */
940 #define MIPS_GCTL0_GEXC_GHFC	9  /* Guest Hardware Field Change */
941 #define MIPS_GCTL0_GEXC_GPA	10 /* Guest Physical Address available */
942 
943 /* GuestCtl0Ext fields */
944 #define MIPS_GCTL0EXT_RPW_SHIFT	8
945 #define MIPS_GCTL0EXT_RPW	(_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
946 #define MIPS_GCTL0EXT_NCC_SHIFT	6
947 #define MIPS_GCTL0EXT_NCC	(_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
948 #define MIPS_GCTL0EXT_CGI_SHIFT	4
949 #define MIPS_GCTL0EXT_CGI	(_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
950 #define MIPS_GCTL0EXT_FCD_SHIFT	3
951 #define MIPS_GCTL0EXT_FCD	(_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
952 #define MIPS_GCTL0EXT_OG_SHIFT	2
953 #define MIPS_GCTL0EXT_OG	(_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
954 #define MIPS_GCTL0EXT_BG_SHIFT	1
955 #define MIPS_GCTL0EXT_BG	(_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
956 #define MIPS_GCTL0EXT_MG_SHIFT	0
957 #define MIPS_GCTL0EXT_MG	(_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
958 
959 /* GuestCtl0Ext.RPW Root page walk configuration */
960 #define MIPS_GCTL0EXT_RPW_BOTH	0  /* Root PW for GPA->RPA and RVA->RPA */
961 #define MIPS_GCTL0EXT_RPW_GPA	2  /* Root PW for GPA->RPA */
962 #define MIPS_GCTL0EXT_RPW_RVA	3  /* Root PW for RVA->RPA */
963 
964 /* GuestCtl0Ext.NCC Nested cache coherency attributes */
965 #define MIPS_GCTL0EXT_NCC_IND	0  /* Guest CCA independent of Root CCA */
966 #define MIPS_GCTL0EXT_NCC_MOD	1  /* Guest CCA modified by Root CCA */
967 
968 /* GuestCtl1 fields */
969 #define MIPS_GCTL1_ID_SHIFT	0
970 #define MIPS_GCTL1_ID_WIDTH	8
971 #define MIPS_GCTL1_ID		(_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
972 #define MIPS_GCTL1_RID_SHIFT	16
973 #define MIPS_GCTL1_RID_WIDTH	8
974 #define MIPS_GCTL1_RID		(_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
975 #define MIPS_GCTL1_EID_SHIFT	24
976 #define MIPS_GCTL1_EID_WIDTH	8
977 #define MIPS_GCTL1_EID		(_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
978 
979 /* GuestID reserved for root context */
980 #define MIPS_GCTL1_ROOT_GUESTID	0
981 
982 /* CDMMBase register bit definitions */
983 #define MIPS_CDMMBASE_SIZE_SHIFT 0
984 #define MIPS_CDMMBASE_SIZE	(_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
985 #define MIPS_CDMMBASE_CI	(_ULCAST_(1) << 9)
986 #define MIPS_CDMMBASE_EN	(_ULCAST_(1) << 10)
987 #define MIPS_CDMMBASE_ADDR_SHIFT 11
988 #define MIPS_CDMMBASE_ADDR_START 15
989 
990 /* RDHWR register numbers */
991 #define MIPS_HWR_CPUNUM		0	/* CPU number */
992 #define MIPS_HWR_SYNCISTEP	1	/* SYNCI step size */
993 #define MIPS_HWR_CC		2	/* Cycle counter */
994 #define MIPS_HWR_CCRES		3	/* Cycle counter resolution */
995 #define MIPS_HWR_ULR		29	/* UserLocal */
996 #define MIPS_HWR_IMPL1		30	/* Implementation dependent */
997 #define MIPS_HWR_IMPL2		31	/* Implementation dependent */
998 
999 /* Bits in HWREna register */
1000 #define MIPS_HWRENA_CPUNUM	(_ULCAST_(1) << MIPS_HWR_CPUNUM)
1001 #define MIPS_HWRENA_SYNCISTEP	(_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
1002 #define MIPS_HWRENA_CC		(_ULCAST_(1) << MIPS_HWR_CC)
1003 #define MIPS_HWRENA_CCRES	(_ULCAST_(1) << MIPS_HWR_CCRES)
1004 #define MIPS_HWRENA_ULR		(_ULCAST_(1) << MIPS_HWR_ULR)
1005 #define MIPS_HWRENA_IMPL1	(_ULCAST_(1) << MIPS_HWR_IMPL1)
1006 #define MIPS_HWRENA_IMPL2	(_ULCAST_(1) << MIPS_HWR_IMPL2)
1007 
1008 /*
1009  * Bitfields in the TX39 family CP0 Configuration Register 3
1010  */
1011 #define TX39_CONF_ICS_SHIFT	19
1012 #define TX39_CONF_ICS_MASK	0x00380000
1013 #define TX39_CONF_ICS_1KB	0x00000000
1014 #define TX39_CONF_ICS_2KB	0x00080000
1015 #define TX39_CONF_ICS_4KB	0x00100000
1016 #define TX39_CONF_ICS_8KB	0x00180000
1017 #define TX39_CONF_ICS_16KB	0x00200000
1018 
1019 #define TX39_CONF_DCS_SHIFT	16
1020 #define TX39_CONF_DCS_MASK	0x00070000
1021 #define TX39_CONF_DCS_1KB	0x00000000
1022 #define TX39_CONF_DCS_2KB	0x00010000
1023 #define TX39_CONF_DCS_4KB	0x00020000
1024 #define TX39_CONF_DCS_8KB	0x00030000
1025 #define TX39_CONF_DCS_16KB	0x00040000
1026 
1027 #define TX39_CONF_CWFON		0x00004000
1028 #define TX39_CONF_WBON		0x00002000
1029 #define TX39_CONF_RF_SHIFT	10
1030 #define TX39_CONF_RF_MASK	0x00000c00
1031 #define TX39_CONF_DOZE		0x00000200
1032 #define TX39_CONF_HALT		0x00000100
1033 #define TX39_CONF_LOCK		0x00000080
1034 #define TX39_CONF_ICE		0x00000020
1035 #define TX39_CONF_DCE		0x00000010
1036 #define TX39_CONF_IRSIZE_SHIFT	2
1037 #define TX39_CONF_IRSIZE_MASK	0x0000000c
1038 #define TX39_CONF_DRSIZE_SHIFT	0
1039 #define TX39_CONF_DRSIZE_MASK	0x00000003
1040 
1041 /*
1042  * Interesting Bits in the R10K CP0 Branch Diagnostic Register
1043  */
1044 /* Disable Branch Target Address Cache */
1045 #define R10K_DIAG_D_BTAC	(_ULCAST_(1) << 27)
1046 /* Enable Branch Prediction Global History */
1047 #define R10K_DIAG_E_GHIST	(_ULCAST_(1) << 26)
1048 /* Disable Branch Return Cache */
1049 #define R10K_DIAG_D_BRC		(_ULCAST_(1) << 22)
1050 
1051 /* Flush BTB */
1052 #define LOONGSON_DIAG_BTB	(_ULCAST_(1) << 1)
1053 /* Flush ITLB */
1054 #define LOONGSON_DIAG_ITLB	(_ULCAST_(1) << 2)
1055 /* Flush DTLB */
1056 #define LOONGSON_DIAG_DTLB	(_ULCAST_(1) << 3)
1057 /* Allow some CACHE instructions (CACHE0, 1, 3, 21 and 23) in user mode */
1058 #define LOONGSON_DIAG_UCAC	(_ULCAST_(1) << 8)
1059 /* Flush VTLB */
1060 #define LOONGSON_DIAG_VTLB	(_ULCAST_(1) << 12)
1061 /* Flush FTLB */
1062 #define LOONGSON_DIAG_FTLB	(_ULCAST_(1) << 13)
1063 
1064 /*
1065  * Diag1 (GSCause in Loongson-speak) fields
1066  */
1067 /* Loongson-specific exception code (GSExcCode) */
1068 #define LOONGSON_DIAG1_EXCCODE_SHIFT	2
1069 #define LOONGSON_DIAG1_EXCCODE		GENMASK(6, 2)
1070 
1071 /* CvmCtl register field definitions */
1072 #define CVMCTL_IPPCI_SHIFT	7
1073 #define CVMCTL_IPPCI		(_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
1074 #define CVMCTL_IPTI_SHIFT	4
1075 #define CVMCTL_IPTI		(_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
1076 
1077 /* CvmMemCtl2 register field definitions */
1078 #define CVMMEMCTL2_INHIBITTS	(_U64CAST_(1) << 17)
1079 
1080 /* CvmVMConfig register field definitions */
1081 #define CVMVMCONF_DGHT		(_U64CAST_(1) << 60)
1082 #define CVMVMCONF_MMUSIZEM1_S	12
1083 #define CVMVMCONF_MMUSIZEM1	(_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
1084 #define CVMVMCONF_RMMUSIZEM1_S	0
1085 #define CVMVMCONF_RMMUSIZEM1	(_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
1086 
1087 /* Debug register field definitions */
1088 #define MIPS_DEBUG_DBP_SHIFT	1
1089 #define MIPS_DEBUG_DBP		(_ULCAST_(1) << MIPS_DEBUG_DBP_SHIFT)
1090 
1091 /*
1092  * Coprocessor 1 (FPU) register names
1093  */
1094 #define CP1_REVISION	$0
1095 #define CP1_UFR		$1
1096 #define CP1_UNFR	$4
1097 #define CP1_FCCR	$25
1098 #define CP1_FEXR	$26
1099 #define CP1_FENR	$28
1100 #define CP1_STATUS	$31
1101 
1102 
1103 /*
1104  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
1105  */
1106 #define MIPS_FPIR_S		(_ULCAST_(1) << 16)
1107 #define MIPS_FPIR_D		(_ULCAST_(1) << 17)
1108 #define MIPS_FPIR_PS		(_ULCAST_(1) << 18)
1109 #define MIPS_FPIR_3D		(_ULCAST_(1) << 19)
1110 #define MIPS_FPIR_W		(_ULCAST_(1) << 20)
1111 #define MIPS_FPIR_L		(_ULCAST_(1) << 21)
1112 #define MIPS_FPIR_F64		(_ULCAST_(1) << 22)
1113 #define MIPS_FPIR_HAS2008	(_ULCAST_(1) << 23)
1114 #define MIPS_FPIR_UFRP		(_ULCAST_(1) << 28)
1115 #define MIPS_FPIR_FREP		(_ULCAST_(1) << 29)
1116 
1117 /*
1118  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
1119  */
1120 #define MIPS_FCCR_CONDX_S	0
1121 #define MIPS_FCCR_CONDX		(_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1122 #define MIPS_FCCR_COND0_S	0
1123 #define MIPS_FCCR_COND0		(_ULCAST_(1) << MIPS_FCCR_COND0_S)
1124 #define MIPS_FCCR_COND1_S	1
1125 #define MIPS_FCCR_COND1		(_ULCAST_(1) << MIPS_FCCR_COND1_S)
1126 #define MIPS_FCCR_COND2_S	2
1127 #define MIPS_FCCR_COND2		(_ULCAST_(1) << MIPS_FCCR_COND2_S)
1128 #define MIPS_FCCR_COND3_S	3
1129 #define MIPS_FCCR_COND3		(_ULCAST_(1) << MIPS_FCCR_COND3_S)
1130 #define MIPS_FCCR_COND4_S	4
1131 #define MIPS_FCCR_COND4		(_ULCAST_(1) << MIPS_FCCR_COND4_S)
1132 #define MIPS_FCCR_COND5_S	5
1133 #define MIPS_FCCR_COND5		(_ULCAST_(1) << MIPS_FCCR_COND5_S)
1134 #define MIPS_FCCR_COND6_S	6
1135 #define MIPS_FCCR_COND6		(_ULCAST_(1) << MIPS_FCCR_COND6_S)
1136 #define MIPS_FCCR_COND7_S	7
1137 #define MIPS_FCCR_COND7		(_ULCAST_(1) << MIPS_FCCR_COND7_S)
1138 
1139 /*
1140  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
1141  */
1142 #define MIPS_FENR_FS_S		2
1143 #define MIPS_FENR_FS		(_ULCAST_(1) << MIPS_FENR_FS_S)
1144 
1145 /*
1146  * FPU Status Register Values
1147  */
1148 #define FPU_CSR_COND_S	23					/* $fcc0 */
1149 #define FPU_CSR_COND	(_ULCAST_(1) << FPU_CSR_COND_S)
1150 
1151 #define FPU_CSR_FS_S	24		/* flush denormalised results to 0 */
1152 #define FPU_CSR_FS	(_ULCAST_(1) << FPU_CSR_FS_S)
1153 
1154 #define FPU_CSR_CONDX_S	25					/* $fcc[7:1] */
1155 #define FPU_CSR_CONDX	(_ULCAST_(127) << FPU_CSR_CONDX_S)
1156 #define FPU_CSR_COND1_S	25					/* $fcc1 */
1157 #define FPU_CSR_COND1	(_ULCAST_(1) << FPU_CSR_COND1_S)
1158 #define FPU_CSR_COND2_S	26					/* $fcc2 */
1159 #define FPU_CSR_COND2	(_ULCAST_(1) << FPU_CSR_COND2_S)
1160 #define FPU_CSR_COND3_S	27					/* $fcc3 */
1161 #define FPU_CSR_COND3	(_ULCAST_(1) << FPU_CSR_COND3_S)
1162 #define FPU_CSR_COND4_S	28					/* $fcc4 */
1163 #define FPU_CSR_COND4	(_ULCAST_(1) << FPU_CSR_COND4_S)
1164 #define FPU_CSR_COND5_S	29					/* $fcc5 */
1165 #define FPU_CSR_COND5	(_ULCAST_(1) << FPU_CSR_COND5_S)
1166 #define FPU_CSR_COND6_S	30					/* $fcc6 */
1167 #define FPU_CSR_COND6	(_ULCAST_(1) << FPU_CSR_COND6_S)
1168 #define FPU_CSR_COND7_S	31					/* $fcc7 */
1169 #define FPU_CSR_COND7	(_ULCAST_(1) << FPU_CSR_COND7_S)
1170 
1171 /*
1172  * Bits 22:20 of the FPU Status Register will be read as 0,
1173  * and should be written as zero.
1174  * MAC2008 was removed in Release 5 so we still treat it as
1175  * reserved.
1176  */
1177 #define FPU_CSR_RSVD	(_ULCAST_(7) << 20)
1178 
1179 #define FPU_CSR_MAC2008	(_ULCAST_(1) << 20)
1180 #define FPU_CSR_ABS2008	(_ULCAST_(1) << 19)
1181 #define FPU_CSR_NAN2008	(_ULCAST_(1) << 18)
1182 
1183 /*
1184  * X the exception cause indicator
1185  * E the exception enable
1186  * S the sticky/flag bit
1187 */
1188 #define FPU_CSR_ALL_X	0x0003f000
1189 #define FPU_CSR_UNI_X	0x00020000
1190 #define FPU_CSR_INV_X	0x00010000
1191 #define FPU_CSR_DIV_X	0x00008000
1192 #define FPU_CSR_OVF_X	0x00004000
1193 #define FPU_CSR_UDF_X	0x00002000
1194 #define FPU_CSR_INE_X	0x00001000
1195 
1196 #define FPU_CSR_ALL_E	0x00000f80
1197 #define FPU_CSR_INV_E	0x00000800
1198 #define FPU_CSR_DIV_E	0x00000400
1199 #define FPU_CSR_OVF_E	0x00000200
1200 #define FPU_CSR_UDF_E	0x00000100
1201 #define FPU_CSR_INE_E	0x00000080
1202 
1203 #define FPU_CSR_ALL_S	0x0000007c
1204 #define FPU_CSR_INV_S	0x00000040
1205 #define FPU_CSR_DIV_S	0x00000020
1206 #define FPU_CSR_OVF_S	0x00000010
1207 #define FPU_CSR_UDF_S	0x00000008
1208 #define FPU_CSR_INE_S	0x00000004
1209 
1210 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1211 #define FPU_CSR_RM	0x00000003
1212 #define FPU_CSR_RN	0x0	/* nearest */
1213 #define FPU_CSR_RZ	0x1	/* towards zero */
1214 #define FPU_CSR_RU	0x2	/* towards +Infinity */
1215 #define FPU_CSR_RD	0x3	/* towards -Infinity */
1216 
1217 
1218 #ifndef __ASSEMBLY__
1219 
1220 /*
1221  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1222  */
1223 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1224     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1225 #define get_isa16_mode(x)		((x) & 0x1)
1226 #define msk_isa16_mode(x)		((x) & ~0x1)
1227 #define set_isa16_mode(x)		do { (x) |= 0x1; } while(0)
1228 #else
1229 #define get_isa16_mode(x)		0
1230 #define msk_isa16_mode(x)		(x)
1231 #define set_isa16_mode(x)		do { } while(0)
1232 #endif
1233 
1234 /*
1235  * microMIPS instructions can be 16-bit or 32-bit in length. This
1236  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1237  */
mm_insn_16bit(u16 insn)1238 static inline int mm_insn_16bit(u16 insn)
1239 {
1240 	u16 opcode = (insn >> 10) & 0x7;
1241 
1242 	return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1243 }
1244 
1245 /*
1246  * Helper macros for generating raw instruction encodings in inline asm.
1247  */
1248 #ifdef CONFIG_CPU_MICROMIPS
1249 #define _ASM_INSN16_IF_MM(_enc)			\
1250 	".insn\n\t"				\
1251 	".hword (" #_enc ")\n\t"
1252 #define _ASM_INSN32_IF_MM(_enc)			\
1253 	".insn\n\t"				\
1254 	".hword ((" #_enc ") >> 16)\n\t"	\
1255 	".hword ((" #_enc ") & 0xffff)\n\t"
1256 #else
1257 #define _ASM_INSN_IF_MIPS(_enc)			\
1258 	".insn\n\t"				\
1259 	".word (" #_enc ")\n\t"
1260 #endif
1261 
1262 #ifndef _ASM_INSN16_IF_MM
1263 #define _ASM_INSN16_IF_MM(_enc)
1264 #endif
1265 #ifndef _ASM_INSN32_IF_MM
1266 #define _ASM_INSN32_IF_MM(_enc)
1267 #endif
1268 #ifndef _ASM_INSN_IF_MIPS
1269 #define _ASM_INSN_IF_MIPS(_enc)
1270 #endif
1271 
1272 /*
1273  * parse_r var, r - Helper assembler macro for parsing register names.
1274  *
1275  * This converts the register name in $n form provided in \r to the
1276  * corresponding register number, which is assigned to the variable \var. It is
1277  * needed to allow explicit encoding of instructions in inline assembly where
1278  * registers are chosen by the compiler in $n form, allowing us to avoid using
1279  * fixed register numbers.
1280  *
1281  * It also allows newer instructions (not implemented by the assembler) to be
1282  * transparently implemented using assembler macros, instead of needing separate
1283  * cases depending on toolchain support.
1284  *
1285  * Simple usage example:
1286  * __asm__ __volatile__("parse_r __rt, %0\n\t"
1287  *			".insn\n\t"
1288  *			"# di    %0\n\t"
1289  *			".word   (0x41606000 | (__rt << 16))"
1290  *			: "=r" (status);
1291  */
1292 
1293 /* Match an individual register number and assign to \var */
1294 #define _IFC_REG(n)				\
1295 	".ifc	\\r, $" #n "\n\t"		\
1296 	"\\var	= " #n "\n\t"			\
1297 	".endif\n\t"
1298 
1299 #define _ASM_SET_PARSE_R						\
1300 	".macro	parse_r var r\n\t"					\
1301 	"\\var	= -1\n\t"						\
1302 	_IFC_REG(0)  _IFC_REG(1)  _IFC_REG(2)  _IFC_REG(3)		\
1303 	_IFC_REG(4)  _IFC_REG(5)  _IFC_REG(6)  _IFC_REG(7)		\
1304 	_IFC_REG(8)  _IFC_REG(9)  _IFC_REG(10) _IFC_REG(11)		\
1305 	_IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)		\
1306 	_IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)		\
1307 	_IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)		\
1308 	_IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)		\
1309 	_IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)		\
1310 	".iflt	\\var\n\t"						\
1311 	".error	\"Unable to parse register name \\r\"\n\t"		\
1312 	".endif\n\t"							\
1313 	".endm\n\t"
1314 #define _ASM_UNSET_PARSE_R ".purgem parse_r\n\t"
1315 
1316 /*
1317  * C macros for generating assembler macros for common instruction formats.
1318  *
1319  * The names of the operands can be chosen by the caller, and the encoding of
1320  * register operand \<Rn> is assigned to __<Rn> where it can be accessed from
1321  * the ENC encodings.
1322  */
1323 
1324 /* Instructions with 1 register operand & 1 immediate operand */
1325 #define _ASM_MACRO_1R1I(OP, R1, I2, ENC)				\
1326 		".macro	" #OP " " #R1 ", " #I2 "\n\t"			\
1327 		_ASM_SET_PARSE_R					\
1328 		"parse_r __" #R1 ", \\" #R1 "\n\t"			\
1329 		ENC							\
1330 		_ASM_UNSET_PARSE_R					\
1331 		".endm\n\t"
1332 
1333 /* Instructions with 2 register operands */
1334 #define _ASM_MACRO_2R(OP, R1, R2, ENC)					\
1335 		".macro	" #OP " " #R1 ", " #R2 "\n\t"			\
1336 		_ASM_SET_PARSE_R					\
1337 		"parse_r __" #R1 ", \\" #R1 "\n\t"			\
1338 		"parse_r __" #R2 ", \\" #R2 "\n\t"			\
1339 		ENC							\
1340 		_ASM_UNSET_PARSE_R					\
1341 		".endm\n\t"
1342 
1343 /* Instructions with 3 register operands */
1344 #define _ASM_MACRO_3R(OP, R1, R2, R3, ENC)				\
1345 		".macro	" #OP " " #R1 ", " #R2 ", " #R3 "\n\t"		\
1346 		_ASM_SET_PARSE_R					\
1347 		"parse_r __" #R1 ", \\" #R1 "\n\t"			\
1348 		"parse_r __" #R2 ", \\" #R2 "\n\t"			\
1349 		"parse_r __" #R3 ", \\" #R3 "\n\t"			\
1350 		ENC							\
1351 		_ASM_UNSET_PARSE_R					\
1352 		".endm\n\t"
1353 
1354 /* Instructions with 2 register operands and 1 optional select operand */
1355 #define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC)				\
1356 		".macro	" #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t"	\
1357 		_ASM_SET_PARSE_R					\
1358 		"parse_r __" #R1 ", \\" #R1 "\n\t"			\
1359 		"parse_r __" #R2 ", \\" #R2 "\n\t"			\
1360 		ENC							\
1361 		_ASM_UNSET_PARSE_R					\
1362 		".endm\n\t"
1363 
1364 /*
1365  * TLB Invalidate Flush
1366  */
tlbinvf(void)1367 static inline void tlbinvf(void)
1368 {
1369 	__asm__ __volatile__(
1370 		".set push\n\t"
1371 		".set noreorder\n\t"
1372 		"# tlbinvf\n\t"
1373 		_ASM_INSN_IF_MIPS(0x42000004)
1374 		_ASM_INSN32_IF_MM(0x0000537c)
1375 		".set pop");
1376 }
1377 
1378 
1379 /*
1380  * Functions to access the R10000 performance counters.	 These are basically
1381  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1382  * performance counter number encoded into bits 1 ... 5 of the instruction.
1383  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1384  * disassembler these will look like an access to sel 0 or 1.
1385  */
1386 #define read_r10k_perf_cntr(counter)				\
1387 ({								\
1388 	unsigned int __res;					\
1389 	__asm__ __volatile__(					\
1390 	"mfpc\t%0, %1"						\
1391 	: "=r" (__res)						\
1392 	: "i" (counter));					\
1393 								\
1394 	__res;							\
1395 })
1396 
1397 #define write_r10k_perf_cntr(counter,val)			\
1398 do {								\
1399 	__asm__ __volatile__(					\
1400 	"mtpc\t%0, %1"						\
1401 	:							\
1402 	: "r" (val), "i" (counter));				\
1403 } while (0)
1404 
1405 #define read_r10k_perf_event(counter)				\
1406 ({								\
1407 	unsigned int __res;					\
1408 	__asm__ __volatile__(					\
1409 	"mfps\t%0, %1"						\
1410 	: "=r" (__res)						\
1411 	: "i" (counter));					\
1412 								\
1413 	__res;							\
1414 })
1415 
1416 #define write_r10k_perf_cntl(counter,val)			\
1417 do {								\
1418 	__asm__ __volatile__(					\
1419 	"mtps\t%0, %1"						\
1420 	:							\
1421 	: "r" (val), "i" (counter));				\
1422 } while (0)
1423 
1424 
1425 /*
1426  * Macros to access the system control coprocessor
1427  */
1428 
1429 #define ___read_32bit_c0_register(source, sel, vol)			\
1430 ({ unsigned int __res;							\
1431 	if (sel == 0)							\
1432 		__asm__ vol(						\
1433 			"mfc0\t%0, " #source "\n\t"			\
1434 			: "=r" (__res));				\
1435 	else								\
1436 		__asm__ vol(						\
1437 			".set\tpush\n\t"				\
1438 			".set\tmips32\n\t"				\
1439 			"mfc0\t%0, " #source ", " #sel "\n\t"		\
1440 			".set\tpop\n\t"					\
1441 			: "=r" (__res));				\
1442 	__res;								\
1443 })
1444 
1445 #define ___read_64bit_c0_register(source, sel, vol)			\
1446 ({ unsigned long long __res;						\
1447 	if (sizeof(unsigned long) == 4)					\
1448 		__res = __read_64bit_c0_split(source, sel, vol);	\
1449 	else if (sel == 0)						\
1450 		__asm__ vol(						\
1451 			".set\tpush\n\t"				\
1452 			".set\tmips3\n\t"				\
1453 			"dmfc0\t%0, " #source "\n\t"			\
1454 			".set\tpop"					\
1455 			: "=r" (__res));				\
1456 	else								\
1457 		__asm__ vol(						\
1458 			".set\tpush\n\t"				\
1459 			".set\tmips64\n\t"				\
1460 			"dmfc0\t%0, " #source ", " #sel "\n\t"		\
1461 			".set\tpop"					\
1462 			: "=r" (__res));				\
1463 	__res;								\
1464 })
1465 
1466 #define __read_32bit_c0_register(source, sel)				\
1467 	___read_32bit_c0_register(source, sel, __volatile__)
1468 
1469 #define __read_const_32bit_c0_register(source, sel)			\
1470 	___read_32bit_c0_register(source, sel,)
1471 
1472 #define __read_64bit_c0_register(source, sel)				\
1473 	___read_64bit_c0_register(source, sel, __volatile__)
1474 
1475 #define __read_const_64bit_c0_register(source, sel)			\
1476 	___read_64bit_c0_register(source, sel,)
1477 
1478 #define __write_32bit_c0_register(register, sel, value)			\
1479 do {									\
1480 	if (sel == 0)							\
1481 		__asm__ __volatile__(					\
1482 			"mtc0\t%z0, " #register "\n\t"			\
1483 			: : "Jr" ((unsigned int)(value)));		\
1484 	else								\
1485 		__asm__ __volatile__(					\
1486 			".set\tpush\n\t"				\
1487 			".set\tmips32\n\t"				\
1488 			"mtc0\t%z0, " #register ", " #sel "\n\t"	\
1489 			".set\tpop"					\
1490 			: : "Jr" ((unsigned int)(value)));		\
1491 } while (0)
1492 
1493 #define __write_64bit_c0_register(register, sel, value)			\
1494 do {									\
1495 	if (sizeof(unsigned long) == 4)					\
1496 		__write_64bit_c0_split(register, sel, value);		\
1497 	else if (sel == 0)						\
1498 		__asm__ __volatile__(					\
1499 			".set\tpush\n\t"				\
1500 			".set\tmips3\n\t"				\
1501 			"dmtc0\t%z0, " #register "\n\t"			\
1502 			".set\tpop"					\
1503 			: : "Jr" (value));				\
1504 	else								\
1505 		__asm__ __volatile__(					\
1506 			".set\tpush\n\t"				\
1507 			".set\tmips64\n\t"				\
1508 			"dmtc0\t%z0, " #register ", " #sel "\n\t"	\
1509 			".set\tpop"					\
1510 			: : "Jr" (value));				\
1511 } while (0)
1512 
1513 #define __read_ulong_c0_register(reg, sel)				\
1514 	((sizeof(unsigned long) == 4) ?					\
1515 	(unsigned long) __read_32bit_c0_register(reg, sel) :		\
1516 	(unsigned long) __read_64bit_c0_register(reg, sel))
1517 
1518 #define __read_const_ulong_c0_register(reg, sel)			\
1519 	((sizeof(unsigned long) == 4) ?					\
1520 	(unsigned long) __read_const_32bit_c0_register(reg, sel) :	\
1521 	(unsigned long) __read_const_64bit_c0_register(reg, sel))
1522 
1523 #define __write_ulong_c0_register(reg, sel, val)			\
1524 do {									\
1525 	if (sizeof(unsigned long) == 4)					\
1526 		__write_32bit_c0_register(reg, sel, val);		\
1527 	else								\
1528 		__write_64bit_c0_register(reg, sel, val);		\
1529 } while (0)
1530 
1531 /*
1532  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1533  */
1534 #define __read_32bit_c0_ctrl_register(source)				\
1535 ({ unsigned int __res;							\
1536 	__asm__ __volatile__(						\
1537 		"cfc0\t%0, " #source "\n\t"				\
1538 		: "=r" (__res));					\
1539 	__res;								\
1540 })
1541 
1542 #define __write_32bit_c0_ctrl_register(register, value)			\
1543 do {									\
1544 	__asm__ __volatile__(						\
1545 		"ctc0\t%z0, " #register "\n\t"				\
1546 		: : "Jr" ((unsigned int)(value)));			\
1547 } while (0)
1548 
1549 /*
1550  * These versions are only needed for systems with more than 38 bits of
1551  * physical address space running the 32-bit kernel.  That's none atm :-)
1552  */
1553 #define __read_64bit_c0_split(source, sel, vol)				\
1554 ({									\
1555 	unsigned long long __val;					\
1556 	unsigned long __flags;						\
1557 									\
1558 	local_irq_save(__flags);					\
1559 	if (sel == 0)							\
1560 		__asm__ vol(						\
1561 			".set\tpush\n\t"				\
1562 			".set\tmips64\n\t"				\
1563 			"dmfc0\t%L0, " #source "\n\t"			\
1564 			"dsra\t%M0, %L0, 32\n\t"			\
1565 			"sll\t%L0, %L0, 0\n\t"				\
1566 			".set\tpop"					\
1567 			: "=r" (__val));				\
1568 	else								\
1569 		__asm__ vol(						\
1570 			".set\tpush\n\t"				\
1571 			".set\tmips64\n\t"				\
1572 			"dmfc0\t%L0, " #source ", " #sel "\n\t"		\
1573 			"dsra\t%M0, %L0, 32\n\t"			\
1574 			"sll\t%L0, %L0, 0\n\t"				\
1575 			".set\tpop"					\
1576 			: "=r" (__val));				\
1577 	local_irq_restore(__flags);					\
1578 									\
1579 	__val;								\
1580 })
1581 
1582 #define __write_64bit_c0_split(source, sel, val)			\
1583 do {									\
1584 	unsigned long long __tmp = (val);				\
1585 	unsigned long __flags;						\
1586 									\
1587 	local_irq_save(__flags);					\
1588 	if (MIPS_ISA_REV >= 2)						\
1589 		__asm__ __volatile__(					\
1590 			".set\tpush\n\t"				\
1591 			".set\t" MIPS_ISA_LEVEL "\n\t"			\
1592 			"dins\t%L0, %M0, 32, 32\n\t"			\
1593 			"dmtc0\t%L0, " #source ", " #sel "\n\t"		\
1594 			".set\tpop"					\
1595 			: "+r" (__tmp));				\
1596 	else if (sel == 0)						\
1597 		__asm__ __volatile__(					\
1598 			".set\tpush\n\t"				\
1599 			".set\tmips64\n\t"				\
1600 			"dsll\t%L0, %L0, 32\n\t"			\
1601 			"dsrl\t%L0, %L0, 32\n\t"			\
1602 			"dsll\t%M0, %M0, 32\n\t"			\
1603 			"or\t%L0, %L0, %M0\n\t"				\
1604 			"dmtc0\t%L0, " #source "\n\t"			\
1605 			".set\tpop"					\
1606 			: "+r" (__tmp));				\
1607 	else								\
1608 		__asm__ __volatile__(					\
1609 			".set\tpush\n\t"				\
1610 			".set\tmips64\n\t"				\
1611 			"dsll\t%L0, %L0, 32\n\t"			\
1612 			"dsrl\t%L0, %L0, 32\n\t"			\
1613 			"dsll\t%M0, %M0, 32\n\t"			\
1614 			"or\t%L0, %L0, %M0\n\t"				\
1615 			"dmtc0\t%L0, " #source ", " #sel "\n\t"		\
1616 			".set\tpop"					\
1617 			: "+r" (__tmp));				\
1618 	local_irq_restore(__flags);					\
1619 } while (0)
1620 
1621 #ifndef TOOLCHAIN_SUPPORTS_XPA
1622 #define _ASM_SET_MFHC0							\
1623 	_ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,				\
1624 			 _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)	\
1625 			 _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11))
1626 #define _ASM_UNSET_MFHC0 ".purgem mfhc0\n\t"
1627 #define _ASM_SET_MTHC0							\
1628 	_ASM_MACRO_2R_1S(mthc0, rt, rd, sel,				\
1629 			 _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)	\
1630 			 _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11))
1631 #define _ASM_UNSET_MTHC0 ".purgem mthc0\n\t"
1632 #else	/* !TOOLCHAIN_SUPPORTS_XPA */
1633 #define _ASM_SET_MFHC0 ".set\txpa\n\t"
1634 #define _ASM_SET_MTHC0 ".set\txpa\n\t"
1635 #define _ASM_UNSET_MFHC0
1636 #define _ASM_UNSET_MTHC0
1637 #endif
1638 
1639 #define __readx_32bit_c0_register(source, sel)				\
1640 ({									\
1641 	unsigned int __res;						\
1642 									\
1643 	__asm__ __volatile__(						\
1644 	"	.set	push					\n"	\
1645 	"	.set	mips32r2				\n"	\
1646 	_ASM_SET_MFHC0							\
1647 	"	mfhc0	%0, " #source ", %1			\n"	\
1648 	_ASM_UNSET_MFHC0						\
1649 	"	.set	pop					\n"	\
1650 	: "=r" (__res)							\
1651 	: "i" (sel));							\
1652 	__res;								\
1653 })
1654 
1655 #define __writex_32bit_c0_register(register, sel, value)		\
1656 do {									\
1657 	__asm__ __volatile__(						\
1658 	"	.set	push					\n"	\
1659 	"	.set	mips32r2				\n"	\
1660 	_ASM_SET_MTHC0							\
1661 	"	mthc0	%z0, " #register ", %1			\n"	\
1662 	_ASM_UNSET_MTHC0						\
1663 	"	.set	pop					\n"	\
1664 	:								\
1665 	: "Jr" (value), "i" (sel));					\
1666 } while (0)
1667 
1668 #define read_c0_index()		__read_32bit_c0_register($0, 0)
1669 #define write_c0_index(val)	__write_32bit_c0_register($0, 0, val)
1670 
1671 #define read_c0_random()	__read_32bit_c0_register($1, 0)
1672 #define write_c0_random(val)	__write_32bit_c0_register($1, 0, val)
1673 
1674 #define read_c0_entrylo0()	__read_ulong_c0_register($2, 0)
1675 #define write_c0_entrylo0(val)	__write_ulong_c0_register($2, 0, val)
1676 
1677 #define readx_c0_entrylo0()	__readx_32bit_c0_register($2, 0)
1678 #define writex_c0_entrylo0(val)	__writex_32bit_c0_register($2, 0, val)
1679 
1680 #define read_c0_entrylo1()	__read_ulong_c0_register($3, 0)
1681 #define write_c0_entrylo1(val)	__write_ulong_c0_register($3, 0, val)
1682 
1683 #define readx_c0_entrylo1()	__readx_32bit_c0_register($3, 0)
1684 #define writex_c0_entrylo1(val)	__writex_32bit_c0_register($3, 0, val)
1685 
1686 #define read_c0_conf()		__read_32bit_c0_register($3, 0)
1687 #define write_c0_conf(val)	__write_32bit_c0_register($3, 0, val)
1688 
1689 #define read_c0_globalnumber()	__read_32bit_c0_register($3, 1)
1690 
1691 #define read_c0_context()	__read_ulong_c0_register($4, 0)
1692 #define write_c0_context(val)	__write_ulong_c0_register($4, 0, val)
1693 
1694 #define read_c0_contextconfig()		__read_32bit_c0_register($4, 1)
1695 #define write_c0_contextconfig(val)	__write_32bit_c0_register($4, 1, val)
1696 
1697 #define read_c0_userlocal()	__read_ulong_c0_register($4, 2)
1698 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1699 
1700 #define read_c0_xcontextconfig()	__read_ulong_c0_register($4, 3)
1701 #define write_c0_xcontextconfig(val)	__write_ulong_c0_register($4, 3, val)
1702 
1703 #define read_c0_memorymapid()		__read_32bit_c0_register($4, 5)
1704 #define write_c0_memorymapid(val)	__write_32bit_c0_register($4, 5, val)
1705 
1706 #define read_c0_pagemask()	__read_32bit_c0_register($5, 0)
1707 #define write_c0_pagemask(val)	__write_32bit_c0_register($5, 0, val)
1708 
1709 #define read_c0_pagegrain()	__read_32bit_c0_register($5, 1)
1710 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1711 
1712 #define read_c0_wired()		__read_32bit_c0_register($6, 0)
1713 #define write_c0_wired(val)	__write_32bit_c0_register($6, 0, val)
1714 
1715 #define read_c0_info()		__read_32bit_c0_register($7, 0)
1716 
1717 #define read_c0_cache()		__read_32bit_c0_register($7, 0) /* TX39xx */
1718 #define write_c0_cache(val)	__write_32bit_c0_register($7, 0, val)
1719 
1720 #define read_c0_badvaddr()	__read_ulong_c0_register($8, 0)
1721 #define write_c0_badvaddr(val)	__write_ulong_c0_register($8, 0, val)
1722 
1723 #define read_c0_badinstr()	__read_32bit_c0_register($8, 1)
1724 #define read_c0_badinstrp()	__read_32bit_c0_register($8, 2)
1725 
1726 #define read_c0_count()		__read_32bit_c0_register($9, 0)
1727 #define write_c0_count(val)	__write_32bit_c0_register($9, 0, val)
1728 
1729 #define read_c0_entryhi()	__read_ulong_c0_register($10, 0)
1730 #define write_c0_entryhi(val)	__write_ulong_c0_register($10, 0, val)
1731 
1732 #define read_c0_guestctl1()	__read_32bit_c0_register($10, 4)
1733 #define write_c0_guestctl1(val)	__write_32bit_c0_register($10, 4, val)
1734 
1735 #define read_c0_guestctl2()	__read_32bit_c0_register($10, 5)
1736 #define write_c0_guestctl2(val)	__write_32bit_c0_register($10, 5, val)
1737 
1738 #define read_c0_guestctl3()	__read_32bit_c0_register($10, 6)
1739 #define write_c0_guestctl3(val)	__write_32bit_c0_register($10, 6, val)
1740 
1741 #define read_c0_compare()	__read_32bit_c0_register($11, 0)
1742 #define write_c0_compare(val)	__write_32bit_c0_register($11, 0, val)
1743 
1744 #define read_c0_guestctl0ext()	__read_32bit_c0_register($11, 4)
1745 #define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1746 
1747 #define read_c0_status()	__read_32bit_c0_register($12, 0)
1748 
1749 #define write_c0_status(val)	__write_32bit_c0_register($12, 0, val)
1750 
1751 #define read_c0_guestctl0()	__read_32bit_c0_register($12, 6)
1752 #define write_c0_guestctl0(val)	__write_32bit_c0_register($12, 6, val)
1753 
1754 #define read_c0_gtoffset()	__read_32bit_c0_register($12, 7)
1755 #define write_c0_gtoffset(val)	__write_32bit_c0_register($12, 7, val)
1756 
1757 #define read_c0_cause()		__read_32bit_c0_register($13, 0)
1758 #define write_c0_cause(val)	__write_32bit_c0_register($13, 0, val)
1759 
1760 #define read_c0_epc()		__read_ulong_c0_register($14, 0)
1761 #define write_c0_epc(val)	__write_ulong_c0_register($14, 0, val)
1762 
1763 #define read_c0_prid()		__read_const_32bit_c0_register($15, 0)
1764 
1765 #define read_c0_cmgcrbase()	__read_ulong_c0_register($15, 3)
1766 
1767 #define read_c0_config()	__read_32bit_c0_register($16, 0)
1768 #define read_c0_config1()	__read_32bit_c0_register($16, 1)
1769 #define read_c0_config2()	__read_32bit_c0_register($16, 2)
1770 #define read_c0_config3()	__read_32bit_c0_register($16, 3)
1771 #define read_c0_config4()	__read_32bit_c0_register($16, 4)
1772 #define read_c0_config5()	__read_32bit_c0_register($16, 5)
1773 #define read_c0_config6()	__read_32bit_c0_register($16, 6)
1774 #define read_c0_config7()	__read_32bit_c0_register($16, 7)
1775 #define write_c0_config(val)	__write_32bit_c0_register($16, 0, val)
1776 #define write_c0_config1(val)	__write_32bit_c0_register($16, 1, val)
1777 #define write_c0_config2(val)	__write_32bit_c0_register($16, 2, val)
1778 #define write_c0_config3(val)	__write_32bit_c0_register($16, 3, val)
1779 #define write_c0_config4(val)	__write_32bit_c0_register($16, 4, val)
1780 #define write_c0_config5(val)	__write_32bit_c0_register($16, 5, val)
1781 #define write_c0_config6(val)	__write_32bit_c0_register($16, 6, val)
1782 #define write_c0_config7(val)	__write_32bit_c0_register($16, 7, val)
1783 
1784 #define read_c0_lladdr()	__read_ulong_c0_register($17, 0)
1785 #define write_c0_lladdr(val)	__write_ulong_c0_register($17, 0, val)
1786 #define read_c0_maar()		__read_ulong_c0_register($17, 1)
1787 #define write_c0_maar(val)	__write_ulong_c0_register($17, 1, val)
1788 #define readx_c0_maar()		__readx_32bit_c0_register($17, 1)
1789 #define writex_c0_maar(val)	__writex_32bit_c0_register($17, 1, val)
1790 #define read_c0_maari()		__read_32bit_c0_register($17, 2)
1791 #define write_c0_maari(val)	__write_32bit_c0_register($17, 2, val)
1792 
1793 /*
1794  * The WatchLo register.  There may be up to 8 of them.
1795  */
1796 #define read_c0_watchlo0()	__read_ulong_c0_register($18, 0)
1797 #define read_c0_watchlo1()	__read_ulong_c0_register($18, 1)
1798 #define read_c0_watchlo2()	__read_ulong_c0_register($18, 2)
1799 #define read_c0_watchlo3()	__read_ulong_c0_register($18, 3)
1800 #define read_c0_watchlo4()	__read_ulong_c0_register($18, 4)
1801 #define read_c0_watchlo5()	__read_ulong_c0_register($18, 5)
1802 #define read_c0_watchlo6()	__read_ulong_c0_register($18, 6)
1803 #define read_c0_watchlo7()	__read_ulong_c0_register($18, 7)
1804 #define write_c0_watchlo0(val)	__write_ulong_c0_register($18, 0, val)
1805 #define write_c0_watchlo1(val)	__write_ulong_c0_register($18, 1, val)
1806 #define write_c0_watchlo2(val)	__write_ulong_c0_register($18, 2, val)
1807 #define write_c0_watchlo3(val)	__write_ulong_c0_register($18, 3, val)
1808 #define write_c0_watchlo4(val)	__write_ulong_c0_register($18, 4, val)
1809 #define write_c0_watchlo5(val)	__write_ulong_c0_register($18, 5, val)
1810 #define write_c0_watchlo6(val)	__write_ulong_c0_register($18, 6, val)
1811 #define write_c0_watchlo7(val)	__write_ulong_c0_register($18, 7, val)
1812 
1813 /*
1814  * The WatchHi register.  There may be up to 8 of them.
1815  */
1816 #define read_c0_watchhi0()	__read_32bit_c0_register($19, 0)
1817 #define read_c0_watchhi1()	__read_32bit_c0_register($19, 1)
1818 #define read_c0_watchhi2()	__read_32bit_c0_register($19, 2)
1819 #define read_c0_watchhi3()	__read_32bit_c0_register($19, 3)
1820 #define read_c0_watchhi4()	__read_32bit_c0_register($19, 4)
1821 #define read_c0_watchhi5()	__read_32bit_c0_register($19, 5)
1822 #define read_c0_watchhi6()	__read_32bit_c0_register($19, 6)
1823 #define read_c0_watchhi7()	__read_32bit_c0_register($19, 7)
1824 
1825 #define write_c0_watchhi0(val)	__write_32bit_c0_register($19, 0, val)
1826 #define write_c0_watchhi1(val)	__write_32bit_c0_register($19, 1, val)
1827 #define write_c0_watchhi2(val)	__write_32bit_c0_register($19, 2, val)
1828 #define write_c0_watchhi3(val)	__write_32bit_c0_register($19, 3, val)
1829 #define write_c0_watchhi4(val)	__write_32bit_c0_register($19, 4, val)
1830 #define write_c0_watchhi5(val)	__write_32bit_c0_register($19, 5, val)
1831 #define write_c0_watchhi6(val)	__write_32bit_c0_register($19, 6, val)
1832 #define write_c0_watchhi7(val)	__write_32bit_c0_register($19, 7, val)
1833 
1834 #define read_c0_xcontext()	__read_ulong_c0_register($20, 0)
1835 #define write_c0_xcontext(val)	__write_ulong_c0_register($20, 0, val)
1836 
1837 #define read_c0_intcontrol()	__read_32bit_c0_ctrl_register($20)
1838 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1839 
1840 #define read_c0_framemask()	__read_32bit_c0_register($21, 0)
1841 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1842 
1843 #define read_c0_diag()		__read_32bit_c0_register($22, 0)
1844 #define write_c0_diag(val)	__write_32bit_c0_register($22, 0, val)
1845 
1846 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1847 #define read_c0_r10k_diag()	__read_64bit_c0_register($22, 0)
1848 #define write_c0_r10k_diag(val)	__write_64bit_c0_register($22, 0, val)
1849 
1850 #define read_c0_diag1()		__read_32bit_c0_register($22, 1)
1851 #define write_c0_diag1(val)	__write_32bit_c0_register($22, 1, val)
1852 
1853 #define read_c0_diag2()		__read_32bit_c0_register($22, 2)
1854 #define write_c0_diag2(val)	__write_32bit_c0_register($22, 2, val)
1855 
1856 #define read_c0_diag3()		__read_32bit_c0_register($22, 3)
1857 #define write_c0_diag3(val)	__write_32bit_c0_register($22, 3, val)
1858 
1859 #define read_c0_diag4()		__read_32bit_c0_register($22, 4)
1860 #define write_c0_diag4(val)	__write_32bit_c0_register($22, 4, val)
1861 
1862 #define read_c0_diag5()		__read_32bit_c0_register($22, 5)
1863 #define write_c0_diag5(val)	__write_32bit_c0_register($22, 5, val)
1864 
1865 #define read_c0_debug()		__read_32bit_c0_register($23, 0)
1866 #define write_c0_debug(val)	__write_32bit_c0_register($23, 0, val)
1867 
1868 #define read_c0_depc()		__read_ulong_c0_register($24, 0)
1869 #define write_c0_depc(val)	__write_ulong_c0_register($24, 0, val)
1870 
1871 /*
1872  * MIPS32 / MIPS64 performance counters
1873  */
1874 #define read_c0_perfctrl0()	__read_32bit_c0_register($25, 0)
1875 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1876 #define read_c0_perfcntr0()	__read_32bit_c0_register($25, 1)
1877 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1878 #define read_c0_perfcntr0_64()	__read_64bit_c0_register($25, 1)
1879 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1880 #define read_c0_perfctrl1()	__read_32bit_c0_register($25, 2)
1881 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1882 #define read_c0_perfcntr1()	__read_32bit_c0_register($25, 3)
1883 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1884 #define read_c0_perfcntr1_64()	__read_64bit_c0_register($25, 3)
1885 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1886 #define read_c0_perfctrl2()	__read_32bit_c0_register($25, 4)
1887 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1888 #define read_c0_perfcntr2()	__read_32bit_c0_register($25, 5)
1889 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1890 #define read_c0_perfcntr2_64()	__read_64bit_c0_register($25, 5)
1891 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1892 #define read_c0_perfctrl3()	__read_32bit_c0_register($25, 6)
1893 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1894 #define read_c0_perfcntr3()	__read_32bit_c0_register($25, 7)
1895 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1896 #define read_c0_perfcntr3_64()	__read_64bit_c0_register($25, 7)
1897 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1898 
1899 #define read_c0_ecc()		__read_32bit_c0_register($26, 0)
1900 #define write_c0_ecc(val)	__write_32bit_c0_register($26, 0, val)
1901 
1902 #define read_c0_derraddr0()	__read_ulong_c0_register($26, 1)
1903 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1904 
1905 #define read_c0_cacheerr()	__read_32bit_c0_register($27, 0)
1906 
1907 #define read_c0_derraddr1()	__read_ulong_c0_register($27, 1)
1908 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1909 
1910 #define read_c0_taglo()		__read_32bit_c0_register($28, 0)
1911 #define write_c0_taglo(val)	__write_32bit_c0_register($28, 0, val)
1912 
1913 #define read_c0_dtaglo()	__read_32bit_c0_register($28, 2)
1914 #define write_c0_dtaglo(val)	__write_32bit_c0_register($28, 2, val)
1915 
1916 #define read_c0_ddatalo()	__read_32bit_c0_register($28, 3)
1917 #define write_c0_ddatalo(val)	__write_32bit_c0_register($28, 3, val)
1918 
1919 #define read_c0_staglo()	__read_32bit_c0_register($28, 4)
1920 #define write_c0_staglo(val)	__write_32bit_c0_register($28, 4, val)
1921 
1922 #define read_c0_taghi()		__read_32bit_c0_register($29, 0)
1923 #define write_c0_taghi(val)	__write_32bit_c0_register($29, 0, val)
1924 
1925 #define read_c0_errorepc()	__read_ulong_c0_register($30, 0)
1926 #define write_c0_errorepc(val)	__write_ulong_c0_register($30, 0, val)
1927 
1928 /* MIPSR2 */
1929 #define read_c0_hwrena()	__read_32bit_c0_register($7, 0)
1930 #define write_c0_hwrena(val)	__write_32bit_c0_register($7, 0, val)
1931 
1932 #define read_c0_intctl()	__read_32bit_c0_register($12, 1)
1933 #define write_c0_intctl(val)	__write_32bit_c0_register($12, 1, val)
1934 
1935 #define read_c0_srsctl()	__read_32bit_c0_register($12, 2)
1936 #define write_c0_srsctl(val)	__write_32bit_c0_register($12, 2, val)
1937 
1938 #define read_c0_srsmap()	__read_32bit_c0_register($12, 3)
1939 #define write_c0_srsmap(val)	__write_32bit_c0_register($12, 3, val)
1940 
1941 #define read_c0_ebase()		__read_32bit_c0_register($15, 1)
1942 #define write_c0_ebase(val)	__write_32bit_c0_register($15, 1, val)
1943 
1944 #define read_c0_ebase_64()	__read_64bit_c0_register($15, 1)
1945 #define write_c0_ebase_64(val)	__write_64bit_c0_register($15, 1, val)
1946 
1947 #define read_c0_cdmmbase()	__read_ulong_c0_register($15, 2)
1948 #define write_c0_cdmmbase(val)	__write_ulong_c0_register($15, 2, val)
1949 
1950 /* MIPSR3 */
1951 #define read_c0_segctl0()	__read_32bit_c0_register($5, 2)
1952 #define write_c0_segctl0(val)	__write_32bit_c0_register($5, 2, val)
1953 
1954 #define read_c0_segctl1()	__read_32bit_c0_register($5, 3)
1955 #define write_c0_segctl1(val)	__write_32bit_c0_register($5, 3, val)
1956 
1957 #define read_c0_segctl2()	__read_32bit_c0_register($5, 4)
1958 #define write_c0_segctl2(val)	__write_32bit_c0_register($5, 4, val)
1959 
1960 /* Hardware Page Table Walker */
1961 #define read_c0_pwbase()	__read_ulong_c0_register($5, 5)
1962 #define write_c0_pwbase(val)	__write_ulong_c0_register($5, 5, val)
1963 
1964 #define read_c0_pwfield()	__read_ulong_c0_register($5, 6)
1965 #define write_c0_pwfield(val)	__write_ulong_c0_register($5, 6, val)
1966 
1967 #define read_c0_pwsize()	__read_ulong_c0_register($5, 7)
1968 #define write_c0_pwsize(val)	__write_ulong_c0_register($5, 7, val)
1969 
1970 #define read_c0_pwctl()		__read_32bit_c0_register($6, 6)
1971 #define write_c0_pwctl(val)	__write_32bit_c0_register($6, 6, val)
1972 
1973 #define read_c0_pgd()		__read_64bit_c0_register($9, 7)
1974 #define write_c0_pgd(val)	__write_64bit_c0_register($9, 7, val)
1975 
1976 #define read_c0_kpgd()		__read_64bit_c0_register($31, 7)
1977 #define write_c0_kpgd(val)	__write_64bit_c0_register($31, 7, val)
1978 
1979 /* Cavium OCTEON (cnMIPS) */
1980 #define read_c0_cvmcount()	__read_ulong_c0_register($9, 6)
1981 #define write_c0_cvmcount(val)	__write_ulong_c0_register($9, 6, val)
1982 
1983 #define read_c0_cvmctl()	__read_64bit_c0_register($9, 7)
1984 #define write_c0_cvmctl(val)	__write_64bit_c0_register($9, 7, val)
1985 
1986 #define read_c0_cvmmemctl()	__read_64bit_c0_register($11, 7)
1987 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1988 
1989 #define read_c0_cvmmemctl2()	__read_64bit_c0_register($16, 6)
1990 #define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
1991 
1992 #define read_c0_cvmvmconfig()	__read_64bit_c0_register($16, 7)
1993 #define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
1994 
1995 /*
1996  * The cacheerr registers are not standardized.	 On OCTEON, they are
1997  * 64 bits wide.
1998  */
1999 #define read_octeon_c0_icacheerr()	__read_64bit_c0_register($27, 0)
2000 #define write_octeon_c0_icacheerr(val)	__write_64bit_c0_register($27, 0, val)
2001 
2002 #define read_octeon_c0_dcacheerr()	__read_64bit_c0_register($27, 1)
2003 #define write_octeon_c0_dcacheerr(val)	__write_64bit_c0_register($27, 1, val)
2004 
2005 /* BMIPS3300 */
2006 #define read_c0_brcm_config_0()		__read_32bit_c0_register($22, 0)
2007 #define write_c0_brcm_config_0(val)	__write_32bit_c0_register($22, 0, val)
2008 
2009 #define read_c0_brcm_bus_pll()		__read_32bit_c0_register($22, 4)
2010 #define write_c0_brcm_bus_pll(val)	__write_32bit_c0_register($22, 4, val)
2011 
2012 #define read_c0_brcm_reset()		__read_32bit_c0_register($22, 5)
2013 #define write_c0_brcm_reset(val)	__write_32bit_c0_register($22, 5, val)
2014 
2015 /* BMIPS43xx */
2016 #define read_c0_brcm_cmt_intr()		__read_32bit_c0_register($22, 1)
2017 #define write_c0_brcm_cmt_intr(val)	__write_32bit_c0_register($22, 1, val)
2018 
2019 #define read_c0_brcm_cmt_ctrl()		__read_32bit_c0_register($22, 2)
2020 #define write_c0_brcm_cmt_ctrl(val)	__write_32bit_c0_register($22, 2, val)
2021 
2022 #define read_c0_brcm_cmt_local()	__read_32bit_c0_register($22, 3)
2023 #define write_c0_brcm_cmt_local(val)	__write_32bit_c0_register($22, 3, val)
2024 
2025 #define read_c0_brcm_config_1()		__read_32bit_c0_register($22, 5)
2026 #define write_c0_brcm_config_1(val)	__write_32bit_c0_register($22, 5, val)
2027 
2028 #define read_c0_brcm_cbr()		__read_32bit_c0_register($22, 6)
2029 #define write_c0_brcm_cbr(val)		__write_32bit_c0_register($22, 6, val)
2030 
2031 /* BMIPS5000 */
2032 #define read_c0_brcm_config()		__read_32bit_c0_register($22, 0)
2033 #define write_c0_brcm_config(val)	__write_32bit_c0_register($22, 0, val)
2034 
2035 #define read_c0_brcm_mode()		__read_32bit_c0_register($22, 1)
2036 #define write_c0_brcm_mode(val)		__write_32bit_c0_register($22, 1, val)
2037 
2038 #define read_c0_brcm_action()		__read_32bit_c0_register($22, 2)
2039 #define write_c0_brcm_action(val)	__write_32bit_c0_register($22, 2, val)
2040 
2041 #define read_c0_brcm_edsp()		__read_32bit_c0_register($22, 3)
2042 #define write_c0_brcm_edsp(val)		__write_32bit_c0_register($22, 3, val)
2043 
2044 #define read_c0_brcm_bootvec()		__read_32bit_c0_register($22, 4)
2045 #define write_c0_brcm_bootvec(val)	__write_32bit_c0_register($22, 4, val)
2046 
2047 #define read_c0_brcm_sleepcount()	__read_32bit_c0_register($22, 7)
2048 #define write_c0_brcm_sleepcount(val)	__write_32bit_c0_register($22, 7, val)
2049 
2050 /* Ingenic page ctrl register */
2051 #define write_c0_page_ctrl(val)	__write_32bit_c0_register($5, 4, val)
2052 
2053 /*
2054  * Macros to access the guest system control coprocessor
2055  */
2056 
2057 #ifndef TOOLCHAIN_SUPPORTS_VIRT
2058 #define _ASM_SET_MFGC0							\
2059 	_ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,				\
2060 			 _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)	\
2061 			 _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11))
2062 #define _ASM_UNSET_MFGC0 ".purgem mfgc0\n\t"
2063 #define _ASM_SET_DMFGC0							\
2064 	_ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel,				\
2065 			 _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel)	\
2066 			 _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11))
2067 #define _ASM_UNSET_DMFGC0 ".purgem dmfgc0\n\t"
2068 #define _ASM_SET_MTGC0							\
2069 	_ASM_MACRO_2R_1S(mtgc0, rt, rd, sel,				\
2070 			 _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel)	\
2071 			 _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11))
2072 #define _ASM_UNSET_MTGC0 ".purgem mtgc0\n\t"
2073 #define _ASM_SET_DMTGC0							\
2074 	_ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel,				\
2075 			 _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel)	\
2076 			 _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11))
2077 #define _ASM_UNSET_DMTGC0 ".purgem dmtgc0\n\t"
2078 
2079 #define __tlbgp()							\
2080 		_ASM_INSN_IF_MIPS(0x42000010)				\
2081 		_ASM_INSN32_IF_MM(0x0000017c)
2082 #define __tlbgr()							\
2083 		_ASM_INSN_IF_MIPS(0x42000009)				\
2084 		_ASM_INSN32_IF_MM(0x0000117c)
2085 #define __tlbgwi()							\
2086 		_ASM_INSN_IF_MIPS(0x4200000a)				\
2087 		_ASM_INSN32_IF_MM(0x0000217c)
2088 #define __tlbgwr()							\
2089 		_ASM_INSN_IF_MIPS(0x4200000e)				\
2090 		_ASM_INSN32_IF_MM(0x0000317c)
2091 #define __tlbginvf()							\
2092 		_ASM_INSN_IF_MIPS(0x4200000c)				\
2093 		_ASM_INSN32_IF_MM(0x0000517c)
2094 #else	/* !TOOLCHAIN_SUPPORTS_VIRT */
2095 #define _ASM_SET_VIRT ".set\tvirt\n\t"
2096 #define _ASM_SET_MFGC0	_ASM_SET_VIRT
2097 #define _ASM_SET_DMFGC0	_ASM_SET_VIRT
2098 #define _ASM_SET_MTGC0	_ASM_SET_VIRT
2099 #define _ASM_SET_DMTGC0	_ASM_SET_VIRT
2100 #define _ASM_UNSET_MFGC0
2101 #define _ASM_UNSET_DMFGC0
2102 #define _ASM_UNSET_MTGC0
2103 #define _ASM_UNSET_DMTGC0
2104 
2105 #define __tlbgp()	_ASM_SET_VIRT "tlbgp\n\t"
2106 #define __tlbgr()	_ASM_SET_VIRT "tlbgr\n\t"
2107 #define __tlbgwi()	_ASM_SET_VIRT "tlbgwi\n\t"
2108 #define __tlbgwr()	_ASM_SET_VIRT "tlbgwr\n\t"
2109 #define __tlbginvf()	_ASM_SET_VIRT "tlbginvf\n\t"
2110 #endif
2111 
2112 #define __read_32bit_gc0_register(source, sel)				\
2113 ({ int __res;								\
2114 	__asm__ __volatile__(						\
2115 		".set\tpush\n\t"					\
2116 		".set\tmips32r5\n\t"					\
2117 		_ASM_SET_MFGC0						\
2118 		"mfgc0\t%0, " #source ", %1\n\t"			\
2119 		_ASM_UNSET_MFGC0					\
2120 		".set\tpop"						\
2121 		: "=r" (__res)						\
2122 		: "i" (sel));						\
2123 	__res;								\
2124 })
2125 
2126 #define __read_64bit_gc0_register(source, sel)				\
2127 ({ unsigned long long __res;						\
2128 	__asm__ __volatile__(						\
2129 		".set\tpush\n\t"					\
2130 		".set\tmips64r5\n\t"					\
2131 		_ASM_SET_DMFGC0						\
2132 		"dmfgc0\t%0, " #source ", %1\n\t"			\
2133 		_ASM_UNSET_DMFGC0					\
2134 		".set\tpop"						\
2135 		: "=r" (__res)						\
2136 		: "i" (sel));						\
2137 	__res;								\
2138 })
2139 
2140 #define __write_32bit_gc0_register(register, sel, value)		\
2141 do {									\
2142 	__asm__ __volatile__(						\
2143 		".set\tpush\n\t"					\
2144 		".set\tmips32r5\n\t"					\
2145 		_ASM_SET_MTGC0						\
2146 		"mtgc0\t%z0, " #register ", %1\n\t"			\
2147 		_ASM_UNSET_MTGC0					\
2148 		".set\tpop"						\
2149 		: : "Jr" ((unsigned int)(value)),			\
2150 		    "i" (sel));						\
2151 } while (0)
2152 
2153 #define __write_64bit_gc0_register(register, sel, value)		\
2154 do {									\
2155 	__asm__ __volatile__(						\
2156 		".set\tpush\n\t"					\
2157 		".set\tmips64r5\n\t"					\
2158 		_ASM_SET_DMTGC0						\
2159 		"dmtgc0\t%z0, " #register ", %1\n\t"			\
2160 		_ASM_UNSET_DMTGC0					\
2161 		".set\tpop"						\
2162 		: : "Jr" (value),					\
2163 		    "i" (sel));						\
2164 } while (0)
2165 
2166 #define __read_ulong_gc0_register(reg, sel)				\
2167 	((sizeof(unsigned long) == 4) ?					\
2168 	(unsigned long) __read_32bit_gc0_register(reg, sel) :		\
2169 	(unsigned long) __read_64bit_gc0_register(reg, sel))
2170 
2171 #define __write_ulong_gc0_register(reg, sel, val)			\
2172 do {									\
2173 	if (sizeof(unsigned long) == 4)					\
2174 		__write_32bit_gc0_register(reg, sel, val);		\
2175 	else								\
2176 		__write_64bit_gc0_register(reg, sel, val);		\
2177 } while (0)
2178 
2179 #define read_gc0_index()		__read_32bit_gc0_register($0, 0)
2180 #define write_gc0_index(val)		__write_32bit_gc0_register($0, 0, val)
2181 
2182 #define read_gc0_entrylo0()		__read_ulong_gc0_register($2, 0)
2183 #define write_gc0_entrylo0(val)		__write_ulong_gc0_register($2, 0, val)
2184 
2185 #define read_gc0_entrylo1()		__read_ulong_gc0_register($3, 0)
2186 #define write_gc0_entrylo1(val)		__write_ulong_gc0_register($3, 0, val)
2187 
2188 #define read_gc0_context()		__read_ulong_gc0_register($4, 0)
2189 #define write_gc0_context(val)		__write_ulong_gc0_register($4, 0, val)
2190 
2191 #define read_gc0_contextconfig()	__read_32bit_gc0_register($4, 1)
2192 #define write_gc0_contextconfig(val)	__write_32bit_gc0_register($4, 1, val)
2193 
2194 #define read_gc0_userlocal()		__read_ulong_gc0_register($4, 2)
2195 #define write_gc0_userlocal(val)	__write_ulong_gc0_register($4, 2, val)
2196 
2197 #define read_gc0_xcontextconfig()	__read_ulong_gc0_register($4, 3)
2198 #define write_gc0_xcontextconfig(val)	__write_ulong_gc0_register($4, 3, val)
2199 
2200 #define read_gc0_pagemask()		__read_32bit_gc0_register($5, 0)
2201 #define write_gc0_pagemask(val)		__write_32bit_gc0_register($5, 0, val)
2202 
2203 #define read_gc0_pagegrain()		__read_32bit_gc0_register($5, 1)
2204 #define write_gc0_pagegrain(val)	__write_32bit_gc0_register($5, 1, val)
2205 
2206 #define read_gc0_segctl0()		__read_ulong_gc0_register($5, 2)
2207 #define write_gc0_segctl0(val)		__write_ulong_gc0_register($5, 2, val)
2208 
2209 #define read_gc0_segctl1()		__read_ulong_gc0_register($5, 3)
2210 #define write_gc0_segctl1(val)		__write_ulong_gc0_register($5, 3, val)
2211 
2212 #define read_gc0_segctl2()		__read_ulong_gc0_register($5, 4)
2213 #define write_gc0_segctl2(val)		__write_ulong_gc0_register($5, 4, val)
2214 
2215 #define read_gc0_pwbase()		__read_ulong_gc0_register($5, 5)
2216 #define write_gc0_pwbase(val)		__write_ulong_gc0_register($5, 5, val)
2217 
2218 #define read_gc0_pwfield()		__read_ulong_gc0_register($5, 6)
2219 #define write_gc0_pwfield(val)		__write_ulong_gc0_register($5, 6, val)
2220 
2221 #define read_gc0_pwsize()		__read_ulong_gc0_register($5, 7)
2222 #define write_gc0_pwsize(val)		__write_ulong_gc0_register($5, 7, val)
2223 
2224 #define read_gc0_wired()		__read_32bit_gc0_register($6, 0)
2225 #define write_gc0_wired(val)		__write_32bit_gc0_register($6, 0, val)
2226 
2227 #define read_gc0_pwctl()		__read_32bit_gc0_register($6, 6)
2228 #define write_gc0_pwctl(val)		__write_32bit_gc0_register($6, 6, val)
2229 
2230 #define read_gc0_hwrena()		__read_32bit_gc0_register($7, 0)
2231 #define write_gc0_hwrena(val)		__write_32bit_gc0_register($7, 0, val)
2232 
2233 #define read_gc0_badvaddr()		__read_ulong_gc0_register($8, 0)
2234 #define write_gc0_badvaddr(val)		__write_ulong_gc0_register($8, 0, val)
2235 
2236 #define read_gc0_badinstr()		__read_32bit_gc0_register($8, 1)
2237 #define write_gc0_badinstr(val)		__write_32bit_gc0_register($8, 1, val)
2238 
2239 #define read_gc0_badinstrp()		__read_32bit_gc0_register($8, 2)
2240 #define write_gc0_badinstrp(val)	__write_32bit_gc0_register($8, 2, val)
2241 
2242 #define read_gc0_count()		__read_32bit_gc0_register($9, 0)
2243 
2244 #define read_gc0_entryhi()		__read_ulong_gc0_register($10, 0)
2245 #define write_gc0_entryhi(val)		__write_ulong_gc0_register($10, 0, val)
2246 
2247 #define read_gc0_compare()		__read_32bit_gc0_register($11, 0)
2248 #define write_gc0_compare(val)		__write_32bit_gc0_register($11, 0, val)
2249 
2250 #define read_gc0_status()		__read_32bit_gc0_register($12, 0)
2251 #define write_gc0_status(val)		__write_32bit_gc0_register($12, 0, val)
2252 
2253 #define read_gc0_intctl()		__read_32bit_gc0_register($12, 1)
2254 #define write_gc0_intctl(val)		__write_32bit_gc0_register($12, 1, val)
2255 
2256 #define read_gc0_cause()		__read_32bit_gc0_register($13, 0)
2257 #define write_gc0_cause(val)		__write_32bit_gc0_register($13, 0, val)
2258 
2259 #define read_gc0_epc()			__read_ulong_gc0_register($14, 0)
2260 #define write_gc0_epc(val)		__write_ulong_gc0_register($14, 0, val)
2261 
2262 #define read_gc0_prid()			__read_32bit_gc0_register($15, 0)
2263 
2264 #define read_gc0_ebase()		__read_32bit_gc0_register($15, 1)
2265 #define write_gc0_ebase(val)		__write_32bit_gc0_register($15, 1, val)
2266 
2267 #define read_gc0_ebase_64()		__read_64bit_gc0_register($15, 1)
2268 #define write_gc0_ebase_64(val)		__write_64bit_gc0_register($15, 1, val)
2269 
2270 #define read_gc0_config()		__read_32bit_gc0_register($16, 0)
2271 #define read_gc0_config1()		__read_32bit_gc0_register($16, 1)
2272 #define read_gc0_config2()		__read_32bit_gc0_register($16, 2)
2273 #define read_gc0_config3()		__read_32bit_gc0_register($16, 3)
2274 #define read_gc0_config4()		__read_32bit_gc0_register($16, 4)
2275 #define read_gc0_config5()		__read_32bit_gc0_register($16, 5)
2276 #define read_gc0_config6()		__read_32bit_gc0_register($16, 6)
2277 #define read_gc0_config7()		__read_32bit_gc0_register($16, 7)
2278 #define write_gc0_config(val)		__write_32bit_gc0_register($16, 0, val)
2279 #define write_gc0_config1(val)		__write_32bit_gc0_register($16, 1, val)
2280 #define write_gc0_config2(val)		__write_32bit_gc0_register($16, 2, val)
2281 #define write_gc0_config3(val)		__write_32bit_gc0_register($16, 3, val)
2282 #define write_gc0_config4(val)		__write_32bit_gc0_register($16, 4, val)
2283 #define write_gc0_config5(val)		__write_32bit_gc0_register($16, 5, val)
2284 #define write_gc0_config6(val)		__write_32bit_gc0_register($16, 6, val)
2285 #define write_gc0_config7(val)		__write_32bit_gc0_register($16, 7, val)
2286 
2287 #define read_gc0_lladdr()		__read_ulong_gc0_register($17, 0)
2288 #define write_gc0_lladdr(val)		__write_ulong_gc0_register($17, 0, val)
2289 
2290 #define read_gc0_watchlo0()		__read_ulong_gc0_register($18, 0)
2291 #define read_gc0_watchlo1()		__read_ulong_gc0_register($18, 1)
2292 #define read_gc0_watchlo2()		__read_ulong_gc0_register($18, 2)
2293 #define read_gc0_watchlo3()		__read_ulong_gc0_register($18, 3)
2294 #define read_gc0_watchlo4()		__read_ulong_gc0_register($18, 4)
2295 #define read_gc0_watchlo5()		__read_ulong_gc0_register($18, 5)
2296 #define read_gc0_watchlo6()		__read_ulong_gc0_register($18, 6)
2297 #define read_gc0_watchlo7()		__read_ulong_gc0_register($18, 7)
2298 #define write_gc0_watchlo0(val)		__write_ulong_gc0_register($18, 0, val)
2299 #define write_gc0_watchlo1(val)		__write_ulong_gc0_register($18, 1, val)
2300 #define write_gc0_watchlo2(val)		__write_ulong_gc0_register($18, 2, val)
2301 #define write_gc0_watchlo3(val)		__write_ulong_gc0_register($18, 3, val)
2302 #define write_gc0_watchlo4(val)		__write_ulong_gc0_register($18, 4, val)
2303 #define write_gc0_watchlo5(val)		__write_ulong_gc0_register($18, 5, val)
2304 #define write_gc0_watchlo6(val)		__write_ulong_gc0_register($18, 6, val)
2305 #define write_gc0_watchlo7(val)		__write_ulong_gc0_register($18, 7, val)
2306 
2307 #define read_gc0_watchhi0()		__read_32bit_gc0_register($19, 0)
2308 #define read_gc0_watchhi1()		__read_32bit_gc0_register($19, 1)
2309 #define read_gc0_watchhi2()		__read_32bit_gc0_register($19, 2)
2310 #define read_gc0_watchhi3()		__read_32bit_gc0_register($19, 3)
2311 #define read_gc0_watchhi4()		__read_32bit_gc0_register($19, 4)
2312 #define read_gc0_watchhi5()		__read_32bit_gc0_register($19, 5)
2313 #define read_gc0_watchhi6()		__read_32bit_gc0_register($19, 6)
2314 #define read_gc0_watchhi7()		__read_32bit_gc0_register($19, 7)
2315 #define write_gc0_watchhi0(val)		__write_32bit_gc0_register($19, 0, val)
2316 #define write_gc0_watchhi1(val)		__write_32bit_gc0_register($19, 1, val)
2317 #define write_gc0_watchhi2(val)		__write_32bit_gc0_register($19, 2, val)
2318 #define write_gc0_watchhi3(val)		__write_32bit_gc0_register($19, 3, val)
2319 #define write_gc0_watchhi4(val)		__write_32bit_gc0_register($19, 4, val)
2320 #define write_gc0_watchhi5(val)		__write_32bit_gc0_register($19, 5, val)
2321 #define write_gc0_watchhi6(val)		__write_32bit_gc0_register($19, 6, val)
2322 #define write_gc0_watchhi7(val)		__write_32bit_gc0_register($19, 7, val)
2323 
2324 #define read_gc0_xcontext()		__read_ulong_gc0_register($20, 0)
2325 #define write_gc0_xcontext(val)		__write_ulong_gc0_register($20, 0, val)
2326 
2327 #define read_gc0_perfctrl0()		__read_32bit_gc0_register($25, 0)
2328 #define write_gc0_perfctrl0(val)	__write_32bit_gc0_register($25, 0, val)
2329 #define read_gc0_perfcntr0()		__read_32bit_gc0_register($25, 1)
2330 #define write_gc0_perfcntr0(val)	__write_32bit_gc0_register($25, 1, val)
2331 #define read_gc0_perfcntr0_64()		__read_64bit_gc0_register($25, 1)
2332 #define write_gc0_perfcntr0_64(val)	__write_64bit_gc0_register($25, 1, val)
2333 #define read_gc0_perfctrl1()		__read_32bit_gc0_register($25, 2)
2334 #define write_gc0_perfctrl1(val)	__write_32bit_gc0_register($25, 2, val)
2335 #define read_gc0_perfcntr1()		__read_32bit_gc0_register($25, 3)
2336 #define write_gc0_perfcntr1(val)	__write_32bit_gc0_register($25, 3, val)
2337 #define read_gc0_perfcntr1_64()		__read_64bit_gc0_register($25, 3)
2338 #define write_gc0_perfcntr1_64(val)	__write_64bit_gc0_register($25, 3, val)
2339 #define read_gc0_perfctrl2()		__read_32bit_gc0_register($25, 4)
2340 #define write_gc0_perfctrl2(val)	__write_32bit_gc0_register($25, 4, val)
2341 #define read_gc0_perfcntr2()		__read_32bit_gc0_register($25, 5)
2342 #define write_gc0_perfcntr2(val)	__write_32bit_gc0_register($25, 5, val)
2343 #define read_gc0_perfcntr2_64()		__read_64bit_gc0_register($25, 5)
2344 #define write_gc0_perfcntr2_64(val)	__write_64bit_gc0_register($25, 5, val)
2345 #define read_gc0_perfctrl3()		__read_32bit_gc0_register($25, 6)
2346 #define write_gc0_perfctrl3(val)	__write_32bit_gc0_register($25, 6, val)
2347 #define read_gc0_perfcntr3()		__read_32bit_gc0_register($25, 7)
2348 #define write_gc0_perfcntr3(val)	__write_32bit_gc0_register($25, 7, val)
2349 #define read_gc0_perfcntr3_64()		__read_64bit_gc0_register($25, 7)
2350 #define write_gc0_perfcntr3_64(val)	__write_64bit_gc0_register($25, 7, val)
2351 
2352 #define read_gc0_errorepc()		__read_ulong_gc0_register($30, 0)
2353 #define write_gc0_errorepc(val)		__write_ulong_gc0_register($30, 0, val)
2354 
2355 #define read_gc0_kscratch1()		__read_ulong_gc0_register($31, 2)
2356 #define read_gc0_kscratch2()		__read_ulong_gc0_register($31, 3)
2357 #define read_gc0_kscratch3()		__read_ulong_gc0_register($31, 4)
2358 #define read_gc0_kscratch4()		__read_ulong_gc0_register($31, 5)
2359 #define read_gc0_kscratch5()		__read_ulong_gc0_register($31, 6)
2360 #define read_gc0_kscratch6()		__read_ulong_gc0_register($31, 7)
2361 #define write_gc0_kscratch1(val)	__write_ulong_gc0_register($31, 2, val)
2362 #define write_gc0_kscratch2(val)	__write_ulong_gc0_register($31, 3, val)
2363 #define write_gc0_kscratch3(val)	__write_ulong_gc0_register($31, 4, val)
2364 #define write_gc0_kscratch4(val)	__write_ulong_gc0_register($31, 5, val)
2365 #define write_gc0_kscratch5(val)	__write_ulong_gc0_register($31, 6, val)
2366 #define write_gc0_kscratch6(val)	__write_ulong_gc0_register($31, 7, val)
2367 
2368 /* Cavium OCTEON (cnMIPS) */
2369 #define read_gc0_cvmcount()		__read_ulong_gc0_register($9, 6)
2370 #define write_gc0_cvmcount(val)		__write_ulong_gc0_register($9, 6, val)
2371 
2372 #define read_gc0_cvmctl()		__read_64bit_gc0_register($9, 7)
2373 #define write_gc0_cvmctl(val)		__write_64bit_gc0_register($9, 7, val)
2374 
2375 #define read_gc0_cvmmemctl()		__read_64bit_gc0_register($11, 7)
2376 #define write_gc0_cvmmemctl(val)	__write_64bit_gc0_register($11, 7, val)
2377 
2378 #define read_gc0_cvmmemctl2()		__read_64bit_gc0_register($16, 6)
2379 #define write_gc0_cvmmemctl2(val)	__write_64bit_gc0_register($16, 6, val)
2380 
2381 /*
2382  * Macros to access the floating point coprocessor control registers
2383  */
2384 #define _read_32bit_cp1_register(source, gas_hardfloat)			\
2385 ({									\
2386 	unsigned int __res;						\
2387 									\
2388 	__asm__ __volatile__(						\
2389 	"	.set	push					\n"	\
2390 	"	.set	reorder					\n"	\
2391 	"	# gas fails to assemble cfc1 for some archs,	\n"	\
2392 	"	# like Octeon.					\n"	\
2393 	"	.set	mips1					\n"	\
2394 	"	"STR(gas_hardfloat)"				\n"	\
2395 	"	cfc1	%0,"STR(source)"			\n"	\
2396 	"	.set	pop					\n"	\
2397 	: "=r" (__res));						\
2398 	__res;								\
2399 })
2400 
2401 #define _write_32bit_cp1_register(dest, val, gas_hardfloat)		\
2402 do {									\
2403 	__asm__ __volatile__(						\
2404 	"	.set	push					\n"	\
2405 	"	.set	reorder					\n"	\
2406 	"	"STR(gas_hardfloat)"				\n"	\
2407 	"	ctc1	%0,"STR(dest)"				\n"	\
2408 	"	.set	pop					\n"	\
2409 	: : "r" (val));							\
2410 } while (0)
2411 
2412 #ifdef GAS_HAS_SET_HARDFLOAT
2413 #define read_32bit_cp1_register(source)					\
2414 	_read_32bit_cp1_register(source, .set hardfloat)
2415 #define write_32bit_cp1_register(dest, val)				\
2416 	_write_32bit_cp1_register(dest, val, .set hardfloat)
2417 #else
2418 #define read_32bit_cp1_register(source)					\
2419 	_read_32bit_cp1_register(source, )
2420 #define write_32bit_cp1_register(dest, val)				\
2421 	_write_32bit_cp1_register(dest, val, )
2422 #endif
2423 
2424 #ifdef TOOLCHAIN_SUPPORTS_DSP
2425 #define rddsp(mask)							\
2426 ({									\
2427 	unsigned int __dspctl;						\
2428 									\
2429 	__asm__ __volatile__(						\
2430 	"	.set push					\n"	\
2431 	"	.set " MIPS_ISA_LEVEL "				\n"	\
2432 	"	.set dsp					\n"	\
2433 	"	rddsp	%0, %x1					\n"	\
2434 	"	.set pop					\n"	\
2435 	: "=r" (__dspctl)						\
2436 	: "i" (mask));							\
2437 	__dspctl;							\
2438 })
2439 
2440 #define wrdsp(val, mask)						\
2441 do {									\
2442 	__asm__ __volatile__(						\
2443 	"	.set push					\n"	\
2444 	"	.set " MIPS_ISA_LEVEL "				\n"	\
2445 	"	.set dsp					\n"	\
2446 	"	wrdsp	%0, %x1					\n"	\
2447 	"	.set pop					\n"	\
2448 	:								\
2449 	: "r" (val), "i" (mask));					\
2450 } while (0)
2451 
2452 #define mflo0()								\
2453 ({									\
2454 	long mflo0;							\
2455 	__asm__(							\
2456 	"	.set push					\n"	\
2457 	"	.set " MIPS_ISA_LEVEL "				\n"	\
2458 	"	.set dsp					\n"	\
2459 	"	mflo %0, $ac0					\n"	\
2460 	"	.set pop					\n" 	\
2461 	: "=r" (mflo0)); 						\
2462 	mflo0;								\
2463 })
2464 
2465 #define mflo1()								\
2466 ({									\
2467 	long mflo1;							\
2468 	__asm__(							\
2469 	"	.set push					\n"	\
2470 	"	.set " MIPS_ISA_LEVEL "				\n"	\
2471 	"	.set dsp					\n"	\
2472 	"	mflo %0, $ac1					\n"	\
2473 	"	.set pop					\n" 	\
2474 	: "=r" (mflo1)); 						\
2475 	mflo1;								\
2476 })
2477 
2478 #define mflo2()								\
2479 ({									\
2480 	long mflo2;							\
2481 	__asm__(							\
2482 	"	.set push					\n"	\
2483 	"	.set " MIPS_ISA_LEVEL "				\n"	\
2484 	"	.set dsp					\n"	\
2485 	"	mflo %0, $ac2					\n"	\
2486 	"	.set pop					\n" 	\
2487 	: "=r" (mflo2)); 						\
2488 	mflo2;								\
2489 })
2490 
2491 #define mflo3()								\
2492 ({									\
2493 	long mflo3;							\
2494 	__asm__(							\
2495 	"	.set push					\n"	\
2496 	"	.set " MIPS_ISA_LEVEL "				\n"	\
2497 	"	.set dsp					\n"	\
2498 	"	mflo %0, $ac3					\n"	\
2499 	"	.set pop					\n" 	\
2500 	: "=r" (mflo3)); 						\
2501 	mflo3;								\
2502 })
2503 
2504 #define mfhi0()								\
2505 ({									\
2506 	long mfhi0;							\
2507 	__asm__(							\
2508 	"	.set push					\n"	\
2509 	"	.set " MIPS_ISA_LEVEL "				\n"	\
2510 	"	.set dsp					\n"	\
2511 	"	mfhi %0, $ac0					\n"	\
2512 	"	.set pop					\n" 	\
2513 	: "=r" (mfhi0)); 						\
2514 	mfhi0;								\
2515 })
2516 
2517 #define mfhi1()								\
2518 ({									\
2519 	long mfhi1;							\
2520 	__asm__(							\
2521 	"	.set push					\n"	\
2522 	"	.set " MIPS_ISA_LEVEL "				\n"	\
2523 	"	.set dsp					\n"	\
2524 	"	mfhi %0, $ac1					\n"	\
2525 	"	.set pop					\n" 	\
2526 	: "=r" (mfhi1)); 						\
2527 	mfhi1;								\
2528 })
2529 
2530 #define mfhi2()								\
2531 ({									\
2532 	long mfhi2;							\
2533 	__asm__(							\
2534 	"	.set push					\n"	\
2535 	"	.set " MIPS_ISA_LEVEL "				\n"	\
2536 	"	.set dsp					\n"	\
2537 	"	mfhi %0, $ac2					\n"	\
2538 	"	.set pop					\n" 	\
2539 	: "=r" (mfhi2)); 						\
2540 	mfhi2;								\
2541 })
2542 
2543 #define mfhi3()								\
2544 ({									\
2545 	long mfhi3;							\
2546 	__asm__(							\
2547 	"	.set push					\n"	\
2548 	"	.set " MIPS_ISA_LEVEL "				\n"	\
2549 	"	.set dsp					\n"	\
2550 	"	mfhi %0, $ac3					\n"	\
2551 	"	.set pop					\n" 	\
2552 	: "=r" (mfhi3)); 						\
2553 	mfhi3;								\
2554 })
2555 
2556 
2557 #define mtlo0(x)							\
2558 ({									\
2559 	__asm__(							\
2560 	"	.set push					\n"	\
2561 	"	.set " MIPS_ISA_LEVEL "				\n"	\
2562 	"	.set dsp					\n"	\
2563 	"	mtlo %0, $ac0					\n"	\
2564 	"	.set pop					\n"	\
2565 	:								\
2566 	: "r" (x));							\
2567 })
2568 
2569 #define mtlo1(x)							\
2570 ({									\
2571 	__asm__(							\
2572 	"	.set push					\n"	\
2573 	"	.set " MIPS_ISA_LEVEL "				\n"	\
2574 	"	.set dsp					\n"	\
2575 	"	mtlo %0, $ac1					\n"	\
2576 	"	.set pop					\n"	\
2577 	:								\
2578 	: "r" (x));							\
2579 })
2580 
2581 #define mtlo2(x)							\
2582 ({									\
2583 	__asm__(							\
2584 	"	.set push					\n"	\
2585 	"	.set " MIPS_ISA_LEVEL "				\n"	\
2586 	"	.set dsp					\n"	\
2587 	"	mtlo %0, $ac2					\n"	\
2588 	"	.set pop					\n"	\
2589 	:								\
2590 	: "r" (x));							\
2591 })
2592 
2593 #define mtlo3(x)							\
2594 ({									\
2595 	__asm__(							\
2596 	"	.set push					\n"	\
2597 	"	.set " MIPS_ISA_LEVEL "				\n"	\
2598 	"	.set dsp					\n"	\
2599 	"	mtlo %0, $ac3					\n"	\
2600 	"	.set pop					\n"	\
2601 	:								\
2602 	: "r" (x));							\
2603 })
2604 
2605 #define mthi0(x)							\
2606 ({									\
2607 	__asm__(							\
2608 	"	.set push					\n"	\
2609 	"	.set " MIPS_ISA_LEVEL "				\n"	\
2610 	"	.set dsp					\n"	\
2611 	"	mthi %0, $ac0					\n"	\
2612 	"	.set pop					\n"	\
2613 	:								\
2614 	: "r" (x));							\
2615 })
2616 
2617 #define mthi1(x)							\
2618 ({									\
2619 	__asm__(							\
2620 	"	.set push					\n"	\
2621 	"	.set " MIPS_ISA_LEVEL "				\n"	\
2622 	"	.set dsp					\n"	\
2623 	"	mthi %0, $ac1					\n"	\
2624 	"	.set pop					\n"	\
2625 	:								\
2626 	: "r" (x));							\
2627 })
2628 
2629 #define mthi2(x)							\
2630 ({									\
2631 	__asm__(							\
2632 	"	.set push					\n"	\
2633 	"	.set " MIPS_ISA_LEVEL "				\n"	\
2634 	"	.set dsp					\n"	\
2635 	"	mthi %0, $ac2					\n"	\
2636 	"	.set pop					\n"	\
2637 	:								\
2638 	: "r" (x));							\
2639 })
2640 
2641 #define mthi3(x)							\
2642 ({									\
2643 	__asm__(							\
2644 	"	.set push					\n"	\
2645 	"	.set " MIPS_ISA_LEVEL "				\n"	\
2646 	"	.set dsp					\n"	\
2647 	"	mthi %0, $ac3					\n"	\
2648 	"	.set pop					\n"	\
2649 	:								\
2650 	: "r" (x));							\
2651 })
2652 
2653 #else
2654 
2655 #define rddsp(mask)							\
2656 ({									\
2657 	unsigned int __res;						\
2658 									\
2659 	__asm__ __volatile__(						\
2660 	"	.set	push					\n"	\
2661 	"	.set	noat					\n"	\
2662 	"	# rddsp $1, %x1					\n"	\
2663 	_ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16))			\
2664 	_ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14))			\
2665 	"	move	%0, $1					\n"	\
2666 	"	.set	pop					\n"	\
2667 	: "=r" (__res)							\
2668 	: "i" (mask));							\
2669 	__res;								\
2670 })
2671 
2672 #define wrdsp(val, mask)						\
2673 do {									\
2674 	__asm__ __volatile__(						\
2675 	"	.set	push					\n"	\
2676 	"	.set	noat					\n"	\
2677 	"	move	$1, %0					\n"	\
2678 	"	# wrdsp $1, %x1					\n"	\
2679 	_ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11))			\
2680 	_ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14))			\
2681 	"	.set	pop					\n"	\
2682 	:								\
2683 	: "r" (val), "i" (mask));					\
2684 } while (0)
2685 
2686 #define _dsp_mfxxx(ins)							\
2687 ({									\
2688 	unsigned long __treg;						\
2689 									\
2690 	__asm__ __volatile__(						\
2691 	"	.set	push					\n"	\
2692 	"	.set	noat					\n"	\
2693 	_ASM_INSN_IF_MIPS(0x00000810 | %X1)				\
2694 	_ASM_INSN32_IF_MM(0x0001007c | %x1)				\
2695 	"	move	%0, $1					\n"	\
2696 	"	.set	pop					\n"	\
2697 	: "=r" (__treg)							\
2698 	: "i" (ins));							\
2699 	__treg;								\
2700 })
2701 
2702 #define _dsp_mtxxx(val, ins)						\
2703 do {									\
2704 	__asm__ __volatile__(						\
2705 	"	.set	push					\n"	\
2706 	"	.set	noat					\n"	\
2707 	"	move	$1, %0					\n"	\
2708 	_ASM_INSN_IF_MIPS(0x00200011 | %X1)				\
2709 	_ASM_INSN32_IF_MM(0x0001207c | %x1)				\
2710 	"	.set	pop					\n"	\
2711 	:								\
2712 	: "r" (val), "i" (ins));					\
2713 } while (0)
2714 
2715 #ifdef CONFIG_CPU_MICROMIPS
2716 
2717 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2718 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2719 
2720 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2721 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2722 
2723 #else  /* !CONFIG_CPU_MICROMIPS */
2724 
2725 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2726 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2727 
2728 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2729 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2730 
2731 #endif /* CONFIG_CPU_MICROMIPS */
2732 
2733 #define mflo0() _dsp_mflo(0)
2734 #define mflo1() _dsp_mflo(1)
2735 #define mflo2() _dsp_mflo(2)
2736 #define mflo3() _dsp_mflo(3)
2737 
2738 #define mfhi0() _dsp_mfhi(0)
2739 #define mfhi1() _dsp_mfhi(1)
2740 #define mfhi2() _dsp_mfhi(2)
2741 #define mfhi3() _dsp_mfhi(3)
2742 
2743 #define mtlo0(x) _dsp_mtlo(x, 0)
2744 #define mtlo1(x) _dsp_mtlo(x, 1)
2745 #define mtlo2(x) _dsp_mtlo(x, 2)
2746 #define mtlo3(x) _dsp_mtlo(x, 3)
2747 
2748 #define mthi0(x) _dsp_mthi(x, 0)
2749 #define mthi1(x) _dsp_mthi(x, 1)
2750 #define mthi2(x) _dsp_mthi(x, 2)
2751 #define mthi3(x) _dsp_mthi(x, 3)
2752 
2753 #endif
2754 
2755 /*
2756  * TLB operations.
2757  *
2758  * It is responsibility of the caller to take care of any TLB hazards.
2759  */
tlb_probe(void)2760 static inline void tlb_probe(void)
2761 {
2762 	__asm__ __volatile__(
2763 		".set noreorder\n\t"
2764 		"tlbp\n\t"
2765 		".set reorder");
2766 }
2767 
tlb_read(void)2768 static inline void tlb_read(void)
2769 {
2770 #ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
2771 	int res = 0;
2772 
2773 	__asm__ __volatile__(
2774 	"	.set	push					\n"
2775 	"	.set	noreorder				\n"
2776 	"	.set	noat					\n"
2777 	"	.set	mips32r2				\n"
2778 	"	.word	0x41610001		# dvpe $1	\n"
2779 	"	move	%0, $1					\n"
2780 	"	ehb						\n"
2781 	"	.set	pop					\n"
2782 	: "=r" (res));
2783 
2784 	instruction_hazard();
2785 #endif
2786 
2787 	__asm__ __volatile__(
2788 		".set noreorder\n\t"
2789 		"tlbr\n\t"
2790 		".set reorder");
2791 
2792 #ifdef CONFIG_WAR_MIPS34K_MISSED_ITLB
2793 	if ((res & _ULCAST_(1)))
2794 		__asm__ __volatile__(
2795 		"	.set	push				\n"
2796 		"	.set	noreorder			\n"
2797 		"	.set	noat				\n"
2798 		"	.set	mips32r2			\n"
2799 		"	.word	0x41600021	# evpe		\n"
2800 		"	ehb					\n"
2801 		"	.set	pop				\n");
2802 #endif
2803 }
2804 
tlb_write_indexed(void)2805 static inline void tlb_write_indexed(void)
2806 {
2807 	__asm__ __volatile__(
2808 		".set noreorder\n\t"
2809 		"tlbwi\n\t"
2810 		".set reorder");
2811 }
2812 
tlb_write_random(void)2813 static inline void tlb_write_random(void)
2814 {
2815 	__asm__ __volatile__(
2816 		".set noreorder\n\t"
2817 		"tlbwr\n\t"
2818 		".set reorder");
2819 }
2820 
2821 /*
2822  * Guest TLB operations.
2823  *
2824  * It is responsibility of the caller to take care of any TLB hazards.
2825  */
guest_tlb_probe(void)2826 static inline void guest_tlb_probe(void)
2827 {
2828 	__asm__ __volatile__(
2829 		".set push\n\t"
2830 		".set noreorder\n\t"
2831 		__tlbgp()
2832 		".set pop");
2833 }
2834 
guest_tlb_read(void)2835 static inline void guest_tlb_read(void)
2836 {
2837 	__asm__ __volatile__(
2838 		".set push\n\t"
2839 		".set noreorder\n\t"
2840 		__tlbgr()
2841 		".set pop");
2842 }
2843 
guest_tlb_write_indexed(void)2844 static inline void guest_tlb_write_indexed(void)
2845 {
2846 	__asm__ __volatile__(
2847 		".set push\n\t"
2848 		".set noreorder\n\t"
2849 		__tlbgwi()
2850 		".set pop");
2851 }
2852 
guest_tlb_write_random(void)2853 static inline void guest_tlb_write_random(void)
2854 {
2855 	__asm__ __volatile__(
2856 		".set push\n\t"
2857 		".set noreorder\n\t"
2858 		__tlbgwr()
2859 		".set pop");
2860 }
2861 
2862 /*
2863  * Guest TLB Invalidate Flush
2864  */
guest_tlbinvf(void)2865 static inline void guest_tlbinvf(void)
2866 {
2867 	__asm__ __volatile__(
2868 		".set push\n\t"
2869 		".set noreorder\n\t"
2870 		__tlbginvf()
2871 		".set pop");
2872 }
2873 
2874 /*
2875  * Manipulate bits in a register.
2876  */
2877 #define __BUILD_SET_COMMON(name)				\
2878 static inline unsigned int					\
2879 set_##name(unsigned int set)					\
2880 {								\
2881 	unsigned int res, new;					\
2882 								\
2883 	res = read_##name();					\
2884 	new = res | set;					\
2885 	write_##name(new);					\
2886 								\
2887 	return res;						\
2888 }								\
2889 								\
2890 static inline unsigned int					\
2891 clear_##name(unsigned int clear)				\
2892 {								\
2893 	unsigned int res, new;					\
2894 								\
2895 	res = read_##name();					\
2896 	new = res & ~clear;					\
2897 	write_##name(new);					\
2898 								\
2899 	return res;						\
2900 }								\
2901 								\
2902 static inline unsigned int					\
2903 change_##name(unsigned int change, unsigned int val)		\
2904 {								\
2905 	unsigned int res, new;					\
2906 								\
2907 	res = read_##name();					\
2908 	new = res & ~change;					\
2909 	new |= (val & change);					\
2910 	write_##name(new);					\
2911 								\
2912 	return res;						\
2913 }
2914 
2915 /*
2916  * Manipulate bits in a c0 register.
2917  */
2918 #define __BUILD_SET_C0(name)	__BUILD_SET_COMMON(c0_##name)
2919 
2920 __BUILD_SET_C0(status)
__BUILD_SET_C0(cause)2921 __BUILD_SET_C0(cause)
2922 __BUILD_SET_C0(config)
2923 __BUILD_SET_C0(config5)
2924 __BUILD_SET_C0(config6)
2925 __BUILD_SET_C0(config7)
2926 __BUILD_SET_C0(diag)
2927 __BUILD_SET_C0(intcontrol)
2928 __BUILD_SET_C0(intctl)
2929 __BUILD_SET_C0(srsmap)
2930 __BUILD_SET_C0(pagegrain)
2931 __BUILD_SET_C0(guestctl0)
2932 __BUILD_SET_C0(guestctl0ext)
2933 __BUILD_SET_C0(guestctl1)
2934 __BUILD_SET_C0(guestctl2)
2935 __BUILD_SET_C0(guestctl3)
2936 __BUILD_SET_C0(brcm_config_0)
2937 __BUILD_SET_C0(brcm_bus_pll)
2938 __BUILD_SET_C0(brcm_reset)
2939 __BUILD_SET_C0(brcm_cmt_intr)
2940 __BUILD_SET_C0(brcm_cmt_ctrl)
2941 __BUILD_SET_C0(brcm_config)
2942 __BUILD_SET_C0(brcm_mode)
2943 
2944 /*
2945  * Manipulate bits in a guest c0 register.
2946  */
2947 #define __BUILD_SET_GC0(name)	__BUILD_SET_COMMON(gc0_##name)
2948 
2949 __BUILD_SET_GC0(wired)
2950 __BUILD_SET_GC0(status)
2951 __BUILD_SET_GC0(cause)
2952 __BUILD_SET_GC0(ebase)
2953 __BUILD_SET_GC0(config1)
2954 
2955 /*
2956  * Return low 10 bits of ebase.
2957  * Note that under KVM (MIPSVZ) this returns vcpu id.
2958  */
2959 static inline unsigned int get_ebase_cpunum(void)
2960 {
2961 	return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2962 }
2963 
2964 #endif /* !__ASSEMBLY__ */
2965 
2966 #endif /* _ASM_MIPSREGS_H */
2967