1 /*
2 * TI DaVinci DM646x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12 #include <linux/clk-provider.h>
13 #include <linux/clk/davinci.h>
14 #include <linux/clkdev.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmaengine.h>
17 #include <linux/init.h>
18 #include <linux/io.h>
19 #include <linux/irqchip/irq-davinci-aintc.h>
20 #include <linux/platform_data/edma.h>
21 #include <linux/platform_data/gpio-davinci.h>
22 #include <linux/platform_device.h>
23 #include <linux/serial_8250.h>
24
25 #include <clocksource/timer-davinci.h>
26
27 #include <asm/mach/map.h>
28
29 #include "common.h"
30 #include "cputype.h"
31 #include "serial.h"
32 #include "asp.h"
33 #include "davinci.h"
34 #include "irqs.h"
35 #include "mux.h"
36
37 #define DAVINCI_VPIF_BASE (0x01C12000)
38
39 #define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
40 BIT_MASK(0))
41 #define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
42 BIT_MASK(8))
43
44 #define DM646X_EMAC_BASE 0x01c80000
45 #define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
46 #define DM646X_EMAC_CNTRL_OFFSET 0x0000
47 #define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
48 #define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
49 #define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
50
51 static struct emac_platform_data dm646x_emac_pdata = {
52 .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
53 .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
54 .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
55 .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
56 .version = EMAC_VERSION_2,
57 };
58
59 static struct resource dm646x_emac_resources[] = {
60 {
61 .start = DM646X_EMAC_BASE,
62 .end = DM646X_EMAC_BASE + SZ_16K - 1,
63 .flags = IORESOURCE_MEM,
64 },
65 {
66 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
67 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXTHINT),
68 .flags = IORESOURCE_IRQ,
69 },
70 {
71 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
72 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACRXINT),
73 .flags = IORESOURCE_IRQ,
74 },
75 {
76 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
77 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACTXINT),
78 .flags = IORESOURCE_IRQ,
79 },
80 {
81 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
82 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_EMACMISCINT),
83 .flags = IORESOURCE_IRQ,
84 },
85 };
86
87 static struct platform_device dm646x_emac_device = {
88 .name = "davinci_emac",
89 .id = 1,
90 .dev = {
91 .platform_data = &dm646x_emac_pdata,
92 },
93 .num_resources = ARRAY_SIZE(dm646x_emac_resources),
94 .resource = dm646x_emac_resources,
95 };
96
97 static struct resource dm646x_mdio_resources[] = {
98 {
99 .start = DM646X_EMAC_MDIO_BASE,
100 .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
101 .flags = IORESOURCE_MEM,
102 },
103 };
104
105 static struct platform_device dm646x_mdio_device = {
106 .name = "davinci_mdio",
107 .id = 0,
108 .num_resources = ARRAY_SIZE(dm646x_mdio_resources),
109 .resource = dm646x_mdio_resources,
110 };
111
112 /*
113 * Device specific mux setup
114 *
115 * soc description mux mode mode mux dbg
116 * reg offset mask mode
117 */
118 static const struct mux_config dm646x_pins[] = {
119 #ifdef CONFIG_DAVINCI_MUX
120 MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
121
122 MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
123
124 MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
125
126 MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
127
128 MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
129
130 MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
131
132 MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
133
134 MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
135
136 MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
137
138 MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
139
140 MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
141
142 MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
143
144 MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
145
146 MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
147 #endif
148 };
149
150 static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
151 [IRQ_DM646X_VP_VERTINT0] = 7,
152 [IRQ_DM646X_VP_VERTINT1] = 7,
153 [IRQ_DM646X_VP_VERTINT2] = 7,
154 [IRQ_DM646X_VP_VERTINT3] = 7,
155 [IRQ_DM646X_VP_ERRINT] = 7,
156 [IRQ_DM646X_RESERVED_1] = 7,
157 [IRQ_DM646X_RESERVED_2] = 7,
158 [IRQ_DM646X_WDINT] = 7,
159 [IRQ_DM646X_CRGENINT0] = 7,
160 [IRQ_DM646X_CRGENINT1] = 7,
161 [IRQ_DM646X_TSIFINT0] = 7,
162 [IRQ_DM646X_TSIFINT1] = 7,
163 [IRQ_DM646X_VDCEINT] = 7,
164 [IRQ_DM646X_USBINT] = 7,
165 [IRQ_DM646X_USBDMAINT] = 7,
166 [IRQ_DM646X_PCIINT] = 7,
167 [IRQ_CCINT0] = 7, /* dma */
168 [IRQ_CCERRINT] = 7, /* dma */
169 [IRQ_TCERRINT0] = 7, /* dma */
170 [IRQ_TCERRINT] = 7, /* dma */
171 [IRQ_DM646X_TCERRINT2] = 7,
172 [IRQ_DM646X_TCERRINT3] = 7,
173 [IRQ_DM646X_IDE] = 7,
174 [IRQ_DM646X_HPIINT] = 7,
175 [IRQ_DM646X_EMACRXTHINT] = 7,
176 [IRQ_DM646X_EMACRXINT] = 7,
177 [IRQ_DM646X_EMACTXINT] = 7,
178 [IRQ_DM646X_EMACMISCINT] = 7,
179 [IRQ_DM646X_MCASP0TXINT] = 7,
180 [IRQ_DM646X_MCASP0RXINT] = 7,
181 [IRQ_DM646X_RESERVED_3] = 7,
182 [IRQ_DM646X_MCASP1TXINT] = 7,
183 [IRQ_TINT0_TINT12] = 7, /* clockevent */
184 [IRQ_TINT0_TINT34] = 7, /* clocksource */
185 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
186 [IRQ_TINT1_TINT34] = 7, /* system tick */
187 [IRQ_PWMINT0] = 7,
188 [IRQ_PWMINT1] = 7,
189 [IRQ_DM646X_VLQINT] = 7,
190 [IRQ_I2C] = 7,
191 [IRQ_UARTINT0] = 7,
192 [IRQ_UARTINT1] = 7,
193 [IRQ_DM646X_UARTINT2] = 7,
194 [IRQ_DM646X_SPINT0] = 7,
195 [IRQ_DM646X_SPINT1] = 7,
196 [IRQ_DM646X_DSP2ARMINT] = 7,
197 [IRQ_DM646X_RESERVED_4] = 7,
198 [IRQ_DM646X_PSCINT] = 7,
199 [IRQ_DM646X_GPIO0] = 7,
200 [IRQ_DM646X_GPIO1] = 7,
201 [IRQ_DM646X_GPIO2] = 7,
202 [IRQ_DM646X_GPIO3] = 7,
203 [IRQ_DM646X_GPIO4] = 7,
204 [IRQ_DM646X_GPIO5] = 7,
205 [IRQ_DM646X_GPIO6] = 7,
206 [IRQ_DM646X_GPIO7] = 7,
207 [IRQ_DM646X_GPIOBNK0] = 7,
208 [IRQ_DM646X_GPIOBNK1] = 7,
209 [IRQ_DM646X_GPIOBNK2] = 7,
210 [IRQ_DM646X_DDRINT] = 7,
211 [IRQ_DM646X_AEMIFINT] = 7,
212 [IRQ_COMMTX] = 7,
213 [IRQ_COMMRX] = 7,
214 [IRQ_EMUINT] = 7,
215 };
216
217 /*----------------------------------------------------------------------*/
218
219 /* Four Transfer Controllers on DM646x */
220 static s8 dm646x_queue_priority_mapping[][2] = {
221 /* {event queue no, Priority} */
222 {0, 4},
223 {1, 0},
224 {2, 5},
225 {3, 1},
226 {-1, -1},
227 };
228
229 static const struct dma_slave_map dm646x_edma_map[] = {
230 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) },
231 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) },
232 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) },
233 { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
234 { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
235 };
236
237 static struct edma_soc_info dm646x_edma_pdata = {
238 .queue_priority_mapping = dm646x_queue_priority_mapping,
239 .default_queue = EVENTQ_1,
240 .slave_map = dm646x_edma_map,
241 .slavecnt = ARRAY_SIZE(dm646x_edma_map),
242 };
243
244 static struct resource edma_resources[] = {
245 {
246 .name = "edma3_cc",
247 .start = 0x01c00000,
248 .end = 0x01c00000 + SZ_64K - 1,
249 .flags = IORESOURCE_MEM,
250 },
251 {
252 .name = "edma3_tc0",
253 .start = 0x01c10000,
254 .end = 0x01c10000 + SZ_1K - 1,
255 .flags = IORESOURCE_MEM,
256 },
257 {
258 .name = "edma3_tc1",
259 .start = 0x01c10400,
260 .end = 0x01c10400 + SZ_1K - 1,
261 .flags = IORESOURCE_MEM,
262 },
263 {
264 .name = "edma3_tc2",
265 .start = 0x01c10800,
266 .end = 0x01c10800 + SZ_1K - 1,
267 .flags = IORESOURCE_MEM,
268 },
269 {
270 .name = "edma3_tc3",
271 .start = 0x01c10c00,
272 .end = 0x01c10c00 + SZ_1K - 1,
273 .flags = IORESOURCE_MEM,
274 },
275 {
276 .name = "edma3_ccint",
277 .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
278 .flags = IORESOURCE_IRQ,
279 },
280 {
281 .name = "edma3_ccerrint",
282 .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
283 .flags = IORESOURCE_IRQ,
284 },
285 /* not using TC*_ERR */
286 };
287
288 static const struct platform_device_info dm646x_edma_device __initconst = {
289 .name = "edma",
290 .id = 0,
291 .dma_mask = DMA_BIT_MASK(32),
292 .res = edma_resources,
293 .num_res = ARRAY_SIZE(edma_resources),
294 .data = &dm646x_edma_pdata,
295 .size_data = sizeof(dm646x_edma_pdata),
296 };
297
298 static struct resource dm646x_mcasp0_resources[] = {
299 {
300 .name = "mpu",
301 .start = DAVINCI_DM646X_MCASP0_REG_BASE,
302 .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
303 .flags = IORESOURCE_MEM,
304 },
305 {
306 .name = "tx",
307 .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
308 .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
309 .flags = IORESOURCE_DMA,
310 },
311 {
312 .name = "rx",
313 .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
314 .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
315 .flags = IORESOURCE_DMA,
316 },
317 {
318 .name = "tx",
319 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0TXINT),
320 .flags = IORESOURCE_IRQ,
321 },
322 {
323 .name = "rx",
324 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP0RXINT),
325 .flags = IORESOURCE_IRQ,
326 },
327 };
328
329 /* DIT mode only, rx is not supported */
330 static struct resource dm646x_mcasp1_resources[] = {
331 {
332 .name = "mpu",
333 .start = DAVINCI_DM646X_MCASP1_REG_BASE,
334 .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
335 .flags = IORESOURCE_MEM,
336 },
337 {
338 .name = "tx",
339 .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
340 .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
341 .flags = IORESOURCE_DMA,
342 },
343 {
344 .name = "tx",
345 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_MCASP1TXINT),
346 .flags = IORESOURCE_IRQ,
347 },
348 };
349
350 static struct platform_device dm646x_mcasp0_device = {
351 .name = "davinci-mcasp",
352 .id = 0,
353 .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources),
354 .resource = dm646x_mcasp0_resources,
355 };
356
357 static struct platform_device dm646x_mcasp1_device = {
358 .name = "davinci-mcasp",
359 .id = 1,
360 .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources),
361 .resource = dm646x_mcasp1_resources,
362 };
363
364 static struct platform_device dm646x_dit_device = {
365 .name = "spdif-dit",
366 .id = -1,
367 };
368
369 static u64 vpif_dma_mask = DMA_BIT_MASK(32);
370
371 static struct resource vpif_resource[] = {
372 {
373 .start = DAVINCI_VPIF_BASE,
374 .end = DAVINCI_VPIF_BASE + 0x03ff,
375 .flags = IORESOURCE_MEM,
376 }
377 };
378
379 static struct platform_device vpif_dev = {
380 .name = "vpif",
381 .id = -1,
382 .dev = {
383 .dma_mask = &vpif_dma_mask,
384 .coherent_dma_mask = DMA_BIT_MASK(32),
385 },
386 .resource = vpif_resource,
387 .num_resources = ARRAY_SIZE(vpif_resource),
388 };
389
390 static struct resource vpif_display_resource[] = {
391 {
392 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
393 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT2),
394 .flags = IORESOURCE_IRQ,
395 },
396 {
397 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
398 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT3),
399 .flags = IORESOURCE_IRQ,
400 },
401 };
402
403 static struct platform_device vpif_display_dev = {
404 .name = "vpif_display",
405 .id = -1,
406 .dev = {
407 .dma_mask = &vpif_dma_mask,
408 .coherent_dma_mask = DMA_BIT_MASK(32),
409 },
410 .resource = vpif_display_resource,
411 .num_resources = ARRAY_SIZE(vpif_display_resource),
412 };
413
414 static struct resource vpif_capture_resource[] = {
415 {
416 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
417 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT0),
418 .flags = IORESOURCE_IRQ,
419 },
420 {
421 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
422 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_VP_VERTINT1),
423 .flags = IORESOURCE_IRQ,
424 },
425 };
426
427 static struct platform_device vpif_capture_dev = {
428 .name = "vpif_capture",
429 .id = -1,
430 .dev = {
431 .dma_mask = &vpif_dma_mask,
432 .coherent_dma_mask = DMA_BIT_MASK(32),
433 },
434 .resource = vpif_capture_resource,
435 .num_resources = ARRAY_SIZE(vpif_capture_resource),
436 };
437
438 static struct resource dm646x_gpio_resources[] = {
439 { /* registers */
440 .start = DAVINCI_GPIO_BASE,
441 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
442 .flags = IORESOURCE_MEM,
443 },
444 { /* interrupt */
445 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
446 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK0),
447 .flags = IORESOURCE_IRQ,
448 },
449 {
450 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
451 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK1),
452 .flags = IORESOURCE_IRQ,
453 },
454 {
455 .start = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
456 .end = DAVINCI_INTC_IRQ(IRQ_DM646X_GPIOBNK2),
457 .flags = IORESOURCE_IRQ,
458 },
459 };
460
461 static struct davinci_gpio_platform_data dm646x_gpio_platform_data = {
462 .no_auto_base = true,
463 .base = 0,
464 .ngpio = 43,
465 };
466
dm646x_gpio_register(void)467 int __init dm646x_gpio_register(void)
468 {
469 return davinci_gpio_register(dm646x_gpio_resources,
470 ARRAY_SIZE(dm646x_gpio_resources),
471 &dm646x_gpio_platform_data);
472 }
473 /*----------------------------------------------------------------------*/
474
475 static struct map_desc dm646x_io_desc[] = {
476 {
477 .virtual = IO_VIRT,
478 .pfn = __phys_to_pfn(IO_PHYS),
479 .length = IO_SIZE,
480 .type = MT_DEVICE
481 },
482 };
483
484 /* Contents of JTAG ID register used to identify exact cpu type */
485 static struct davinci_id dm646x_ids[] = {
486 {
487 .variant = 0x0,
488 .part_no = 0xb770,
489 .manufacturer = 0x017,
490 .cpu_id = DAVINCI_CPU_ID_DM6467,
491 .name = "dm6467_rev1.x",
492 },
493 {
494 .variant = 0x1,
495 .part_no = 0xb770,
496 .manufacturer = 0x017,
497 .cpu_id = DAVINCI_CPU_ID_DM6467,
498 .name = "dm6467_rev3.x",
499 },
500 };
501
502 /*
503 * Bottom half of timer0 is used for clockevent, top half is used for
504 * clocksource.
505 */
506 static const struct davinci_timer_cfg dm646x_timer_cfg = {
507 .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
508 .irq = {
509 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
510 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
511 },
512 };
513
514 static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
515 {
516 .mapbase = DAVINCI_UART0_BASE,
517 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
518 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
519 UPF_IOREMAP,
520 .iotype = UPIO_MEM32,
521 .regshift = 2,
522 },
523 {
524 .flags = 0,
525 }
526 };
527 static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
528 {
529 .mapbase = DAVINCI_UART1_BASE,
530 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
531 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
532 UPF_IOREMAP,
533 .iotype = UPIO_MEM32,
534 .regshift = 2,
535 },
536 {
537 .flags = 0,
538 }
539 };
540 static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
541 {
542 .mapbase = DAVINCI_UART2_BASE,
543 .irq = DAVINCI_INTC_IRQ(IRQ_DM646X_UARTINT2),
544 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
545 UPF_IOREMAP,
546 .iotype = UPIO_MEM32,
547 .regshift = 2,
548 },
549 {
550 .flags = 0,
551 }
552 };
553
554 struct platform_device dm646x_serial_device[] = {
555 {
556 .name = "serial8250",
557 .id = PLAT8250_DEV_PLATFORM,
558 .dev = {
559 .platform_data = dm646x_serial0_platform_data,
560 }
561 },
562 {
563 .name = "serial8250",
564 .id = PLAT8250_DEV_PLATFORM1,
565 .dev = {
566 .platform_data = dm646x_serial1_platform_data,
567 }
568 },
569 {
570 .name = "serial8250",
571 .id = PLAT8250_DEV_PLATFORM2,
572 .dev = {
573 .platform_data = dm646x_serial2_platform_data,
574 }
575 },
576 {
577 }
578 };
579
580 static const struct davinci_soc_info davinci_soc_info_dm646x = {
581 .io_desc = dm646x_io_desc,
582 .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
583 .jtag_id_reg = 0x01c40028,
584 .ids = dm646x_ids,
585 .ids_num = ARRAY_SIZE(dm646x_ids),
586 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
587 .pinmux_pins = dm646x_pins,
588 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
589 .emac_pdata = &dm646x_emac_pdata,
590 .sram_dma = 0x10010000,
591 .sram_len = SZ_32K,
592 };
593
dm646x_init_mcasp0(struct snd_platform_data * pdata)594 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
595 {
596 dm646x_mcasp0_device.dev.platform_data = pdata;
597 platform_device_register(&dm646x_mcasp0_device);
598 }
599
dm646x_init_mcasp1(struct snd_platform_data * pdata)600 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
601 {
602 dm646x_mcasp1_device.dev.platform_data = pdata;
603 platform_device_register(&dm646x_mcasp1_device);
604 platform_device_register(&dm646x_dit_device);
605 }
606
dm646x_setup_vpif(struct vpif_display_config * display_config,struct vpif_capture_config * capture_config)607 void dm646x_setup_vpif(struct vpif_display_config *display_config,
608 struct vpif_capture_config *capture_config)
609 {
610 unsigned int value;
611
612 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
613 value &= ~VSCLKDIS_MASK;
614 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
615
616 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
617 value &= ~VDD3P3V_VID_MASK;
618 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
619
620 davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
621 davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
622 davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
623 davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
624
625 vpif_display_dev.dev.platform_data = display_config;
626 vpif_capture_dev.dev.platform_data = capture_config;
627 platform_device_register(&vpif_dev);
628 platform_device_register(&vpif_display_dev);
629 platform_device_register(&vpif_capture_dev);
630 }
631
dm646x_init_edma(struct edma_rsv_info * rsv)632 int __init dm646x_init_edma(struct edma_rsv_info *rsv)
633 {
634 struct platform_device *edma_pdev;
635
636 dm646x_edma_pdata.rsv = rsv;
637
638 edma_pdev = platform_device_register_full(&dm646x_edma_device);
639 return PTR_ERR_OR_ZERO(edma_pdev);
640 }
641
dm646x_init(void)642 void __init dm646x_init(void)
643 {
644 davinci_common_init(&davinci_soc_info_dm646x);
645 davinci_map_sysmod();
646 }
647
dm646x_init_time(unsigned long ref_clk_rate,unsigned long aux_clkin_rate)648 void __init dm646x_init_time(unsigned long ref_clk_rate,
649 unsigned long aux_clkin_rate)
650 {
651 void __iomem *pll1, *psc;
652 struct clk *clk;
653 int rv;
654
655 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate);
656 clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate);
657
658 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
659 dm646x_pll1_init(NULL, pll1, NULL);
660
661 psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
662 dm646x_psc_init(NULL, psc);
663
664 clk = clk_get(NULL, "timer0");
665 if (WARN_ON(IS_ERR(clk))) {
666 pr_err("Unable to get the timer clock\n");
667 return;
668 }
669
670 rv = davinci_timer_register(clk, &dm646x_timer_cfg);
671 WARN(rv, "Unable to register the timer: %d\n", rv);
672 }
673
674 static struct resource dm646x_pll2_resources[] = {
675 {
676 .start = DAVINCI_PLL2_BASE,
677 .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
678 .flags = IORESOURCE_MEM,
679 },
680 };
681
682 static struct platform_device dm646x_pll2_device = {
683 .name = "dm646x-pll2",
684 .id = -1,
685 .resource = dm646x_pll2_resources,
686 .num_resources = ARRAY_SIZE(dm646x_pll2_resources),
687 };
688
dm646x_register_clocks(void)689 void __init dm646x_register_clocks(void)
690 {
691 /* PLL1 and PSC are registered in dm646x_init_time() */
692 platform_device_register(&dm646x_pll2_device);
693 }
694
695 static const struct davinci_aintc_config dm646x_aintc_config = {
696 .reg = {
697 .start = DAVINCI_ARM_INTC_BASE,
698 .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
699 .flags = IORESOURCE_MEM,
700 },
701 .num_irqs = 64,
702 .prios = dm646x_default_priorities,
703 };
704
dm646x_init_irq(void)705 void __init dm646x_init_irq(void)
706 {
707 davinci_aintc_init(&dm646x_aintc_config);
708 }
709
dm646x_init_devices(void)710 static int __init dm646x_init_devices(void)
711 {
712 int ret = 0;
713
714 if (!cpu_is_davinci_dm646x())
715 return 0;
716
717 platform_device_register(&dm646x_mdio_device);
718 platform_device_register(&dm646x_emac_device);
719
720 ret = davinci_init_wdt();
721 if (ret)
722 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
723
724 return ret;
725 }
726 postcore_initcall(dm646x_init_devices);
727