1 /*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12 #include <linux/clk-provider.h>
13 #include <linux/clk/davinci.h>
14 #include <linux/clkdev.h>
15 #include <linux/dmaengine.h>
16 #include <linux/init.h>
17 #include <linux/io.h>
18 #include <linux/irqchip/irq-davinci-aintc.h>
19 #include <linux/platform_data/edma.h>
20 #include <linux/platform_data/gpio-davinci.h>
21 #include <linux/platform_device.h>
22 #include <linux/serial_8250.h>
23
24 #include <clocksource/timer-davinci.h>
25
26 #include <asm/mach/map.h>
27
28 #include "common.h"
29 #include "cputype.h"
30 #include "serial.h"
31 #include "asp.h"
32 #include "davinci.h"
33 #include "irqs.h"
34 #include "mux.h"
35
36 /*
37 * Device specific clocks
38 */
39 #define DM644X_REF_FREQ 27000000
40
41 #define DM644X_EMAC_BASE 0x01c80000
42 #define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
43 #define DM644X_EMAC_CNTRL_OFFSET 0x0000
44 #define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
45 #define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
46 #define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
47
48 static struct emac_platform_data dm644x_emac_pdata = {
49 .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
50 .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
51 .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
52 .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
53 .version = EMAC_VERSION_1,
54 };
55
56 static struct resource dm644x_emac_resources[] = {
57 {
58 .start = DM644X_EMAC_BASE,
59 .end = DM644X_EMAC_BASE + SZ_16K - 1,
60 .flags = IORESOURCE_MEM,
61 },
62 {
63 .start = DAVINCI_INTC_IRQ(IRQ_EMACINT),
64 .end = DAVINCI_INTC_IRQ(IRQ_EMACINT),
65 .flags = IORESOURCE_IRQ,
66 },
67 };
68
69 static struct platform_device dm644x_emac_device = {
70 .name = "davinci_emac",
71 .id = 1,
72 .dev = {
73 .platform_data = &dm644x_emac_pdata,
74 },
75 .num_resources = ARRAY_SIZE(dm644x_emac_resources),
76 .resource = dm644x_emac_resources,
77 };
78
79 static struct resource dm644x_mdio_resources[] = {
80 {
81 .start = DM644X_EMAC_MDIO_BASE,
82 .end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
83 .flags = IORESOURCE_MEM,
84 },
85 };
86
87 static struct platform_device dm644x_mdio_device = {
88 .name = "davinci_mdio",
89 .id = 0,
90 .num_resources = ARRAY_SIZE(dm644x_mdio_resources),
91 .resource = dm644x_mdio_resources,
92 };
93
94 /*
95 * Device specific mux setup
96 *
97 * soc description mux mode mode mux dbg
98 * reg offset mask mode
99 */
100 static const struct mux_config dm644x_pins[] = {
101 #ifdef CONFIG_DAVINCI_MUX
102 MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
103 MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
104 MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
105
106 MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
107
108 MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
109 MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true)
110 MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true)
111 MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true)
112 MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true)
113 MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true)
114
115 MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
116
117 MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
118
119 MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
120
121 MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
122 MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
123
124 MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
125
126 MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
127
128 MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
129
130 MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
131 MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
132 MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
133
134 MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
135
136 MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
137
138 MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
139 MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
140 MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
141 MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
142
143 MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
144
145 MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
146 MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
147 #endif
148 };
149
150 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
151 static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
152 [IRQ_VDINT0] = 2,
153 [IRQ_VDINT1] = 6,
154 [IRQ_VDINT2] = 6,
155 [IRQ_HISTINT] = 6,
156 [IRQ_H3AINT] = 6,
157 [IRQ_PRVUINT] = 6,
158 [IRQ_RSZINT] = 6,
159 [7] = 7,
160 [IRQ_VENCINT] = 6,
161 [IRQ_ASQINT] = 6,
162 [IRQ_IMXINT] = 6,
163 [IRQ_VLCDINT] = 6,
164 [IRQ_USBINT] = 4,
165 [IRQ_EMACINT] = 4,
166 [14] = 7,
167 [15] = 7,
168 [IRQ_CCINT0] = 5, /* dma */
169 [IRQ_CCERRINT] = 5, /* dma */
170 [IRQ_TCERRINT0] = 5, /* dma */
171 [IRQ_TCERRINT] = 5, /* dma */
172 [IRQ_PSCIN] = 7,
173 [21] = 7,
174 [IRQ_IDE] = 4,
175 [23] = 7,
176 [IRQ_MBXINT] = 7,
177 [IRQ_MBRINT] = 7,
178 [IRQ_MMCINT] = 7,
179 [IRQ_SDIOINT] = 7,
180 [28] = 7,
181 [IRQ_DDRINT] = 7,
182 [IRQ_AEMIFINT] = 7,
183 [IRQ_VLQINT] = 4,
184 [IRQ_TINT0_TINT12] = 2, /* clockevent */
185 [IRQ_TINT0_TINT34] = 2, /* clocksource */
186 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
187 [IRQ_TINT1_TINT34] = 7, /* system tick */
188 [IRQ_PWMINT0] = 7,
189 [IRQ_PWMINT1] = 7,
190 [IRQ_PWMINT2] = 7,
191 [IRQ_I2C] = 3,
192 [IRQ_UARTINT0] = 3,
193 [IRQ_UARTINT1] = 3,
194 [IRQ_UARTINT2] = 3,
195 [IRQ_SPINT0] = 3,
196 [IRQ_SPINT1] = 3,
197 [45] = 7,
198 [IRQ_DSP2ARM0] = 4,
199 [IRQ_DSP2ARM1] = 4,
200 [IRQ_GPIO0] = 7,
201 [IRQ_GPIO1] = 7,
202 [IRQ_GPIO2] = 7,
203 [IRQ_GPIO3] = 7,
204 [IRQ_GPIO4] = 7,
205 [IRQ_GPIO5] = 7,
206 [IRQ_GPIO6] = 7,
207 [IRQ_GPIO7] = 7,
208 [IRQ_GPIOBNK0] = 7,
209 [IRQ_GPIOBNK1] = 7,
210 [IRQ_GPIOBNK2] = 7,
211 [IRQ_GPIOBNK3] = 7,
212 [IRQ_GPIOBNK4] = 7,
213 [IRQ_COMMTX] = 7,
214 [IRQ_COMMRX] = 7,
215 [IRQ_EMUINT] = 7,
216 };
217
218 /*----------------------------------------------------------------------*/
219
220 static s8 queue_priority_mapping[][2] = {
221 /* {event queue no, Priority} */
222 {0, 3},
223 {1, 7},
224 {-1, -1},
225 };
226
227 static const struct dma_slave_map dm644x_edma_map[] = {
228 { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
229 { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
230 { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
231 { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
232 { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
233 { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
234 };
235
236 static struct edma_soc_info dm644x_edma_pdata = {
237 .queue_priority_mapping = queue_priority_mapping,
238 .default_queue = EVENTQ_1,
239 .slave_map = dm644x_edma_map,
240 .slavecnt = ARRAY_SIZE(dm644x_edma_map),
241 };
242
243 static struct resource edma_resources[] = {
244 {
245 .name = "edma3_cc",
246 .start = 0x01c00000,
247 .end = 0x01c00000 + SZ_64K - 1,
248 .flags = IORESOURCE_MEM,
249 },
250 {
251 .name = "edma3_tc0",
252 .start = 0x01c10000,
253 .end = 0x01c10000 + SZ_1K - 1,
254 .flags = IORESOURCE_MEM,
255 },
256 {
257 .name = "edma3_tc1",
258 .start = 0x01c10400,
259 .end = 0x01c10400 + SZ_1K - 1,
260 .flags = IORESOURCE_MEM,
261 },
262 {
263 .name = "edma3_ccint",
264 .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
265 .flags = IORESOURCE_IRQ,
266 },
267 {
268 .name = "edma3_ccerrint",
269 .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
270 .flags = IORESOURCE_IRQ,
271 },
272 /* not using TC*_ERR */
273 };
274
275 static const struct platform_device_info dm644x_edma_device __initconst = {
276 .name = "edma",
277 .id = 0,
278 .dma_mask = DMA_BIT_MASK(32),
279 .res = edma_resources,
280 .num_res = ARRAY_SIZE(edma_resources),
281 .data = &dm644x_edma_pdata,
282 .size_data = sizeof(dm644x_edma_pdata),
283 };
284
285 /* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
286 static struct resource dm644x_asp_resources[] = {
287 {
288 .name = "mpu",
289 .start = DAVINCI_ASP0_BASE,
290 .end = DAVINCI_ASP0_BASE + SZ_8K - 1,
291 .flags = IORESOURCE_MEM,
292 },
293 {
294 .start = DAVINCI_DMA_ASP0_TX,
295 .end = DAVINCI_DMA_ASP0_TX,
296 .flags = IORESOURCE_DMA,
297 },
298 {
299 .start = DAVINCI_DMA_ASP0_RX,
300 .end = DAVINCI_DMA_ASP0_RX,
301 .flags = IORESOURCE_DMA,
302 },
303 };
304
305 static struct platform_device dm644x_asp_device = {
306 .name = "davinci-mcbsp",
307 .id = -1,
308 .num_resources = ARRAY_SIZE(dm644x_asp_resources),
309 .resource = dm644x_asp_resources,
310 };
311
312 #define DM644X_VPSS_BASE 0x01c73400
313
314 static struct resource dm644x_vpss_resources[] = {
315 {
316 /* VPSS Base address */
317 .name = "vpss",
318 .start = DM644X_VPSS_BASE,
319 .end = DM644X_VPSS_BASE + 0xff,
320 .flags = IORESOURCE_MEM,
321 },
322 };
323
324 static struct platform_device dm644x_vpss_device = {
325 .name = "vpss",
326 .id = -1,
327 .dev.platform_data = "dm644x_vpss",
328 .num_resources = ARRAY_SIZE(dm644x_vpss_resources),
329 .resource = dm644x_vpss_resources,
330 };
331
332 static struct resource dm644x_vpfe_resources[] = {
333 {
334 .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
335 .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
336 .flags = IORESOURCE_IRQ,
337 },
338 {
339 .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
340 .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
341 .flags = IORESOURCE_IRQ,
342 },
343 };
344
345 static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
346 static struct resource dm644x_ccdc_resource[] = {
347 /* CCDC Base address */
348 {
349 .start = 0x01c70400,
350 .end = 0x01c70400 + 0xff,
351 .flags = IORESOURCE_MEM,
352 },
353 };
354
355 static struct platform_device dm644x_ccdc_dev = {
356 .name = "dm644x_ccdc",
357 .id = -1,
358 .num_resources = ARRAY_SIZE(dm644x_ccdc_resource),
359 .resource = dm644x_ccdc_resource,
360 .dev = {
361 .dma_mask = &dm644x_video_dma_mask,
362 .coherent_dma_mask = DMA_BIT_MASK(32),
363 },
364 };
365
366 static struct platform_device dm644x_vpfe_dev = {
367 .name = CAPTURE_DRV_NAME,
368 .id = -1,
369 .num_resources = ARRAY_SIZE(dm644x_vpfe_resources),
370 .resource = dm644x_vpfe_resources,
371 .dev = {
372 .dma_mask = &dm644x_video_dma_mask,
373 .coherent_dma_mask = DMA_BIT_MASK(32),
374 },
375 };
376
377 #define DM644X_OSD_BASE 0x01c72600
378
379 static struct resource dm644x_osd_resources[] = {
380 {
381 .start = DM644X_OSD_BASE,
382 .end = DM644X_OSD_BASE + 0x1ff,
383 .flags = IORESOURCE_MEM,
384 },
385 };
386
387 static struct platform_device dm644x_osd_dev = {
388 .name = DM644X_VPBE_OSD_SUBDEV_NAME,
389 .id = -1,
390 .num_resources = ARRAY_SIZE(dm644x_osd_resources),
391 .resource = dm644x_osd_resources,
392 .dev = {
393 .dma_mask = &dm644x_video_dma_mask,
394 .coherent_dma_mask = DMA_BIT_MASK(32),
395 },
396 };
397
398 #define DM644X_VENC_BASE 0x01c72400
399
400 static struct resource dm644x_venc_resources[] = {
401 {
402 .start = DM644X_VENC_BASE,
403 .end = DM644X_VENC_BASE + 0x17f,
404 .flags = IORESOURCE_MEM,
405 },
406 };
407
408 #define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0)
409 #define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1)
410 #define DM644X_VPSS_VENCLKEN BIT(3)
411 #define DM644X_VPSS_DACCLKEN BIT(4)
412
dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,unsigned int pclock)413 static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
414 unsigned int pclock)
415 {
416 int ret = 0;
417 u32 v = DM644X_VPSS_VENCLKEN;
418
419 switch (type) {
420 case VPBE_ENC_STD:
421 v |= DM644X_VPSS_DACCLKEN;
422 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
423 break;
424 case VPBE_ENC_DV_TIMINGS:
425 if (pclock <= 27000000) {
426 v |= DM644X_VPSS_DACCLKEN;
427 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
428 } else {
429 /*
430 * For HD, use external clock source since
431 * HD requires higher clock rate
432 */
433 v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
434 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
435 }
436 break;
437 default:
438 ret = -EINVAL;
439 }
440
441 return ret;
442 }
443
444 static struct resource dm644x_v4l2_disp_resources[] = {
445 {
446 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
447 .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
448 .flags = IORESOURCE_IRQ,
449 },
450 };
451
452 static struct platform_device dm644x_vpbe_display = {
453 .name = "vpbe-v4l2",
454 .id = -1,
455 .num_resources = ARRAY_SIZE(dm644x_v4l2_disp_resources),
456 .resource = dm644x_v4l2_disp_resources,
457 .dev = {
458 .dma_mask = &dm644x_video_dma_mask,
459 .coherent_dma_mask = DMA_BIT_MASK(32),
460 },
461 };
462
463 static struct venc_platform_data dm644x_venc_pdata = {
464 .setup_clock = dm644x_venc_setup_clock,
465 };
466
467 static struct platform_device dm644x_venc_dev = {
468 .name = DM644X_VPBE_VENC_SUBDEV_NAME,
469 .id = -1,
470 .num_resources = ARRAY_SIZE(dm644x_venc_resources),
471 .resource = dm644x_venc_resources,
472 .dev = {
473 .dma_mask = &dm644x_video_dma_mask,
474 .coherent_dma_mask = DMA_BIT_MASK(32),
475 .platform_data = &dm644x_venc_pdata,
476 },
477 };
478
479 static struct platform_device dm644x_vpbe_dev = {
480 .name = "vpbe_controller",
481 .id = -1,
482 .dev = {
483 .dma_mask = &dm644x_video_dma_mask,
484 .coherent_dma_mask = DMA_BIT_MASK(32),
485 },
486 };
487
488 static struct resource dm644_gpio_resources[] = {
489 { /* registers */
490 .start = DAVINCI_GPIO_BASE,
491 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
492 .flags = IORESOURCE_MEM,
493 },
494 { /* interrupt */
495 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
496 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
497 .flags = IORESOURCE_IRQ,
498 },
499 {
500 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
501 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
502 .flags = IORESOURCE_IRQ,
503 },
504 {
505 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
506 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
507 .flags = IORESOURCE_IRQ,
508 },
509 {
510 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
511 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
512 .flags = IORESOURCE_IRQ,
513 },
514 {
515 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
516 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
517 .flags = IORESOURCE_IRQ,
518 },
519 };
520
521 static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
522 .no_auto_base = true,
523 .base = 0,
524 .ngpio = 71,
525 };
526
dm644x_gpio_register(void)527 int __init dm644x_gpio_register(void)
528 {
529 return davinci_gpio_register(dm644_gpio_resources,
530 ARRAY_SIZE(dm644_gpio_resources),
531 &dm644_gpio_platform_data);
532 }
533 /*----------------------------------------------------------------------*/
534
535 static struct map_desc dm644x_io_desc[] = {
536 {
537 .virtual = IO_VIRT,
538 .pfn = __phys_to_pfn(IO_PHYS),
539 .length = IO_SIZE,
540 .type = MT_DEVICE
541 },
542 };
543
544 /* Contents of JTAG ID register used to identify exact cpu type */
545 static struct davinci_id dm644x_ids[] = {
546 {
547 .variant = 0x0,
548 .part_no = 0xb700,
549 .manufacturer = 0x017,
550 .cpu_id = DAVINCI_CPU_ID_DM6446,
551 .name = "dm6446",
552 },
553 {
554 .variant = 0x1,
555 .part_no = 0xb700,
556 .manufacturer = 0x017,
557 .cpu_id = DAVINCI_CPU_ID_DM6446,
558 .name = "dm6446a",
559 },
560 };
561
562 /*
563 * Bottom half of timer0 is used for clockevent, top half is used for
564 * clocksource.
565 */
566 static const struct davinci_timer_cfg dm644x_timer_cfg = {
567 .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
568 .irq = {
569 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
570 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
571 },
572 };
573
574 static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
575 {
576 .mapbase = DAVINCI_UART0_BASE,
577 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
578 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
579 UPF_IOREMAP,
580 .iotype = UPIO_MEM,
581 .regshift = 2,
582 },
583 {
584 .flags = 0,
585 }
586 };
587 static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
588 {
589 .mapbase = DAVINCI_UART1_BASE,
590 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
591 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
592 UPF_IOREMAP,
593 .iotype = UPIO_MEM,
594 .regshift = 2,
595 },
596 {
597 .flags = 0,
598 }
599 };
600 static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
601 {
602 .mapbase = DAVINCI_UART2_BASE,
603 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT2),
604 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
605 UPF_IOREMAP,
606 .iotype = UPIO_MEM,
607 .regshift = 2,
608 },
609 {
610 .flags = 0,
611 }
612 };
613
614 struct platform_device dm644x_serial_device[] = {
615 {
616 .name = "serial8250",
617 .id = PLAT8250_DEV_PLATFORM,
618 .dev = {
619 .platform_data = dm644x_serial0_platform_data,
620 }
621 },
622 {
623 .name = "serial8250",
624 .id = PLAT8250_DEV_PLATFORM1,
625 .dev = {
626 .platform_data = dm644x_serial1_platform_data,
627 }
628 },
629 {
630 .name = "serial8250",
631 .id = PLAT8250_DEV_PLATFORM2,
632 .dev = {
633 .platform_data = dm644x_serial2_platform_data,
634 }
635 },
636 {
637 }
638 };
639
640 static const struct davinci_soc_info davinci_soc_info_dm644x = {
641 .io_desc = dm644x_io_desc,
642 .io_desc_num = ARRAY_SIZE(dm644x_io_desc),
643 .jtag_id_reg = 0x01c40028,
644 .ids = dm644x_ids,
645 .ids_num = ARRAY_SIZE(dm644x_ids),
646 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
647 .pinmux_pins = dm644x_pins,
648 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
649 .emac_pdata = &dm644x_emac_pdata,
650 .sram_dma = 0x00008000,
651 .sram_len = SZ_16K,
652 };
653
dm644x_init_asp(void)654 void __init dm644x_init_asp(void)
655 {
656 davinci_cfg_reg(DM644X_MCBSP);
657 platform_device_register(&dm644x_asp_device);
658 }
659
dm644x_init(void)660 void __init dm644x_init(void)
661 {
662 davinci_common_init(&davinci_soc_info_dm644x);
663 davinci_map_sysmod();
664 }
665
dm644x_init_time(void)666 void __init dm644x_init_time(void)
667 {
668 void __iomem *pll1, *psc;
669 struct clk *clk;
670 int rv;
671
672 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ);
673
674 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
675 dm644x_pll1_init(NULL, pll1, NULL);
676
677 psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
678 dm644x_psc_init(NULL, psc);
679
680 clk = clk_get(NULL, "timer0");
681 if (WARN_ON(IS_ERR(clk))) {
682 pr_err("Unable to get the timer clock\n");
683 return;
684 }
685
686 rv = davinci_timer_register(clk, &dm644x_timer_cfg);
687 WARN(rv, "Unable to register the timer: %d\n", rv);
688 }
689
690 static struct resource dm644x_pll2_resources[] = {
691 {
692 .start = DAVINCI_PLL2_BASE,
693 .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
694 .flags = IORESOURCE_MEM,
695 },
696 };
697
698 static struct platform_device dm644x_pll2_device = {
699 .name = "dm644x-pll2",
700 .id = -1,
701 .resource = dm644x_pll2_resources,
702 .num_resources = ARRAY_SIZE(dm644x_pll2_resources),
703 };
704
dm644x_register_clocks(void)705 void __init dm644x_register_clocks(void)
706 {
707 /* PLL1 and PSC are registered in dm644x_init_time() */
708 platform_device_register(&dm644x_pll2_device);
709 }
710
dm644x_init_video(struct vpfe_config * vpfe_cfg,struct vpbe_config * vpbe_cfg)711 int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
712 struct vpbe_config *vpbe_cfg)
713 {
714 if (vpfe_cfg || vpbe_cfg)
715 platform_device_register(&dm644x_vpss_device);
716
717 if (vpfe_cfg) {
718 dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
719 platform_device_register(&dm644x_ccdc_dev);
720 platform_device_register(&dm644x_vpfe_dev);
721 }
722
723 if (vpbe_cfg) {
724 dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
725 platform_device_register(&dm644x_osd_dev);
726 platform_device_register(&dm644x_venc_dev);
727 platform_device_register(&dm644x_vpbe_dev);
728 platform_device_register(&dm644x_vpbe_display);
729 }
730
731 return 0;
732 }
733
734 static const struct davinci_aintc_config dm644x_aintc_config = {
735 .reg = {
736 .start = DAVINCI_ARM_INTC_BASE,
737 .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
738 .flags = IORESOURCE_MEM,
739 },
740 .num_irqs = 64,
741 .prios = dm644x_default_priorities,
742 };
743
dm644x_init_irq(void)744 void __init dm644x_init_irq(void)
745 {
746 davinci_aintc_init(&dm644x_aintc_config);
747 }
748
dm644x_init_devices(void)749 void __init dm644x_init_devices(void)
750 {
751 struct platform_device *edma_pdev;
752 int ret;
753
754 edma_pdev = platform_device_register_full(&dm644x_edma_device);
755 if (IS_ERR(edma_pdev))
756 pr_warn("%s: Failed to register eDMA\n", __func__);
757
758 platform_device_register(&dm644x_mdio_device);
759 platform_device_register(&dm644x_emac_device);
760
761 ret = davinci_init_wdt();
762 if (ret)
763 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
764
765 }
766