1 /*
2  * include/linux/mfd/wm8994/registers.h -- Register definitions for WM8994
3  *
4  * Copyright 2009 Wolfson Microelectronics PLC.
5  *
6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7  *
8  *  This program is free software; you can redistribute  it and/or modify it
9  *  under  the terms of  the GNU General  Public License as published by the
10  *  Free Software Foundation;  either version 2 of the  License, or (at your
11  *  option) any later version.
12  *
13  */
14 
15 #ifndef __MFD_WM8994_REGISTERS_H__
16 #define __MFD_WM8994_REGISTERS_H__
17 
18 /*
19  * Register values.
20  */
21 #define WM8994_SOFTWARE_RESET                   0x00
22 #define WM8994_POWER_MANAGEMENT_1               0x01
23 #define WM8994_POWER_MANAGEMENT_2               0x02
24 #define WM8994_POWER_MANAGEMENT_3               0x03
25 #define WM8994_POWER_MANAGEMENT_4               0x04
26 #define WM8994_POWER_MANAGEMENT_5               0x05
27 #define WM8994_POWER_MANAGEMENT_6               0x06
28 #define WM8994_INPUT_MIXER_1                    0x15
29 #define WM8994_LEFT_LINE_INPUT_1_2_VOLUME       0x18
30 #define WM8994_LEFT_LINE_INPUT_3_4_VOLUME       0x19
31 #define WM8994_RIGHT_LINE_INPUT_1_2_VOLUME      0x1A
32 #define WM8994_RIGHT_LINE_INPUT_3_4_VOLUME      0x1B
33 #define WM8994_LEFT_OUTPUT_VOLUME               0x1C
34 #define WM8994_RIGHT_OUTPUT_VOLUME              0x1D
35 #define WM8994_LINE_OUTPUTS_VOLUME              0x1E
36 #define WM8994_HPOUT2_VOLUME                    0x1F
37 #define WM8994_LEFT_OPGA_VOLUME                 0x20
38 #define WM8994_RIGHT_OPGA_VOLUME                0x21
39 #define WM8994_SPKMIXL_ATTENUATION              0x22
40 #define WM8994_SPKMIXR_ATTENUATION              0x23
41 #define WM8994_SPKOUT_MIXERS                    0x24
42 #define WM8994_CLASSD                           0x25
43 #define WM8994_SPEAKER_VOLUME_LEFT              0x26
44 #define WM8994_SPEAKER_VOLUME_RIGHT             0x27
45 #define WM8994_INPUT_MIXER_2                    0x28
46 #define WM8994_INPUT_MIXER_3                    0x29
47 #define WM8994_INPUT_MIXER_4                    0x2A
48 #define WM8994_INPUT_MIXER_5                    0x2B
49 #define WM8994_INPUT_MIXER_6                    0x2C
50 #define WM8994_OUTPUT_MIXER_1                   0x2D
51 #define WM8994_OUTPUT_MIXER_2                   0x2E
52 #define WM8994_OUTPUT_MIXER_3                   0x2F
53 #define WM8994_OUTPUT_MIXER_4                   0x30
54 #define WM8994_OUTPUT_MIXER_5                   0x31
55 #define WM8994_OUTPUT_MIXER_6                   0x32
56 #define WM8994_HPOUT2_MIXER                     0x33
57 #define WM8994_LINE_MIXER_1                     0x34
58 #define WM8994_LINE_MIXER_2                     0x35
59 #define WM8994_SPEAKER_MIXER                    0x36
60 #define WM8994_ADDITIONAL_CONTROL               0x37
61 #define WM8994_ANTIPOP_1                        0x38
62 #define WM8994_ANTIPOP_2                        0x39
63 #define WM8994_MICBIAS                          0x3A
64 #define WM8994_LDO_1                            0x3B
65 #define WM8994_LDO_2                            0x3C
66 #define WM8958_MICBIAS1				0x3D
67 #define WM8958_MICBIAS2				0x3E
68 #define WM8994_CHARGE_PUMP_1                    0x4C
69 #define WM8958_CHARGE_PUMP_2                    0x4D
70 #define WM8994_CLASS_W_1                        0x51
71 #define WM8994_DC_SERVO_1                       0x54
72 #define WM8994_DC_SERVO_2                       0x55
73 #define WM8994_DC_SERVO_4                       0x57
74 #define WM8994_DC_SERVO_READBACK                0x58
75 #define WM8994_DC_SERVO_4E			0x59
76 #define WM8994_ANALOGUE_HP_1                    0x60
77 #define WM8958_MIC_DETECT_1                     0xD0
78 #define WM8958_MIC_DETECT_2                     0xD1
79 #define WM8958_MIC_DETECT_3                     0xD2
80 #define WM8994_CHIP_REVISION                    0x100
81 #define WM8994_CONTROL_INTERFACE                0x101
82 #define WM8994_WRITE_SEQUENCER_CTRL_1           0x110
83 #define WM8994_WRITE_SEQUENCER_CTRL_2           0x111
84 #define WM8994_AIF1_CLOCKING_1                  0x200
85 #define WM8994_AIF1_CLOCKING_2                  0x201
86 #define WM8994_AIF2_CLOCKING_1                  0x204
87 #define WM8994_AIF2_CLOCKING_2                  0x205
88 #define WM8994_CLOCKING_1                       0x208
89 #define WM8994_CLOCKING_2                       0x209
90 #define WM8994_AIF1_RATE                        0x210
91 #define WM8994_AIF2_RATE                        0x211
92 #define WM8994_RATE_STATUS                      0x212
93 #define WM8994_FLL1_CONTROL_1                   0x220
94 #define WM8994_FLL1_CONTROL_2                   0x221
95 #define WM8994_FLL1_CONTROL_3                   0x222
96 #define WM8994_FLL1_CONTROL_4                   0x223
97 #define WM8994_FLL1_CONTROL_5                   0x224
98 #define WM8958_FLL1_EFS_1                       0x226
99 #define WM8958_FLL1_EFS_2                       0x227
100 #define WM8994_FLL2_CONTROL_1                   0x240
101 #define WM8994_FLL2_CONTROL_2                   0x241
102 #define WM8994_FLL2_CONTROL_3                   0x242
103 #define WM8994_FLL2_CONTROL_4                   0x243
104 #define WM8994_FLL2_CONTROL_5                   0x244
105 #define WM8958_FLL2_EFS_1                       0x246
106 #define WM8958_FLL2_EFS_2                       0x247
107 #define WM8994_AIF1_CONTROL_1                   0x300
108 #define WM8994_AIF1_CONTROL_2                   0x301
109 #define WM8994_AIF1_MASTER_SLAVE                0x302
110 #define WM8994_AIF1_BCLK                        0x303
111 #define WM8994_AIF1ADC_LRCLK                    0x304
112 #define WM8994_AIF1DAC_LRCLK                    0x305
113 #define WM8994_AIF1DAC_DATA                     0x306
114 #define WM8994_AIF1ADC_DATA                     0x307
115 #define WM8994_AIF2_CONTROL_1                   0x310
116 #define WM8994_AIF2_CONTROL_2                   0x311
117 #define WM8994_AIF2_MASTER_SLAVE                0x312
118 #define WM8994_AIF2_BCLK                        0x313
119 #define WM8994_AIF2ADC_LRCLK                    0x314
120 #define WM8994_AIF2DAC_LRCLK                    0x315
121 #define WM8994_AIF2DAC_DATA                     0x316
122 #define WM8994_AIF2ADC_DATA                     0x317
123 #define WM1811_AIF2TX_CONTROL                   0x318
124 #define WM8958_AIF3_CONTROL_1                   0x320
125 #define WM8958_AIF3_CONTROL_2                   0x321
126 #define WM8958_AIF3DAC_DATA                     0x322
127 #define WM8958_AIF3ADC_DATA                     0x323
128 #define WM8994_AIF1_ADC1_LEFT_VOLUME            0x400
129 #define WM8994_AIF1_ADC1_RIGHT_VOLUME           0x401
130 #define WM8994_AIF1_DAC1_LEFT_VOLUME            0x402
131 #define WM8994_AIF1_DAC1_RIGHT_VOLUME           0x403
132 #define WM8994_AIF1_ADC2_LEFT_VOLUME            0x404
133 #define WM8994_AIF1_ADC2_RIGHT_VOLUME           0x405
134 #define WM8994_AIF1_DAC2_LEFT_VOLUME            0x406
135 #define WM8994_AIF1_DAC2_RIGHT_VOLUME           0x407
136 #define WM8994_AIF1_ADC1_FILTERS                0x410
137 #define WM8994_AIF1_ADC2_FILTERS                0x411
138 #define WM8994_AIF1_DAC1_FILTERS_1              0x420
139 #define WM8994_AIF1_DAC1_FILTERS_2              0x421
140 #define WM8994_AIF1_DAC2_FILTERS_1              0x422
141 #define WM8994_AIF1_DAC2_FILTERS_2              0x423
142 #define WM8958_AIF1_DAC1_NOISE_GATE             0x430
143 #define WM8958_AIF1_DAC2_NOISE_GATE             0x431
144 #define WM8994_AIF1_DRC1_1                      0x440
145 #define WM8994_AIF1_DRC1_2                      0x441
146 #define WM8994_AIF1_DRC1_3                      0x442
147 #define WM8994_AIF1_DRC1_4                      0x443
148 #define WM8994_AIF1_DRC1_5                      0x444
149 #define WM8994_AIF1_DRC2_1                      0x450
150 #define WM8994_AIF1_DRC2_2                      0x451
151 #define WM8994_AIF1_DRC2_3                      0x452
152 #define WM8994_AIF1_DRC2_4                      0x453
153 #define WM8994_AIF1_DRC2_5                      0x454
154 #define WM8994_AIF1_DAC1_EQ_GAINS_1             0x480
155 #define WM8994_AIF1_DAC1_EQ_GAINS_2             0x481
156 #define WM8994_AIF1_DAC1_EQ_BAND_1_A            0x482
157 #define WM8994_AIF1_DAC1_EQ_BAND_1_B            0x483
158 #define WM8994_AIF1_DAC1_EQ_BAND_1_PG           0x484
159 #define WM8994_AIF1_DAC1_EQ_BAND_2_A            0x485
160 #define WM8994_AIF1_DAC1_EQ_BAND_2_B            0x486
161 #define WM8994_AIF1_DAC1_EQ_BAND_2_C            0x487
162 #define WM8994_AIF1_DAC1_EQ_BAND_2_PG           0x488
163 #define WM8994_AIF1_DAC1_EQ_BAND_3_A            0x489
164 #define WM8994_AIF1_DAC1_EQ_BAND_3_B            0x48A
165 #define WM8994_AIF1_DAC1_EQ_BAND_3_C            0x48B
166 #define WM8994_AIF1_DAC1_EQ_BAND_3_PG           0x48C
167 #define WM8994_AIF1_DAC1_EQ_BAND_4_A            0x48D
168 #define WM8994_AIF1_DAC1_EQ_BAND_4_B            0x48E
169 #define WM8994_AIF1_DAC1_EQ_BAND_4_C            0x48F
170 #define WM8994_AIF1_DAC1_EQ_BAND_4_PG           0x490
171 #define WM8994_AIF1_DAC1_EQ_BAND_5_A            0x491
172 #define WM8994_AIF1_DAC1_EQ_BAND_5_B            0x492
173 #define WM8994_AIF1_DAC1_EQ_BAND_5_PG           0x493
174 #define WM8994_AIF1_DAC1_EQ_BAND_1_C            0x494
175 #define WM8994_AIF1_DAC2_EQ_GAINS_1             0x4A0
176 #define WM8994_AIF1_DAC2_EQ_GAINS_2             0x4A1
177 #define WM8994_AIF1_DAC2_EQ_BAND_1_A            0x4A2
178 #define WM8994_AIF1_DAC2_EQ_BAND_1_B            0x4A3
179 #define WM8994_AIF1_DAC2_EQ_BAND_1_PG           0x4A4
180 #define WM8994_AIF1_DAC2_EQ_BAND_2_A            0x4A5
181 #define WM8994_AIF1_DAC2_EQ_BAND_2_B            0x4A6
182 #define WM8994_AIF1_DAC2_EQ_BAND_2_C            0x4A7
183 #define WM8994_AIF1_DAC2_EQ_BAND_2_PG           0x4A8
184 #define WM8994_AIF1_DAC2_EQ_BAND_3_A            0x4A9
185 #define WM8994_AIF1_DAC2_EQ_BAND_3_B            0x4AA
186 #define WM8994_AIF1_DAC2_EQ_BAND_3_C            0x4AB
187 #define WM8994_AIF1_DAC2_EQ_BAND_3_PG           0x4AC
188 #define WM8994_AIF1_DAC2_EQ_BAND_4_A            0x4AD
189 #define WM8994_AIF1_DAC2_EQ_BAND_4_B            0x4AE
190 #define WM8994_AIF1_DAC2_EQ_BAND_4_C            0x4AF
191 #define WM8994_AIF1_DAC2_EQ_BAND_4_PG           0x4B0
192 #define WM8994_AIF1_DAC2_EQ_BAND_5_A            0x4B1
193 #define WM8994_AIF1_DAC2_EQ_BAND_5_B            0x4B2
194 #define WM8994_AIF1_DAC2_EQ_BAND_5_PG           0x4B3
195 #define WM8994_AIF1_DAC2_EQ_BAND_1_C            0x4B4
196 #define WM8994_AIF2_ADC_LEFT_VOLUME             0x500
197 #define WM8994_AIF2_ADC_RIGHT_VOLUME            0x501
198 #define WM8994_AIF2_DAC_LEFT_VOLUME             0x502
199 #define WM8994_AIF2_DAC_RIGHT_VOLUME            0x503
200 #define WM8994_AIF2_ADC_FILTERS                 0x510
201 #define WM8994_AIF2_DAC_FILTERS_1               0x520
202 #define WM8994_AIF2_DAC_FILTERS_2               0x521
203 #define WM8958_AIF2_DAC_NOISE_GATE              0x530
204 #define WM8994_AIF2_DRC_1                       0x540
205 #define WM8994_AIF2_DRC_2                       0x541
206 #define WM8994_AIF2_DRC_3                       0x542
207 #define WM8994_AIF2_DRC_4                       0x543
208 #define WM8994_AIF2_DRC_5                       0x544
209 #define WM8994_AIF2_EQ_GAINS_1                  0x580
210 #define WM8994_AIF2_EQ_GAINS_2                  0x581
211 #define WM8994_AIF2_EQ_BAND_1_A                 0x582
212 #define WM8994_AIF2_EQ_BAND_1_B                 0x583
213 #define WM8994_AIF2_EQ_BAND_1_PG                0x584
214 #define WM8994_AIF2_EQ_BAND_2_A                 0x585
215 #define WM8994_AIF2_EQ_BAND_2_B                 0x586
216 #define WM8994_AIF2_EQ_BAND_2_C                 0x587
217 #define WM8994_AIF2_EQ_BAND_2_PG                0x588
218 #define WM8994_AIF2_EQ_BAND_3_A                 0x589
219 #define WM8994_AIF2_EQ_BAND_3_B                 0x58A
220 #define WM8994_AIF2_EQ_BAND_3_C                 0x58B
221 #define WM8994_AIF2_EQ_BAND_3_PG                0x58C
222 #define WM8994_AIF2_EQ_BAND_4_A                 0x58D
223 #define WM8994_AIF2_EQ_BAND_4_B                 0x58E
224 #define WM8994_AIF2_EQ_BAND_4_C                 0x58F
225 #define WM8994_AIF2_EQ_BAND_4_PG                0x590
226 #define WM8994_AIF2_EQ_BAND_5_A                 0x591
227 #define WM8994_AIF2_EQ_BAND_5_B                 0x592
228 #define WM8994_AIF2_EQ_BAND_5_PG                0x593
229 #define WM8994_AIF2_EQ_BAND_1_C                 0x594
230 #define WM8994_DAC1_MIXER_VOLUMES               0x600
231 #define WM8994_DAC1_LEFT_MIXER_ROUTING          0x601
232 #define WM8994_DAC1_RIGHT_MIXER_ROUTING         0x602
233 #define WM8994_DAC2_MIXER_VOLUMES               0x603
234 #define WM8994_DAC2_LEFT_MIXER_ROUTING          0x604
235 #define WM8994_DAC2_RIGHT_MIXER_ROUTING         0x605
236 #define WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING     0x606
237 #define WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING    0x607
238 #define WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING     0x608
239 #define WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING    0x609
240 #define WM8994_DAC1_LEFT_VOLUME                 0x610
241 #define WM8994_DAC1_RIGHT_VOLUME                0x611
242 #define WM8994_DAC2_LEFT_VOLUME                 0x612
243 #define WM8994_DAC2_RIGHT_VOLUME                0x613
244 #define WM8994_DAC_SOFTMUTE                     0x614
245 #define WM8994_OVERSAMPLING                     0x620
246 #define WM8994_SIDETONE                         0x621
247 #define WM8994_GPIO_1                           0x700
248 #define WM8994_GPIO_2                           0x701
249 #define WM8994_GPIO_3                           0x702
250 #define WM8994_GPIO_4                           0x703
251 #define WM8994_GPIO_5                           0x704
252 #define WM8994_GPIO_6                           0x705
253 #define WM1811_JACKDET_CTRL			0x705
254 #define WM8994_GPIO_7                           0x706
255 #define WM8994_GPIO_8                           0x707
256 #define WM8994_GPIO_9                           0x708
257 #define WM8994_GPIO_10                          0x709
258 #define WM8994_GPIO_11                          0x70A
259 #define WM8994_PULL_CONTROL_1                   0x720
260 #define WM8994_PULL_CONTROL_2                   0x721
261 #define WM8994_INTERRUPT_STATUS_1               0x730
262 #define WM8994_INTERRUPT_STATUS_2               0x731
263 #define WM8994_INTERRUPT_RAW_STATUS_2           0x732
264 #define WM8994_INTERRUPT_STATUS_1_MASK          0x738
265 #define WM8994_INTERRUPT_STATUS_2_MASK          0x739
266 #define WM8994_INTERRUPT_CONTROL                0x740
267 #define WM8994_IRQ_DEBOUNCE                     0x748
268 #define WM8958_DSP2_PROGRAM                     0x900
269 #define WM8958_DSP2_CONFIG                      0x901
270 #define WM8958_DSP2_MAGICNUM                    0xA00
271 #define WM8958_DSP2_RELEASEYEAR                 0xA01
272 #define WM8958_DSP2_RELEASEMONTHDAY             0xA02
273 #define WM8958_DSP2_RELEASETIME                 0xA03
274 #define WM8958_DSP2_VERMAJMIN                   0xA04
275 #define WM8958_DSP2_VERBUILD                    0xA05
276 #define WM8958_DSP2_TESTREG                     0xA06
277 #define WM8958_DSP2_XORREG                      0xA07
278 #define WM8958_DSP2_SHIFTMAXX                   0xA08
279 #define WM8958_DSP2_SHIFTMAXY                   0xA09
280 #define WM8958_DSP2_SHIFTMAXZ                   0xA0A
281 #define WM8958_DSP2_SHIFTMAXEXTLO               0xA0B
282 #define WM8958_DSP2_AESSELECT                   0xA0C
283 #define WM8958_DSP2_EXECCONTROL                 0xA0D
284 #define WM8958_DSP2_SAMPLEBREAK                 0xA0E
285 #define WM8958_DSP2_COUNTBREAK                  0xA0F
286 #define WM8958_DSP2_INTSTATUS                   0xA10
287 #define WM8958_DSP2_EVENTSTATUS                 0xA11
288 #define WM8958_DSP2_INTMASK                     0xA12
289 #define WM8958_DSP2_CONFIGDWIDTH                0xA13
290 #define WM8958_DSP2_CONFIGINSTR                 0xA14
291 #define WM8958_DSP2_CONFIGDMEM                  0xA15
292 #define WM8958_DSP2_CONFIGDELAYS                0xA16
293 #define WM8958_DSP2_CONFIGNUMIO                 0xA17
294 #define WM8958_DSP2_CONFIGEXTDEPTH              0xA18
295 #define WM8958_DSP2_CONFIGMULTIPLIER            0xA19
296 #define WM8958_DSP2_CONFIGCTRLDWIDTH            0xA1A
297 #define WM8958_DSP2_CONFIGPIPELINE              0xA1B
298 #define WM8958_DSP2_SHIFTMAXEXTHI               0xA1C
299 #define WM8958_DSP2_SWVERSIONREG                0xA1D
300 #define WM8958_DSP2_CONFIGXMEM                  0xA1E
301 #define WM8958_DSP2_CONFIGYMEM                  0xA1F
302 #define WM8958_DSP2_CONFIGZMEM                  0xA20
303 #define WM8958_FW_BUILD_1                       0x2000
304 #define WM8958_FW_BUILD_0                       0x2001
305 #define WM8958_FW_ID_1                          0x2002
306 #define WM8958_FW_ID_0                          0x2003
307 #define WM8958_FW_MAJOR_1                       0x2004
308 #define WM8958_FW_MAJOR_0                       0x2005
309 #define WM8958_FW_MINOR_1                       0x2006
310 #define WM8958_FW_MINOR_0                       0x2007
311 #define WM8958_FW_PATCH_1                       0x2008
312 #define WM8958_FW_PATCH_0                       0x2009
313 #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1     0x2200
314 #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_2     0x2201
315 #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_1     0x2202
316 #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_2     0x2203
317 #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C3_1     0x2204
318 #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C3_2     0x2205
319 #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C2_1     0x2206
320 #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C2_2     0x2207
321 #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C3_1     0x2208
322 #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C3_2     0x2209
323 #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C1_1     0x220A
324 #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C1_2     0x220B
325 #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C1_1     0x220C
326 #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C1_2     0x220D
327 #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C2_1     0x220E
328 #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C2_2     0x220F
329 #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C3_1     0x2210
330 #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C3_2     0x2211
331 #define WM8958_MBC_BAND_1_LOWER_CUTOFF_1        0x2212
332 #define WM8958_MBC_BAND_1_LOWER_CUTOFF_2        0x2213
333 #define WM8958_MBC_BAND_1_K_1                   0x2400
334 #define WM8958_MBC_BAND_1_K_2                   0x2401
335 #define WM8958_MBC_BAND_1_N1_1                  0x2402
336 #define WM8958_MBC_BAND_1_N1_2                  0x2403
337 #define WM8958_MBC_BAND_1_N2_1                  0x2404
338 #define WM8958_MBC_BAND_1_N2_2                  0x2405
339 #define WM8958_MBC_BAND_1_N3_1                  0x2406
340 #define WM8958_MBC_BAND_1_N3_2                  0x2407
341 #define WM8958_MBC_BAND_1_N4_1                  0x2408
342 #define WM8958_MBC_BAND_1_N4_2                  0x2409
343 #define WM8958_MBC_BAND_1_N5_1                  0x240A
344 #define WM8958_MBC_BAND_1_N5_2                  0x240B
345 #define WM8958_MBC_BAND_1_X1_1                  0x240C
346 #define WM8958_MBC_BAND_1_X1_2                  0x240D
347 #define WM8958_MBC_BAND_1_X2_1                  0x240E
348 #define WM8958_MBC_BAND_1_X2_2                  0x240F
349 #define WM8958_MBC_BAND_1_X3_1                  0x2410
350 #define WM8958_MBC_BAND_1_X3_2                  0x2411
351 #define WM8958_MBC_BAND_1_ATTACK_1              0x2412
352 #define WM8958_MBC_BAND_1_ATTACK_2              0x2413
353 #define WM8958_MBC_BAND_1_DECAY_1               0x2414
354 #define WM8958_MBC_BAND_1_DECAY_2               0x2415
355 #define WM8958_MBC_BAND_2_K_1                   0x2416
356 #define WM8958_MBC_BAND_2_K_2                   0x2417
357 #define WM8958_MBC_BAND_2_N1_1                  0x2418
358 #define WM8958_MBC_BAND_2_N1_2                  0x2419
359 #define WM8958_MBC_BAND_2_N2_1                  0x241A
360 #define WM8958_MBC_BAND_2_N2_2                  0x241B
361 #define WM8958_MBC_BAND_2_N3_1                  0x241C
362 #define WM8958_MBC_BAND_2_N3_2                  0x241D
363 #define WM8958_MBC_BAND_2_N4_1                  0x241E
364 #define WM8958_MBC_BAND_2_N4_2                  0x241F
365 #define WM8958_MBC_BAND_2_N5_1                  0x2420
366 #define WM8958_MBC_BAND_2_N5_2                  0x2421
367 #define WM8958_MBC_BAND_2_X1_1                  0x2422
368 #define WM8958_MBC_BAND_2_X1_2                  0x2423
369 #define WM8958_MBC_BAND_2_X2_1                  0x2424
370 #define WM8958_MBC_BAND_2_X2_2                  0x2425
371 #define WM8958_MBC_BAND_2_X3_1                  0x2426
372 #define WM8958_MBC_BAND_2_X3_2                  0x2427
373 #define WM8958_MBC_BAND_2_ATTACK_1              0x2428
374 #define WM8958_MBC_BAND_2_ATTACK_2              0x2429
375 #define WM8958_MBC_BAND_2_DECAY_1               0x242A
376 #define WM8958_MBC_BAND_2_DECAY_2               0x242B
377 #define WM8958_MBC_B2_PG2_1                     0x242C
378 #define WM8958_MBC_B2_PG2_2                     0x242D
379 #define WM8958_MBC_B1_PG2_1                     0x242E
380 #define WM8958_MBC_B1_PG2_2                     0x242F
381 #define WM8958_MBC_CROSSOVER_1                  0x2600
382 #define WM8958_MBC_CROSSOVER_2                  0x2601
383 #define WM8958_MBC_HPF_1                        0x2602
384 #define WM8958_MBC_HPF_2                        0x2603
385 #define WM8958_MBC_LPF_1                        0x2606
386 #define WM8958_MBC_LPF_2                        0x2607
387 #define WM8958_MBC_RMS_LIMIT_1                  0x260A
388 #define WM8958_MBC_RMS_LIMIT_2                  0x260B
389 #define WM8994_WRITE_SEQUENCER_0                0x3000
390 #define WM8994_WRITE_SEQUENCER_1                0x3001
391 #define WM8994_WRITE_SEQUENCER_2                0x3002
392 #define WM8994_WRITE_SEQUENCER_3                0x3003
393 #define WM8994_WRITE_SEQUENCER_4                0x3004
394 #define WM8994_WRITE_SEQUENCER_5                0x3005
395 #define WM8994_WRITE_SEQUENCER_6                0x3006
396 #define WM8994_WRITE_SEQUENCER_7                0x3007
397 #define WM8994_WRITE_SEQUENCER_8                0x3008
398 #define WM8994_WRITE_SEQUENCER_9                0x3009
399 #define WM8994_WRITE_SEQUENCER_10               0x300A
400 #define WM8994_WRITE_SEQUENCER_11               0x300B
401 #define WM8994_WRITE_SEQUENCER_12               0x300C
402 #define WM8994_WRITE_SEQUENCER_13               0x300D
403 #define WM8994_WRITE_SEQUENCER_14               0x300E
404 #define WM8994_WRITE_SEQUENCER_15               0x300F
405 #define WM8994_WRITE_SEQUENCER_16               0x3010
406 #define WM8994_WRITE_SEQUENCER_17               0x3011
407 #define WM8994_WRITE_SEQUENCER_18               0x3012
408 #define WM8994_WRITE_SEQUENCER_19               0x3013
409 #define WM8994_WRITE_SEQUENCER_20               0x3014
410 #define WM8994_WRITE_SEQUENCER_21               0x3015
411 #define WM8994_WRITE_SEQUENCER_22               0x3016
412 #define WM8994_WRITE_SEQUENCER_23               0x3017
413 #define WM8994_WRITE_SEQUENCER_24               0x3018
414 #define WM8994_WRITE_SEQUENCER_25               0x3019
415 #define WM8994_WRITE_SEQUENCER_26               0x301A
416 #define WM8994_WRITE_SEQUENCER_27               0x301B
417 #define WM8994_WRITE_SEQUENCER_28               0x301C
418 #define WM8994_WRITE_SEQUENCER_29               0x301D
419 #define WM8994_WRITE_SEQUENCER_30               0x301E
420 #define WM8994_WRITE_SEQUENCER_31               0x301F
421 #define WM8994_WRITE_SEQUENCER_32               0x3020
422 #define WM8994_WRITE_SEQUENCER_33               0x3021
423 #define WM8994_WRITE_SEQUENCER_34               0x3022
424 #define WM8994_WRITE_SEQUENCER_35               0x3023
425 #define WM8994_WRITE_SEQUENCER_36               0x3024
426 #define WM8994_WRITE_SEQUENCER_37               0x3025
427 #define WM8994_WRITE_SEQUENCER_38               0x3026
428 #define WM8994_WRITE_SEQUENCER_39               0x3027
429 #define WM8994_WRITE_SEQUENCER_40               0x3028
430 #define WM8994_WRITE_SEQUENCER_41               0x3029
431 #define WM8994_WRITE_SEQUENCER_42               0x302A
432 #define WM8994_WRITE_SEQUENCER_43               0x302B
433 #define WM8994_WRITE_SEQUENCER_44               0x302C
434 #define WM8994_WRITE_SEQUENCER_45               0x302D
435 #define WM8994_WRITE_SEQUENCER_46               0x302E
436 #define WM8994_WRITE_SEQUENCER_47               0x302F
437 #define WM8994_WRITE_SEQUENCER_48               0x3030
438 #define WM8994_WRITE_SEQUENCER_49               0x3031
439 #define WM8994_WRITE_SEQUENCER_50               0x3032
440 #define WM8994_WRITE_SEQUENCER_51               0x3033
441 #define WM8994_WRITE_SEQUENCER_52               0x3034
442 #define WM8994_WRITE_SEQUENCER_53               0x3035
443 #define WM8994_WRITE_SEQUENCER_54               0x3036
444 #define WM8994_WRITE_SEQUENCER_55               0x3037
445 #define WM8994_WRITE_SEQUENCER_56               0x3038
446 #define WM8994_WRITE_SEQUENCER_57               0x3039
447 #define WM8994_WRITE_SEQUENCER_58               0x303A
448 #define WM8994_WRITE_SEQUENCER_59               0x303B
449 #define WM8994_WRITE_SEQUENCER_60               0x303C
450 #define WM8994_WRITE_SEQUENCER_61               0x303D
451 #define WM8994_WRITE_SEQUENCER_62               0x303E
452 #define WM8994_WRITE_SEQUENCER_63               0x303F
453 #define WM8994_WRITE_SEQUENCER_64               0x3040
454 #define WM8994_WRITE_SEQUENCER_65               0x3041
455 #define WM8994_WRITE_SEQUENCER_66               0x3042
456 #define WM8994_WRITE_SEQUENCER_67               0x3043
457 #define WM8994_WRITE_SEQUENCER_68               0x3044
458 #define WM8994_WRITE_SEQUENCER_69               0x3045
459 #define WM8994_WRITE_SEQUENCER_70               0x3046
460 #define WM8994_WRITE_SEQUENCER_71               0x3047
461 #define WM8994_WRITE_SEQUENCER_72               0x3048
462 #define WM8994_WRITE_SEQUENCER_73               0x3049
463 #define WM8994_WRITE_SEQUENCER_74               0x304A
464 #define WM8994_WRITE_SEQUENCER_75               0x304B
465 #define WM8994_WRITE_SEQUENCER_76               0x304C
466 #define WM8994_WRITE_SEQUENCER_77               0x304D
467 #define WM8994_WRITE_SEQUENCER_78               0x304E
468 #define WM8994_WRITE_SEQUENCER_79               0x304F
469 #define WM8994_WRITE_SEQUENCER_80               0x3050
470 #define WM8994_WRITE_SEQUENCER_81               0x3051
471 #define WM8994_WRITE_SEQUENCER_82               0x3052
472 #define WM8994_WRITE_SEQUENCER_83               0x3053
473 #define WM8994_WRITE_SEQUENCER_84               0x3054
474 #define WM8994_WRITE_SEQUENCER_85               0x3055
475 #define WM8994_WRITE_SEQUENCER_86               0x3056
476 #define WM8994_WRITE_SEQUENCER_87               0x3057
477 #define WM8994_WRITE_SEQUENCER_88               0x3058
478 #define WM8994_WRITE_SEQUENCER_89               0x3059
479 #define WM8994_WRITE_SEQUENCER_90               0x305A
480 #define WM8994_WRITE_SEQUENCER_91               0x305B
481 #define WM8994_WRITE_SEQUENCER_92               0x305C
482 #define WM8994_WRITE_SEQUENCER_93               0x305D
483 #define WM8994_WRITE_SEQUENCER_94               0x305E
484 #define WM8994_WRITE_SEQUENCER_95               0x305F
485 #define WM8994_WRITE_SEQUENCER_96               0x3060
486 #define WM8994_WRITE_SEQUENCER_97               0x3061
487 #define WM8994_WRITE_SEQUENCER_98               0x3062
488 #define WM8994_WRITE_SEQUENCER_99               0x3063
489 #define WM8994_WRITE_SEQUENCER_100              0x3064
490 #define WM8994_WRITE_SEQUENCER_101              0x3065
491 #define WM8994_WRITE_SEQUENCER_102              0x3066
492 #define WM8994_WRITE_SEQUENCER_103              0x3067
493 #define WM8994_WRITE_SEQUENCER_104              0x3068
494 #define WM8994_WRITE_SEQUENCER_105              0x3069
495 #define WM8994_WRITE_SEQUENCER_106              0x306A
496 #define WM8994_WRITE_SEQUENCER_107              0x306B
497 #define WM8994_WRITE_SEQUENCER_108              0x306C
498 #define WM8994_WRITE_SEQUENCER_109              0x306D
499 #define WM8994_WRITE_SEQUENCER_110              0x306E
500 #define WM8994_WRITE_SEQUENCER_111              0x306F
501 #define WM8994_WRITE_SEQUENCER_112              0x3070
502 #define WM8994_WRITE_SEQUENCER_113              0x3071
503 #define WM8994_WRITE_SEQUENCER_114              0x3072
504 #define WM8994_WRITE_SEQUENCER_115              0x3073
505 #define WM8994_WRITE_SEQUENCER_116              0x3074
506 #define WM8994_WRITE_SEQUENCER_117              0x3075
507 #define WM8994_WRITE_SEQUENCER_118              0x3076
508 #define WM8994_WRITE_SEQUENCER_119              0x3077
509 #define WM8994_WRITE_SEQUENCER_120              0x3078
510 #define WM8994_WRITE_SEQUENCER_121              0x3079
511 #define WM8994_WRITE_SEQUENCER_122              0x307A
512 #define WM8994_WRITE_SEQUENCER_123              0x307B
513 #define WM8994_WRITE_SEQUENCER_124              0x307C
514 #define WM8994_WRITE_SEQUENCER_125              0x307D
515 #define WM8994_WRITE_SEQUENCER_126              0x307E
516 #define WM8994_WRITE_SEQUENCER_127              0x307F
517 #define WM8994_WRITE_SEQUENCER_128              0x3080
518 #define WM8994_WRITE_SEQUENCER_129              0x3081
519 #define WM8994_WRITE_SEQUENCER_130              0x3082
520 #define WM8994_WRITE_SEQUENCER_131              0x3083
521 #define WM8994_WRITE_SEQUENCER_132              0x3084
522 #define WM8994_WRITE_SEQUENCER_133              0x3085
523 #define WM8994_WRITE_SEQUENCER_134              0x3086
524 #define WM8994_WRITE_SEQUENCER_135              0x3087
525 #define WM8994_WRITE_SEQUENCER_136              0x3088
526 #define WM8994_WRITE_SEQUENCER_137              0x3089
527 #define WM8994_WRITE_SEQUENCER_138              0x308A
528 #define WM8994_WRITE_SEQUENCER_139              0x308B
529 #define WM8994_WRITE_SEQUENCER_140              0x308C
530 #define WM8994_WRITE_SEQUENCER_141              0x308D
531 #define WM8994_WRITE_SEQUENCER_142              0x308E
532 #define WM8994_WRITE_SEQUENCER_143              0x308F
533 #define WM8994_WRITE_SEQUENCER_144              0x3090
534 #define WM8994_WRITE_SEQUENCER_145              0x3091
535 #define WM8994_WRITE_SEQUENCER_146              0x3092
536 #define WM8994_WRITE_SEQUENCER_147              0x3093
537 #define WM8994_WRITE_SEQUENCER_148              0x3094
538 #define WM8994_WRITE_SEQUENCER_149              0x3095
539 #define WM8994_WRITE_SEQUENCER_150              0x3096
540 #define WM8994_WRITE_SEQUENCER_151              0x3097
541 #define WM8994_WRITE_SEQUENCER_152              0x3098
542 #define WM8994_WRITE_SEQUENCER_153              0x3099
543 #define WM8994_WRITE_SEQUENCER_154              0x309A
544 #define WM8994_WRITE_SEQUENCER_155              0x309B
545 #define WM8994_WRITE_SEQUENCER_156              0x309C
546 #define WM8994_WRITE_SEQUENCER_157              0x309D
547 #define WM8994_WRITE_SEQUENCER_158              0x309E
548 #define WM8994_WRITE_SEQUENCER_159              0x309F
549 #define WM8994_WRITE_SEQUENCER_160              0x30A0
550 #define WM8994_WRITE_SEQUENCER_161              0x30A1
551 #define WM8994_WRITE_SEQUENCER_162              0x30A2
552 #define WM8994_WRITE_SEQUENCER_163              0x30A3
553 #define WM8994_WRITE_SEQUENCER_164              0x30A4
554 #define WM8994_WRITE_SEQUENCER_165              0x30A5
555 #define WM8994_WRITE_SEQUENCER_166              0x30A6
556 #define WM8994_WRITE_SEQUENCER_167              0x30A7
557 #define WM8994_WRITE_SEQUENCER_168              0x30A8
558 #define WM8994_WRITE_SEQUENCER_169              0x30A9
559 #define WM8994_WRITE_SEQUENCER_170              0x30AA
560 #define WM8994_WRITE_SEQUENCER_171              0x30AB
561 #define WM8994_WRITE_SEQUENCER_172              0x30AC
562 #define WM8994_WRITE_SEQUENCER_173              0x30AD
563 #define WM8994_WRITE_SEQUENCER_174              0x30AE
564 #define WM8994_WRITE_SEQUENCER_175              0x30AF
565 #define WM8994_WRITE_SEQUENCER_176              0x30B0
566 #define WM8994_WRITE_SEQUENCER_177              0x30B1
567 #define WM8994_WRITE_SEQUENCER_178              0x30B2
568 #define WM8994_WRITE_SEQUENCER_179              0x30B3
569 #define WM8994_WRITE_SEQUENCER_180              0x30B4
570 #define WM8994_WRITE_SEQUENCER_181              0x30B5
571 #define WM8994_WRITE_SEQUENCER_182              0x30B6
572 #define WM8994_WRITE_SEQUENCER_183              0x30B7
573 #define WM8994_WRITE_SEQUENCER_184              0x30B8
574 #define WM8994_WRITE_SEQUENCER_185              0x30B9
575 #define WM8994_WRITE_SEQUENCER_186              0x30BA
576 #define WM8994_WRITE_SEQUENCER_187              0x30BB
577 #define WM8994_WRITE_SEQUENCER_188              0x30BC
578 #define WM8994_WRITE_SEQUENCER_189              0x30BD
579 #define WM8994_WRITE_SEQUENCER_190              0x30BE
580 #define WM8994_WRITE_SEQUENCER_191              0x30BF
581 #define WM8994_WRITE_SEQUENCER_192              0x30C0
582 #define WM8994_WRITE_SEQUENCER_193              0x30C1
583 #define WM8994_WRITE_SEQUENCER_194              0x30C2
584 #define WM8994_WRITE_SEQUENCER_195              0x30C3
585 #define WM8994_WRITE_SEQUENCER_196              0x30C4
586 #define WM8994_WRITE_SEQUENCER_197              0x30C5
587 #define WM8994_WRITE_SEQUENCER_198              0x30C6
588 #define WM8994_WRITE_SEQUENCER_199              0x30C7
589 #define WM8994_WRITE_SEQUENCER_200              0x30C8
590 #define WM8994_WRITE_SEQUENCER_201              0x30C9
591 #define WM8994_WRITE_SEQUENCER_202              0x30CA
592 #define WM8994_WRITE_SEQUENCER_203              0x30CB
593 #define WM8994_WRITE_SEQUENCER_204              0x30CC
594 #define WM8994_WRITE_SEQUENCER_205              0x30CD
595 #define WM8994_WRITE_SEQUENCER_206              0x30CE
596 #define WM8994_WRITE_SEQUENCER_207              0x30CF
597 #define WM8994_WRITE_SEQUENCER_208              0x30D0
598 #define WM8994_WRITE_SEQUENCER_209              0x30D1
599 #define WM8994_WRITE_SEQUENCER_210              0x30D2
600 #define WM8994_WRITE_SEQUENCER_211              0x30D3
601 #define WM8994_WRITE_SEQUENCER_212              0x30D4
602 #define WM8994_WRITE_SEQUENCER_213              0x30D5
603 #define WM8994_WRITE_SEQUENCER_214              0x30D6
604 #define WM8994_WRITE_SEQUENCER_215              0x30D7
605 #define WM8994_WRITE_SEQUENCER_216              0x30D8
606 #define WM8994_WRITE_SEQUENCER_217              0x30D9
607 #define WM8994_WRITE_SEQUENCER_218              0x30DA
608 #define WM8994_WRITE_SEQUENCER_219              0x30DB
609 #define WM8994_WRITE_SEQUENCER_220              0x30DC
610 #define WM8994_WRITE_SEQUENCER_221              0x30DD
611 #define WM8994_WRITE_SEQUENCER_222              0x30DE
612 #define WM8994_WRITE_SEQUENCER_223              0x30DF
613 #define WM8994_WRITE_SEQUENCER_224              0x30E0
614 #define WM8994_WRITE_SEQUENCER_225              0x30E1
615 #define WM8994_WRITE_SEQUENCER_226              0x30E2
616 #define WM8994_WRITE_SEQUENCER_227              0x30E3
617 #define WM8994_WRITE_SEQUENCER_228              0x30E4
618 #define WM8994_WRITE_SEQUENCER_229              0x30E5
619 #define WM8994_WRITE_SEQUENCER_230              0x30E6
620 #define WM8994_WRITE_SEQUENCER_231              0x30E7
621 #define WM8994_WRITE_SEQUENCER_232              0x30E8
622 #define WM8994_WRITE_SEQUENCER_233              0x30E9
623 #define WM8994_WRITE_SEQUENCER_234              0x30EA
624 #define WM8994_WRITE_SEQUENCER_235              0x30EB
625 #define WM8994_WRITE_SEQUENCER_236              0x30EC
626 #define WM8994_WRITE_SEQUENCER_237              0x30ED
627 #define WM8994_WRITE_SEQUENCER_238              0x30EE
628 #define WM8994_WRITE_SEQUENCER_239              0x30EF
629 #define WM8994_WRITE_SEQUENCER_240              0x30F0
630 #define WM8994_WRITE_SEQUENCER_241              0x30F1
631 #define WM8994_WRITE_SEQUENCER_242              0x30F2
632 #define WM8994_WRITE_SEQUENCER_243              0x30F3
633 #define WM8994_WRITE_SEQUENCER_244              0x30F4
634 #define WM8994_WRITE_SEQUENCER_245              0x30F5
635 #define WM8994_WRITE_SEQUENCER_246              0x30F6
636 #define WM8994_WRITE_SEQUENCER_247              0x30F7
637 #define WM8994_WRITE_SEQUENCER_248              0x30F8
638 #define WM8994_WRITE_SEQUENCER_249              0x30F9
639 #define WM8994_WRITE_SEQUENCER_250              0x30FA
640 #define WM8994_WRITE_SEQUENCER_251              0x30FB
641 #define WM8994_WRITE_SEQUENCER_252              0x30FC
642 #define WM8994_WRITE_SEQUENCER_253              0x30FD
643 #define WM8994_WRITE_SEQUENCER_254              0x30FE
644 #define WM8994_WRITE_SEQUENCER_255              0x30FF
645 #define WM8994_WRITE_SEQUENCER_256              0x3100
646 #define WM8994_WRITE_SEQUENCER_257              0x3101
647 #define WM8994_WRITE_SEQUENCER_258              0x3102
648 #define WM8994_WRITE_SEQUENCER_259              0x3103
649 #define WM8994_WRITE_SEQUENCER_260              0x3104
650 #define WM8994_WRITE_SEQUENCER_261              0x3105
651 #define WM8994_WRITE_SEQUENCER_262              0x3106
652 #define WM8994_WRITE_SEQUENCER_263              0x3107
653 #define WM8994_WRITE_SEQUENCER_264              0x3108
654 #define WM8994_WRITE_SEQUENCER_265              0x3109
655 #define WM8994_WRITE_SEQUENCER_266              0x310A
656 #define WM8994_WRITE_SEQUENCER_267              0x310B
657 #define WM8994_WRITE_SEQUENCER_268              0x310C
658 #define WM8994_WRITE_SEQUENCER_269              0x310D
659 #define WM8994_WRITE_SEQUENCER_270              0x310E
660 #define WM8994_WRITE_SEQUENCER_271              0x310F
661 #define WM8994_WRITE_SEQUENCER_272              0x3110
662 #define WM8994_WRITE_SEQUENCER_273              0x3111
663 #define WM8994_WRITE_SEQUENCER_274              0x3112
664 #define WM8994_WRITE_SEQUENCER_275              0x3113
665 #define WM8994_WRITE_SEQUENCER_276              0x3114
666 #define WM8994_WRITE_SEQUENCER_277              0x3115
667 #define WM8994_WRITE_SEQUENCER_278              0x3116
668 #define WM8994_WRITE_SEQUENCER_279              0x3117
669 #define WM8994_WRITE_SEQUENCER_280              0x3118
670 #define WM8994_WRITE_SEQUENCER_281              0x3119
671 #define WM8994_WRITE_SEQUENCER_282              0x311A
672 #define WM8994_WRITE_SEQUENCER_283              0x311B
673 #define WM8994_WRITE_SEQUENCER_284              0x311C
674 #define WM8994_WRITE_SEQUENCER_285              0x311D
675 #define WM8994_WRITE_SEQUENCER_286              0x311E
676 #define WM8994_WRITE_SEQUENCER_287              0x311F
677 #define WM8994_WRITE_SEQUENCER_288              0x3120
678 #define WM8994_WRITE_SEQUENCER_289              0x3121
679 #define WM8994_WRITE_SEQUENCER_290              0x3122
680 #define WM8994_WRITE_SEQUENCER_291              0x3123
681 #define WM8994_WRITE_SEQUENCER_292              0x3124
682 #define WM8994_WRITE_SEQUENCER_293              0x3125
683 #define WM8994_WRITE_SEQUENCER_294              0x3126
684 #define WM8994_WRITE_SEQUENCER_295              0x3127
685 #define WM8994_WRITE_SEQUENCER_296              0x3128
686 #define WM8994_WRITE_SEQUENCER_297              0x3129
687 #define WM8994_WRITE_SEQUENCER_298              0x312A
688 #define WM8994_WRITE_SEQUENCER_299              0x312B
689 #define WM8994_WRITE_SEQUENCER_300              0x312C
690 #define WM8994_WRITE_SEQUENCER_301              0x312D
691 #define WM8994_WRITE_SEQUENCER_302              0x312E
692 #define WM8994_WRITE_SEQUENCER_303              0x312F
693 #define WM8994_WRITE_SEQUENCER_304              0x3130
694 #define WM8994_WRITE_SEQUENCER_305              0x3131
695 #define WM8994_WRITE_SEQUENCER_306              0x3132
696 #define WM8994_WRITE_SEQUENCER_307              0x3133
697 #define WM8994_WRITE_SEQUENCER_308              0x3134
698 #define WM8994_WRITE_SEQUENCER_309              0x3135
699 #define WM8994_WRITE_SEQUENCER_310              0x3136
700 #define WM8994_WRITE_SEQUENCER_311              0x3137
701 #define WM8994_WRITE_SEQUENCER_312              0x3138
702 #define WM8994_WRITE_SEQUENCER_313              0x3139
703 #define WM8994_WRITE_SEQUENCER_314              0x313A
704 #define WM8994_WRITE_SEQUENCER_315              0x313B
705 #define WM8994_WRITE_SEQUENCER_316              0x313C
706 #define WM8994_WRITE_SEQUENCER_317              0x313D
707 #define WM8994_WRITE_SEQUENCER_318              0x313E
708 #define WM8994_WRITE_SEQUENCER_319              0x313F
709 #define WM8994_WRITE_SEQUENCER_320              0x3140
710 #define WM8994_WRITE_SEQUENCER_321              0x3141
711 #define WM8994_WRITE_SEQUENCER_322              0x3142
712 #define WM8994_WRITE_SEQUENCER_323              0x3143
713 #define WM8994_WRITE_SEQUENCER_324              0x3144
714 #define WM8994_WRITE_SEQUENCER_325              0x3145
715 #define WM8994_WRITE_SEQUENCER_326              0x3146
716 #define WM8994_WRITE_SEQUENCER_327              0x3147
717 #define WM8994_WRITE_SEQUENCER_328              0x3148
718 #define WM8994_WRITE_SEQUENCER_329              0x3149
719 #define WM8994_WRITE_SEQUENCER_330              0x314A
720 #define WM8994_WRITE_SEQUENCER_331              0x314B
721 #define WM8994_WRITE_SEQUENCER_332              0x314C
722 #define WM8994_WRITE_SEQUENCER_333              0x314D
723 #define WM8994_WRITE_SEQUENCER_334              0x314E
724 #define WM8994_WRITE_SEQUENCER_335              0x314F
725 #define WM8994_WRITE_SEQUENCER_336              0x3150
726 #define WM8994_WRITE_SEQUENCER_337              0x3151
727 #define WM8994_WRITE_SEQUENCER_338              0x3152
728 #define WM8994_WRITE_SEQUENCER_339              0x3153
729 #define WM8994_WRITE_SEQUENCER_340              0x3154
730 #define WM8994_WRITE_SEQUENCER_341              0x3155
731 #define WM8994_WRITE_SEQUENCER_342              0x3156
732 #define WM8994_WRITE_SEQUENCER_343              0x3157
733 #define WM8994_WRITE_SEQUENCER_344              0x3158
734 #define WM8994_WRITE_SEQUENCER_345              0x3159
735 #define WM8994_WRITE_SEQUENCER_346              0x315A
736 #define WM8994_WRITE_SEQUENCER_347              0x315B
737 #define WM8994_WRITE_SEQUENCER_348              0x315C
738 #define WM8994_WRITE_SEQUENCER_349              0x315D
739 #define WM8994_WRITE_SEQUENCER_350              0x315E
740 #define WM8994_WRITE_SEQUENCER_351              0x315F
741 #define WM8994_WRITE_SEQUENCER_352              0x3160
742 #define WM8994_WRITE_SEQUENCER_353              0x3161
743 #define WM8994_WRITE_SEQUENCER_354              0x3162
744 #define WM8994_WRITE_SEQUENCER_355              0x3163
745 #define WM8994_WRITE_SEQUENCER_356              0x3164
746 #define WM8994_WRITE_SEQUENCER_357              0x3165
747 #define WM8994_WRITE_SEQUENCER_358              0x3166
748 #define WM8994_WRITE_SEQUENCER_359              0x3167
749 #define WM8994_WRITE_SEQUENCER_360              0x3168
750 #define WM8994_WRITE_SEQUENCER_361              0x3169
751 #define WM8994_WRITE_SEQUENCER_362              0x316A
752 #define WM8994_WRITE_SEQUENCER_363              0x316B
753 #define WM8994_WRITE_SEQUENCER_364              0x316C
754 #define WM8994_WRITE_SEQUENCER_365              0x316D
755 #define WM8994_WRITE_SEQUENCER_366              0x316E
756 #define WM8994_WRITE_SEQUENCER_367              0x316F
757 #define WM8994_WRITE_SEQUENCER_368              0x3170
758 #define WM8994_WRITE_SEQUENCER_369              0x3171
759 #define WM8994_WRITE_SEQUENCER_370              0x3172
760 #define WM8994_WRITE_SEQUENCER_371              0x3173
761 #define WM8994_WRITE_SEQUENCER_372              0x3174
762 #define WM8994_WRITE_SEQUENCER_373              0x3175
763 #define WM8994_WRITE_SEQUENCER_374              0x3176
764 #define WM8994_WRITE_SEQUENCER_375              0x3177
765 #define WM8994_WRITE_SEQUENCER_376              0x3178
766 #define WM8994_WRITE_SEQUENCER_377              0x3179
767 #define WM8994_WRITE_SEQUENCER_378              0x317A
768 #define WM8994_WRITE_SEQUENCER_379              0x317B
769 #define WM8994_WRITE_SEQUENCER_380              0x317C
770 #define WM8994_WRITE_SEQUENCER_381              0x317D
771 #define WM8994_WRITE_SEQUENCER_382              0x317E
772 #define WM8994_WRITE_SEQUENCER_383              0x317F
773 #define WM8994_WRITE_SEQUENCER_384              0x3180
774 #define WM8994_WRITE_SEQUENCER_385              0x3181
775 #define WM8994_WRITE_SEQUENCER_386              0x3182
776 #define WM8994_WRITE_SEQUENCER_387              0x3183
777 #define WM8994_WRITE_SEQUENCER_388              0x3184
778 #define WM8994_WRITE_SEQUENCER_389              0x3185
779 #define WM8994_WRITE_SEQUENCER_390              0x3186
780 #define WM8994_WRITE_SEQUENCER_391              0x3187
781 #define WM8994_WRITE_SEQUENCER_392              0x3188
782 #define WM8994_WRITE_SEQUENCER_393              0x3189
783 #define WM8994_WRITE_SEQUENCER_394              0x318A
784 #define WM8994_WRITE_SEQUENCER_395              0x318B
785 #define WM8994_WRITE_SEQUENCER_396              0x318C
786 #define WM8994_WRITE_SEQUENCER_397              0x318D
787 #define WM8994_WRITE_SEQUENCER_398              0x318E
788 #define WM8994_WRITE_SEQUENCER_399              0x318F
789 #define WM8994_WRITE_SEQUENCER_400              0x3190
790 #define WM8994_WRITE_SEQUENCER_401              0x3191
791 #define WM8994_WRITE_SEQUENCER_402              0x3192
792 #define WM8994_WRITE_SEQUENCER_403              0x3193
793 #define WM8994_WRITE_SEQUENCER_404              0x3194
794 #define WM8994_WRITE_SEQUENCER_405              0x3195
795 #define WM8994_WRITE_SEQUENCER_406              0x3196
796 #define WM8994_WRITE_SEQUENCER_407              0x3197
797 #define WM8994_WRITE_SEQUENCER_408              0x3198
798 #define WM8994_WRITE_SEQUENCER_409              0x3199
799 #define WM8994_WRITE_SEQUENCER_410              0x319A
800 #define WM8994_WRITE_SEQUENCER_411              0x319B
801 #define WM8994_WRITE_SEQUENCER_412              0x319C
802 #define WM8994_WRITE_SEQUENCER_413              0x319D
803 #define WM8994_WRITE_SEQUENCER_414              0x319E
804 #define WM8994_WRITE_SEQUENCER_415              0x319F
805 #define WM8994_WRITE_SEQUENCER_416              0x31A0
806 #define WM8994_WRITE_SEQUENCER_417              0x31A1
807 #define WM8994_WRITE_SEQUENCER_418              0x31A2
808 #define WM8994_WRITE_SEQUENCER_419              0x31A3
809 #define WM8994_WRITE_SEQUENCER_420              0x31A4
810 #define WM8994_WRITE_SEQUENCER_421              0x31A5
811 #define WM8994_WRITE_SEQUENCER_422              0x31A6
812 #define WM8994_WRITE_SEQUENCER_423              0x31A7
813 #define WM8994_WRITE_SEQUENCER_424              0x31A8
814 #define WM8994_WRITE_SEQUENCER_425              0x31A9
815 #define WM8994_WRITE_SEQUENCER_426              0x31AA
816 #define WM8994_WRITE_SEQUENCER_427              0x31AB
817 #define WM8994_WRITE_SEQUENCER_428              0x31AC
818 #define WM8994_WRITE_SEQUENCER_429              0x31AD
819 #define WM8994_WRITE_SEQUENCER_430              0x31AE
820 #define WM8994_WRITE_SEQUENCER_431              0x31AF
821 #define WM8994_WRITE_SEQUENCER_432              0x31B0
822 #define WM8994_WRITE_SEQUENCER_433              0x31B1
823 #define WM8994_WRITE_SEQUENCER_434              0x31B2
824 #define WM8994_WRITE_SEQUENCER_435              0x31B3
825 #define WM8994_WRITE_SEQUENCER_436              0x31B4
826 #define WM8994_WRITE_SEQUENCER_437              0x31B5
827 #define WM8994_WRITE_SEQUENCER_438              0x31B6
828 #define WM8994_WRITE_SEQUENCER_439              0x31B7
829 #define WM8994_WRITE_SEQUENCER_440              0x31B8
830 #define WM8994_WRITE_SEQUENCER_441              0x31B9
831 #define WM8994_WRITE_SEQUENCER_442              0x31BA
832 #define WM8994_WRITE_SEQUENCER_443              0x31BB
833 #define WM8994_WRITE_SEQUENCER_444              0x31BC
834 #define WM8994_WRITE_SEQUENCER_445              0x31BD
835 #define WM8994_WRITE_SEQUENCER_446              0x31BE
836 #define WM8994_WRITE_SEQUENCER_447              0x31BF
837 #define WM8994_WRITE_SEQUENCER_448              0x31C0
838 #define WM8994_WRITE_SEQUENCER_449              0x31C1
839 #define WM8994_WRITE_SEQUENCER_450              0x31C2
840 #define WM8994_WRITE_SEQUENCER_451              0x31C3
841 #define WM8994_WRITE_SEQUENCER_452              0x31C4
842 #define WM8994_WRITE_SEQUENCER_453              0x31C5
843 #define WM8994_WRITE_SEQUENCER_454              0x31C6
844 #define WM8994_WRITE_SEQUENCER_455              0x31C7
845 #define WM8994_WRITE_SEQUENCER_456              0x31C8
846 #define WM8994_WRITE_SEQUENCER_457              0x31C9
847 #define WM8994_WRITE_SEQUENCER_458              0x31CA
848 #define WM8994_WRITE_SEQUENCER_459              0x31CB
849 #define WM8994_WRITE_SEQUENCER_460              0x31CC
850 #define WM8994_WRITE_SEQUENCER_461              0x31CD
851 #define WM8994_WRITE_SEQUENCER_462              0x31CE
852 #define WM8994_WRITE_SEQUENCER_463              0x31CF
853 #define WM8994_WRITE_SEQUENCER_464              0x31D0
854 #define WM8994_WRITE_SEQUENCER_465              0x31D1
855 #define WM8994_WRITE_SEQUENCER_466              0x31D2
856 #define WM8994_WRITE_SEQUENCER_467              0x31D3
857 #define WM8994_WRITE_SEQUENCER_468              0x31D4
858 #define WM8994_WRITE_SEQUENCER_469              0x31D5
859 #define WM8994_WRITE_SEQUENCER_470              0x31D6
860 #define WM8994_WRITE_SEQUENCER_471              0x31D7
861 #define WM8994_WRITE_SEQUENCER_472              0x31D8
862 #define WM8994_WRITE_SEQUENCER_473              0x31D9
863 #define WM8994_WRITE_SEQUENCER_474              0x31DA
864 #define WM8994_WRITE_SEQUENCER_475              0x31DB
865 #define WM8994_WRITE_SEQUENCER_476              0x31DC
866 #define WM8994_WRITE_SEQUENCER_477              0x31DD
867 #define WM8994_WRITE_SEQUENCER_478              0x31DE
868 #define WM8994_WRITE_SEQUENCER_479              0x31DF
869 #define WM8994_WRITE_SEQUENCER_480              0x31E0
870 #define WM8994_WRITE_SEQUENCER_481              0x31E1
871 #define WM8994_WRITE_SEQUENCER_482              0x31E2
872 #define WM8994_WRITE_SEQUENCER_483              0x31E3
873 #define WM8994_WRITE_SEQUENCER_484              0x31E4
874 #define WM8994_WRITE_SEQUENCER_485              0x31E5
875 #define WM8994_WRITE_SEQUENCER_486              0x31E6
876 #define WM8994_WRITE_SEQUENCER_487              0x31E7
877 #define WM8994_WRITE_SEQUENCER_488              0x31E8
878 #define WM8994_WRITE_SEQUENCER_489              0x31E9
879 #define WM8994_WRITE_SEQUENCER_490              0x31EA
880 #define WM8994_WRITE_SEQUENCER_491              0x31EB
881 #define WM8994_WRITE_SEQUENCER_492              0x31EC
882 #define WM8994_WRITE_SEQUENCER_493              0x31ED
883 #define WM8994_WRITE_SEQUENCER_494              0x31EE
884 #define WM8994_WRITE_SEQUENCER_495              0x31EF
885 #define WM8994_WRITE_SEQUENCER_496              0x31F0
886 #define WM8994_WRITE_SEQUENCER_497              0x31F1
887 #define WM8994_WRITE_SEQUENCER_498              0x31F2
888 #define WM8994_WRITE_SEQUENCER_499              0x31F3
889 #define WM8994_WRITE_SEQUENCER_500              0x31F4
890 #define WM8994_WRITE_SEQUENCER_501              0x31F5
891 #define WM8994_WRITE_SEQUENCER_502              0x31F6
892 #define WM8994_WRITE_SEQUENCER_503              0x31F7
893 #define WM8994_WRITE_SEQUENCER_504              0x31F8
894 #define WM8994_WRITE_SEQUENCER_505              0x31F9
895 #define WM8994_WRITE_SEQUENCER_506              0x31FA
896 #define WM8994_WRITE_SEQUENCER_507              0x31FB
897 #define WM8994_WRITE_SEQUENCER_508              0x31FC
898 #define WM8994_WRITE_SEQUENCER_509              0x31FD
899 #define WM8994_WRITE_SEQUENCER_510              0x31FE
900 #define WM8994_WRITE_SEQUENCER_511              0x31FF
901 
902 #define WM8994_REGISTER_COUNT                   736
903 #define WM8994_MAX_REGISTER                     0x31FF
904 #define WM8994_MAX_CACHED_REGISTER              0x749
905 
906 /*
907  * Field Definitions.
908  */
909 
910 /*
911  * R0 (0x00) - Software Reset
912  */
913 #define WM8994_SW_RESET_MASK                    0xFFFF  /* SW_RESET - [15:0] */
914 #define WM8994_SW_RESET_SHIFT                        0  /* SW_RESET - [15:0] */
915 #define WM8994_SW_RESET_WIDTH                       16  /* SW_RESET - [15:0] */
916 
917 /*
918  * R1 (0x01) - Power Management (1)
919  */
920 #define WM8994_SPKOUTR_ENA                      0x2000  /* SPKOUTR_ENA */
921 #define WM8994_SPKOUTR_ENA_MASK                 0x2000  /* SPKOUTR_ENA */
922 #define WM8994_SPKOUTR_ENA_SHIFT                    13  /* SPKOUTR_ENA */
923 #define WM8994_SPKOUTR_ENA_WIDTH                     1  /* SPKOUTR_ENA */
924 #define WM8994_SPKOUTL_ENA                      0x1000  /* SPKOUTL_ENA */
925 #define WM8994_SPKOUTL_ENA_MASK                 0x1000  /* SPKOUTL_ENA */
926 #define WM8994_SPKOUTL_ENA_SHIFT                    12  /* SPKOUTL_ENA */
927 #define WM8994_SPKOUTL_ENA_WIDTH                     1  /* SPKOUTL_ENA */
928 #define WM8994_HPOUT2_ENA                       0x0800  /* HPOUT2_ENA */
929 #define WM8994_HPOUT2_ENA_MASK                  0x0800  /* HPOUT2_ENA */
930 #define WM8994_HPOUT2_ENA_SHIFT                     11  /* HPOUT2_ENA */
931 #define WM8994_HPOUT2_ENA_WIDTH                      1  /* HPOUT2_ENA */
932 #define WM8994_HPOUT1L_ENA                      0x0200  /* HPOUT1L_ENA */
933 #define WM8994_HPOUT1L_ENA_MASK                 0x0200  /* HPOUT1L_ENA */
934 #define WM8994_HPOUT1L_ENA_SHIFT                     9  /* HPOUT1L_ENA */
935 #define WM8994_HPOUT1L_ENA_WIDTH                     1  /* HPOUT1L_ENA */
936 #define WM8994_HPOUT1R_ENA                      0x0100  /* HPOUT1R_ENA */
937 #define WM8994_HPOUT1R_ENA_MASK                 0x0100  /* HPOUT1R_ENA */
938 #define WM8994_HPOUT1R_ENA_SHIFT                     8  /* HPOUT1R_ENA */
939 #define WM8994_HPOUT1R_ENA_WIDTH                     1  /* HPOUT1R_ENA */
940 #define WM8994_MICB2_ENA                        0x0020  /* MICB2_ENA */
941 #define WM8994_MICB2_ENA_MASK                   0x0020  /* MICB2_ENA */
942 #define WM8994_MICB2_ENA_SHIFT                       5  /* MICB2_ENA */
943 #define WM8994_MICB2_ENA_WIDTH                       1  /* MICB2_ENA */
944 #define WM8994_MICB1_ENA                        0x0010  /* MICB1_ENA */
945 #define WM8994_MICB1_ENA_MASK                   0x0010  /* MICB1_ENA */
946 #define WM8994_MICB1_ENA_SHIFT                       4  /* MICB1_ENA */
947 #define WM8994_MICB1_ENA_WIDTH                       1  /* MICB1_ENA */
948 #define WM8994_VMID_SEL_MASK                    0x0006  /* VMID_SEL - [2:1] */
949 #define WM8994_VMID_SEL_SHIFT                        1  /* VMID_SEL - [2:1] */
950 #define WM8994_VMID_SEL_WIDTH                        2  /* VMID_SEL - [2:1] */
951 #define WM8994_BIAS_ENA                         0x0001  /* BIAS_ENA */
952 #define WM8994_BIAS_ENA_MASK                    0x0001  /* BIAS_ENA */
953 #define WM8994_BIAS_ENA_SHIFT                        0  /* BIAS_ENA */
954 #define WM8994_BIAS_ENA_WIDTH                        1  /* BIAS_ENA */
955 
956 /*
957  * R2 (0x02) - Power Management (2)
958  */
959 #define WM8994_TSHUT_ENA                        0x4000  /* TSHUT_ENA */
960 #define WM8994_TSHUT_ENA_MASK                   0x4000  /* TSHUT_ENA */
961 #define WM8994_TSHUT_ENA_SHIFT                      14  /* TSHUT_ENA */
962 #define WM8994_TSHUT_ENA_WIDTH                       1  /* TSHUT_ENA */
963 #define WM8994_TSHUT_OPDIS                      0x2000  /* TSHUT_OPDIS */
964 #define WM8994_TSHUT_OPDIS_MASK                 0x2000  /* TSHUT_OPDIS */
965 #define WM8994_TSHUT_OPDIS_SHIFT                    13  /* TSHUT_OPDIS */
966 #define WM8994_TSHUT_OPDIS_WIDTH                     1  /* TSHUT_OPDIS */
967 #define WM8994_OPCLK_ENA                        0x0800  /* OPCLK_ENA */
968 #define WM8994_OPCLK_ENA_MASK                   0x0800  /* OPCLK_ENA */
969 #define WM8994_OPCLK_ENA_SHIFT                      11  /* OPCLK_ENA */
970 #define WM8994_OPCLK_ENA_WIDTH                       1  /* OPCLK_ENA */
971 #define WM8994_MIXINL_ENA                       0x0200  /* MIXINL_ENA */
972 #define WM8994_MIXINL_ENA_MASK                  0x0200  /* MIXINL_ENA */
973 #define WM8994_MIXINL_ENA_SHIFT                      9  /* MIXINL_ENA */
974 #define WM8994_MIXINL_ENA_WIDTH                      1  /* MIXINL_ENA */
975 #define WM8994_MIXINR_ENA                       0x0100  /* MIXINR_ENA */
976 #define WM8994_MIXINR_ENA_MASK                  0x0100  /* MIXINR_ENA */
977 #define WM8994_MIXINR_ENA_SHIFT                      8  /* MIXINR_ENA */
978 #define WM8994_MIXINR_ENA_WIDTH                      1  /* MIXINR_ENA */
979 #define WM8994_IN2L_ENA                         0x0080  /* IN2L_ENA */
980 #define WM8994_IN2L_ENA_MASK                    0x0080  /* IN2L_ENA */
981 #define WM8994_IN2L_ENA_SHIFT                        7  /* IN2L_ENA */
982 #define WM8994_IN2L_ENA_WIDTH                        1  /* IN2L_ENA */
983 #define WM8994_IN1L_ENA                         0x0040  /* IN1L_ENA */
984 #define WM8994_IN1L_ENA_MASK                    0x0040  /* IN1L_ENA */
985 #define WM8994_IN1L_ENA_SHIFT                        6  /* IN1L_ENA */
986 #define WM8994_IN1L_ENA_WIDTH                        1  /* IN1L_ENA */
987 #define WM8994_IN2R_ENA                         0x0020  /* IN2R_ENA */
988 #define WM8994_IN2R_ENA_MASK                    0x0020  /* IN2R_ENA */
989 #define WM8994_IN2R_ENA_SHIFT                        5  /* IN2R_ENA */
990 #define WM8994_IN2R_ENA_WIDTH                        1  /* IN2R_ENA */
991 #define WM8994_IN1R_ENA                         0x0010  /* IN1R_ENA */
992 #define WM8994_IN1R_ENA_MASK                    0x0010  /* IN1R_ENA */
993 #define WM8994_IN1R_ENA_SHIFT                        4  /* IN1R_ENA */
994 #define WM8994_IN1R_ENA_WIDTH                        1  /* IN1R_ENA */
995 
996 /*
997  * R3 (0x03) - Power Management (3)
998  */
999 #define WM8994_LINEOUT1N_ENA                    0x2000  /* LINEOUT1N_ENA */
1000 #define WM8994_LINEOUT1N_ENA_MASK               0x2000  /* LINEOUT1N_ENA */
1001 #define WM8994_LINEOUT1N_ENA_SHIFT                  13  /* LINEOUT1N_ENA */
1002 #define WM8994_LINEOUT1N_ENA_WIDTH                   1  /* LINEOUT1N_ENA */
1003 #define WM8994_LINEOUT1P_ENA                    0x1000  /* LINEOUT1P_ENA */
1004 #define WM8994_LINEOUT1P_ENA_MASK               0x1000  /* LINEOUT1P_ENA */
1005 #define WM8994_LINEOUT1P_ENA_SHIFT                  12  /* LINEOUT1P_ENA */
1006 #define WM8994_LINEOUT1P_ENA_WIDTH                   1  /* LINEOUT1P_ENA */
1007 #define WM8994_LINEOUT2N_ENA                    0x0800  /* LINEOUT2N_ENA */
1008 #define WM8994_LINEOUT2N_ENA_MASK               0x0800  /* LINEOUT2N_ENA */
1009 #define WM8994_LINEOUT2N_ENA_SHIFT                  11  /* LINEOUT2N_ENA */
1010 #define WM8994_LINEOUT2N_ENA_WIDTH                   1  /* LINEOUT2N_ENA */
1011 #define WM8994_LINEOUT2P_ENA                    0x0400  /* LINEOUT2P_ENA */
1012 #define WM8994_LINEOUT2P_ENA_MASK               0x0400  /* LINEOUT2P_ENA */
1013 #define WM8994_LINEOUT2P_ENA_SHIFT                  10  /* LINEOUT2P_ENA */
1014 #define WM8994_LINEOUT2P_ENA_WIDTH                   1  /* LINEOUT2P_ENA */
1015 #define WM8994_SPKRVOL_ENA                      0x0200  /* SPKRVOL_ENA */
1016 #define WM8994_SPKRVOL_ENA_MASK                 0x0200  /* SPKRVOL_ENA */
1017 #define WM8994_SPKRVOL_ENA_SHIFT                     9  /* SPKRVOL_ENA */
1018 #define WM8994_SPKRVOL_ENA_WIDTH                     1  /* SPKRVOL_ENA */
1019 #define WM8994_SPKLVOL_ENA                      0x0100  /* SPKLVOL_ENA */
1020 #define WM8994_SPKLVOL_ENA_MASK                 0x0100  /* SPKLVOL_ENA */
1021 #define WM8994_SPKLVOL_ENA_SHIFT                     8  /* SPKLVOL_ENA */
1022 #define WM8994_SPKLVOL_ENA_WIDTH                     1  /* SPKLVOL_ENA */
1023 #define WM8994_MIXOUTLVOL_ENA                   0x0080  /* MIXOUTLVOL_ENA */
1024 #define WM8994_MIXOUTLVOL_ENA_MASK              0x0080  /* MIXOUTLVOL_ENA */
1025 #define WM8994_MIXOUTLVOL_ENA_SHIFT                  7  /* MIXOUTLVOL_ENA */
1026 #define WM8994_MIXOUTLVOL_ENA_WIDTH                  1  /* MIXOUTLVOL_ENA */
1027 #define WM8994_MIXOUTRVOL_ENA                   0x0040  /* MIXOUTRVOL_ENA */
1028 #define WM8994_MIXOUTRVOL_ENA_MASK              0x0040  /* MIXOUTRVOL_ENA */
1029 #define WM8994_MIXOUTRVOL_ENA_SHIFT                  6  /* MIXOUTRVOL_ENA */
1030 #define WM8994_MIXOUTRVOL_ENA_WIDTH                  1  /* MIXOUTRVOL_ENA */
1031 #define WM8994_MIXOUTL_ENA                      0x0020  /* MIXOUTL_ENA */
1032 #define WM8994_MIXOUTL_ENA_MASK                 0x0020  /* MIXOUTL_ENA */
1033 #define WM8994_MIXOUTL_ENA_SHIFT                     5  /* MIXOUTL_ENA */
1034 #define WM8994_MIXOUTL_ENA_WIDTH                     1  /* MIXOUTL_ENA */
1035 #define WM8994_MIXOUTR_ENA                      0x0010  /* MIXOUTR_ENA */
1036 #define WM8994_MIXOUTR_ENA_MASK                 0x0010  /* MIXOUTR_ENA */
1037 #define WM8994_MIXOUTR_ENA_SHIFT                     4  /* MIXOUTR_ENA */
1038 #define WM8994_MIXOUTR_ENA_WIDTH                     1  /* MIXOUTR_ENA */
1039 
1040 /*
1041  * R4 (0x04) - Power Management (4)
1042  */
1043 #define WM8994_AIF2ADCL_ENA                     0x2000  /* AIF2ADCL_ENA */
1044 #define WM8994_AIF2ADCL_ENA_MASK                0x2000  /* AIF2ADCL_ENA */
1045 #define WM8994_AIF2ADCL_ENA_SHIFT                   13  /* AIF2ADCL_ENA */
1046 #define WM8994_AIF2ADCL_ENA_WIDTH                    1  /* AIF2ADCL_ENA */
1047 #define WM8994_AIF2ADCR_ENA                     0x1000  /* AIF2ADCR_ENA */
1048 #define WM8994_AIF2ADCR_ENA_MASK                0x1000  /* AIF2ADCR_ENA */
1049 #define WM8994_AIF2ADCR_ENA_SHIFT                   12  /* AIF2ADCR_ENA */
1050 #define WM8994_AIF2ADCR_ENA_WIDTH                    1  /* AIF2ADCR_ENA */
1051 #define WM8994_AIF1ADC2L_ENA                    0x0800  /* AIF1ADC2L_ENA */
1052 #define WM8994_AIF1ADC2L_ENA_MASK               0x0800  /* AIF1ADC2L_ENA */
1053 #define WM8994_AIF1ADC2L_ENA_SHIFT                  11  /* AIF1ADC2L_ENA */
1054 #define WM8994_AIF1ADC2L_ENA_WIDTH                   1  /* AIF1ADC2L_ENA */
1055 #define WM8994_AIF1ADC2R_ENA                    0x0400  /* AIF1ADC2R_ENA */
1056 #define WM8994_AIF1ADC2R_ENA_MASK               0x0400  /* AIF1ADC2R_ENA */
1057 #define WM8994_AIF1ADC2R_ENA_SHIFT                  10  /* AIF1ADC2R_ENA */
1058 #define WM8994_AIF1ADC2R_ENA_WIDTH                   1  /* AIF1ADC2R_ENA */
1059 #define WM8994_AIF1ADC1L_ENA                    0x0200  /* AIF1ADC1L_ENA */
1060 #define WM8994_AIF1ADC1L_ENA_MASK               0x0200  /* AIF1ADC1L_ENA */
1061 #define WM8994_AIF1ADC1L_ENA_SHIFT                   9  /* AIF1ADC1L_ENA */
1062 #define WM8994_AIF1ADC1L_ENA_WIDTH                   1  /* AIF1ADC1L_ENA */
1063 #define WM8994_AIF1ADC1R_ENA                    0x0100  /* AIF1ADC1R_ENA */
1064 #define WM8994_AIF1ADC1R_ENA_MASK               0x0100  /* AIF1ADC1R_ENA */
1065 #define WM8994_AIF1ADC1R_ENA_SHIFT                   8  /* AIF1ADC1R_ENA */
1066 #define WM8994_AIF1ADC1R_ENA_WIDTH                   1  /* AIF1ADC1R_ENA */
1067 #define WM8994_DMIC2L_ENA                       0x0020  /* DMIC2L_ENA */
1068 #define WM8994_DMIC2L_ENA_MASK                  0x0020  /* DMIC2L_ENA */
1069 #define WM8994_DMIC2L_ENA_SHIFT                      5  /* DMIC2L_ENA */
1070 #define WM8994_DMIC2L_ENA_WIDTH                      1  /* DMIC2L_ENA */
1071 #define WM8994_DMIC2R_ENA                       0x0010  /* DMIC2R_ENA */
1072 #define WM8994_DMIC2R_ENA_MASK                  0x0010  /* DMIC2R_ENA */
1073 #define WM8994_DMIC2R_ENA_SHIFT                      4  /* DMIC2R_ENA */
1074 #define WM8994_DMIC2R_ENA_WIDTH                      1  /* DMIC2R_ENA */
1075 #define WM8994_DMIC1L_ENA                       0x0008  /* DMIC1L_ENA */
1076 #define WM8994_DMIC1L_ENA_MASK                  0x0008  /* DMIC1L_ENA */
1077 #define WM8994_DMIC1L_ENA_SHIFT                      3  /* DMIC1L_ENA */
1078 #define WM8994_DMIC1L_ENA_WIDTH                      1  /* DMIC1L_ENA */
1079 #define WM8994_DMIC1R_ENA                       0x0004  /* DMIC1R_ENA */
1080 #define WM8994_DMIC1R_ENA_MASK                  0x0004  /* DMIC1R_ENA */
1081 #define WM8994_DMIC1R_ENA_SHIFT                      2  /* DMIC1R_ENA */
1082 #define WM8994_DMIC1R_ENA_WIDTH                      1  /* DMIC1R_ENA */
1083 #define WM8994_ADCL_ENA                         0x0002  /* ADCL_ENA */
1084 #define WM8994_ADCL_ENA_MASK                    0x0002  /* ADCL_ENA */
1085 #define WM8994_ADCL_ENA_SHIFT                        1  /* ADCL_ENA */
1086 #define WM8994_ADCL_ENA_WIDTH                        1  /* ADCL_ENA */
1087 #define WM8994_ADCR_ENA                         0x0001  /* ADCR_ENA */
1088 #define WM8994_ADCR_ENA_MASK                    0x0001  /* ADCR_ENA */
1089 #define WM8994_ADCR_ENA_SHIFT                        0  /* ADCR_ENA */
1090 #define WM8994_ADCR_ENA_WIDTH                        1  /* ADCR_ENA */
1091 
1092 /*
1093  * R5 (0x05) - Power Management (5)
1094  */
1095 #define WM8994_AIF2DACL_ENA                     0x2000  /* AIF2DACL_ENA */
1096 #define WM8994_AIF2DACL_ENA_MASK                0x2000  /* AIF2DACL_ENA */
1097 #define WM8994_AIF2DACL_ENA_SHIFT                   13  /* AIF2DACL_ENA */
1098 #define WM8994_AIF2DACL_ENA_WIDTH                    1  /* AIF2DACL_ENA */
1099 #define WM8994_AIF2DACR_ENA                     0x1000  /* AIF2DACR_ENA */
1100 #define WM8994_AIF2DACR_ENA_MASK                0x1000  /* AIF2DACR_ENA */
1101 #define WM8994_AIF2DACR_ENA_SHIFT                   12  /* AIF2DACR_ENA */
1102 #define WM8994_AIF2DACR_ENA_WIDTH                    1  /* AIF2DACR_ENA */
1103 #define WM8994_AIF1DAC2L_ENA                    0x0800  /* AIF1DAC2L_ENA */
1104 #define WM8994_AIF1DAC2L_ENA_MASK               0x0800  /* AIF1DAC2L_ENA */
1105 #define WM8994_AIF1DAC2L_ENA_SHIFT                  11  /* AIF1DAC2L_ENA */
1106 #define WM8994_AIF1DAC2L_ENA_WIDTH                   1  /* AIF1DAC2L_ENA */
1107 #define WM8994_AIF1DAC2R_ENA                    0x0400  /* AIF1DAC2R_ENA */
1108 #define WM8994_AIF1DAC2R_ENA_MASK               0x0400  /* AIF1DAC2R_ENA */
1109 #define WM8994_AIF1DAC2R_ENA_SHIFT                  10  /* AIF1DAC2R_ENA */
1110 #define WM8994_AIF1DAC2R_ENA_WIDTH                   1  /* AIF1DAC2R_ENA */
1111 #define WM8994_AIF1DAC1L_ENA                    0x0200  /* AIF1DAC1L_ENA */
1112 #define WM8994_AIF1DAC1L_ENA_MASK               0x0200  /* AIF1DAC1L_ENA */
1113 #define WM8994_AIF1DAC1L_ENA_SHIFT                   9  /* AIF1DAC1L_ENA */
1114 #define WM8994_AIF1DAC1L_ENA_WIDTH                   1  /* AIF1DAC1L_ENA */
1115 #define WM8994_AIF1DAC1R_ENA                    0x0100  /* AIF1DAC1R_ENA */
1116 #define WM8994_AIF1DAC1R_ENA_MASK               0x0100  /* AIF1DAC1R_ENA */
1117 #define WM8994_AIF1DAC1R_ENA_SHIFT                   8  /* AIF1DAC1R_ENA */
1118 #define WM8994_AIF1DAC1R_ENA_WIDTH                   1  /* AIF1DAC1R_ENA */
1119 #define WM8994_DAC2L_ENA                        0x0008  /* DAC2L_ENA */
1120 #define WM8994_DAC2L_ENA_MASK                   0x0008  /* DAC2L_ENA */
1121 #define WM8994_DAC2L_ENA_SHIFT                       3  /* DAC2L_ENA */
1122 #define WM8994_DAC2L_ENA_WIDTH                       1  /* DAC2L_ENA */
1123 #define WM8994_DAC2R_ENA                        0x0004  /* DAC2R_ENA */
1124 #define WM8994_DAC2R_ENA_MASK                   0x0004  /* DAC2R_ENA */
1125 #define WM8994_DAC2R_ENA_SHIFT                       2  /* DAC2R_ENA */
1126 #define WM8994_DAC2R_ENA_WIDTH                       1  /* DAC2R_ENA */
1127 #define WM8994_DAC1L_ENA                        0x0002  /* DAC1L_ENA */
1128 #define WM8994_DAC1L_ENA_MASK                   0x0002  /* DAC1L_ENA */
1129 #define WM8994_DAC1L_ENA_SHIFT                       1  /* DAC1L_ENA */
1130 #define WM8994_DAC1L_ENA_WIDTH                       1  /* DAC1L_ENA */
1131 #define WM8994_DAC1R_ENA                        0x0001  /* DAC1R_ENA */
1132 #define WM8994_DAC1R_ENA_MASK                   0x0001  /* DAC1R_ENA */
1133 #define WM8994_DAC1R_ENA_SHIFT                       0  /* DAC1R_ENA */
1134 #define WM8994_DAC1R_ENA_WIDTH                       1  /* DAC1R_ENA */
1135 
1136 /*
1137  * R6 (0x06) - Power Management (6)
1138  */
1139 #define WM8958_AIF3ADC_SRC_MASK                 0x0600  /* AIF3ADC_SRC - [10:9] */
1140 #define WM8958_AIF3ADC_SRC_SHIFT                     9  /* AIF3ADC_SRC - [10:9] */
1141 #define WM8958_AIF3ADC_SRC_WIDTH                     2  /* AIF3ADC_SRC - [10:9] */
1142 #define WM8958_AIF2DAC_SRC_MASK                 0x0180  /* AIF2DAC_SRC - [8:7] */
1143 #define WM8958_AIF2DAC_SRC_SHIFT                     7  /* AIF2DAC_SRC - [8:7] */
1144 #define WM8958_AIF2DAC_SRC_WIDTH                     2  /* AIF2DAC_SRC - [8:7] */
1145 #define WM8994_AIF3_TRI                         0x0020  /* AIF3_TRI */
1146 #define WM8994_AIF3_TRI_MASK                    0x0020  /* AIF3_TRI */
1147 #define WM8994_AIF3_TRI_SHIFT                        5  /* AIF3_TRI */
1148 #define WM8994_AIF3_TRI_WIDTH                        1  /* AIF3_TRI */
1149 #define WM8994_AIF3_ADCDAT_SRC_MASK             0x0018  /* AIF3_ADCDAT_SRC - [4:3] */
1150 #define WM8994_AIF3_ADCDAT_SRC_SHIFT                 3  /* AIF3_ADCDAT_SRC - [4:3] */
1151 #define WM8994_AIF3_ADCDAT_SRC_WIDTH                 2  /* AIF3_ADCDAT_SRC - [4:3] */
1152 #define WM8994_AIF2_ADCDAT_SRC                  0x0004  /* AIF2_ADCDAT_SRC */
1153 #define WM8994_AIF2_ADCDAT_SRC_MASK             0x0004  /* AIF2_ADCDAT_SRC */
1154 #define WM8994_AIF2_ADCDAT_SRC_SHIFT                 2  /* AIF2_ADCDAT_SRC */
1155 #define WM8994_AIF2_ADCDAT_SRC_WIDTH                 1  /* AIF2_ADCDAT_SRC */
1156 #define WM8994_AIF2_DACDAT_SRC                  0x0002  /* AIF2_DACDAT_SRC */
1157 #define WM8994_AIF2_DACDAT_SRC_MASK             0x0002  /* AIF2_DACDAT_SRC */
1158 #define WM8994_AIF2_DACDAT_SRC_SHIFT                 1  /* AIF2_DACDAT_SRC */
1159 #define WM8994_AIF2_DACDAT_SRC_WIDTH                 1  /* AIF2_DACDAT_SRC */
1160 #define WM8994_AIF1_DACDAT_SRC                  0x0001  /* AIF1_DACDAT_SRC */
1161 #define WM8994_AIF1_DACDAT_SRC_MASK             0x0001  /* AIF1_DACDAT_SRC */
1162 #define WM8994_AIF1_DACDAT_SRC_SHIFT                 0  /* AIF1_DACDAT_SRC */
1163 #define WM8994_AIF1_DACDAT_SRC_WIDTH                 1  /* AIF1_DACDAT_SRC */
1164 
1165 /*
1166  * R21 (0x15) - Input Mixer (1)
1167  */
1168 #define WM8994_IN1RP_MIXINR_BOOST               0x0100  /* IN1RP_MIXINR_BOOST */
1169 #define WM8994_IN1RP_MIXINR_BOOST_MASK          0x0100  /* IN1RP_MIXINR_BOOST */
1170 #define WM8994_IN1RP_MIXINR_BOOST_SHIFT              8  /* IN1RP_MIXINR_BOOST */
1171 #define WM8994_IN1RP_MIXINR_BOOST_WIDTH              1  /* IN1RP_MIXINR_BOOST */
1172 #define WM8994_IN1LP_MIXINL_BOOST               0x0080  /* IN1LP_MIXINL_BOOST */
1173 #define WM8994_IN1LP_MIXINL_BOOST_MASK          0x0080  /* IN1LP_MIXINL_BOOST */
1174 #define WM8994_IN1LP_MIXINL_BOOST_SHIFT              7  /* IN1LP_MIXINL_BOOST */
1175 #define WM8994_IN1LP_MIXINL_BOOST_WIDTH              1  /* IN1LP_MIXINL_BOOST */
1176 #define WM8994_INPUTS_CLAMP                     0x0040  /* INPUTS_CLAMP */
1177 #define WM8994_INPUTS_CLAMP_MASK                0x0040  /* INPUTS_CLAMP */
1178 #define WM8994_INPUTS_CLAMP_SHIFT                    6  /* INPUTS_CLAMP */
1179 #define WM8994_INPUTS_CLAMP_WIDTH                    1  /* INPUTS_CLAMP */
1180 
1181 /*
1182  * R24 (0x18) - Left Line Input 1&2 Volume
1183  */
1184 #define WM8994_IN1_VU                           0x0100  /* IN1_VU */
1185 #define WM8994_IN1_VU_MASK                      0x0100  /* IN1_VU */
1186 #define WM8994_IN1_VU_SHIFT                          8  /* IN1_VU */
1187 #define WM8994_IN1_VU_WIDTH                          1  /* IN1_VU */
1188 #define WM8994_IN1L_MUTE                        0x0080  /* IN1L_MUTE */
1189 #define WM8994_IN1L_MUTE_MASK                   0x0080  /* IN1L_MUTE */
1190 #define WM8994_IN1L_MUTE_SHIFT                       7  /* IN1L_MUTE */
1191 #define WM8994_IN1L_MUTE_WIDTH                       1  /* IN1L_MUTE */
1192 #define WM8994_IN1L_ZC                          0x0040  /* IN1L_ZC */
1193 #define WM8994_IN1L_ZC_MASK                     0x0040  /* IN1L_ZC */
1194 #define WM8994_IN1L_ZC_SHIFT                         6  /* IN1L_ZC */
1195 #define WM8994_IN1L_ZC_WIDTH                         1  /* IN1L_ZC */
1196 #define WM8994_IN1L_VOL_MASK                    0x001F  /* IN1L_VOL - [4:0] */
1197 #define WM8994_IN1L_VOL_SHIFT                        0  /* IN1L_VOL - [4:0] */
1198 #define WM8994_IN1L_VOL_WIDTH                        5  /* IN1L_VOL - [4:0] */
1199 
1200 /*
1201  * R25 (0x19) - Left Line Input 3&4 Volume
1202  */
1203 #define WM8994_IN2_VU                           0x0100  /* IN2_VU */
1204 #define WM8994_IN2_VU_MASK                      0x0100  /* IN2_VU */
1205 #define WM8994_IN2_VU_SHIFT                          8  /* IN2_VU */
1206 #define WM8994_IN2_VU_WIDTH                          1  /* IN2_VU */
1207 #define WM8994_IN2L_MUTE                        0x0080  /* IN2L_MUTE */
1208 #define WM8994_IN2L_MUTE_MASK                   0x0080  /* IN2L_MUTE */
1209 #define WM8994_IN2L_MUTE_SHIFT                       7  /* IN2L_MUTE */
1210 #define WM8994_IN2L_MUTE_WIDTH                       1  /* IN2L_MUTE */
1211 #define WM8994_IN2L_ZC                          0x0040  /* IN2L_ZC */
1212 #define WM8994_IN2L_ZC_MASK                     0x0040  /* IN2L_ZC */
1213 #define WM8994_IN2L_ZC_SHIFT                         6  /* IN2L_ZC */
1214 #define WM8994_IN2L_ZC_WIDTH                         1  /* IN2L_ZC */
1215 #define WM8994_IN2L_VOL_MASK                    0x001F  /* IN2L_VOL - [4:0] */
1216 #define WM8994_IN2L_VOL_SHIFT                        0  /* IN2L_VOL - [4:0] */
1217 #define WM8994_IN2L_VOL_WIDTH                        5  /* IN2L_VOL - [4:0] */
1218 
1219 /*
1220  * R26 (0x1A) - Right Line Input 1&2 Volume
1221  */
1222 #define WM8994_IN1_VU                           0x0100  /* IN1_VU */
1223 #define WM8994_IN1_VU_MASK                      0x0100  /* IN1_VU */
1224 #define WM8994_IN1_VU_SHIFT                          8  /* IN1_VU */
1225 #define WM8994_IN1_VU_WIDTH                          1  /* IN1_VU */
1226 #define WM8994_IN1R_MUTE                        0x0080  /* IN1R_MUTE */
1227 #define WM8994_IN1R_MUTE_MASK                   0x0080  /* IN1R_MUTE */
1228 #define WM8994_IN1R_MUTE_SHIFT                       7  /* IN1R_MUTE */
1229 #define WM8994_IN1R_MUTE_WIDTH                       1  /* IN1R_MUTE */
1230 #define WM8994_IN1R_ZC                          0x0040  /* IN1R_ZC */
1231 #define WM8994_IN1R_ZC_MASK                     0x0040  /* IN1R_ZC */
1232 #define WM8994_IN1R_ZC_SHIFT                         6  /* IN1R_ZC */
1233 #define WM8994_IN1R_ZC_WIDTH                         1  /* IN1R_ZC */
1234 #define WM8994_IN1R_VOL_MASK                    0x001F  /* IN1R_VOL - [4:0] */
1235 #define WM8994_IN1R_VOL_SHIFT                        0  /* IN1R_VOL - [4:0] */
1236 #define WM8994_IN1R_VOL_WIDTH                        5  /* IN1R_VOL - [4:0] */
1237 
1238 /*
1239  * R27 (0x1B) - Right Line Input 3&4 Volume
1240  */
1241 #define WM8994_IN2_VU                           0x0100  /* IN2_VU */
1242 #define WM8994_IN2_VU_MASK                      0x0100  /* IN2_VU */
1243 #define WM8994_IN2_VU_SHIFT                          8  /* IN2_VU */
1244 #define WM8994_IN2_VU_WIDTH                          1  /* IN2_VU */
1245 #define WM8994_IN2R_MUTE                        0x0080  /* IN2R_MUTE */
1246 #define WM8994_IN2R_MUTE_MASK                   0x0080  /* IN2R_MUTE */
1247 #define WM8994_IN2R_MUTE_SHIFT                       7  /* IN2R_MUTE */
1248 #define WM8994_IN2R_MUTE_WIDTH                       1  /* IN2R_MUTE */
1249 #define WM8994_IN2R_ZC                          0x0040  /* IN2R_ZC */
1250 #define WM8994_IN2R_ZC_MASK                     0x0040  /* IN2R_ZC */
1251 #define WM8994_IN2R_ZC_SHIFT                         6  /* IN2R_ZC */
1252 #define WM8994_IN2R_ZC_WIDTH                         1  /* IN2R_ZC */
1253 #define WM8994_IN2R_VOL_MASK                    0x001F  /* IN2R_VOL - [4:0] */
1254 #define WM8994_IN2R_VOL_SHIFT                        0  /* IN2R_VOL - [4:0] */
1255 #define WM8994_IN2R_VOL_WIDTH                        5  /* IN2R_VOL - [4:0] */
1256 
1257 /*
1258  * R28 (0x1C) - Left Output Volume
1259  */
1260 #define WM8994_HPOUT1_VU                        0x0100  /* HPOUT1_VU */
1261 #define WM8994_HPOUT1_VU_MASK                   0x0100  /* HPOUT1_VU */
1262 #define WM8994_HPOUT1_VU_SHIFT                       8  /* HPOUT1_VU */
1263 #define WM8994_HPOUT1_VU_WIDTH                       1  /* HPOUT1_VU */
1264 #define WM8994_HPOUT1L_ZC                       0x0080  /* HPOUT1L_ZC */
1265 #define WM8994_HPOUT1L_ZC_MASK                  0x0080  /* HPOUT1L_ZC */
1266 #define WM8994_HPOUT1L_ZC_SHIFT                      7  /* HPOUT1L_ZC */
1267 #define WM8994_HPOUT1L_ZC_WIDTH                      1  /* HPOUT1L_ZC */
1268 #define WM8994_HPOUT1L_MUTE_N                   0x0040  /* HPOUT1L_MUTE_N */
1269 #define WM8994_HPOUT1L_MUTE_N_MASK              0x0040  /* HPOUT1L_MUTE_N */
1270 #define WM8994_HPOUT1L_MUTE_N_SHIFT                  6  /* HPOUT1L_MUTE_N */
1271 #define WM8994_HPOUT1L_MUTE_N_WIDTH                  1  /* HPOUT1L_MUTE_N */
1272 #define WM8994_HPOUT1L_VOL_MASK                 0x003F  /* HPOUT1L_VOL - [5:0] */
1273 #define WM8994_HPOUT1L_VOL_SHIFT                     0  /* HPOUT1L_VOL - [5:0] */
1274 #define WM8994_HPOUT1L_VOL_WIDTH                     6  /* HPOUT1L_VOL - [5:0] */
1275 
1276 /*
1277  * R29 (0x1D) - Right Output Volume
1278  */
1279 #define WM8994_HPOUT1_VU                        0x0100  /* HPOUT1_VU */
1280 #define WM8994_HPOUT1_VU_MASK                   0x0100  /* HPOUT1_VU */
1281 #define WM8994_HPOUT1_VU_SHIFT                       8  /* HPOUT1_VU */
1282 #define WM8994_HPOUT1_VU_WIDTH                       1  /* HPOUT1_VU */
1283 #define WM8994_HPOUT1R_ZC                       0x0080  /* HPOUT1R_ZC */
1284 #define WM8994_HPOUT1R_ZC_MASK                  0x0080  /* HPOUT1R_ZC */
1285 #define WM8994_HPOUT1R_ZC_SHIFT                      7  /* HPOUT1R_ZC */
1286 #define WM8994_HPOUT1R_ZC_WIDTH                      1  /* HPOUT1R_ZC */
1287 #define WM8994_HPOUT1R_MUTE_N                   0x0040  /* HPOUT1R_MUTE_N */
1288 #define WM8994_HPOUT1R_MUTE_N_MASK              0x0040  /* HPOUT1R_MUTE_N */
1289 #define WM8994_HPOUT1R_MUTE_N_SHIFT                  6  /* HPOUT1R_MUTE_N */
1290 #define WM8994_HPOUT1R_MUTE_N_WIDTH                  1  /* HPOUT1R_MUTE_N */
1291 #define WM8994_HPOUT1R_VOL_MASK                 0x003F  /* HPOUT1R_VOL - [5:0] */
1292 #define WM8994_HPOUT1R_VOL_SHIFT                     0  /* HPOUT1R_VOL - [5:0] */
1293 #define WM8994_HPOUT1R_VOL_WIDTH                     6  /* HPOUT1R_VOL - [5:0] */
1294 
1295 /*
1296  * R30 (0x1E) - Line Outputs Volume
1297  */
1298 #define WM8994_LINEOUT1N_MUTE                   0x0040  /* LINEOUT1N_MUTE */
1299 #define WM8994_LINEOUT1N_MUTE_MASK              0x0040  /* LINEOUT1N_MUTE */
1300 #define WM8994_LINEOUT1N_MUTE_SHIFT                  6  /* LINEOUT1N_MUTE */
1301 #define WM8994_LINEOUT1N_MUTE_WIDTH                  1  /* LINEOUT1N_MUTE */
1302 #define WM8994_LINEOUT1P_MUTE                   0x0020  /* LINEOUT1P_MUTE */
1303 #define WM8994_LINEOUT1P_MUTE_MASK              0x0020  /* LINEOUT1P_MUTE */
1304 #define WM8994_LINEOUT1P_MUTE_SHIFT                  5  /* LINEOUT1P_MUTE */
1305 #define WM8994_LINEOUT1P_MUTE_WIDTH                  1  /* LINEOUT1P_MUTE */
1306 #define WM8994_LINEOUT1_VOL                     0x0010  /* LINEOUT1_VOL */
1307 #define WM8994_LINEOUT1_VOL_MASK                0x0010  /* LINEOUT1_VOL */
1308 #define WM8994_LINEOUT1_VOL_SHIFT                    4  /* LINEOUT1_VOL */
1309 #define WM8994_LINEOUT1_VOL_WIDTH                    1  /* LINEOUT1_VOL */
1310 #define WM8994_LINEOUT2N_MUTE                   0x0004  /* LINEOUT2N_MUTE */
1311 #define WM8994_LINEOUT2N_MUTE_MASK              0x0004  /* LINEOUT2N_MUTE */
1312 #define WM8994_LINEOUT2N_MUTE_SHIFT                  2  /* LINEOUT2N_MUTE */
1313 #define WM8994_LINEOUT2N_MUTE_WIDTH                  1  /* LINEOUT2N_MUTE */
1314 #define WM8994_LINEOUT2P_MUTE                   0x0002  /* LINEOUT2P_MUTE */
1315 #define WM8994_LINEOUT2P_MUTE_MASK              0x0002  /* LINEOUT2P_MUTE */
1316 #define WM8994_LINEOUT2P_MUTE_SHIFT                  1  /* LINEOUT2P_MUTE */
1317 #define WM8994_LINEOUT2P_MUTE_WIDTH                  1  /* LINEOUT2P_MUTE */
1318 #define WM8994_LINEOUT2_VOL                     0x0001  /* LINEOUT2_VOL */
1319 #define WM8994_LINEOUT2_VOL_MASK                0x0001  /* LINEOUT2_VOL */
1320 #define WM8994_LINEOUT2_VOL_SHIFT                    0  /* LINEOUT2_VOL */
1321 #define WM8994_LINEOUT2_VOL_WIDTH                    1  /* LINEOUT2_VOL */
1322 
1323 /*
1324  * R31 (0x1F) - HPOUT2 Volume
1325  */
1326 #define WM8994_HPOUT2_MUTE                      0x0020  /* HPOUT2_MUTE */
1327 #define WM8994_HPOUT2_MUTE_MASK                 0x0020  /* HPOUT2_MUTE */
1328 #define WM8994_HPOUT2_MUTE_SHIFT                     5  /* HPOUT2_MUTE */
1329 #define WM8994_HPOUT2_MUTE_WIDTH                     1  /* HPOUT2_MUTE */
1330 #define WM8994_HPOUT2_VOL                       0x0010  /* HPOUT2_VOL */
1331 #define WM8994_HPOUT2_VOL_MASK                  0x0010  /* HPOUT2_VOL */
1332 #define WM8994_HPOUT2_VOL_SHIFT                      4  /* HPOUT2_VOL */
1333 #define WM8994_HPOUT2_VOL_WIDTH                      1  /* HPOUT2_VOL */
1334 
1335 /*
1336  * R32 (0x20) - Left OPGA Volume
1337  */
1338 #define WM8994_MIXOUT_VU                        0x0100  /* MIXOUT_VU */
1339 #define WM8994_MIXOUT_VU_MASK                   0x0100  /* MIXOUT_VU */
1340 #define WM8994_MIXOUT_VU_SHIFT                       8  /* MIXOUT_VU */
1341 #define WM8994_MIXOUT_VU_WIDTH                       1  /* MIXOUT_VU */
1342 #define WM8994_MIXOUTL_ZC                       0x0080  /* MIXOUTL_ZC */
1343 #define WM8994_MIXOUTL_ZC_MASK                  0x0080  /* MIXOUTL_ZC */
1344 #define WM8994_MIXOUTL_ZC_SHIFT                      7  /* MIXOUTL_ZC */
1345 #define WM8994_MIXOUTL_ZC_WIDTH                      1  /* MIXOUTL_ZC */
1346 #define WM8994_MIXOUTL_MUTE_N                   0x0040  /* MIXOUTL_MUTE_N */
1347 #define WM8994_MIXOUTL_MUTE_N_MASK              0x0040  /* MIXOUTL_MUTE_N */
1348 #define WM8994_MIXOUTL_MUTE_N_SHIFT                  6  /* MIXOUTL_MUTE_N */
1349 #define WM8994_MIXOUTL_MUTE_N_WIDTH                  1  /* MIXOUTL_MUTE_N */
1350 #define WM8994_MIXOUTL_VOL_MASK                 0x003F  /* MIXOUTL_VOL - [5:0] */
1351 #define WM8994_MIXOUTL_VOL_SHIFT                     0  /* MIXOUTL_VOL - [5:0] */
1352 #define WM8994_MIXOUTL_VOL_WIDTH                     6  /* MIXOUTL_VOL - [5:0] */
1353 
1354 /*
1355  * R33 (0x21) - Right OPGA Volume
1356  */
1357 #define WM8994_MIXOUT_VU                        0x0100  /* MIXOUT_VU */
1358 #define WM8994_MIXOUT_VU_MASK                   0x0100  /* MIXOUT_VU */
1359 #define WM8994_MIXOUT_VU_SHIFT                       8  /* MIXOUT_VU */
1360 #define WM8994_MIXOUT_VU_WIDTH                       1  /* MIXOUT_VU */
1361 #define WM8994_MIXOUTR_ZC                       0x0080  /* MIXOUTR_ZC */
1362 #define WM8994_MIXOUTR_ZC_MASK                  0x0080  /* MIXOUTR_ZC */
1363 #define WM8994_MIXOUTR_ZC_SHIFT                      7  /* MIXOUTR_ZC */
1364 #define WM8994_MIXOUTR_ZC_WIDTH                      1  /* MIXOUTR_ZC */
1365 #define WM8994_MIXOUTR_MUTE_N                   0x0040  /* MIXOUTR_MUTE_N */
1366 #define WM8994_MIXOUTR_MUTE_N_MASK              0x0040  /* MIXOUTR_MUTE_N */
1367 #define WM8994_MIXOUTR_MUTE_N_SHIFT                  6  /* MIXOUTR_MUTE_N */
1368 #define WM8994_MIXOUTR_MUTE_N_WIDTH                  1  /* MIXOUTR_MUTE_N */
1369 #define WM8994_MIXOUTR_VOL_MASK                 0x003F  /* MIXOUTR_VOL - [5:0] */
1370 #define WM8994_MIXOUTR_VOL_SHIFT                     0  /* MIXOUTR_VOL - [5:0] */
1371 #define WM8994_MIXOUTR_VOL_WIDTH                     6  /* MIXOUTR_VOL - [5:0] */
1372 
1373 /*
1374  * R34 (0x22) - SPKMIXL Attenuation
1375  */
1376 #define WM8994_DAC2L_SPKMIXL_VOL                0x0040  /* DAC2L_SPKMIXL_VOL */
1377 #define WM8994_DAC2L_SPKMIXL_VOL_MASK           0x0040  /* DAC2L_SPKMIXL_VOL */
1378 #define WM8994_DAC2L_SPKMIXL_VOL_SHIFT               6  /* DAC2L_SPKMIXL_VOL */
1379 #define WM8994_DAC2L_SPKMIXL_VOL_WIDTH               1  /* DAC2L_SPKMIXL_VOL */
1380 #define WM8994_MIXINL_SPKMIXL_VOL               0x0020  /* MIXINL_SPKMIXL_VOL */
1381 #define WM8994_MIXINL_SPKMIXL_VOL_MASK          0x0020  /* MIXINL_SPKMIXL_VOL */
1382 #define WM8994_MIXINL_SPKMIXL_VOL_SHIFT              5  /* MIXINL_SPKMIXL_VOL */
1383 #define WM8994_MIXINL_SPKMIXL_VOL_WIDTH              1  /* MIXINL_SPKMIXL_VOL */
1384 #define WM8994_IN1LP_SPKMIXL_VOL                0x0010  /* IN1LP_SPKMIXL_VOL */
1385 #define WM8994_IN1LP_SPKMIXL_VOL_MASK           0x0010  /* IN1LP_SPKMIXL_VOL */
1386 #define WM8994_IN1LP_SPKMIXL_VOL_SHIFT               4  /* IN1LP_SPKMIXL_VOL */
1387 #define WM8994_IN1LP_SPKMIXL_VOL_WIDTH               1  /* IN1LP_SPKMIXL_VOL */
1388 #define WM8994_MIXOUTL_SPKMIXL_VOL              0x0008  /* MIXOUTL_SPKMIXL_VOL */
1389 #define WM8994_MIXOUTL_SPKMIXL_VOL_MASK         0x0008  /* MIXOUTL_SPKMIXL_VOL */
1390 #define WM8994_MIXOUTL_SPKMIXL_VOL_SHIFT             3  /* MIXOUTL_SPKMIXL_VOL */
1391 #define WM8994_MIXOUTL_SPKMIXL_VOL_WIDTH             1  /* MIXOUTL_SPKMIXL_VOL */
1392 #define WM8994_DAC1L_SPKMIXL_VOL                0x0004  /* DAC1L_SPKMIXL_VOL */
1393 #define WM8994_DAC1L_SPKMIXL_VOL_MASK           0x0004  /* DAC1L_SPKMIXL_VOL */
1394 #define WM8994_DAC1L_SPKMIXL_VOL_SHIFT               2  /* DAC1L_SPKMIXL_VOL */
1395 #define WM8994_DAC1L_SPKMIXL_VOL_WIDTH               1  /* DAC1L_SPKMIXL_VOL */
1396 #define WM8994_SPKMIXL_VOL_MASK                 0x0003  /* SPKMIXL_VOL - [1:0] */
1397 #define WM8994_SPKMIXL_VOL_SHIFT                     0  /* SPKMIXL_VOL - [1:0] */
1398 #define WM8994_SPKMIXL_VOL_WIDTH                     2  /* SPKMIXL_VOL - [1:0] */
1399 
1400 /*
1401  * R35 (0x23) - SPKMIXR Attenuation
1402  */
1403 #define WM8994_SPKOUT_CLASSAB                   0x0100  /* SPKOUT_CLASSAB */
1404 #define WM8994_SPKOUT_CLASSAB_MASK              0x0100  /* SPKOUT_CLASSAB */
1405 #define WM8994_SPKOUT_CLASSAB_SHIFT                  8  /* SPKOUT_CLASSAB */
1406 #define WM8994_SPKOUT_CLASSAB_WIDTH                  1  /* SPKOUT_CLASSAB */
1407 #define WM8994_DAC2R_SPKMIXR_VOL                0x0040  /* DAC2R_SPKMIXR_VOL */
1408 #define WM8994_DAC2R_SPKMIXR_VOL_MASK           0x0040  /* DAC2R_SPKMIXR_VOL */
1409 #define WM8994_DAC2R_SPKMIXR_VOL_SHIFT               6  /* DAC2R_SPKMIXR_VOL */
1410 #define WM8994_DAC2R_SPKMIXR_VOL_WIDTH               1  /* DAC2R_SPKMIXR_VOL */
1411 #define WM8994_MIXINR_SPKMIXR_VOL               0x0020  /* MIXINR_SPKMIXR_VOL */
1412 #define WM8994_MIXINR_SPKMIXR_VOL_MASK          0x0020  /* MIXINR_SPKMIXR_VOL */
1413 #define WM8994_MIXINR_SPKMIXR_VOL_SHIFT              5  /* MIXINR_SPKMIXR_VOL */
1414 #define WM8994_MIXINR_SPKMIXR_VOL_WIDTH              1  /* MIXINR_SPKMIXR_VOL */
1415 #define WM8994_IN1RP_SPKMIXR_VOL                0x0010  /* IN1RP_SPKMIXR_VOL */
1416 #define WM8994_IN1RP_SPKMIXR_VOL_MASK           0x0010  /* IN1RP_SPKMIXR_VOL */
1417 #define WM8994_IN1RP_SPKMIXR_VOL_SHIFT               4  /* IN1RP_SPKMIXR_VOL */
1418 #define WM8994_IN1RP_SPKMIXR_VOL_WIDTH               1  /* IN1RP_SPKMIXR_VOL */
1419 #define WM8994_MIXOUTR_SPKMIXR_VOL              0x0008  /* MIXOUTR_SPKMIXR_VOL */
1420 #define WM8994_MIXOUTR_SPKMIXR_VOL_MASK         0x0008  /* MIXOUTR_SPKMIXR_VOL */
1421 #define WM8994_MIXOUTR_SPKMIXR_VOL_SHIFT             3  /* MIXOUTR_SPKMIXR_VOL */
1422 #define WM8994_MIXOUTR_SPKMIXR_VOL_WIDTH             1  /* MIXOUTR_SPKMIXR_VOL */
1423 #define WM8994_DAC1R_SPKMIXR_VOL                0x0004  /* DAC1R_SPKMIXR_VOL */
1424 #define WM8994_DAC1R_SPKMIXR_VOL_MASK           0x0004  /* DAC1R_SPKMIXR_VOL */
1425 #define WM8994_DAC1R_SPKMIXR_VOL_SHIFT               2  /* DAC1R_SPKMIXR_VOL */
1426 #define WM8994_DAC1R_SPKMIXR_VOL_WIDTH               1  /* DAC1R_SPKMIXR_VOL */
1427 #define WM8994_SPKMIXR_VOL_MASK                 0x0003  /* SPKMIXR_VOL - [1:0] */
1428 #define WM8994_SPKMIXR_VOL_SHIFT                     0  /* SPKMIXR_VOL - [1:0] */
1429 #define WM8994_SPKMIXR_VOL_WIDTH                     2  /* SPKMIXR_VOL - [1:0] */
1430 
1431 /*
1432  * R36 (0x24) - SPKOUT Mixers
1433  */
1434 #define WM8994_IN2LRP_TO_SPKOUTL                0x0020  /* IN2LRP_TO_SPKOUTL */
1435 #define WM8994_IN2LRP_TO_SPKOUTL_MASK           0x0020  /* IN2LRP_TO_SPKOUTL */
1436 #define WM8994_IN2LRP_TO_SPKOUTL_SHIFT               5  /* IN2LRP_TO_SPKOUTL */
1437 #define WM8994_IN2LRP_TO_SPKOUTL_WIDTH               1  /* IN2LRP_TO_SPKOUTL */
1438 #define WM8994_SPKMIXL_TO_SPKOUTL               0x0010  /* SPKMIXL_TO_SPKOUTL */
1439 #define WM8994_SPKMIXL_TO_SPKOUTL_MASK          0x0010  /* SPKMIXL_TO_SPKOUTL */
1440 #define WM8994_SPKMIXL_TO_SPKOUTL_SHIFT              4  /* SPKMIXL_TO_SPKOUTL */
1441 #define WM8994_SPKMIXL_TO_SPKOUTL_WIDTH              1  /* SPKMIXL_TO_SPKOUTL */
1442 #define WM8994_SPKMIXR_TO_SPKOUTL               0x0008  /* SPKMIXR_TO_SPKOUTL */
1443 #define WM8994_SPKMIXR_TO_SPKOUTL_MASK          0x0008  /* SPKMIXR_TO_SPKOUTL */
1444 #define WM8994_SPKMIXR_TO_SPKOUTL_SHIFT              3  /* SPKMIXR_TO_SPKOUTL */
1445 #define WM8994_SPKMIXR_TO_SPKOUTL_WIDTH              1  /* SPKMIXR_TO_SPKOUTL */
1446 #define WM8994_IN2LRP_TO_SPKOUTR                0x0004  /* IN2LRP_TO_SPKOUTR */
1447 #define WM8994_IN2LRP_TO_SPKOUTR_MASK           0x0004  /* IN2LRP_TO_SPKOUTR */
1448 #define WM8994_IN2LRP_TO_SPKOUTR_SHIFT               2  /* IN2LRP_TO_SPKOUTR */
1449 #define WM8994_IN2LRP_TO_SPKOUTR_WIDTH               1  /* IN2LRP_TO_SPKOUTR */
1450 #define WM8994_SPKMIXL_TO_SPKOUTR               0x0002  /* SPKMIXL_TO_SPKOUTR */
1451 #define WM8994_SPKMIXL_TO_SPKOUTR_MASK          0x0002  /* SPKMIXL_TO_SPKOUTR */
1452 #define WM8994_SPKMIXL_TO_SPKOUTR_SHIFT              1  /* SPKMIXL_TO_SPKOUTR */
1453 #define WM8994_SPKMIXL_TO_SPKOUTR_WIDTH              1  /* SPKMIXL_TO_SPKOUTR */
1454 #define WM8994_SPKMIXR_TO_SPKOUTR               0x0001  /* SPKMIXR_TO_SPKOUTR */
1455 #define WM8994_SPKMIXR_TO_SPKOUTR_MASK          0x0001  /* SPKMIXR_TO_SPKOUTR */
1456 #define WM8994_SPKMIXR_TO_SPKOUTR_SHIFT              0  /* SPKMIXR_TO_SPKOUTR */
1457 #define WM8994_SPKMIXR_TO_SPKOUTR_WIDTH              1  /* SPKMIXR_TO_SPKOUTR */
1458 
1459 /*
1460  * R37 (0x25) - ClassD
1461  */
1462 #define WM8994_SPKOUTL_BOOST_MASK               0x0038  /* SPKOUTL_BOOST - [5:3] */
1463 #define WM8994_SPKOUTL_BOOST_SHIFT                   3  /* SPKOUTL_BOOST - [5:3] */
1464 #define WM8994_SPKOUTL_BOOST_WIDTH                   3  /* SPKOUTL_BOOST - [5:3] */
1465 #define WM8994_SPKOUTR_BOOST_MASK               0x0007  /* SPKOUTR_BOOST - [2:0] */
1466 #define WM8994_SPKOUTR_BOOST_SHIFT                   0  /* SPKOUTR_BOOST - [2:0] */
1467 #define WM8994_SPKOUTR_BOOST_WIDTH                   3  /* SPKOUTR_BOOST - [2:0] */
1468 
1469 /*
1470  * R38 (0x26) - Speaker Volume Left
1471  */
1472 #define WM8994_SPKOUT_VU                        0x0100  /* SPKOUT_VU */
1473 #define WM8994_SPKOUT_VU_MASK                   0x0100  /* SPKOUT_VU */
1474 #define WM8994_SPKOUT_VU_SHIFT                       8  /* SPKOUT_VU */
1475 #define WM8994_SPKOUT_VU_WIDTH                       1  /* SPKOUT_VU */
1476 #define WM8994_SPKOUTL_ZC                       0x0080  /* SPKOUTL_ZC */
1477 #define WM8994_SPKOUTL_ZC_MASK                  0x0080  /* SPKOUTL_ZC */
1478 #define WM8994_SPKOUTL_ZC_SHIFT                      7  /* SPKOUTL_ZC */
1479 #define WM8994_SPKOUTL_ZC_WIDTH                      1  /* SPKOUTL_ZC */
1480 #define WM8994_SPKOUTL_MUTE_N                   0x0040  /* SPKOUTL_MUTE_N */
1481 #define WM8994_SPKOUTL_MUTE_N_MASK              0x0040  /* SPKOUTL_MUTE_N */
1482 #define WM8994_SPKOUTL_MUTE_N_SHIFT                  6  /* SPKOUTL_MUTE_N */
1483 #define WM8994_SPKOUTL_MUTE_N_WIDTH                  1  /* SPKOUTL_MUTE_N */
1484 #define WM8994_SPKOUTL_VOL_MASK                 0x003F  /* SPKOUTL_VOL - [5:0] */
1485 #define WM8994_SPKOUTL_VOL_SHIFT                     0  /* SPKOUTL_VOL - [5:0] */
1486 #define WM8994_SPKOUTL_VOL_WIDTH                     6  /* SPKOUTL_VOL - [5:0] */
1487 
1488 /*
1489  * R39 (0x27) - Speaker Volume Right
1490  */
1491 #define WM8994_SPKOUT_VU                        0x0100  /* SPKOUT_VU */
1492 #define WM8994_SPKOUT_VU_MASK                   0x0100  /* SPKOUT_VU */
1493 #define WM8994_SPKOUT_VU_SHIFT                       8  /* SPKOUT_VU */
1494 #define WM8994_SPKOUT_VU_WIDTH                       1  /* SPKOUT_VU */
1495 #define WM8994_SPKOUTR_ZC                       0x0080  /* SPKOUTR_ZC */
1496 #define WM8994_SPKOUTR_ZC_MASK                  0x0080  /* SPKOUTR_ZC */
1497 #define WM8994_SPKOUTR_ZC_SHIFT                      7  /* SPKOUTR_ZC */
1498 #define WM8994_SPKOUTR_ZC_WIDTH                      1  /* SPKOUTR_ZC */
1499 #define WM8994_SPKOUTR_MUTE_N                   0x0040  /* SPKOUTR_MUTE_N */
1500 #define WM8994_SPKOUTR_MUTE_N_MASK              0x0040  /* SPKOUTR_MUTE_N */
1501 #define WM8994_SPKOUTR_MUTE_N_SHIFT                  6  /* SPKOUTR_MUTE_N */
1502 #define WM8994_SPKOUTR_MUTE_N_WIDTH                  1  /* SPKOUTR_MUTE_N */
1503 #define WM8994_SPKOUTR_VOL_MASK                 0x003F  /* SPKOUTR_VOL - [5:0] */
1504 #define WM8994_SPKOUTR_VOL_SHIFT                     0  /* SPKOUTR_VOL - [5:0] */
1505 #define WM8994_SPKOUTR_VOL_WIDTH                     6  /* SPKOUTR_VOL - [5:0] */
1506 
1507 /*
1508  * R40 (0x28) - Input Mixer (2)
1509  */
1510 #define WM8994_IN2LP_TO_IN2L                    0x0080  /* IN2LP_TO_IN2L */
1511 #define WM8994_IN2LP_TO_IN2L_MASK               0x0080  /* IN2LP_TO_IN2L */
1512 #define WM8994_IN2LP_TO_IN2L_SHIFT                   7  /* IN2LP_TO_IN2L */
1513 #define WM8994_IN2LP_TO_IN2L_WIDTH                   1  /* IN2LP_TO_IN2L */
1514 #define WM8994_IN2LN_TO_IN2L                    0x0040  /* IN2LN_TO_IN2L */
1515 #define WM8994_IN2LN_TO_IN2L_MASK               0x0040  /* IN2LN_TO_IN2L */
1516 #define WM8994_IN2LN_TO_IN2L_SHIFT                   6  /* IN2LN_TO_IN2L */
1517 #define WM8994_IN2LN_TO_IN2L_WIDTH                   1  /* IN2LN_TO_IN2L */
1518 #define WM8994_IN1LP_TO_IN1L                    0x0020  /* IN1LP_TO_IN1L */
1519 #define WM8994_IN1LP_TO_IN1L_MASK               0x0020  /* IN1LP_TO_IN1L */
1520 #define WM8994_IN1LP_TO_IN1L_SHIFT                   5  /* IN1LP_TO_IN1L */
1521 #define WM8994_IN1LP_TO_IN1L_WIDTH                   1  /* IN1LP_TO_IN1L */
1522 #define WM8994_IN1LN_TO_IN1L                    0x0010  /* IN1LN_TO_IN1L */
1523 #define WM8994_IN1LN_TO_IN1L_MASK               0x0010  /* IN1LN_TO_IN1L */
1524 #define WM8994_IN1LN_TO_IN1L_SHIFT                   4  /* IN1LN_TO_IN1L */
1525 #define WM8994_IN1LN_TO_IN1L_WIDTH                   1  /* IN1LN_TO_IN1L */
1526 #define WM8994_IN2RP_TO_IN2R                    0x0008  /* IN2RP_TO_IN2R */
1527 #define WM8994_IN2RP_TO_IN2R_MASK               0x0008  /* IN2RP_TO_IN2R */
1528 #define WM8994_IN2RP_TO_IN2R_SHIFT                   3  /* IN2RP_TO_IN2R */
1529 #define WM8994_IN2RP_TO_IN2R_WIDTH                   1  /* IN2RP_TO_IN2R */
1530 #define WM8994_IN2RN_TO_IN2R                    0x0004  /* IN2RN_TO_IN2R */
1531 #define WM8994_IN2RN_TO_IN2R_MASK               0x0004  /* IN2RN_TO_IN2R */
1532 #define WM8994_IN2RN_TO_IN2R_SHIFT                   2  /* IN2RN_TO_IN2R */
1533 #define WM8994_IN2RN_TO_IN2R_WIDTH                   1  /* IN2RN_TO_IN2R */
1534 #define WM8994_IN1RP_TO_IN1R                    0x0002  /* IN1RP_TO_IN1R */
1535 #define WM8994_IN1RP_TO_IN1R_MASK               0x0002  /* IN1RP_TO_IN1R */
1536 #define WM8994_IN1RP_TO_IN1R_SHIFT                   1  /* IN1RP_TO_IN1R */
1537 #define WM8994_IN1RP_TO_IN1R_WIDTH                   1  /* IN1RP_TO_IN1R */
1538 #define WM8994_IN1RN_TO_IN1R                    0x0001  /* IN1RN_TO_IN1R */
1539 #define WM8994_IN1RN_TO_IN1R_MASK               0x0001  /* IN1RN_TO_IN1R */
1540 #define WM8994_IN1RN_TO_IN1R_SHIFT                   0  /* IN1RN_TO_IN1R */
1541 #define WM8994_IN1RN_TO_IN1R_WIDTH                   1  /* IN1RN_TO_IN1R */
1542 
1543 /*
1544  * R41 (0x29) - Input Mixer (3)
1545  */
1546 #define WM8994_IN2L_TO_MIXINL                   0x0100  /* IN2L_TO_MIXINL */
1547 #define WM8994_IN2L_TO_MIXINL_MASK              0x0100  /* IN2L_TO_MIXINL */
1548 #define WM8994_IN2L_TO_MIXINL_SHIFT                  8  /* IN2L_TO_MIXINL */
1549 #define WM8994_IN2L_TO_MIXINL_WIDTH                  1  /* IN2L_TO_MIXINL */
1550 #define WM8994_IN2L_MIXINL_VOL                  0x0080  /* IN2L_MIXINL_VOL */
1551 #define WM8994_IN2L_MIXINL_VOL_MASK             0x0080  /* IN2L_MIXINL_VOL */
1552 #define WM8994_IN2L_MIXINL_VOL_SHIFT                 7  /* IN2L_MIXINL_VOL */
1553 #define WM8994_IN2L_MIXINL_VOL_WIDTH                 1  /* IN2L_MIXINL_VOL */
1554 #define WM8994_IN1L_TO_MIXINL                   0x0020  /* IN1L_TO_MIXINL */
1555 #define WM8994_IN1L_TO_MIXINL_MASK              0x0020  /* IN1L_TO_MIXINL */
1556 #define WM8994_IN1L_TO_MIXINL_SHIFT                  5  /* IN1L_TO_MIXINL */
1557 #define WM8994_IN1L_TO_MIXINL_WIDTH                  1  /* IN1L_TO_MIXINL */
1558 #define WM8994_IN1L_MIXINL_VOL                  0x0010  /* IN1L_MIXINL_VOL */
1559 #define WM8994_IN1L_MIXINL_VOL_MASK             0x0010  /* IN1L_MIXINL_VOL */
1560 #define WM8994_IN1L_MIXINL_VOL_SHIFT                 4  /* IN1L_MIXINL_VOL */
1561 #define WM8994_IN1L_MIXINL_VOL_WIDTH                 1  /* IN1L_MIXINL_VOL */
1562 #define WM8994_MIXOUTL_MIXINL_VOL_MASK          0x0007  /* MIXOUTL_MIXINL_VOL - [2:0] */
1563 #define WM8994_MIXOUTL_MIXINL_VOL_SHIFT              0  /* MIXOUTL_MIXINL_VOL - [2:0] */
1564 #define WM8994_MIXOUTL_MIXINL_VOL_WIDTH              3  /* MIXOUTL_MIXINL_VOL - [2:0] */
1565 
1566 /*
1567  * R42 (0x2A) - Input Mixer (4)
1568  */
1569 #define WM8994_IN2R_TO_MIXINR                   0x0100  /* IN2R_TO_MIXINR */
1570 #define WM8994_IN2R_TO_MIXINR_MASK              0x0100  /* IN2R_TO_MIXINR */
1571 #define WM8994_IN2R_TO_MIXINR_SHIFT                  8  /* IN2R_TO_MIXINR */
1572 #define WM8994_IN2R_TO_MIXINR_WIDTH                  1  /* IN2R_TO_MIXINR */
1573 #define WM8994_IN2R_MIXINR_VOL                  0x0080  /* IN2R_MIXINR_VOL */
1574 #define WM8994_IN2R_MIXINR_VOL_MASK             0x0080  /* IN2R_MIXINR_VOL */
1575 #define WM8994_IN2R_MIXINR_VOL_SHIFT                 7  /* IN2R_MIXINR_VOL */
1576 #define WM8994_IN2R_MIXINR_VOL_WIDTH                 1  /* IN2R_MIXINR_VOL */
1577 #define WM8994_IN1R_TO_MIXINR                   0x0020  /* IN1R_TO_MIXINR */
1578 #define WM8994_IN1R_TO_MIXINR_MASK              0x0020  /* IN1R_TO_MIXINR */
1579 #define WM8994_IN1R_TO_MIXINR_SHIFT                  5  /* IN1R_TO_MIXINR */
1580 #define WM8994_IN1R_TO_MIXINR_WIDTH                  1  /* IN1R_TO_MIXINR */
1581 #define WM8994_IN1R_MIXINR_VOL                  0x0010  /* IN1R_MIXINR_VOL */
1582 #define WM8994_IN1R_MIXINR_VOL_MASK             0x0010  /* IN1R_MIXINR_VOL */
1583 #define WM8994_IN1R_MIXINR_VOL_SHIFT                 4  /* IN1R_MIXINR_VOL */
1584 #define WM8994_IN1R_MIXINR_VOL_WIDTH                 1  /* IN1R_MIXINR_VOL */
1585 #define WM8994_MIXOUTR_MIXINR_VOL_MASK          0x0007  /* MIXOUTR_MIXINR_VOL - [2:0] */
1586 #define WM8994_MIXOUTR_MIXINR_VOL_SHIFT              0  /* MIXOUTR_MIXINR_VOL - [2:0] */
1587 #define WM8994_MIXOUTR_MIXINR_VOL_WIDTH              3  /* MIXOUTR_MIXINR_VOL - [2:0] */
1588 
1589 /*
1590  * R43 (0x2B) - Input Mixer (5)
1591  */
1592 #define WM8994_IN1LP_MIXINL_VOL_MASK            0x01C0  /* IN1LP_MIXINL_VOL - [8:6] */
1593 #define WM8994_IN1LP_MIXINL_VOL_SHIFT                6  /* IN1LP_MIXINL_VOL - [8:6] */
1594 #define WM8994_IN1LP_MIXINL_VOL_WIDTH                3  /* IN1LP_MIXINL_VOL - [8:6] */
1595 #define WM8994_IN2LRP_MIXINL_VOL_MASK           0x0007  /* IN2LRP_MIXINL_VOL - [2:0] */
1596 #define WM8994_IN2LRP_MIXINL_VOL_SHIFT               0  /* IN2LRP_MIXINL_VOL - [2:0] */
1597 #define WM8994_IN2LRP_MIXINL_VOL_WIDTH               3  /* IN2LRP_MIXINL_VOL - [2:0] */
1598 
1599 /*
1600  * R44 (0x2C) - Input Mixer (6)
1601  */
1602 #define WM8994_IN1RP_MIXINR_VOL_MASK            0x01C0  /* IN1RP_MIXINR_VOL - [8:6] */
1603 #define WM8994_IN1RP_MIXINR_VOL_SHIFT                6  /* IN1RP_MIXINR_VOL - [8:6] */
1604 #define WM8994_IN1RP_MIXINR_VOL_WIDTH                3  /* IN1RP_MIXINR_VOL - [8:6] */
1605 #define WM8994_IN2LRP_MIXINR_VOL_MASK           0x0007  /* IN2LRP_MIXINR_VOL - [2:0] */
1606 #define WM8994_IN2LRP_MIXINR_VOL_SHIFT               0  /* IN2LRP_MIXINR_VOL - [2:0] */
1607 #define WM8994_IN2LRP_MIXINR_VOL_WIDTH               3  /* IN2LRP_MIXINR_VOL - [2:0] */
1608 
1609 /*
1610  * R45 (0x2D) - Output Mixer (1)
1611  */
1612 #define WM8994_DAC1L_TO_HPOUT1L                 0x0100  /* DAC1L_TO_HPOUT1L */
1613 #define WM8994_DAC1L_TO_HPOUT1L_MASK            0x0100  /* DAC1L_TO_HPOUT1L */
1614 #define WM8994_DAC1L_TO_HPOUT1L_SHIFT                8  /* DAC1L_TO_HPOUT1L */
1615 #define WM8994_DAC1L_TO_HPOUT1L_WIDTH                1  /* DAC1L_TO_HPOUT1L */
1616 #define WM8994_MIXINR_TO_MIXOUTL                0x0080  /* MIXINR_TO_MIXOUTL */
1617 #define WM8994_MIXINR_TO_MIXOUTL_MASK           0x0080  /* MIXINR_TO_MIXOUTL */
1618 #define WM8994_MIXINR_TO_MIXOUTL_SHIFT               7  /* MIXINR_TO_MIXOUTL */
1619 #define WM8994_MIXINR_TO_MIXOUTL_WIDTH               1  /* MIXINR_TO_MIXOUTL */
1620 #define WM8994_MIXINL_TO_MIXOUTL                0x0040  /* MIXINL_TO_MIXOUTL */
1621 #define WM8994_MIXINL_TO_MIXOUTL_MASK           0x0040  /* MIXINL_TO_MIXOUTL */
1622 #define WM8994_MIXINL_TO_MIXOUTL_SHIFT               6  /* MIXINL_TO_MIXOUTL */
1623 #define WM8994_MIXINL_TO_MIXOUTL_WIDTH               1  /* MIXINL_TO_MIXOUTL */
1624 #define WM8994_IN2RN_TO_MIXOUTL                 0x0020  /* IN2RN_TO_MIXOUTL */
1625 #define WM8994_IN2RN_TO_MIXOUTL_MASK            0x0020  /* IN2RN_TO_MIXOUTL */
1626 #define WM8994_IN2RN_TO_MIXOUTL_SHIFT                5  /* IN2RN_TO_MIXOUTL */
1627 #define WM8994_IN2RN_TO_MIXOUTL_WIDTH                1  /* IN2RN_TO_MIXOUTL */
1628 #define WM8994_IN2LN_TO_MIXOUTL                 0x0010  /* IN2LN_TO_MIXOUTL */
1629 #define WM8994_IN2LN_TO_MIXOUTL_MASK            0x0010  /* IN2LN_TO_MIXOUTL */
1630 #define WM8994_IN2LN_TO_MIXOUTL_SHIFT                4  /* IN2LN_TO_MIXOUTL */
1631 #define WM8994_IN2LN_TO_MIXOUTL_WIDTH                1  /* IN2LN_TO_MIXOUTL */
1632 #define WM8994_IN1R_TO_MIXOUTL                  0x0008  /* IN1R_TO_MIXOUTL */
1633 #define WM8994_IN1R_TO_MIXOUTL_MASK             0x0008  /* IN1R_TO_MIXOUTL */
1634 #define WM8994_IN1R_TO_MIXOUTL_SHIFT                 3  /* IN1R_TO_MIXOUTL */
1635 #define WM8994_IN1R_TO_MIXOUTL_WIDTH                 1  /* IN1R_TO_MIXOUTL */
1636 #define WM8994_IN1L_TO_MIXOUTL                  0x0004  /* IN1L_TO_MIXOUTL */
1637 #define WM8994_IN1L_TO_MIXOUTL_MASK             0x0004  /* IN1L_TO_MIXOUTL */
1638 #define WM8994_IN1L_TO_MIXOUTL_SHIFT                 2  /* IN1L_TO_MIXOUTL */
1639 #define WM8994_IN1L_TO_MIXOUTL_WIDTH                 1  /* IN1L_TO_MIXOUTL */
1640 #define WM8994_IN2LP_TO_MIXOUTL                 0x0002  /* IN2LP_TO_MIXOUTL */
1641 #define WM8994_IN2LP_TO_MIXOUTL_MASK            0x0002  /* IN2LP_TO_MIXOUTL */
1642 #define WM8994_IN2LP_TO_MIXOUTL_SHIFT                1  /* IN2LP_TO_MIXOUTL */
1643 #define WM8994_IN2LP_TO_MIXOUTL_WIDTH                1  /* IN2LP_TO_MIXOUTL */
1644 #define WM8994_DAC1L_TO_MIXOUTL                 0x0001  /* DAC1L_TO_MIXOUTL */
1645 #define WM8994_DAC1L_TO_MIXOUTL_MASK            0x0001  /* DAC1L_TO_MIXOUTL */
1646 #define WM8994_DAC1L_TO_MIXOUTL_SHIFT                0  /* DAC1L_TO_MIXOUTL */
1647 #define WM8994_DAC1L_TO_MIXOUTL_WIDTH                1  /* DAC1L_TO_MIXOUTL */
1648 
1649 /*
1650  * R46 (0x2E) - Output Mixer (2)
1651  */
1652 #define WM8994_DAC1R_TO_HPOUT1R                 0x0100  /* DAC1R_TO_HPOUT1R */
1653 #define WM8994_DAC1R_TO_HPOUT1R_MASK            0x0100  /* DAC1R_TO_HPOUT1R */
1654 #define WM8994_DAC1R_TO_HPOUT1R_SHIFT                8  /* DAC1R_TO_HPOUT1R */
1655 #define WM8994_DAC1R_TO_HPOUT1R_WIDTH                1  /* DAC1R_TO_HPOUT1R */
1656 #define WM8994_MIXINL_TO_MIXOUTR                0x0080  /* MIXINL_TO_MIXOUTR */
1657 #define WM8994_MIXINL_TO_MIXOUTR_MASK           0x0080  /* MIXINL_TO_MIXOUTR */
1658 #define WM8994_MIXINL_TO_MIXOUTR_SHIFT               7  /* MIXINL_TO_MIXOUTR */
1659 #define WM8994_MIXINL_TO_MIXOUTR_WIDTH               1  /* MIXINL_TO_MIXOUTR */
1660 #define WM8994_MIXINR_TO_MIXOUTR                0x0040  /* MIXINR_TO_MIXOUTR */
1661 #define WM8994_MIXINR_TO_MIXOUTR_MASK           0x0040  /* MIXINR_TO_MIXOUTR */
1662 #define WM8994_MIXINR_TO_MIXOUTR_SHIFT               6  /* MIXINR_TO_MIXOUTR */
1663 #define WM8994_MIXINR_TO_MIXOUTR_WIDTH               1  /* MIXINR_TO_MIXOUTR */
1664 #define WM8994_IN2LN_TO_MIXOUTR                 0x0020  /* IN2LN_TO_MIXOUTR */
1665 #define WM8994_IN2LN_TO_MIXOUTR_MASK            0x0020  /* IN2LN_TO_MIXOUTR */
1666 #define WM8994_IN2LN_TO_MIXOUTR_SHIFT                5  /* IN2LN_TO_MIXOUTR */
1667 #define WM8994_IN2LN_TO_MIXOUTR_WIDTH                1  /* IN2LN_TO_MIXOUTR */
1668 #define WM8994_IN2RN_TO_MIXOUTR                 0x0010  /* IN2RN_TO_MIXOUTR */
1669 #define WM8994_IN2RN_TO_MIXOUTR_MASK            0x0010  /* IN2RN_TO_MIXOUTR */
1670 #define WM8994_IN2RN_TO_MIXOUTR_SHIFT                4  /* IN2RN_TO_MIXOUTR */
1671 #define WM8994_IN2RN_TO_MIXOUTR_WIDTH                1  /* IN2RN_TO_MIXOUTR */
1672 #define WM8994_IN1L_TO_MIXOUTR                  0x0008  /* IN1L_TO_MIXOUTR */
1673 #define WM8994_IN1L_TO_MIXOUTR_MASK             0x0008  /* IN1L_TO_MIXOUTR */
1674 #define WM8994_IN1L_TO_MIXOUTR_SHIFT                 3  /* IN1L_TO_MIXOUTR */
1675 #define WM8994_IN1L_TO_MIXOUTR_WIDTH                 1  /* IN1L_TO_MIXOUTR */
1676 #define WM8994_IN1R_TO_MIXOUTR                  0x0004  /* IN1R_TO_MIXOUTR */
1677 #define WM8994_IN1R_TO_MIXOUTR_MASK             0x0004  /* IN1R_TO_MIXOUTR */
1678 #define WM8994_IN1R_TO_MIXOUTR_SHIFT                 2  /* IN1R_TO_MIXOUTR */
1679 #define WM8994_IN1R_TO_MIXOUTR_WIDTH                 1  /* IN1R_TO_MIXOUTR */
1680 #define WM8994_IN2RP_TO_MIXOUTR                 0x0002  /* IN2RP_TO_MIXOUTR */
1681 #define WM8994_IN2RP_TO_MIXOUTR_MASK            0x0002  /* IN2RP_TO_MIXOUTR */
1682 #define WM8994_IN2RP_TO_MIXOUTR_SHIFT                1  /* IN2RP_TO_MIXOUTR */
1683 #define WM8994_IN2RP_TO_MIXOUTR_WIDTH                1  /* IN2RP_TO_MIXOUTR */
1684 #define WM8994_DAC1R_TO_MIXOUTR                 0x0001  /* DAC1R_TO_MIXOUTR */
1685 #define WM8994_DAC1R_TO_MIXOUTR_MASK            0x0001  /* DAC1R_TO_MIXOUTR */
1686 #define WM8994_DAC1R_TO_MIXOUTR_SHIFT                0  /* DAC1R_TO_MIXOUTR */
1687 #define WM8994_DAC1R_TO_MIXOUTR_WIDTH                1  /* DAC1R_TO_MIXOUTR */
1688 
1689 /*
1690  * R47 (0x2F) - Output Mixer (3)
1691  */
1692 #define WM8994_IN2LP_MIXOUTL_VOL_MASK           0x0E00  /* IN2LP_MIXOUTL_VOL - [11:9] */
1693 #define WM8994_IN2LP_MIXOUTL_VOL_SHIFT               9  /* IN2LP_MIXOUTL_VOL - [11:9] */
1694 #define WM8994_IN2LP_MIXOUTL_VOL_WIDTH               3  /* IN2LP_MIXOUTL_VOL - [11:9] */
1695 #define WM8994_IN2LN_MIXOUTL_VOL_MASK           0x01C0  /* IN2LN_MIXOUTL_VOL - [8:6] */
1696 #define WM8994_IN2LN_MIXOUTL_VOL_SHIFT               6  /* IN2LN_MIXOUTL_VOL - [8:6] */
1697 #define WM8994_IN2LN_MIXOUTL_VOL_WIDTH               3  /* IN2LN_MIXOUTL_VOL - [8:6] */
1698 #define WM8994_IN1R_MIXOUTL_VOL_MASK            0x0038  /* IN1R_MIXOUTL_VOL - [5:3] */
1699 #define WM8994_IN1R_MIXOUTL_VOL_SHIFT                3  /* IN1R_MIXOUTL_VOL - [5:3] */
1700 #define WM8994_IN1R_MIXOUTL_VOL_WIDTH                3  /* IN1R_MIXOUTL_VOL - [5:3] */
1701 #define WM8994_IN1L_MIXOUTL_VOL_MASK            0x0007  /* IN1L_MIXOUTL_VOL - [2:0] */
1702 #define WM8994_IN1L_MIXOUTL_VOL_SHIFT                0  /* IN1L_MIXOUTL_VOL - [2:0] */
1703 #define WM8994_IN1L_MIXOUTL_VOL_WIDTH                3  /* IN1L_MIXOUTL_VOL - [2:0] */
1704 
1705 /*
1706  * R48 (0x30) - Output Mixer (4)
1707  */
1708 #define WM8994_IN2RP_MIXOUTR_VOL_MASK           0x0E00  /* IN2RP_MIXOUTR_VOL - [11:9] */
1709 #define WM8994_IN2RP_MIXOUTR_VOL_SHIFT               9  /* IN2RP_MIXOUTR_VOL - [11:9] */
1710 #define WM8994_IN2RP_MIXOUTR_VOL_WIDTH               3  /* IN2RP_MIXOUTR_VOL - [11:9] */
1711 #define WM8994_IN2RN_MIXOUTR_VOL_MASK           0x01C0  /* IN2RN_MIXOUTR_VOL - [8:6] */
1712 #define WM8994_IN2RN_MIXOUTR_VOL_SHIFT               6  /* IN2RN_MIXOUTR_VOL - [8:6] */
1713 #define WM8994_IN2RN_MIXOUTR_VOL_WIDTH               3  /* IN2RN_MIXOUTR_VOL - [8:6] */
1714 #define WM8994_IN1L_MIXOUTR_VOL_MASK            0x0038  /* IN1L_MIXOUTR_VOL - [5:3] */
1715 #define WM8994_IN1L_MIXOUTR_VOL_SHIFT                3  /* IN1L_MIXOUTR_VOL - [5:3] */
1716 #define WM8994_IN1L_MIXOUTR_VOL_WIDTH                3  /* IN1L_MIXOUTR_VOL - [5:3] */
1717 #define WM8994_IN1R_MIXOUTR_VOL_MASK            0x0007  /* IN1R_MIXOUTR_VOL - [2:0] */
1718 #define WM8994_IN1R_MIXOUTR_VOL_SHIFT                0  /* IN1R_MIXOUTR_VOL - [2:0] */
1719 #define WM8994_IN1R_MIXOUTR_VOL_WIDTH                3  /* IN1R_MIXOUTR_VOL - [2:0] */
1720 
1721 /*
1722  * R49 (0x31) - Output Mixer (5)
1723  */
1724 #define WM8994_DAC1L_MIXOUTL_VOL_MASK           0x0E00  /* DAC1L_MIXOUTL_VOL - [11:9] */
1725 #define WM8994_DAC1L_MIXOUTL_VOL_SHIFT               9  /* DAC1L_MIXOUTL_VOL - [11:9] */
1726 #define WM8994_DAC1L_MIXOUTL_VOL_WIDTH               3  /* DAC1L_MIXOUTL_VOL - [11:9] */
1727 #define WM8994_IN2RN_MIXOUTL_VOL_MASK           0x01C0  /* IN2RN_MIXOUTL_VOL - [8:6] */
1728 #define WM8994_IN2RN_MIXOUTL_VOL_SHIFT               6  /* IN2RN_MIXOUTL_VOL - [8:6] */
1729 #define WM8994_IN2RN_MIXOUTL_VOL_WIDTH               3  /* IN2RN_MIXOUTL_VOL - [8:6] */
1730 #define WM8994_MIXINR_MIXOUTL_VOL_MASK          0x0038  /* MIXINR_MIXOUTL_VOL - [5:3] */
1731 #define WM8994_MIXINR_MIXOUTL_VOL_SHIFT              3  /* MIXINR_MIXOUTL_VOL - [5:3] */
1732 #define WM8994_MIXINR_MIXOUTL_VOL_WIDTH              3  /* MIXINR_MIXOUTL_VOL - [5:3] */
1733 #define WM8994_MIXINL_MIXOUTL_VOL_MASK          0x0007  /* MIXINL_MIXOUTL_VOL - [2:0] */
1734 #define WM8994_MIXINL_MIXOUTL_VOL_SHIFT              0  /* MIXINL_MIXOUTL_VOL - [2:0] */
1735 #define WM8994_MIXINL_MIXOUTL_VOL_WIDTH              3  /* MIXINL_MIXOUTL_VOL - [2:0] */
1736 
1737 /*
1738  * R50 (0x32) - Output Mixer (6)
1739  */
1740 #define WM8994_DAC1R_MIXOUTR_VOL_MASK           0x0E00  /* DAC1R_MIXOUTR_VOL - [11:9] */
1741 #define WM8994_DAC1R_MIXOUTR_VOL_SHIFT               9  /* DAC1R_MIXOUTR_VOL - [11:9] */
1742 #define WM8994_DAC1R_MIXOUTR_VOL_WIDTH               3  /* DAC1R_MIXOUTR_VOL - [11:9] */
1743 #define WM8994_IN2LN_MIXOUTR_VOL_MASK           0x01C0  /* IN2LN_MIXOUTR_VOL - [8:6] */
1744 #define WM8994_IN2LN_MIXOUTR_VOL_SHIFT               6  /* IN2LN_MIXOUTR_VOL - [8:6] */
1745 #define WM8994_IN2LN_MIXOUTR_VOL_WIDTH               3  /* IN2LN_MIXOUTR_VOL - [8:6] */
1746 #define WM8994_MIXINL_MIXOUTR_VOL_MASK          0x0038  /* MIXINL_MIXOUTR_VOL - [5:3] */
1747 #define WM8994_MIXINL_MIXOUTR_VOL_SHIFT              3  /* MIXINL_MIXOUTR_VOL - [5:3] */
1748 #define WM8994_MIXINL_MIXOUTR_VOL_WIDTH              3  /* MIXINL_MIXOUTR_VOL - [5:3] */
1749 #define WM8994_MIXINR_MIXOUTR_VOL_MASK          0x0007  /* MIXINR_MIXOUTR_VOL - [2:0] */
1750 #define WM8994_MIXINR_MIXOUTR_VOL_SHIFT              0  /* MIXINR_MIXOUTR_VOL - [2:0] */
1751 #define WM8994_MIXINR_MIXOUTR_VOL_WIDTH              3  /* MIXINR_MIXOUTR_VOL - [2:0] */
1752 
1753 /*
1754  * R51 (0x33) - HPOUT2 Mixer
1755  */
1756 #define WM8994_IN2LRP_TO_HPOUT2                 0x0020  /* IN2LRP_TO_HPOUT2 */
1757 #define WM8994_IN2LRP_TO_HPOUT2_MASK            0x0020  /* IN2LRP_TO_HPOUT2 */
1758 #define WM8994_IN2LRP_TO_HPOUT2_SHIFT                5  /* IN2LRP_TO_HPOUT2 */
1759 #define WM8994_IN2LRP_TO_HPOUT2_WIDTH                1  /* IN2LRP_TO_HPOUT2 */
1760 #define WM8994_MIXOUTLVOL_TO_HPOUT2             0x0010  /* MIXOUTLVOL_TO_HPOUT2 */
1761 #define WM8994_MIXOUTLVOL_TO_HPOUT2_MASK        0x0010  /* MIXOUTLVOL_TO_HPOUT2 */
1762 #define WM8994_MIXOUTLVOL_TO_HPOUT2_SHIFT            4  /* MIXOUTLVOL_TO_HPOUT2 */
1763 #define WM8994_MIXOUTLVOL_TO_HPOUT2_WIDTH            1  /* MIXOUTLVOL_TO_HPOUT2 */
1764 #define WM8994_MIXOUTRVOL_TO_HPOUT2             0x0008  /* MIXOUTRVOL_TO_HPOUT2 */
1765 #define WM8994_MIXOUTRVOL_TO_HPOUT2_MASK        0x0008  /* MIXOUTRVOL_TO_HPOUT2 */
1766 #define WM8994_MIXOUTRVOL_TO_HPOUT2_SHIFT            3  /* MIXOUTRVOL_TO_HPOUT2 */
1767 #define WM8994_MIXOUTRVOL_TO_HPOUT2_WIDTH            1  /* MIXOUTRVOL_TO_HPOUT2 */
1768 
1769 /*
1770  * R52 (0x34) - Line Mixer (1)
1771  */
1772 #define WM8994_MIXOUTL_TO_LINEOUT1N             0x0040  /* MIXOUTL_TO_LINEOUT1N */
1773 #define WM8994_MIXOUTL_TO_LINEOUT1N_MASK        0x0040  /* MIXOUTL_TO_LINEOUT1N */
1774 #define WM8994_MIXOUTL_TO_LINEOUT1N_SHIFT            6  /* MIXOUTL_TO_LINEOUT1N */
1775 #define WM8994_MIXOUTL_TO_LINEOUT1N_WIDTH            1  /* MIXOUTL_TO_LINEOUT1N */
1776 #define WM8994_MIXOUTR_TO_LINEOUT1N             0x0020  /* MIXOUTR_TO_LINEOUT1N */
1777 #define WM8994_MIXOUTR_TO_LINEOUT1N_MASK        0x0020  /* MIXOUTR_TO_LINEOUT1N */
1778 #define WM8994_MIXOUTR_TO_LINEOUT1N_SHIFT            5  /* MIXOUTR_TO_LINEOUT1N */
1779 #define WM8994_MIXOUTR_TO_LINEOUT1N_WIDTH            1  /* MIXOUTR_TO_LINEOUT1N */
1780 #define WM8994_LINEOUT1_MODE                    0x0010  /* LINEOUT1_MODE */
1781 #define WM8994_LINEOUT1_MODE_MASK               0x0010  /* LINEOUT1_MODE */
1782 #define WM8994_LINEOUT1_MODE_SHIFT                   4  /* LINEOUT1_MODE */
1783 #define WM8994_LINEOUT1_MODE_WIDTH                   1  /* LINEOUT1_MODE */
1784 #define WM8994_IN1R_TO_LINEOUT1P                0x0004  /* IN1R_TO_LINEOUT1P */
1785 #define WM8994_IN1R_TO_LINEOUT1P_MASK           0x0004  /* IN1R_TO_LINEOUT1P */
1786 #define WM8994_IN1R_TO_LINEOUT1P_SHIFT               2  /* IN1R_TO_LINEOUT1P */
1787 #define WM8994_IN1R_TO_LINEOUT1P_WIDTH               1  /* IN1R_TO_LINEOUT1P */
1788 #define WM8994_IN1L_TO_LINEOUT1P                0x0002  /* IN1L_TO_LINEOUT1P */
1789 #define WM8994_IN1L_TO_LINEOUT1P_MASK           0x0002  /* IN1L_TO_LINEOUT1P */
1790 #define WM8994_IN1L_TO_LINEOUT1P_SHIFT               1  /* IN1L_TO_LINEOUT1P */
1791 #define WM8994_IN1L_TO_LINEOUT1P_WIDTH               1  /* IN1L_TO_LINEOUT1P */
1792 #define WM8994_MIXOUTL_TO_LINEOUT1P             0x0001  /* MIXOUTL_TO_LINEOUT1P */
1793 #define WM8994_MIXOUTL_TO_LINEOUT1P_MASK        0x0001  /* MIXOUTL_TO_LINEOUT1P */
1794 #define WM8994_MIXOUTL_TO_LINEOUT1P_SHIFT            0  /* MIXOUTL_TO_LINEOUT1P */
1795 #define WM8994_MIXOUTL_TO_LINEOUT1P_WIDTH            1  /* MIXOUTL_TO_LINEOUT1P */
1796 
1797 /*
1798  * R53 (0x35) - Line Mixer (2)
1799  */
1800 #define WM8994_MIXOUTR_TO_LINEOUT2N             0x0040  /* MIXOUTR_TO_LINEOUT2N */
1801 #define WM8994_MIXOUTR_TO_LINEOUT2N_MASK        0x0040  /* MIXOUTR_TO_LINEOUT2N */
1802 #define WM8994_MIXOUTR_TO_LINEOUT2N_SHIFT            6  /* MIXOUTR_TO_LINEOUT2N */
1803 #define WM8994_MIXOUTR_TO_LINEOUT2N_WIDTH            1  /* MIXOUTR_TO_LINEOUT2N */
1804 #define WM8994_MIXOUTL_TO_LINEOUT2N             0x0020  /* MIXOUTL_TO_LINEOUT2N */
1805 #define WM8994_MIXOUTL_TO_LINEOUT2N_MASK        0x0020  /* MIXOUTL_TO_LINEOUT2N */
1806 #define WM8994_MIXOUTL_TO_LINEOUT2N_SHIFT            5  /* MIXOUTL_TO_LINEOUT2N */
1807 #define WM8994_MIXOUTL_TO_LINEOUT2N_WIDTH            1  /* MIXOUTL_TO_LINEOUT2N */
1808 #define WM8994_LINEOUT2_MODE                    0x0010  /* LINEOUT2_MODE */
1809 #define WM8994_LINEOUT2_MODE_MASK               0x0010  /* LINEOUT2_MODE */
1810 #define WM8994_LINEOUT2_MODE_SHIFT                   4  /* LINEOUT2_MODE */
1811 #define WM8994_LINEOUT2_MODE_WIDTH                   1  /* LINEOUT2_MODE */
1812 #define WM8994_IN1L_TO_LINEOUT2P                0x0004  /* IN1L_TO_LINEOUT2P */
1813 #define WM8994_IN1L_TO_LINEOUT2P_MASK           0x0004  /* IN1L_TO_LINEOUT2P */
1814 #define WM8994_IN1L_TO_LINEOUT2P_SHIFT               2  /* IN1L_TO_LINEOUT2P */
1815 #define WM8994_IN1L_TO_LINEOUT2P_WIDTH               1  /* IN1L_TO_LINEOUT2P */
1816 #define WM8994_IN1R_TO_LINEOUT2P                0x0002  /* IN1R_TO_LINEOUT2P */
1817 #define WM8994_IN1R_TO_LINEOUT2P_MASK           0x0002  /* IN1R_TO_LINEOUT2P */
1818 #define WM8994_IN1R_TO_LINEOUT2P_SHIFT               1  /* IN1R_TO_LINEOUT2P */
1819 #define WM8994_IN1R_TO_LINEOUT2P_WIDTH               1  /* IN1R_TO_LINEOUT2P */
1820 #define WM8994_MIXOUTR_TO_LINEOUT2P             0x0001  /* MIXOUTR_TO_LINEOUT2P */
1821 #define WM8994_MIXOUTR_TO_LINEOUT2P_MASK        0x0001  /* MIXOUTR_TO_LINEOUT2P */
1822 #define WM8994_MIXOUTR_TO_LINEOUT2P_SHIFT            0  /* MIXOUTR_TO_LINEOUT2P */
1823 #define WM8994_MIXOUTR_TO_LINEOUT2P_WIDTH            1  /* MIXOUTR_TO_LINEOUT2P */
1824 
1825 /*
1826  * R54 (0x36) - Speaker Mixer
1827  */
1828 #define WM8994_DAC2L_TO_SPKMIXL                 0x0200  /* DAC2L_TO_SPKMIXL */
1829 #define WM8994_DAC2L_TO_SPKMIXL_MASK            0x0200  /* DAC2L_TO_SPKMIXL */
1830 #define WM8994_DAC2L_TO_SPKMIXL_SHIFT                9  /* DAC2L_TO_SPKMIXL */
1831 #define WM8994_DAC2L_TO_SPKMIXL_WIDTH                1  /* DAC2L_TO_SPKMIXL */
1832 #define WM8994_DAC2R_TO_SPKMIXR                 0x0100  /* DAC2R_TO_SPKMIXR */
1833 #define WM8994_DAC2R_TO_SPKMIXR_MASK            0x0100  /* DAC2R_TO_SPKMIXR */
1834 #define WM8994_DAC2R_TO_SPKMIXR_SHIFT                8  /* DAC2R_TO_SPKMIXR */
1835 #define WM8994_DAC2R_TO_SPKMIXR_WIDTH                1  /* DAC2R_TO_SPKMIXR */
1836 #define WM8994_MIXINL_TO_SPKMIXL                0x0080  /* MIXINL_TO_SPKMIXL */
1837 #define WM8994_MIXINL_TO_SPKMIXL_MASK           0x0080  /* MIXINL_TO_SPKMIXL */
1838 #define WM8994_MIXINL_TO_SPKMIXL_SHIFT               7  /* MIXINL_TO_SPKMIXL */
1839 #define WM8994_MIXINL_TO_SPKMIXL_WIDTH               1  /* MIXINL_TO_SPKMIXL */
1840 #define WM8994_MIXINR_TO_SPKMIXR                0x0040  /* MIXINR_TO_SPKMIXR */
1841 #define WM8994_MIXINR_TO_SPKMIXR_MASK           0x0040  /* MIXINR_TO_SPKMIXR */
1842 #define WM8994_MIXINR_TO_SPKMIXR_SHIFT               6  /* MIXINR_TO_SPKMIXR */
1843 #define WM8994_MIXINR_TO_SPKMIXR_WIDTH               1  /* MIXINR_TO_SPKMIXR */
1844 #define WM8994_IN1LP_TO_SPKMIXL                 0x0020  /* IN1LP_TO_SPKMIXL */
1845 #define WM8994_IN1LP_TO_SPKMIXL_MASK            0x0020  /* IN1LP_TO_SPKMIXL */
1846 #define WM8994_IN1LP_TO_SPKMIXL_SHIFT                5  /* IN1LP_TO_SPKMIXL */
1847 #define WM8994_IN1LP_TO_SPKMIXL_WIDTH                1  /* IN1LP_TO_SPKMIXL */
1848 #define WM8994_IN1RP_TO_SPKMIXR                 0x0010  /* IN1RP_TO_SPKMIXR */
1849 #define WM8994_IN1RP_TO_SPKMIXR_MASK            0x0010  /* IN1RP_TO_SPKMIXR */
1850 #define WM8994_IN1RP_TO_SPKMIXR_SHIFT                4  /* IN1RP_TO_SPKMIXR */
1851 #define WM8994_IN1RP_TO_SPKMIXR_WIDTH                1  /* IN1RP_TO_SPKMIXR */
1852 #define WM8994_MIXOUTL_TO_SPKMIXL               0x0008  /* MIXOUTL_TO_SPKMIXL */
1853 #define WM8994_MIXOUTL_TO_SPKMIXL_MASK          0x0008  /* MIXOUTL_TO_SPKMIXL */
1854 #define WM8994_MIXOUTL_TO_SPKMIXL_SHIFT              3  /* MIXOUTL_TO_SPKMIXL */
1855 #define WM8994_MIXOUTL_TO_SPKMIXL_WIDTH              1  /* MIXOUTL_TO_SPKMIXL */
1856 #define WM8994_MIXOUTR_TO_SPKMIXR               0x0004  /* MIXOUTR_TO_SPKMIXR */
1857 #define WM8994_MIXOUTR_TO_SPKMIXR_MASK          0x0004  /* MIXOUTR_TO_SPKMIXR */
1858 #define WM8994_MIXOUTR_TO_SPKMIXR_SHIFT              2  /* MIXOUTR_TO_SPKMIXR */
1859 #define WM8994_MIXOUTR_TO_SPKMIXR_WIDTH              1  /* MIXOUTR_TO_SPKMIXR */
1860 #define WM8994_DAC1L_TO_SPKMIXL                 0x0002  /* DAC1L_TO_SPKMIXL */
1861 #define WM8994_DAC1L_TO_SPKMIXL_MASK            0x0002  /* DAC1L_TO_SPKMIXL */
1862 #define WM8994_DAC1L_TO_SPKMIXL_SHIFT                1  /* DAC1L_TO_SPKMIXL */
1863 #define WM8994_DAC1L_TO_SPKMIXL_WIDTH                1  /* DAC1L_TO_SPKMIXL */
1864 #define WM8994_DAC1R_TO_SPKMIXR                 0x0001  /* DAC1R_TO_SPKMIXR */
1865 #define WM8994_DAC1R_TO_SPKMIXR_MASK            0x0001  /* DAC1R_TO_SPKMIXR */
1866 #define WM8994_DAC1R_TO_SPKMIXR_SHIFT                0  /* DAC1R_TO_SPKMIXR */
1867 #define WM8994_DAC1R_TO_SPKMIXR_WIDTH                1  /* DAC1R_TO_SPKMIXR */
1868 
1869 /*
1870  * R55 (0x37) - Additional Control
1871  */
1872 #define WM8994_LINEOUT1_FB                      0x0080  /* LINEOUT1_FB */
1873 #define WM8994_LINEOUT1_FB_MASK                 0x0080  /* LINEOUT1_FB */
1874 #define WM8994_LINEOUT1_FB_SHIFT                     7  /* LINEOUT1_FB */
1875 #define WM8994_LINEOUT1_FB_WIDTH                     1  /* LINEOUT1_FB */
1876 #define WM8994_LINEOUT2_FB                      0x0040  /* LINEOUT2_FB */
1877 #define WM8994_LINEOUT2_FB_MASK                 0x0040  /* LINEOUT2_FB */
1878 #define WM8994_LINEOUT2_FB_SHIFT                     6  /* LINEOUT2_FB */
1879 #define WM8994_LINEOUT2_FB_WIDTH                     1  /* LINEOUT2_FB */
1880 #define WM8994_VROI                             0x0001  /* VROI */
1881 #define WM8994_VROI_MASK                        0x0001  /* VROI */
1882 #define WM8994_VROI_SHIFT                            0  /* VROI */
1883 #define WM8994_VROI_WIDTH                            1  /* VROI */
1884 
1885 /*
1886  * R56 (0x38) - AntiPOP (1)
1887  */
1888 #define WM8994_LINEOUT_VMID_BUF_ENA             0x0080  /* LINEOUT_VMID_BUF_ENA */
1889 #define WM8994_LINEOUT_VMID_BUF_ENA_MASK        0x0080  /* LINEOUT_VMID_BUF_ENA */
1890 #define WM8994_LINEOUT_VMID_BUF_ENA_SHIFT            7  /* LINEOUT_VMID_BUF_ENA */
1891 #define WM8994_LINEOUT_VMID_BUF_ENA_WIDTH            1  /* LINEOUT_VMID_BUF_ENA */
1892 #define WM8994_HPOUT2_IN_ENA                    0x0040  /* HPOUT2_IN_ENA */
1893 #define WM8994_HPOUT2_IN_ENA_MASK               0x0040  /* HPOUT2_IN_ENA */
1894 #define WM8994_HPOUT2_IN_ENA_SHIFT                   6  /* HPOUT2_IN_ENA */
1895 #define WM8994_HPOUT2_IN_ENA_WIDTH                   1  /* HPOUT2_IN_ENA */
1896 #define WM8994_LINEOUT1_DISCH                   0x0020  /* LINEOUT1_DISCH */
1897 #define WM8994_LINEOUT1_DISCH_MASK              0x0020  /* LINEOUT1_DISCH */
1898 #define WM8994_LINEOUT1_DISCH_SHIFT                  5  /* LINEOUT1_DISCH */
1899 #define WM8994_LINEOUT1_DISCH_WIDTH                  1  /* LINEOUT1_DISCH */
1900 #define WM8994_LINEOUT2_DISCH                   0x0010  /* LINEOUT2_DISCH */
1901 #define WM8994_LINEOUT2_DISCH_MASK              0x0010  /* LINEOUT2_DISCH */
1902 #define WM8994_LINEOUT2_DISCH_SHIFT                  4  /* LINEOUT2_DISCH */
1903 #define WM8994_LINEOUT2_DISCH_WIDTH                  1  /* LINEOUT2_DISCH */
1904 
1905 /*
1906  * R57 (0x39) - AntiPOP (2)
1907  */
1908 #define WM1811_JACKDET_MODE_MASK                0x0180  /* JACKDET_MODE - [8:7] */
1909 #define WM1811_JACKDET_MODE_SHIFT                    7  /* JACKDET_MODE - [8:7] */
1910 #define WM1811_JACKDET_MODE_WIDTH                    2  /* JACKDET_MODE - [8:7] */
1911 #define WM8994_MICB2_DISCH                      0x0100  /* MICB2_DISCH */
1912 #define WM8994_MICB2_DISCH_MASK                 0x0100  /* MICB2_DISCH */
1913 #define WM8994_MICB2_DISCH_SHIFT                     8  /* MICB2_DISCH */
1914 #define WM8994_MICB2_DISCH_WIDTH                     1  /* MICB2_DISCH */
1915 #define WM8994_MICB1_DISCH                      0x0080  /* MICB1_DISCH */
1916 #define WM8994_MICB1_DISCH_MASK                 0x0080  /* MICB1_DISCH */
1917 #define WM8994_MICB1_DISCH_SHIFT                     7  /* MICB1_DISCH */
1918 #define WM8994_MICB1_DISCH_WIDTH                     1  /* MICB1_DISCH */
1919 #define WM8994_VMID_RAMP_MASK                   0x0060  /* VMID_RAMP - [6:5] */
1920 #define WM8994_VMID_RAMP_SHIFT                       5  /* VMID_RAMP - [6:5] */
1921 #define WM8994_VMID_RAMP_WIDTH                       2  /* VMID_RAMP - [6:5] */
1922 #define WM8994_VMID_BUF_ENA                     0x0008  /* VMID_BUF_ENA */
1923 #define WM8994_VMID_BUF_ENA_MASK                0x0008  /* VMID_BUF_ENA */
1924 #define WM8994_VMID_BUF_ENA_SHIFT                    3  /* VMID_BUF_ENA */
1925 #define WM8994_VMID_BUF_ENA_WIDTH                    1  /* VMID_BUF_ENA */
1926 #define WM8994_STARTUP_BIAS_ENA                 0x0004  /* STARTUP_BIAS_ENA */
1927 #define WM8994_STARTUP_BIAS_ENA_MASK            0x0004  /* STARTUP_BIAS_ENA */
1928 #define WM8994_STARTUP_BIAS_ENA_SHIFT                2  /* STARTUP_BIAS_ENA */
1929 #define WM8994_STARTUP_BIAS_ENA_WIDTH                1  /* STARTUP_BIAS_ENA */
1930 #define WM8994_BIAS_SRC                         0x0002  /* BIAS_SRC */
1931 #define WM8994_BIAS_SRC_MASK                    0x0002  /* BIAS_SRC */
1932 #define WM8994_BIAS_SRC_SHIFT                        1  /* BIAS_SRC */
1933 #define WM8994_BIAS_SRC_WIDTH                        1  /* BIAS_SRC */
1934 #define WM8994_VMID_DISCH                       0x0001  /* VMID_DISCH */
1935 #define WM8994_VMID_DISCH_MASK                  0x0001  /* VMID_DISCH */
1936 #define WM8994_VMID_DISCH_SHIFT                      0  /* VMID_DISCH */
1937 #define WM8994_VMID_DISCH_WIDTH                      1  /* VMID_DISCH */
1938 
1939 /*
1940  * R58 (0x3A) - MICBIAS
1941  */
1942 #define WM8994_MICD_SCTHR_MASK                  0x00C0  /* MICD_SCTHR - [7:6] */
1943 #define WM8994_MICD_SCTHR_SHIFT                      6  /* MICD_SCTHR - [7:6] */
1944 #define WM8994_MICD_SCTHR_WIDTH                      2  /* MICD_SCTHR - [7:6] */
1945 #define WM8994_MICD_THR_MASK                    0x0038  /* MICD_THR - [5:3] */
1946 #define WM8994_MICD_THR_SHIFT                        3  /* MICD_THR - [5:3] */
1947 #define WM8994_MICD_THR_WIDTH                        3  /* MICD_THR - [5:3] */
1948 #define WM8994_MICD_ENA                         0x0004  /* MICD_ENA */
1949 #define WM8994_MICD_ENA_MASK                    0x0004  /* MICD_ENA */
1950 #define WM8994_MICD_ENA_SHIFT                        2  /* MICD_ENA */
1951 #define WM8994_MICD_ENA_WIDTH                        1  /* MICD_ENA */
1952 #define WM8994_MICB2_LVL                        0x0002  /* MICB2_LVL */
1953 #define WM8994_MICB2_LVL_MASK                   0x0002  /* MICB2_LVL */
1954 #define WM8994_MICB2_LVL_SHIFT                       1  /* MICB2_LVL */
1955 #define WM8994_MICB2_LVL_WIDTH                       1  /* MICB2_LVL */
1956 #define WM8994_MICB1_LVL                        0x0001  /* MICB1_LVL */
1957 #define WM8994_MICB1_LVL_MASK                   0x0001  /* MICB1_LVL */
1958 #define WM8994_MICB1_LVL_SHIFT                       0  /* MICB1_LVL */
1959 #define WM8994_MICB1_LVL_WIDTH                       1  /* MICB1_LVL */
1960 
1961 /*
1962  * R59 (0x3B) - LDO 1
1963  */
1964 #define WM8994_LDO1_VSEL_MASK                   0x000E  /* LDO1_VSEL - [3:1] */
1965 #define WM8994_LDO1_VSEL_SHIFT                       1  /* LDO1_VSEL - [3:1] */
1966 #define WM8994_LDO1_VSEL_WIDTH                       3  /* LDO1_VSEL - [3:1] */
1967 #define WM8994_LDO1_DISCH                       0x0001  /* LDO1_DISCH */
1968 #define WM8994_LDO1_DISCH_MASK                  0x0001  /* LDO1_DISCH */
1969 #define WM8994_LDO1_DISCH_SHIFT                      0  /* LDO1_DISCH */
1970 #define WM8994_LDO1_DISCH_WIDTH                      1  /* LDO1_DISCH */
1971 
1972 /*
1973  * R60 (0x3C) - LDO 2
1974  */
1975 #define WM8994_LDO2_VSEL_MASK                   0x0006  /* LDO2_VSEL - [2:1] */
1976 #define WM8994_LDO2_VSEL_SHIFT                       1  /* LDO2_VSEL - [2:1] */
1977 #define WM8994_LDO2_VSEL_WIDTH                       2  /* LDO2_VSEL - [2:1] */
1978 #define WM8994_LDO2_DISCH                       0x0001  /* LDO2_DISCH */
1979 #define WM8994_LDO2_DISCH_MASK                  0x0001  /* LDO2_DISCH */
1980 #define WM8994_LDO2_DISCH_SHIFT                      0  /* LDO2_DISCH */
1981 #define WM8994_LDO2_DISCH_WIDTH                      1  /* LDO2_DISCH */
1982 
1983 /*
1984  * R61 (0x3D) - MICBIAS1
1985  */
1986 #define WM8958_MICB1_RATE                       0x0020  /* MICB1_RATE */
1987 #define WM8958_MICB1_RATE_MASK                  0x0020  /* MICB1_RATE */
1988 #define WM8958_MICB1_RATE_SHIFT                      5  /* MICB1_RATE */
1989 #define WM8958_MICB1_RATE_WIDTH                      1  /* MICB1_RATE */
1990 #define WM8958_MICB1_MODE                       0x0010  /* MICB1_MODE */
1991 #define WM8958_MICB1_MODE_MASK                  0x0010  /* MICB1_MODE */
1992 #define WM8958_MICB1_MODE_SHIFT                      4  /* MICB1_MODE */
1993 #define WM8958_MICB1_MODE_WIDTH                      1  /* MICB1_MODE */
1994 #define WM8958_MICB1_LVL_MASK                   0x000E  /* MICB1_LVL - [3:1] */
1995 #define WM8958_MICB1_LVL_SHIFT                       1  /* MICB1_LVL - [3:1] */
1996 #define WM8958_MICB1_LVL_WIDTH                       3  /* MICB1_LVL - [3:1] */
1997 #define WM8958_MICB1_DISCH                      0x0001  /* MICB1_DISCH */
1998 #define WM8958_MICB1_DISCH_MASK                 0x0001  /* MICB1_DISCH */
1999 #define WM8958_MICB1_DISCH_SHIFT                     0  /* MICB1_DISCH */
2000 #define WM8958_MICB1_DISCH_WIDTH                     1  /* MICB1_DISCH */
2001 
2002 /*
2003  * R62 (0x3E) - MICBIAS2
2004  */
2005 #define WM8958_MICB2_RATE                       0x0020  /* MICB2_RATE */
2006 #define WM8958_MICB2_RATE_MASK                  0x0020  /* MICB2_RATE */
2007 #define WM8958_MICB2_RATE_SHIFT                      5  /* MICB2_RATE */
2008 #define WM8958_MICB2_RATE_WIDTH                      1  /* MICB2_RATE */
2009 #define WM8958_MICB2_MODE                       0x0010  /* MICB2_MODE */
2010 #define WM8958_MICB2_MODE_MASK                  0x0010  /* MICB2_MODE */
2011 #define WM8958_MICB2_MODE_SHIFT                      4  /* MICB2_MODE */
2012 #define WM8958_MICB2_MODE_WIDTH                      1  /* MICB2_MODE */
2013 #define WM8958_MICB2_LVL_MASK                   0x000E  /* MICB2_LVL - [3:1] */
2014 #define WM8958_MICB2_LVL_SHIFT                       1  /* MICB2_LVL - [3:1] */
2015 #define WM8958_MICB2_LVL_WIDTH                       3  /* MICB2_LVL - [3:1] */
2016 #define WM8958_MICB2_DISCH                      0x0001  /* MICB2_DISCH */
2017 #define WM8958_MICB2_DISCH_MASK                 0x0001  /* MICB2_DISCH */
2018 #define WM8958_MICB2_DISCH_SHIFT                     0  /* MICB2_DISCH */
2019 #define WM8958_MICB2_DISCH_WIDTH                     1  /* MICB2_DISCH */
2020 
2021 /*
2022  * R210 (0xD2) - Mic Detect 3
2023  */
2024 #define WM8958_MICD_LVL_MASK                    0x07FC  /* MICD_LVL - [10:2] */
2025 #define WM8958_MICD_LVL_SHIFT                        2  /* MICD_LVL - [10:2] */
2026 #define WM8958_MICD_LVL_WIDTH                        9  /* MICD_LVL - [10:2] */
2027 #define WM8958_MICD_VALID                       0x0002  /* MICD_VALID */
2028 #define WM8958_MICD_VALID_MASK                  0x0002  /* MICD_VALID */
2029 #define WM8958_MICD_VALID_SHIFT                      1  /* MICD_VALID */
2030 #define WM8958_MICD_VALID_WIDTH                      1  /* MICD_VALID */
2031 #define WM8958_MICD_STS                         0x0001  /* MICD_STS */
2032 #define WM8958_MICD_STS_MASK                    0x0001  /* MICD_STS */
2033 #define WM8958_MICD_STS_SHIFT                        0  /* MICD_STS */
2034 #define WM8958_MICD_STS_WIDTH                        1  /* MICD_STS */
2035 
2036 /*
2037  * R76 (0x4C) - Charge Pump (1)
2038  */
2039 #define WM8994_CP_ENA                           0x8000  /* CP_ENA */
2040 #define WM8994_CP_ENA_MASK                      0x8000  /* CP_ENA */
2041 #define WM8994_CP_ENA_SHIFT                         15  /* CP_ENA */
2042 #define WM8994_CP_ENA_WIDTH                          1  /* CP_ENA */
2043 
2044 /*
2045  * R77 (0x4D) - Charge Pump (2)
2046  */
2047 #define WM8958_CP_DISCH                         0x8000  /* CP_DISCH */
2048 #define WM8958_CP_DISCH_MASK                    0x8000  /* CP_DISCH */
2049 #define WM8958_CP_DISCH_SHIFT                       15  /* CP_DISCH */
2050 #define WM8958_CP_DISCH_WIDTH                        1  /* CP_DISCH */
2051 
2052 /*
2053  * R81 (0x51) - Class W (1)
2054  */
2055 #define WM8994_CP_DYN_SRC_SEL_MASK              0x0300  /* CP_DYN_SRC_SEL - [9:8] */
2056 #define WM8994_CP_DYN_SRC_SEL_SHIFT                  8  /* CP_DYN_SRC_SEL - [9:8] */
2057 #define WM8994_CP_DYN_SRC_SEL_WIDTH                  2  /* CP_DYN_SRC_SEL - [9:8] */
2058 #define WM8994_CP_DYN_PWR                       0x0001  /* CP_DYN_PWR */
2059 #define WM8994_CP_DYN_PWR_MASK                  0x0001  /* CP_DYN_PWR */
2060 #define WM8994_CP_DYN_PWR_SHIFT                      0  /* CP_DYN_PWR */
2061 #define WM8994_CP_DYN_PWR_WIDTH                      1  /* CP_DYN_PWR */
2062 
2063 /*
2064  * R84 (0x54) - DC Servo (1)
2065  */
2066 #define WM8994_DCS_TRIG_SINGLE_1                0x2000  /* DCS_TRIG_SINGLE_1 */
2067 #define WM8994_DCS_TRIG_SINGLE_1_MASK           0x2000  /* DCS_TRIG_SINGLE_1 */
2068 #define WM8994_DCS_TRIG_SINGLE_1_SHIFT              13  /* DCS_TRIG_SINGLE_1 */
2069 #define WM8994_DCS_TRIG_SINGLE_1_WIDTH               1  /* DCS_TRIG_SINGLE_1 */
2070 #define WM8994_DCS_TRIG_SINGLE_0                0x1000  /* DCS_TRIG_SINGLE_0 */
2071 #define WM8994_DCS_TRIG_SINGLE_0_MASK           0x1000  /* DCS_TRIG_SINGLE_0 */
2072 #define WM8994_DCS_TRIG_SINGLE_0_SHIFT              12  /* DCS_TRIG_SINGLE_0 */
2073 #define WM8994_DCS_TRIG_SINGLE_0_WIDTH               1  /* DCS_TRIG_SINGLE_0 */
2074 #define WM8994_DCS_TRIG_SERIES_1                0x0200  /* DCS_TRIG_SERIES_1 */
2075 #define WM8994_DCS_TRIG_SERIES_1_MASK           0x0200  /* DCS_TRIG_SERIES_1 */
2076 #define WM8994_DCS_TRIG_SERIES_1_SHIFT               9  /* DCS_TRIG_SERIES_1 */
2077 #define WM8994_DCS_TRIG_SERIES_1_WIDTH               1  /* DCS_TRIG_SERIES_1 */
2078 #define WM8994_DCS_TRIG_SERIES_0                0x0100  /* DCS_TRIG_SERIES_0 */
2079 #define WM8994_DCS_TRIG_SERIES_0_MASK           0x0100  /* DCS_TRIG_SERIES_0 */
2080 #define WM8994_DCS_TRIG_SERIES_0_SHIFT               8  /* DCS_TRIG_SERIES_0 */
2081 #define WM8994_DCS_TRIG_SERIES_0_WIDTH               1  /* DCS_TRIG_SERIES_0 */
2082 #define WM8994_DCS_TRIG_STARTUP_1               0x0020  /* DCS_TRIG_STARTUP_1 */
2083 #define WM8994_DCS_TRIG_STARTUP_1_MASK          0x0020  /* DCS_TRIG_STARTUP_1 */
2084 #define WM8994_DCS_TRIG_STARTUP_1_SHIFT              5  /* DCS_TRIG_STARTUP_1 */
2085 #define WM8994_DCS_TRIG_STARTUP_1_WIDTH              1  /* DCS_TRIG_STARTUP_1 */
2086 #define WM8994_DCS_TRIG_STARTUP_0               0x0010  /* DCS_TRIG_STARTUP_0 */
2087 #define WM8994_DCS_TRIG_STARTUP_0_MASK          0x0010  /* DCS_TRIG_STARTUP_0 */
2088 #define WM8994_DCS_TRIG_STARTUP_0_SHIFT              4  /* DCS_TRIG_STARTUP_0 */
2089 #define WM8994_DCS_TRIG_STARTUP_0_WIDTH              1  /* DCS_TRIG_STARTUP_0 */
2090 #define WM8994_DCS_TRIG_DAC_WR_1                0x0008  /* DCS_TRIG_DAC_WR_1 */
2091 #define WM8994_DCS_TRIG_DAC_WR_1_MASK           0x0008  /* DCS_TRIG_DAC_WR_1 */
2092 #define WM8994_DCS_TRIG_DAC_WR_1_SHIFT               3  /* DCS_TRIG_DAC_WR_1 */
2093 #define WM8994_DCS_TRIG_DAC_WR_1_WIDTH               1  /* DCS_TRIG_DAC_WR_1 */
2094 #define WM8994_DCS_TRIG_DAC_WR_0                0x0004  /* DCS_TRIG_DAC_WR_0 */
2095 #define WM8994_DCS_TRIG_DAC_WR_0_MASK           0x0004  /* DCS_TRIG_DAC_WR_0 */
2096 #define WM8994_DCS_TRIG_DAC_WR_0_SHIFT               2  /* DCS_TRIG_DAC_WR_0 */
2097 #define WM8994_DCS_TRIG_DAC_WR_0_WIDTH               1  /* DCS_TRIG_DAC_WR_0 */
2098 #define WM8994_DCS_ENA_CHAN_1                   0x0002  /* DCS_ENA_CHAN_1 */
2099 #define WM8994_DCS_ENA_CHAN_1_MASK              0x0002  /* DCS_ENA_CHAN_1 */
2100 #define WM8994_DCS_ENA_CHAN_1_SHIFT                  1  /* DCS_ENA_CHAN_1 */
2101 #define WM8994_DCS_ENA_CHAN_1_WIDTH                  1  /* DCS_ENA_CHAN_1 */
2102 #define WM8994_DCS_ENA_CHAN_0                   0x0001  /* DCS_ENA_CHAN_0 */
2103 #define WM8994_DCS_ENA_CHAN_0_MASK              0x0001  /* DCS_ENA_CHAN_0 */
2104 #define WM8994_DCS_ENA_CHAN_0_SHIFT                  0  /* DCS_ENA_CHAN_0 */
2105 #define WM8994_DCS_ENA_CHAN_0_WIDTH                  1  /* DCS_ENA_CHAN_0 */
2106 
2107 /*
2108  * R85 (0x55) - DC Servo (2)
2109  */
2110 #define WM8994_DCS_SERIES_NO_01_MASK            0x0FE0  /* DCS_SERIES_NO_01 - [11:5] */
2111 #define WM8994_DCS_SERIES_NO_01_SHIFT                5  /* DCS_SERIES_NO_01 - [11:5] */
2112 #define WM8994_DCS_SERIES_NO_01_WIDTH                7  /* DCS_SERIES_NO_01 - [11:5] */
2113 #define WM8994_DCS_TIMER_PERIOD_01_MASK         0x000F  /* DCS_TIMER_PERIOD_01 - [3:0] */
2114 #define WM8994_DCS_TIMER_PERIOD_01_SHIFT             0  /* DCS_TIMER_PERIOD_01 - [3:0] */
2115 #define WM8994_DCS_TIMER_PERIOD_01_WIDTH             4  /* DCS_TIMER_PERIOD_01 - [3:0] */
2116 
2117 /*
2118  * R87 (0x57) - DC Servo (4)
2119  */
2120 #define WM8994_DCS_DAC_WR_VAL_1_MASK            0xFF00  /* DCS_DAC_WR_VAL_1 - [15:8] */
2121 #define WM8994_DCS_DAC_WR_VAL_1_SHIFT                8  /* DCS_DAC_WR_VAL_1 - [15:8] */
2122 #define WM8994_DCS_DAC_WR_VAL_1_WIDTH                8  /* DCS_DAC_WR_VAL_1 - [15:8] */
2123 #define WM8994_DCS_DAC_WR_VAL_0_MASK            0x00FF  /* DCS_DAC_WR_VAL_0 - [7:0] */
2124 #define WM8994_DCS_DAC_WR_VAL_0_SHIFT                0  /* DCS_DAC_WR_VAL_0 - [7:0] */
2125 #define WM8994_DCS_DAC_WR_VAL_0_WIDTH                8  /* DCS_DAC_WR_VAL_0 - [7:0] */
2126 
2127 /*
2128  * R88 (0x58) - DC Servo Readback
2129  */
2130 #define WM8994_DCS_CAL_COMPLETE_MASK            0x0300  /* DCS_CAL_COMPLETE - [9:8] */
2131 #define WM8994_DCS_CAL_COMPLETE_SHIFT                8  /* DCS_CAL_COMPLETE - [9:8] */
2132 #define WM8994_DCS_CAL_COMPLETE_WIDTH                2  /* DCS_CAL_COMPLETE - [9:8] */
2133 #define WM8994_DCS_DAC_WR_COMPLETE_MASK         0x0030  /* DCS_DAC_WR_COMPLETE - [5:4] */
2134 #define WM8994_DCS_DAC_WR_COMPLETE_SHIFT             4  /* DCS_DAC_WR_COMPLETE - [5:4] */
2135 #define WM8994_DCS_DAC_WR_COMPLETE_WIDTH             2  /* DCS_DAC_WR_COMPLETE - [5:4] */
2136 #define WM8994_DCS_STARTUP_COMPLETE_MASK        0x0003  /* DCS_STARTUP_COMPLETE - [1:0] */
2137 #define WM8994_DCS_STARTUP_COMPLETE_SHIFT            0  /* DCS_STARTUP_COMPLETE - [1:0] */
2138 #define WM8994_DCS_STARTUP_COMPLETE_WIDTH            2  /* DCS_STARTUP_COMPLETE - [1:0] */
2139 
2140 /*
2141  * R96 (0x60) - Analogue HP (1)
2142  */
2143 #define WM1811_HPOUT1_ATTN                      0x0100  /* HPOUT1_ATTN */
2144 #define WM1811_HPOUT1_ATTN_MASK                 0x0100  /* HPOUT1_ATTN */
2145 #define WM1811_HPOUT1_ATTN_SHIFT                     8  /* HPOUT1_ATTN */
2146 #define WM1811_HPOUT1_ATTN_WIDTH                     1  /* HPOUT1_ATTN */
2147 #define WM8994_HPOUT1L_RMV_SHORT                0x0080  /* HPOUT1L_RMV_SHORT */
2148 #define WM8994_HPOUT1L_RMV_SHORT_MASK           0x0080  /* HPOUT1L_RMV_SHORT */
2149 #define WM8994_HPOUT1L_RMV_SHORT_SHIFT               7  /* HPOUT1L_RMV_SHORT */
2150 #define WM8994_HPOUT1L_RMV_SHORT_WIDTH               1  /* HPOUT1L_RMV_SHORT */
2151 #define WM8994_HPOUT1L_OUTP                     0x0040  /* HPOUT1L_OUTP */
2152 #define WM8994_HPOUT1L_OUTP_MASK                0x0040  /* HPOUT1L_OUTP */
2153 #define WM8994_HPOUT1L_OUTP_SHIFT                    6  /* HPOUT1L_OUTP */
2154 #define WM8994_HPOUT1L_OUTP_WIDTH                    1  /* HPOUT1L_OUTP */
2155 #define WM8994_HPOUT1L_DLY                      0x0020  /* HPOUT1L_DLY */
2156 #define WM8994_HPOUT1L_DLY_MASK                 0x0020  /* HPOUT1L_DLY */
2157 #define WM8994_HPOUT1L_DLY_SHIFT                     5  /* HPOUT1L_DLY */
2158 #define WM8994_HPOUT1L_DLY_WIDTH                     1  /* HPOUT1L_DLY */
2159 #define WM8994_HPOUT1R_RMV_SHORT                0x0008  /* HPOUT1R_RMV_SHORT */
2160 #define WM8994_HPOUT1R_RMV_SHORT_MASK           0x0008  /* HPOUT1R_RMV_SHORT */
2161 #define WM8994_HPOUT1R_RMV_SHORT_SHIFT               3  /* HPOUT1R_RMV_SHORT */
2162 #define WM8994_HPOUT1R_RMV_SHORT_WIDTH               1  /* HPOUT1R_RMV_SHORT */
2163 #define WM8994_HPOUT1R_OUTP                     0x0004  /* HPOUT1R_OUTP */
2164 #define WM8994_HPOUT1R_OUTP_MASK                0x0004  /* HPOUT1R_OUTP */
2165 #define WM8994_HPOUT1R_OUTP_SHIFT                    2  /* HPOUT1R_OUTP */
2166 #define WM8994_HPOUT1R_OUTP_WIDTH                    1  /* HPOUT1R_OUTP */
2167 #define WM8994_HPOUT1R_DLY                      0x0002  /* HPOUT1R_DLY */
2168 #define WM8994_HPOUT1R_DLY_MASK                 0x0002  /* HPOUT1R_DLY */
2169 #define WM8994_HPOUT1R_DLY_SHIFT                     1  /* HPOUT1R_DLY */
2170 #define WM8994_HPOUT1R_DLY_WIDTH                     1  /* HPOUT1R_DLY */
2171 
2172 /*
2173  * R208 (0xD0) - Mic Detect 1
2174  */
2175 #define WM8958_MICD_BIAS_STARTTIME_MASK         0xF000  /* MICD_BIAS_STARTTIME - [15:12] */
2176 #define WM8958_MICD_BIAS_STARTTIME_SHIFT            12  /* MICD_BIAS_STARTTIME - [15:12] */
2177 #define WM8958_MICD_BIAS_STARTTIME_WIDTH             4  /* MICD_BIAS_STARTTIME - [15:12] */
2178 #define WM8958_MICD_RATE_MASK                   0x0F00  /* MICD_RATE - [11:8] */
2179 #define WM8958_MICD_RATE_SHIFT                       8  /* MICD_RATE - [11:8] */
2180 #define WM8958_MICD_RATE_WIDTH                       4  /* MICD_RATE - [11:8] */
2181 #define WM8958_MICD_DBTIME                      0x0002  /* MICD_DBTIME */
2182 #define WM8958_MICD_DBTIME_MASK                 0x0002  /* MICD_DBTIME */
2183 #define WM8958_MICD_DBTIME_SHIFT                     1  /* MICD_DBTIME */
2184 #define WM8958_MICD_DBTIME_WIDTH                     1  /* MICD_DBTIME */
2185 #define WM8958_MICD_ENA                         0x0001  /* MICD_ENA */
2186 #define WM8958_MICD_ENA_MASK                    0x0001  /* MICD_ENA */
2187 #define WM8958_MICD_ENA_SHIFT                        0  /* MICD_ENA */
2188 #define WM8958_MICD_ENA_WIDTH                        1  /* MICD_ENA */
2189 
2190 /*
2191  * R209 (0xD1) - Mic Detect 2
2192  */
2193 #define WM8958_MICD_LVL_SEL_MASK                0x00FF  /* MICD_LVL_SEL - [7:0] */
2194 #define WM8958_MICD_LVL_SEL_SHIFT                    0  /* MICD_LVL_SEL - [7:0] */
2195 #define WM8958_MICD_LVL_SEL_WIDTH                    8  /* MICD_LVL_SEL - [7:0] */
2196 
2197 /*
2198  * R210 (0xD2) - Mic Detect 3
2199  */
2200 #define WM8958_MICD_LVL_MASK                    0x07FC  /* MICD_LVL - [10:2] */
2201 #define WM8958_MICD_LVL_SHIFT                        2  /* MICD_LVL - [10:2] */
2202 #define WM8958_MICD_LVL_WIDTH                        9  /* MICD_LVL - [10:2] */
2203 #define WM8958_MICD_VALID                       0x0002  /* MICD_VALID */
2204 #define WM8958_MICD_VALID_MASK                  0x0002  /* MICD_VALID */
2205 #define WM8958_MICD_VALID_SHIFT                      1  /* MICD_VALID */
2206 #define WM8958_MICD_VALID_WIDTH                      1  /* MICD_VALID */
2207 #define WM8958_MICD_STS                         0x0001  /* MICD_STS */
2208 #define WM8958_MICD_STS_MASK                    0x0001  /* MICD_STS */
2209 #define WM8958_MICD_STS_SHIFT                        0  /* MICD_STS */
2210 #define WM8958_MICD_STS_WIDTH                        1  /* MICD_STS */
2211 
2212 /*
2213  * R256 (0x100) - Chip Revision
2214  */
2215 #define WM8994_CHIP_REV_MASK                    0x000F  /* CHIP_REV - [3:0] */
2216 #define WM8994_CHIP_REV_SHIFT                        0  /* CHIP_REV - [3:0] */
2217 #define WM8994_CHIP_REV_WIDTH                        4  /* CHIP_REV - [3:0] */
2218 
2219 /*
2220  * R257 (0x101) - Control Interface
2221  */
2222 #define WM8994_SPI_CONTRD                       0x0040  /* SPI_CONTRD */
2223 #define WM8994_SPI_CONTRD_MASK                  0x0040  /* SPI_CONTRD */
2224 #define WM8994_SPI_CONTRD_SHIFT                      6  /* SPI_CONTRD */
2225 #define WM8994_SPI_CONTRD_WIDTH                      1  /* SPI_CONTRD */
2226 #define WM8994_SPI_4WIRE                        0x0020  /* SPI_4WIRE */
2227 #define WM8994_SPI_4WIRE_MASK                   0x0020  /* SPI_4WIRE */
2228 #define WM8994_SPI_4WIRE_SHIFT                       5  /* SPI_4WIRE */
2229 #define WM8994_SPI_4WIRE_WIDTH                       1  /* SPI_4WIRE */
2230 #define WM8994_SPI_CFG                          0x0010  /* SPI_CFG */
2231 #define WM8994_SPI_CFG_MASK                     0x0010  /* SPI_CFG */
2232 #define WM8994_SPI_CFG_SHIFT                         4  /* SPI_CFG */
2233 #define WM8994_SPI_CFG_WIDTH                         1  /* SPI_CFG */
2234 #define WM8994_AUTO_INC                         0x0004  /* AUTO_INC */
2235 #define WM8994_AUTO_INC_MASK                    0x0004  /* AUTO_INC */
2236 #define WM8994_AUTO_INC_SHIFT                        2  /* AUTO_INC */
2237 #define WM8994_AUTO_INC_WIDTH                        1  /* AUTO_INC */
2238 
2239 /*
2240  * R272 (0x110) - Write Sequencer Ctrl (1)
2241  */
2242 #define WM8994_WSEQ_ENA                         0x8000  /* WSEQ_ENA */
2243 #define WM8994_WSEQ_ENA_MASK                    0x8000  /* WSEQ_ENA */
2244 #define WM8994_WSEQ_ENA_SHIFT                       15  /* WSEQ_ENA */
2245 #define WM8994_WSEQ_ENA_WIDTH                        1  /* WSEQ_ENA */
2246 #define WM8994_WSEQ_ABORT                       0x0200  /* WSEQ_ABORT */
2247 #define WM8994_WSEQ_ABORT_MASK                  0x0200  /* WSEQ_ABORT */
2248 #define WM8994_WSEQ_ABORT_SHIFT                      9  /* WSEQ_ABORT */
2249 #define WM8994_WSEQ_ABORT_WIDTH                      1  /* WSEQ_ABORT */
2250 #define WM8994_WSEQ_START                       0x0100  /* WSEQ_START */
2251 #define WM8994_WSEQ_START_MASK                  0x0100  /* WSEQ_START */
2252 #define WM8994_WSEQ_START_SHIFT                      8  /* WSEQ_START */
2253 #define WM8994_WSEQ_START_WIDTH                      1  /* WSEQ_START */
2254 #define WM8994_WSEQ_START_INDEX_MASK            0x007F  /* WSEQ_START_INDEX - [6:0] */
2255 #define WM8994_WSEQ_START_INDEX_SHIFT                0  /* WSEQ_START_INDEX - [6:0] */
2256 #define WM8994_WSEQ_START_INDEX_WIDTH                7  /* WSEQ_START_INDEX - [6:0] */
2257 
2258 /*
2259  * R273 (0x111) - Write Sequencer Ctrl (2)
2260  */
2261 #define WM8994_WSEQ_BUSY                        0x0100  /* WSEQ_BUSY */
2262 #define WM8994_WSEQ_BUSY_MASK                   0x0100  /* WSEQ_BUSY */
2263 #define WM8994_WSEQ_BUSY_SHIFT                       8  /* WSEQ_BUSY */
2264 #define WM8994_WSEQ_BUSY_WIDTH                       1  /* WSEQ_BUSY */
2265 #define WM8994_WSEQ_CURRENT_INDEX_MASK          0x007F  /* WSEQ_CURRENT_INDEX - [6:0] */
2266 #define WM8994_WSEQ_CURRENT_INDEX_SHIFT              0  /* WSEQ_CURRENT_INDEX - [6:0] */
2267 #define WM8994_WSEQ_CURRENT_INDEX_WIDTH              7  /* WSEQ_CURRENT_INDEX - [6:0] */
2268 
2269 /*
2270  * R512 (0x200) - AIF1 Clocking (1)
2271  */
2272 #define WM8994_AIF1CLK_SRC_MASK                 0x0018  /* AIF1CLK_SRC - [4:3] */
2273 #define WM8994_AIF1CLK_SRC_SHIFT                     3  /* AIF1CLK_SRC - [4:3] */
2274 #define WM8994_AIF1CLK_SRC_WIDTH                     2  /* AIF1CLK_SRC - [4:3] */
2275 #define WM8994_AIF1CLK_INV                      0x0004  /* AIF1CLK_INV */
2276 #define WM8994_AIF1CLK_INV_MASK                 0x0004  /* AIF1CLK_INV */
2277 #define WM8994_AIF1CLK_INV_SHIFT                     2  /* AIF1CLK_INV */
2278 #define WM8994_AIF1CLK_INV_WIDTH                     1  /* AIF1CLK_INV */
2279 #define WM8994_AIF1CLK_DIV                      0x0002  /* AIF1CLK_DIV */
2280 #define WM8994_AIF1CLK_DIV_MASK                 0x0002  /* AIF1CLK_DIV */
2281 #define WM8994_AIF1CLK_DIV_SHIFT                     1  /* AIF1CLK_DIV */
2282 #define WM8994_AIF1CLK_DIV_WIDTH                     1  /* AIF1CLK_DIV */
2283 #define WM8994_AIF1CLK_ENA                      0x0001  /* AIF1CLK_ENA */
2284 #define WM8994_AIF1CLK_ENA_MASK                 0x0001  /* AIF1CLK_ENA */
2285 #define WM8994_AIF1CLK_ENA_SHIFT                     0  /* AIF1CLK_ENA */
2286 #define WM8994_AIF1CLK_ENA_WIDTH                     1  /* AIF1CLK_ENA */
2287 
2288 /*
2289  * R513 (0x201) - AIF1 Clocking (2)
2290  */
2291 #define WM8994_AIF1DAC_DIV_MASK                 0x0038  /* AIF1DAC_DIV - [5:3] */
2292 #define WM8994_AIF1DAC_DIV_SHIFT                     3  /* AIF1DAC_DIV - [5:3] */
2293 #define WM8994_AIF1DAC_DIV_WIDTH                     3  /* AIF1DAC_DIV - [5:3] */
2294 #define WM8994_AIF1ADC_DIV_MASK                 0x0007  /* AIF1ADC_DIV - [2:0] */
2295 #define WM8994_AIF1ADC_DIV_SHIFT                     0  /* AIF1ADC_DIV - [2:0] */
2296 #define WM8994_AIF1ADC_DIV_WIDTH                     3  /* AIF1ADC_DIV - [2:0] */
2297 
2298 /*
2299  * R516 (0x204) - AIF2 Clocking (1)
2300  */
2301 #define WM8994_AIF2CLK_SRC_MASK                 0x0018  /* AIF2CLK_SRC - [4:3] */
2302 #define WM8994_AIF2CLK_SRC_SHIFT                     3  /* AIF2CLK_SRC - [4:3] */
2303 #define WM8994_AIF2CLK_SRC_WIDTH                     2  /* AIF2CLK_SRC - [4:3] */
2304 #define WM8994_AIF2CLK_INV                      0x0004  /* AIF2CLK_INV */
2305 #define WM8994_AIF2CLK_INV_MASK                 0x0004  /* AIF2CLK_INV */
2306 #define WM8994_AIF2CLK_INV_SHIFT                     2  /* AIF2CLK_INV */
2307 #define WM8994_AIF2CLK_INV_WIDTH                     1  /* AIF2CLK_INV */
2308 #define WM8994_AIF2CLK_DIV                      0x0002  /* AIF2CLK_DIV */
2309 #define WM8994_AIF2CLK_DIV_MASK                 0x0002  /* AIF2CLK_DIV */
2310 #define WM8994_AIF2CLK_DIV_SHIFT                     1  /* AIF2CLK_DIV */
2311 #define WM8994_AIF2CLK_DIV_WIDTH                     1  /* AIF2CLK_DIV */
2312 #define WM8994_AIF2CLK_ENA                      0x0001  /* AIF2CLK_ENA */
2313 #define WM8994_AIF2CLK_ENA_MASK                 0x0001  /* AIF2CLK_ENA */
2314 #define WM8994_AIF2CLK_ENA_SHIFT                     0  /* AIF2CLK_ENA */
2315 #define WM8994_AIF2CLK_ENA_WIDTH                     1  /* AIF2CLK_ENA */
2316 
2317 /*
2318  * R517 (0x205) - AIF2 Clocking (2)
2319  */
2320 #define WM8994_AIF2DAC_DIV_MASK                 0x0038  /* AIF2DAC_DIV - [5:3] */
2321 #define WM8994_AIF2DAC_DIV_SHIFT                     3  /* AIF2DAC_DIV - [5:3] */
2322 #define WM8994_AIF2DAC_DIV_WIDTH                     3  /* AIF2DAC_DIV - [5:3] */
2323 #define WM8994_AIF2ADC_DIV_MASK                 0x0007  /* AIF2ADC_DIV - [2:0] */
2324 #define WM8994_AIF2ADC_DIV_SHIFT                     0  /* AIF2ADC_DIV - [2:0] */
2325 #define WM8994_AIF2ADC_DIV_WIDTH                     3  /* AIF2ADC_DIV - [2:0] */
2326 
2327 /*
2328  * R520 (0x208) - Clocking (1)
2329  */
2330 #define WM8958_DSP2CLK_ENA                      0x4000  /* DSP2CLK_ENA */
2331 #define WM8958_DSP2CLK_ENA_MASK                 0x4000  /* DSP2CLK_ENA */
2332 #define WM8958_DSP2CLK_ENA_SHIFT                    14  /* DSP2CLK_ENA */
2333 #define WM8958_DSP2CLK_ENA_WIDTH                     1  /* DSP2CLK_ENA */
2334 #define WM8958_DSP2CLK_SRC                      0x1000  /* DSP2CLK_SRC */
2335 #define WM8958_DSP2CLK_SRC_MASK                 0x1000  /* DSP2CLK_SRC */
2336 #define WM8958_DSP2CLK_SRC_SHIFT                    12  /* DSP2CLK_SRC */
2337 #define WM8958_DSP2CLK_SRC_WIDTH                     1  /* DSP2CLK_SRC */
2338 #define WM8994_TOCLK_ENA                        0x0010  /* TOCLK_ENA */
2339 #define WM8994_TOCLK_ENA_MASK                   0x0010  /* TOCLK_ENA */
2340 #define WM8994_TOCLK_ENA_SHIFT                       4  /* TOCLK_ENA */
2341 #define WM8994_TOCLK_ENA_WIDTH                       1  /* TOCLK_ENA */
2342 #define WM8994_AIF1DSPCLK_ENA                   0x0008  /* AIF1DSPCLK_ENA */
2343 #define WM8994_AIF1DSPCLK_ENA_MASK              0x0008  /* AIF1DSPCLK_ENA */
2344 #define WM8994_AIF1DSPCLK_ENA_SHIFT                  3  /* AIF1DSPCLK_ENA */
2345 #define WM8994_AIF1DSPCLK_ENA_WIDTH                  1  /* AIF1DSPCLK_ENA */
2346 #define WM8994_AIF2DSPCLK_ENA                   0x0004  /* AIF2DSPCLK_ENA */
2347 #define WM8994_AIF2DSPCLK_ENA_MASK              0x0004  /* AIF2DSPCLK_ENA */
2348 #define WM8994_AIF2DSPCLK_ENA_SHIFT                  2  /* AIF2DSPCLK_ENA */
2349 #define WM8994_AIF2DSPCLK_ENA_WIDTH                  1  /* AIF2DSPCLK_ENA */
2350 #define WM8994_SYSDSPCLK_ENA                    0x0002  /* SYSDSPCLK_ENA */
2351 #define WM8994_SYSDSPCLK_ENA_MASK               0x0002  /* SYSDSPCLK_ENA */
2352 #define WM8994_SYSDSPCLK_ENA_SHIFT                   1  /* SYSDSPCLK_ENA */
2353 #define WM8994_SYSDSPCLK_ENA_WIDTH                   1  /* SYSDSPCLK_ENA */
2354 #define WM8994_SYSCLK_SRC                       0x0001  /* SYSCLK_SRC */
2355 #define WM8994_SYSCLK_SRC_MASK                  0x0001  /* SYSCLK_SRC */
2356 #define WM8994_SYSCLK_SRC_SHIFT                      0  /* SYSCLK_SRC */
2357 #define WM8994_SYSCLK_SRC_WIDTH                      1  /* SYSCLK_SRC */
2358 
2359 /*
2360  * R521 (0x209) - Clocking (2)
2361  */
2362 #define WM8994_TOCLK_DIV_MASK                   0x0700  /* TOCLK_DIV - [10:8] */
2363 #define WM8994_TOCLK_DIV_SHIFT                       8  /* TOCLK_DIV - [10:8] */
2364 #define WM8994_TOCLK_DIV_WIDTH                       3  /* TOCLK_DIV - [10:8] */
2365 #define WM8994_DBCLK_DIV_MASK                   0x0070  /* DBCLK_DIV - [6:4] */
2366 #define WM8994_DBCLK_DIV_SHIFT                       4  /* DBCLK_DIV - [6:4] */
2367 #define WM8994_DBCLK_DIV_WIDTH                       3  /* DBCLK_DIV - [6:4] */
2368 #define WM8994_OPCLK_DIV_MASK                   0x0007  /* OPCLK_DIV - [2:0] */
2369 #define WM8994_OPCLK_DIV_SHIFT                       0  /* OPCLK_DIV - [2:0] */
2370 #define WM8994_OPCLK_DIV_WIDTH                       3  /* OPCLK_DIV - [2:0] */
2371 
2372 /*
2373  * R528 (0x210) - AIF1 Rate
2374  */
2375 #define WM8994_AIF1_SR_MASK                     0x00F0  /* AIF1_SR - [7:4] */
2376 #define WM8994_AIF1_SR_SHIFT                         4  /* AIF1_SR - [7:4] */
2377 #define WM8994_AIF1_SR_WIDTH                         4  /* AIF1_SR - [7:4] */
2378 #define WM8994_AIF1CLK_RATE_MASK                0x000F  /* AIF1CLK_RATE - [3:0] */
2379 #define WM8994_AIF1CLK_RATE_SHIFT                    0  /* AIF1CLK_RATE - [3:0] */
2380 #define WM8994_AIF1CLK_RATE_WIDTH                    4  /* AIF1CLK_RATE - [3:0] */
2381 
2382 /*
2383  * R529 (0x211) - AIF2 Rate
2384  */
2385 #define WM8994_AIF2_SR_MASK                     0x00F0  /* AIF2_SR - [7:4] */
2386 #define WM8994_AIF2_SR_SHIFT                         4  /* AIF2_SR - [7:4] */
2387 #define WM8994_AIF2_SR_WIDTH                         4  /* AIF2_SR - [7:4] */
2388 #define WM8994_AIF2CLK_RATE_MASK                0x000F  /* AIF2CLK_RATE - [3:0] */
2389 #define WM8994_AIF2CLK_RATE_SHIFT                    0  /* AIF2CLK_RATE - [3:0] */
2390 #define WM8994_AIF2CLK_RATE_WIDTH                    4  /* AIF2CLK_RATE - [3:0] */
2391 
2392 /*
2393  * R530 (0x212) - Rate Status
2394  */
2395 #define WM8994_SR_ERROR_MASK                    0x000F  /* SR_ERROR - [3:0] */
2396 #define WM8994_SR_ERROR_SHIFT                        0  /* SR_ERROR - [3:0] */
2397 #define WM8994_SR_ERROR_WIDTH                        4  /* SR_ERROR - [3:0] */
2398 
2399 /*
2400  * R544 (0x220) - FLL1 Control (1)
2401  */
2402 #define WM8994_FLL1_FRAC                        0x0004  /* FLL1_FRAC */
2403 #define WM8994_FLL1_FRAC_MASK                   0x0004  /* FLL1_FRAC */
2404 #define WM8994_FLL1_FRAC_SHIFT                       2  /* FLL1_FRAC */
2405 #define WM8994_FLL1_FRAC_WIDTH                       1  /* FLL1_FRAC */
2406 #define WM8994_FLL1_OSC_ENA                     0x0002  /* FLL1_OSC_ENA */
2407 #define WM8994_FLL1_OSC_ENA_MASK                0x0002  /* FLL1_OSC_ENA */
2408 #define WM8994_FLL1_OSC_ENA_SHIFT                    1  /* FLL1_OSC_ENA */
2409 #define WM8994_FLL1_OSC_ENA_WIDTH                    1  /* FLL1_OSC_ENA */
2410 #define WM8994_FLL1_ENA                         0x0001  /* FLL1_ENA */
2411 #define WM8994_FLL1_ENA_MASK                    0x0001  /* FLL1_ENA */
2412 #define WM8994_FLL1_ENA_SHIFT                        0  /* FLL1_ENA */
2413 #define WM8994_FLL1_ENA_WIDTH                        1  /* FLL1_ENA */
2414 
2415 /*
2416  * R545 (0x221) - FLL1 Control (2)
2417  */
2418 #define WM8994_FLL1_OUTDIV_MASK                 0x3F00  /* FLL1_OUTDIV - [13:8] */
2419 #define WM8994_FLL1_OUTDIV_SHIFT                     8  /* FLL1_OUTDIV - [13:8] */
2420 #define WM8994_FLL1_OUTDIV_WIDTH                     6  /* FLL1_OUTDIV - [13:8] */
2421 #define WM8994_FLL1_CTRL_RATE_MASK              0x0070  /* FLL1_CTRL_RATE - [6:4] */
2422 #define WM8994_FLL1_CTRL_RATE_SHIFT                  4  /* FLL1_CTRL_RATE - [6:4] */
2423 #define WM8994_FLL1_CTRL_RATE_WIDTH                  3  /* FLL1_CTRL_RATE - [6:4] */
2424 #define WM8994_FLL1_FRATIO_MASK                 0x0007  /* FLL1_FRATIO - [2:0] */
2425 #define WM8994_FLL1_FRATIO_SHIFT                     0  /* FLL1_FRATIO - [2:0] */
2426 #define WM8994_FLL1_FRATIO_WIDTH                     3  /* FLL1_FRATIO - [2:0] */
2427 
2428 /*
2429  * R546 (0x222) - FLL1 Control (3)
2430  */
2431 #define WM8994_FLL1_K_MASK                      0xFFFF  /* FLL1_K - [15:0] */
2432 #define WM8994_FLL1_K_SHIFT                          0  /* FLL1_K - [15:0] */
2433 #define WM8994_FLL1_K_WIDTH                         16  /* FLL1_K - [15:0] */
2434 
2435 /*
2436  * R547 (0x223) - FLL1 Control (4)
2437  */
2438 #define WM8994_FLL1_N_MASK                      0x7FE0  /* FLL1_N - [14:5] */
2439 #define WM8994_FLL1_N_SHIFT                          5  /* FLL1_N - [14:5] */
2440 #define WM8994_FLL1_N_WIDTH                         10  /* FLL1_N - [14:5] */
2441 #define WM8994_FLL1_LOOP_GAIN_MASK              0x000F  /* FLL1_LOOP_GAIN - [3:0] */
2442 #define WM8994_FLL1_LOOP_GAIN_SHIFT                  0  /* FLL1_LOOP_GAIN - [3:0] */
2443 #define WM8994_FLL1_LOOP_GAIN_WIDTH                  4  /* FLL1_LOOP_GAIN - [3:0] */
2444 
2445 /*
2446  * R548 (0x224) - FLL1 Control (5)
2447  */
2448 #define WM8958_FLL1_BYP                         0x8000  /* FLL1_BYP */
2449 #define WM8958_FLL1_BYP_MASK                    0x8000  /* FLL1_BYP */
2450 #define WM8958_FLL1_BYP_SHIFT                       15  /* FLL1_BYP */
2451 #define WM8958_FLL1_BYP_WIDTH                        1  /* FLL1_BYP */
2452 #define WM8994_FLL1_FRC_NCO_VAL_MASK            0x1F80  /* FLL1_FRC_NCO_VAL - [12:7] */
2453 #define WM8994_FLL1_FRC_NCO_VAL_SHIFT                7  /* FLL1_FRC_NCO_VAL - [12:7] */
2454 #define WM8994_FLL1_FRC_NCO_VAL_WIDTH                6  /* FLL1_FRC_NCO_VAL - [12:7] */
2455 #define WM8994_FLL1_FRC_NCO                     0x0040  /* FLL1_FRC_NCO */
2456 #define WM8994_FLL1_FRC_NCO_MASK                0x0040  /* FLL1_FRC_NCO */
2457 #define WM8994_FLL1_FRC_NCO_SHIFT                    6  /* FLL1_FRC_NCO */
2458 #define WM8994_FLL1_FRC_NCO_WIDTH                    1  /* FLL1_FRC_NCO */
2459 #define WM8994_FLL1_REFCLK_DIV_MASK             0x0018  /* FLL1_REFCLK_DIV - [4:3] */
2460 #define WM8994_FLL1_REFCLK_DIV_SHIFT                 3  /* FLL1_REFCLK_DIV - [4:3] */
2461 #define WM8994_FLL1_REFCLK_DIV_WIDTH                 2  /* FLL1_REFCLK_DIV - [4:3] */
2462 #define WM8994_FLL1_REFCLK_SRC_MASK             0x0003  /* FLL1_REFCLK_SRC - [1:0] */
2463 #define WM8994_FLL1_REFCLK_SRC_SHIFT                 0  /* FLL1_REFCLK_SRC - [1:0] */
2464 #define WM8994_FLL1_REFCLK_SRC_WIDTH                 2  /* FLL1_REFCLK_SRC - [1:0] */
2465 
2466 /*
2467  * R550 (0x226) - FLL1 EFS 1
2468  */
2469 #define WM8958_FLL1_LAMBDA_MASK                 0xFFFF  /* FLL1_LAMBDA - [15:0] */
2470 #define WM8958_FLL1_LAMBDA_SHIFT                     0  /* FLL1_LAMBDA - [15:0] */
2471 #define WM8958_FLL1_LAMBDA_WIDTH                    16  /* FLL1_LAMBDA - [15:0] */
2472 
2473 /*
2474  * R551 (0x227) - FLL1 EFS 2
2475  */
2476 #define WM8958_FLL1_LFSR_SEL_MASK               0x0006  /* FLL1_LFSR_SEL - [2:1] */
2477 #define WM8958_FLL1_LFSR_SEL_SHIFT                   1  /* FLL1_LFSR_SEL - [2:1] */
2478 #define WM8958_FLL1_LFSR_SEL_WIDTH                   2  /* FLL1_LFSR_SEL - [2:1] */
2479 #define WM8958_FLL1_EFS_ENA                     0x0001  /* FLL1_EFS_ENA */
2480 #define WM8958_FLL1_EFS_ENA_MASK                0x0001  /* FLL1_EFS_ENA */
2481 #define WM8958_FLL1_EFS_ENA_SHIFT                    0  /* FLL1_EFS_ENA */
2482 #define WM8958_FLL1_EFS_ENA_WIDTH                    1  /* FLL1_EFS_ENA */
2483 
2484 /*
2485  * R576 (0x240) - FLL2 Control (1)
2486  */
2487 #define WM8994_FLL2_FRAC                        0x0004  /* FLL2_FRAC */
2488 #define WM8994_FLL2_FRAC_MASK                   0x0004  /* FLL2_FRAC */
2489 #define WM8994_FLL2_FRAC_SHIFT                       2  /* FLL2_FRAC */
2490 #define WM8994_FLL2_FRAC_WIDTH                       1  /* FLL2_FRAC */
2491 #define WM8994_FLL2_OSC_ENA                     0x0002  /* FLL2_OSC_ENA */
2492 #define WM8994_FLL2_OSC_ENA_MASK                0x0002  /* FLL2_OSC_ENA */
2493 #define WM8994_FLL2_OSC_ENA_SHIFT                    1  /* FLL2_OSC_ENA */
2494 #define WM8994_FLL2_OSC_ENA_WIDTH                    1  /* FLL2_OSC_ENA */
2495 #define WM8994_FLL2_ENA                         0x0001  /* FLL2_ENA */
2496 #define WM8994_FLL2_ENA_MASK                    0x0001  /* FLL2_ENA */
2497 #define WM8994_FLL2_ENA_SHIFT                        0  /* FLL2_ENA */
2498 #define WM8994_FLL2_ENA_WIDTH                        1  /* FLL2_ENA */
2499 
2500 /*
2501  * R577 (0x241) - FLL2 Control (2)
2502  */
2503 #define WM8994_FLL2_OUTDIV_MASK                 0x3F00  /* FLL2_OUTDIV - [13:8] */
2504 #define WM8994_FLL2_OUTDIV_SHIFT                     8  /* FLL2_OUTDIV - [13:8] */
2505 #define WM8994_FLL2_OUTDIV_WIDTH                     6  /* FLL2_OUTDIV - [13:8] */
2506 #define WM8994_FLL2_CTRL_RATE_MASK              0x0070  /* FLL2_CTRL_RATE - [6:4] */
2507 #define WM8994_FLL2_CTRL_RATE_SHIFT                  4  /* FLL2_CTRL_RATE - [6:4] */
2508 #define WM8994_FLL2_CTRL_RATE_WIDTH                  3  /* FLL2_CTRL_RATE - [6:4] */
2509 #define WM8994_FLL2_FRATIO_MASK                 0x0007  /* FLL2_FRATIO - [2:0] */
2510 #define WM8994_FLL2_FRATIO_SHIFT                     0  /* FLL2_FRATIO - [2:0] */
2511 #define WM8994_FLL2_FRATIO_WIDTH                     3  /* FLL2_FRATIO - [2:0] */
2512 
2513 /*
2514  * R578 (0x242) - FLL2 Control (3)
2515  */
2516 #define WM8994_FLL2_K_MASK                      0xFFFF  /* FLL2_K - [15:0] */
2517 #define WM8994_FLL2_K_SHIFT                          0  /* FLL2_K - [15:0] */
2518 #define WM8994_FLL2_K_WIDTH                         16  /* FLL2_K - [15:0] */
2519 
2520 /*
2521  * R579 (0x243) - FLL2 Control (4)
2522  */
2523 #define WM8994_FLL2_N_MASK                      0x7FE0  /* FLL2_N - [14:5] */
2524 #define WM8994_FLL2_N_SHIFT                          5  /* FLL2_N - [14:5] */
2525 #define WM8994_FLL2_N_WIDTH                         10  /* FLL2_N - [14:5] */
2526 #define WM8994_FLL2_LOOP_GAIN_MASK              0x000F  /* FLL2_LOOP_GAIN - [3:0] */
2527 #define WM8994_FLL2_LOOP_GAIN_SHIFT                  0  /* FLL2_LOOP_GAIN - [3:0] */
2528 #define WM8994_FLL2_LOOP_GAIN_WIDTH                  4  /* FLL2_LOOP_GAIN - [3:0] */
2529 
2530 /*
2531  * R580 (0x244) - FLL2 Control (5)
2532  */
2533 #define WM8958_FLL2_BYP                         0x8000  /* FLL2_BYP */
2534 #define WM8958_FLL2_BYP_MASK                    0x8000  /* FLL2_BYP */
2535 #define WM8958_FLL2_BYP_SHIFT                       15  /* FLL2_BYP */
2536 #define WM8958_FLL2_BYP_WIDTH                        1  /* FLL2_BYP */
2537 #define WM8994_FLL2_FRC_NCO_VAL_MASK            0x1F80  /* FLL2_FRC_NCO_VAL - [12:7] */
2538 #define WM8994_FLL2_FRC_NCO_VAL_SHIFT                7  /* FLL2_FRC_NCO_VAL - [12:7] */
2539 #define WM8994_FLL2_FRC_NCO_VAL_WIDTH                6  /* FLL2_FRC_NCO_VAL - [12:7] */
2540 #define WM8994_FLL2_FRC_NCO                     0x0040  /* FLL2_FRC_NCO */
2541 #define WM8994_FLL2_FRC_NCO_MASK                0x0040  /* FLL2_FRC_NCO */
2542 #define WM8994_FLL2_FRC_NCO_SHIFT                    6  /* FLL2_FRC_NCO */
2543 #define WM8994_FLL2_FRC_NCO_WIDTH                    1  /* FLL2_FRC_NCO */
2544 #define WM8994_FLL2_REFCLK_DIV_MASK             0x0018  /* FLL2_REFCLK_DIV - [4:3] */
2545 #define WM8994_FLL2_REFCLK_DIV_SHIFT                 3  /* FLL2_REFCLK_DIV - [4:3] */
2546 #define WM8994_FLL2_REFCLK_DIV_WIDTH                 2  /* FLL2_REFCLK_DIV - [4:3] */
2547 #define WM8994_FLL2_REFCLK_SRC_MASK             0x0003  /* FLL2_REFCLK_SRC - [1:0] */
2548 #define WM8994_FLL2_REFCLK_SRC_SHIFT                 0  /* FLL2_REFCLK_SRC - [1:0] */
2549 #define WM8994_FLL2_REFCLK_SRC_WIDTH                 2  /* FLL2_REFCLK_SRC - [1:0] */
2550 
2551 /*
2552  * R582 (0x246) - FLL2 EFS 1
2553  */
2554 #define WM8958_FLL2_LAMBDA_MASK                 0xFFFF  /* FLL2_LAMBDA - [15:0] */
2555 #define WM8958_FLL2_LAMBDA_SHIFT                     0  /* FLL2_LAMBDA - [15:0] */
2556 #define WM8958_FLL2_LAMBDA_WIDTH                    16  /* FLL2_LAMBDA - [15:0] */
2557 
2558 /*
2559  * R583 (0x247) - FLL2 EFS 2
2560  */
2561 #define WM8958_FLL2_LFSR_SEL_MASK               0x0006  /* FLL2_LFSR_SEL - [2:1] */
2562 #define WM8958_FLL2_LFSR_SEL_SHIFT                   1  /* FLL2_LFSR_SEL - [2:1] */
2563 #define WM8958_FLL2_LFSR_SEL_WIDTH                   2  /* FLL2_LFSR_SEL - [2:1] */
2564 #define WM8958_FLL2_EFS_ENA                     0x0001  /* FLL2_EFS_ENA */
2565 #define WM8958_FLL2_EFS_ENA_MASK                0x0001  /* FLL2_EFS_ENA */
2566 #define WM8958_FLL2_EFS_ENA_SHIFT                    0  /* FLL2_EFS_ENA */
2567 #define WM8958_FLL2_EFS_ENA_WIDTH                    1  /* FLL2_EFS_ENA */
2568 
2569 /*
2570  * R768 (0x300) - AIF1 Control (1)
2571  */
2572 #define WM8994_AIF1ADCL_SRC                     0x8000  /* AIF1ADCL_SRC */
2573 #define WM8994_AIF1ADCL_SRC_MASK                0x8000  /* AIF1ADCL_SRC */
2574 #define WM8994_AIF1ADCL_SRC_SHIFT                   15  /* AIF1ADCL_SRC */
2575 #define WM8994_AIF1ADCL_SRC_WIDTH                    1  /* AIF1ADCL_SRC */
2576 #define WM8994_AIF1ADCR_SRC                     0x4000  /* AIF1ADCR_SRC */
2577 #define WM8994_AIF1ADCR_SRC_MASK                0x4000  /* AIF1ADCR_SRC */
2578 #define WM8994_AIF1ADCR_SRC_SHIFT                   14  /* AIF1ADCR_SRC */
2579 #define WM8994_AIF1ADCR_SRC_WIDTH                    1  /* AIF1ADCR_SRC */
2580 #define WM8994_AIF1ADC_TDM                      0x2000  /* AIF1ADC_TDM */
2581 #define WM8994_AIF1ADC_TDM_MASK                 0x2000  /* AIF1ADC_TDM */
2582 #define WM8994_AIF1ADC_TDM_SHIFT                    13  /* AIF1ADC_TDM */
2583 #define WM8994_AIF1ADC_TDM_WIDTH                     1  /* AIF1ADC_TDM */
2584 #define WM8994_AIF1_BCLK_INV                    0x0100  /* AIF1_BCLK_INV */
2585 #define WM8994_AIF1_BCLK_INV_MASK               0x0100  /* AIF1_BCLK_INV */
2586 #define WM8994_AIF1_BCLK_INV_SHIFT                   8  /* AIF1_BCLK_INV */
2587 #define WM8994_AIF1_BCLK_INV_WIDTH                   1  /* AIF1_BCLK_INV */
2588 #define WM8994_AIF1_LRCLK_INV                   0x0080  /* AIF1_LRCLK_INV */
2589 #define WM8994_AIF1_LRCLK_INV_MASK              0x0080  /* AIF1_LRCLK_INV */
2590 #define WM8994_AIF1_LRCLK_INV_SHIFT                  7  /* AIF1_LRCLK_INV */
2591 #define WM8994_AIF1_LRCLK_INV_WIDTH                  1  /* AIF1_LRCLK_INV */
2592 #define WM8994_AIF1_WL_MASK                     0x0060  /* AIF1_WL - [6:5] */
2593 #define WM8994_AIF1_WL_SHIFT                         5  /* AIF1_WL - [6:5] */
2594 #define WM8994_AIF1_WL_WIDTH                         2  /* AIF1_WL - [6:5] */
2595 #define WM8994_AIF1_FMT_MASK                    0x0018  /* AIF1_FMT - [4:3] */
2596 #define WM8994_AIF1_FMT_SHIFT                        3  /* AIF1_FMT - [4:3] */
2597 #define WM8994_AIF1_FMT_WIDTH                        2  /* AIF1_FMT - [4:3] */
2598 
2599 /*
2600  * R769 (0x301) - AIF1 Control (2)
2601  */
2602 #define WM8994_AIF1DACL_SRC                     0x8000  /* AIF1DACL_SRC */
2603 #define WM8994_AIF1DACL_SRC_MASK                0x8000  /* AIF1DACL_SRC */
2604 #define WM8994_AIF1DACL_SRC_SHIFT                   15  /* AIF1DACL_SRC */
2605 #define WM8994_AIF1DACL_SRC_WIDTH                    1  /* AIF1DACL_SRC */
2606 #define WM8994_AIF1DACR_SRC                     0x4000  /* AIF1DACR_SRC */
2607 #define WM8994_AIF1DACR_SRC_MASK                0x4000  /* AIF1DACR_SRC */
2608 #define WM8994_AIF1DACR_SRC_SHIFT                   14  /* AIF1DACR_SRC */
2609 #define WM8994_AIF1DACR_SRC_WIDTH                    1  /* AIF1DACR_SRC */
2610 #define WM8994_AIF1DAC_BOOST_MASK               0x0C00  /* AIF1DAC_BOOST - [11:10] */
2611 #define WM8994_AIF1DAC_BOOST_SHIFT                  10  /* AIF1DAC_BOOST - [11:10] */
2612 #define WM8994_AIF1DAC_BOOST_WIDTH                   2  /* AIF1DAC_BOOST - [11:10] */
2613 #define WM8994_AIF1_MONO                        0x0100  /* AIF1_MONO */
2614 #define WM8994_AIF1_MONO_MASK                   0x0100  /* AIF1_MONO */
2615 #define WM8994_AIF1_MONO_SHIFT                       8  /* AIF1_MONO */
2616 #define WM8994_AIF1_MONO_WIDTH                       1  /* AIF1_MONO */
2617 #define WM8994_AIF1DAC_COMP                     0x0010  /* AIF1DAC_COMP */
2618 #define WM8994_AIF1DAC_COMP_MASK                0x0010  /* AIF1DAC_COMP */
2619 #define WM8994_AIF1DAC_COMP_SHIFT                    4  /* AIF1DAC_COMP */
2620 #define WM8994_AIF1DAC_COMP_WIDTH                    1  /* AIF1DAC_COMP */
2621 #define WM8994_AIF1DAC_COMPMODE                 0x0008  /* AIF1DAC_COMPMODE */
2622 #define WM8994_AIF1DAC_COMPMODE_MASK            0x0008  /* AIF1DAC_COMPMODE */
2623 #define WM8994_AIF1DAC_COMPMODE_SHIFT                3  /* AIF1DAC_COMPMODE */
2624 #define WM8994_AIF1DAC_COMPMODE_WIDTH                1  /* AIF1DAC_COMPMODE */
2625 #define WM8994_AIF1ADC_COMP                     0x0004  /* AIF1ADC_COMP */
2626 #define WM8994_AIF1ADC_COMP_MASK                0x0004  /* AIF1ADC_COMP */
2627 #define WM8994_AIF1ADC_COMP_SHIFT                    2  /* AIF1ADC_COMP */
2628 #define WM8994_AIF1ADC_COMP_WIDTH                    1  /* AIF1ADC_COMP */
2629 #define WM8994_AIF1ADC_COMPMODE                 0x0002  /* AIF1ADC_COMPMODE */
2630 #define WM8994_AIF1ADC_COMPMODE_MASK            0x0002  /* AIF1ADC_COMPMODE */
2631 #define WM8994_AIF1ADC_COMPMODE_SHIFT                1  /* AIF1ADC_COMPMODE */
2632 #define WM8994_AIF1ADC_COMPMODE_WIDTH                1  /* AIF1ADC_COMPMODE */
2633 #define WM8994_AIF1_LOOPBACK                    0x0001  /* AIF1_LOOPBACK */
2634 #define WM8994_AIF1_LOOPBACK_MASK               0x0001  /* AIF1_LOOPBACK */
2635 #define WM8994_AIF1_LOOPBACK_SHIFT                   0  /* AIF1_LOOPBACK */
2636 #define WM8994_AIF1_LOOPBACK_WIDTH                   1  /* AIF1_LOOPBACK */
2637 
2638 /*
2639  * R770 (0x302) - AIF1 Master/Slave
2640  */
2641 #define WM8994_AIF1_TRI                         0x8000  /* AIF1_TRI */
2642 #define WM8994_AIF1_TRI_MASK                    0x8000  /* AIF1_TRI */
2643 #define WM8994_AIF1_TRI_SHIFT                       15  /* AIF1_TRI */
2644 #define WM8994_AIF1_TRI_WIDTH                        1  /* AIF1_TRI */
2645 #define WM8994_AIF1_MSTR                        0x4000  /* AIF1_MSTR */
2646 #define WM8994_AIF1_MSTR_MASK                   0x4000  /* AIF1_MSTR */
2647 #define WM8994_AIF1_MSTR_SHIFT                      14  /* AIF1_MSTR */
2648 #define WM8994_AIF1_MSTR_WIDTH                       1  /* AIF1_MSTR */
2649 #define WM8994_AIF1_CLK_FRC                     0x2000  /* AIF1_CLK_FRC */
2650 #define WM8994_AIF1_CLK_FRC_MASK                0x2000  /* AIF1_CLK_FRC */
2651 #define WM8994_AIF1_CLK_FRC_SHIFT                   13  /* AIF1_CLK_FRC */
2652 #define WM8994_AIF1_CLK_FRC_WIDTH                    1  /* AIF1_CLK_FRC */
2653 #define WM8994_AIF1_LRCLK_FRC                   0x1000  /* AIF1_LRCLK_FRC */
2654 #define WM8994_AIF1_LRCLK_FRC_MASK              0x1000  /* AIF1_LRCLK_FRC */
2655 #define WM8994_AIF1_LRCLK_FRC_SHIFT                 12  /* AIF1_LRCLK_FRC */
2656 #define WM8994_AIF1_LRCLK_FRC_WIDTH                  1  /* AIF1_LRCLK_FRC */
2657 
2658 /*
2659  * R771 (0x303) - AIF1 BCLK
2660  */
2661 #define WM8994_AIF1_BCLK_DIV_MASK               0x01F0  /* AIF1_BCLK_DIV - [8:4] */
2662 #define WM8994_AIF1_BCLK_DIV_SHIFT                   4  /* AIF1_BCLK_DIV - [8:4] */
2663 #define WM8994_AIF1_BCLK_DIV_WIDTH                   5  /* AIF1_BCLK_DIV - [8:4] */
2664 
2665 /*
2666  * R772 (0x304) - AIF1ADC LRCLK
2667  */
2668 #define WM8994_AIF1ADC_LRCLK_DIR                0x0800  /* AIF1ADC_LRCLK_DIR */
2669 #define WM8994_AIF1ADC_LRCLK_DIR_MASK           0x0800  /* AIF1ADC_LRCLK_DIR */
2670 #define WM8994_AIF1ADC_LRCLK_DIR_SHIFT              11  /* AIF1ADC_LRCLK_DIR */
2671 #define WM8994_AIF1ADC_LRCLK_DIR_WIDTH               1  /* AIF1ADC_LRCLK_DIR */
2672 #define WM8994_AIF1ADC_RATE_MASK                0x07FF  /* AIF1ADC_RATE - [10:0] */
2673 #define WM8994_AIF1ADC_RATE_SHIFT                    0  /* AIF1ADC_RATE - [10:0] */
2674 #define WM8994_AIF1ADC_RATE_WIDTH                   11  /* AIF1ADC_RATE - [10:0] */
2675 
2676 /*
2677  * R773 (0x305) - AIF1DAC LRCLK
2678  */
2679 #define WM8994_AIF1DAC_LRCLK_DIR                0x0800  /* AIF1DAC_LRCLK_DIR */
2680 #define WM8994_AIF1DAC_LRCLK_DIR_MASK           0x0800  /* AIF1DAC_LRCLK_DIR */
2681 #define WM8994_AIF1DAC_LRCLK_DIR_SHIFT              11  /* AIF1DAC_LRCLK_DIR */
2682 #define WM8994_AIF1DAC_LRCLK_DIR_WIDTH               1  /* AIF1DAC_LRCLK_DIR */
2683 #define WM8994_AIF1DAC_RATE_MASK                0x07FF  /* AIF1DAC_RATE - [10:0] */
2684 #define WM8994_AIF1DAC_RATE_SHIFT                    0  /* AIF1DAC_RATE - [10:0] */
2685 #define WM8994_AIF1DAC_RATE_WIDTH                   11  /* AIF1DAC_RATE - [10:0] */
2686 
2687 /*
2688  * R774 (0x306) - AIF1DAC Data
2689  */
2690 #define WM8994_AIF1DACL_DAT_INV                 0x0002  /* AIF1DACL_DAT_INV */
2691 #define WM8994_AIF1DACL_DAT_INV_MASK            0x0002  /* AIF1DACL_DAT_INV */
2692 #define WM8994_AIF1DACL_DAT_INV_SHIFT                1  /* AIF1DACL_DAT_INV */
2693 #define WM8994_AIF1DACL_DAT_INV_WIDTH                1  /* AIF1DACL_DAT_INV */
2694 #define WM8994_AIF1DACR_DAT_INV                 0x0001  /* AIF1DACR_DAT_INV */
2695 #define WM8994_AIF1DACR_DAT_INV_MASK            0x0001  /* AIF1DACR_DAT_INV */
2696 #define WM8994_AIF1DACR_DAT_INV_SHIFT                0  /* AIF1DACR_DAT_INV */
2697 #define WM8994_AIF1DACR_DAT_INV_WIDTH                1  /* AIF1DACR_DAT_INV */
2698 
2699 /*
2700  * R775 (0x307) - AIF1ADC Data
2701  */
2702 #define WM8994_AIF1ADCL_DAT_INV                 0x0002  /* AIF1ADCL_DAT_INV */
2703 #define WM8994_AIF1ADCL_DAT_INV_MASK            0x0002  /* AIF1ADCL_DAT_INV */
2704 #define WM8994_AIF1ADCL_DAT_INV_SHIFT                1  /* AIF1ADCL_DAT_INV */
2705 #define WM8994_AIF1ADCL_DAT_INV_WIDTH                1  /* AIF1ADCL_DAT_INV */
2706 #define WM8994_AIF1ADCR_DAT_INV                 0x0001  /* AIF1ADCR_DAT_INV */
2707 #define WM8994_AIF1ADCR_DAT_INV_MASK            0x0001  /* AIF1ADCR_DAT_INV */
2708 #define WM8994_AIF1ADCR_DAT_INV_SHIFT                0  /* AIF1ADCR_DAT_INV */
2709 #define WM8994_AIF1ADCR_DAT_INV_WIDTH                1  /* AIF1ADCR_DAT_INV */
2710 
2711 /*
2712  * R784 (0x310) - AIF2 Control (1)
2713  */
2714 #define WM8994_AIF2ADCL_SRC                     0x8000  /* AIF2ADCL_SRC */
2715 #define WM8994_AIF2ADCL_SRC_MASK                0x8000  /* AIF2ADCL_SRC */
2716 #define WM8994_AIF2ADCL_SRC_SHIFT                   15  /* AIF2ADCL_SRC */
2717 #define WM8994_AIF2ADCL_SRC_WIDTH                    1  /* AIF2ADCL_SRC */
2718 #define WM8994_AIF2ADCR_SRC                     0x4000  /* AIF2ADCR_SRC */
2719 #define WM8994_AIF2ADCR_SRC_MASK                0x4000  /* AIF2ADCR_SRC */
2720 #define WM8994_AIF2ADCR_SRC_SHIFT                   14  /* AIF2ADCR_SRC */
2721 #define WM8994_AIF2ADCR_SRC_WIDTH                    1  /* AIF2ADCR_SRC */
2722 #define WM8994_AIF2ADC_TDM                      0x2000  /* AIF2ADC_TDM */
2723 #define WM8994_AIF2ADC_TDM_MASK                 0x2000  /* AIF2ADC_TDM */
2724 #define WM8994_AIF2ADC_TDM_SHIFT                    13  /* AIF2ADC_TDM */
2725 #define WM8994_AIF2ADC_TDM_WIDTH                     1  /* AIF2ADC_TDM */
2726 #define WM8994_AIF2ADC_TDM_CHAN                 0x1000  /* AIF2ADC_TDM_CHAN */
2727 #define WM8994_AIF2ADC_TDM_CHAN_MASK            0x1000  /* AIF2ADC_TDM_CHAN */
2728 #define WM8994_AIF2ADC_TDM_CHAN_SHIFT               12  /* AIF2ADC_TDM_CHAN */
2729 #define WM8994_AIF2ADC_TDM_CHAN_WIDTH                1  /* AIF2ADC_TDM_CHAN */
2730 #define WM8994_AIF2_BCLK_INV                    0x0100  /* AIF2_BCLK_INV */
2731 #define WM8994_AIF2_BCLK_INV_MASK               0x0100  /* AIF2_BCLK_INV */
2732 #define WM8994_AIF2_BCLK_INV_SHIFT                   8  /* AIF2_BCLK_INV */
2733 #define WM8994_AIF2_BCLK_INV_WIDTH                   1  /* AIF2_BCLK_INV */
2734 #define WM8994_AIF2_LRCLK_INV                   0x0080  /* AIF2_LRCLK_INV */
2735 #define WM8994_AIF2_LRCLK_INV_MASK              0x0080  /* AIF2_LRCLK_INV */
2736 #define WM8994_AIF2_LRCLK_INV_SHIFT                  7  /* AIF2_LRCLK_INV */
2737 #define WM8994_AIF2_LRCLK_INV_WIDTH                  1  /* AIF2_LRCLK_INV */
2738 #define WM8994_AIF2_WL_MASK                     0x0060  /* AIF2_WL - [6:5] */
2739 #define WM8994_AIF2_WL_SHIFT                         5  /* AIF2_WL - [6:5] */
2740 #define WM8994_AIF2_WL_WIDTH                         2  /* AIF2_WL - [6:5] */
2741 #define WM8994_AIF2_FMT_MASK                    0x0018  /* AIF2_FMT - [4:3] */
2742 #define WM8994_AIF2_FMT_SHIFT                        3  /* AIF2_FMT - [4:3] */
2743 #define WM8994_AIF2_FMT_WIDTH                        2  /* AIF2_FMT - [4:3] */
2744 
2745 /*
2746  * R785 (0x311) - AIF2 Control (2)
2747  */
2748 #define WM8994_AIF2DACL_SRC                     0x8000  /* AIF2DACL_SRC */
2749 #define WM8994_AIF2DACL_SRC_MASK                0x8000  /* AIF2DACL_SRC */
2750 #define WM8994_AIF2DACL_SRC_SHIFT                   15  /* AIF2DACL_SRC */
2751 #define WM8994_AIF2DACL_SRC_WIDTH                    1  /* AIF2DACL_SRC */
2752 #define WM8994_AIF2DACR_SRC                     0x4000  /* AIF2DACR_SRC */
2753 #define WM8994_AIF2DACR_SRC_MASK                0x4000  /* AIF2DACR_SRC */
2754 #define WM8994_AIF2DACR_SRC_SHIFT                   14  /* AIF2DACR_SRC */
2755 #define WM8994_AIF2DACR_SRC_WIDTH                    1  /* AIF2DACR_SRC */
2756 #define WM8994_AIF2DAC_TDM                      0x2000  /* AIF2DAC_TDM */
2757 #define WM8994_AIF2DAC_TDM_MASK                 0x2000  /* AIF2DAC_TDM */
2758 #define WM8994_AIF2DAC_TDM_SHIFT                    13  /* AIF2DAC_TDM */
2759 #define WM8994_AIF2DAC_TDM_WIDTH                     1  /* AIF2DAC_TDM */
2760 #define WM8994_AIF2DAC_TDM_CHAN                 0x1000  /* AIF2DAC_TDM_CHAN */
2761 #define WM8994_AIF2DAC_TDM_CHAN_MASK            0x1000  /* AIF2DAC_TDM_CHAN */
2762 #define WM8994_AIF2DAC_TDM_CHAN_SHIFT               12  /* AIF2DAC_TDM_CHAN */
2763 #define WM8994_AIF2DAC_TDM_CHAN_WIDTH                1  /* AIF2DAC_TDM_CHAN */
2764 #define WM8994_AIF2DAC_BOOST_MASK               0x0C00  /* AIF2DAC_BOOST - [11:10] */
2765 #define WM8994_AIF2DAC_BOOST_SHIFT                  10  /* AIF2DAC_BOOST - [11:10] */
2766 #define WM8994_AIF2DAC_BOOST_WIDTH                   2  /* AIF2DAC_BOOST - [11:10] */
2767 #define WM8994_AIF2_MONO                        0x0100  /* AIF2_MONO */
2768 #define WM8994_AIF2_MONO_MASK                   0x0100  /* AIF2_MONO */
2769 #define WM8994_AIF2_MONO_SHIFT                       8  /* AIF2_MONO */
2770 #define WM8994_AIF2_MONO_WIDTH                       1  /* AIF2_MONO */
2771 #define WM8994_AIF2DAC_COMP                     0x0010  /* AIF2DAC_COMP */
2772 #define WM8994_AIF2DAC_COMP_MASK                0x0010  /* AIF2DAC_COMP */
2773 #define WM8994_AIF2DAC_COMP_SHIFT                    4  /* AIF2DAC_COMP */
2774 #define WM8994_AIF2DAC_COMP_WIDTH                    1  /* AIF2DAC_COMP */
2775 #define WM8994_AIF2DAC_COMPMODE                 0x0008  /* AIF2DAC_COMPMODE */
2776 #define WM8994_AIF2DAC_COMPMODE_MASK            0x0008  /* AIF2DAC_COMPMODE */
2777 #define WM8994_AIF2DAC_COMPMODE_SHIFT                3  /* AIF2DAC_COMPMODE */
2778 #define WM8994_AIF2DAC_COMPMODE_WIDTH                1  /* AIF2DAC_COMPMODE */
2779 #define WM8994_AIF2ADC_COMP                     0x0004  /* AIF2ADC_COMP */
2780 #define WM8994_AIF2ADC_COMP_MASK                0x0004  /* AIF2ADC_COMP */
2781 #define WM8994_AIF2ADC_COMP_SHIFT                    2  /* AIF2ADC_COMP */
2782 #define WM8994_AIF2ADC_COMP_WIDTH                    1  /* AIF2ADC_COMP */
2783 #define WM8994_AIF2ADC_COMPMODE                 0x0002  /* AIF2ADC_COMPMODE */
2784 #define WM8994_AIF2ADC_COMPMODE_MASK            0x0002  /* AIF2ADC_COMPMODE */
2785 #define WM8994_AIF2ADC_COMPMODE_SHIFT                1  /* AIF2ADC_COMPMODE */
2786 #define WM8994_AIF2ADC_COMPMODE_WIDTH                1  /* AIF2ADC_COMPMODE */
2787 #define WM8994_AIF2_LOOPBACK                    0x0001  /* AIF2_LOOPBACK */
2788 #define WM8994_AIF2_LOOPBACK_MASK               0x0001  /* AIF2_LOOPBACK */
2789 #define WM8994_AIF2_LOOPBACK_SHIFT                   0  /* AIF2_LOOPBACK */
2790 #define WM8994_AIF2_LOOPBACK_WIDTH                   1  /* AIF2_LOOPBACK */
2791 
2792 /*
2793  * R786 (0x312) - AIF2 Master/Slave
2794  */
2795 #define WM8994_AIF2_TRI                         0x8000  /* AIF2_TRI */
2796 #define WM8994_AIF2_TRI_MASK                    0x8000  /* AIF2_TRI */
2797 #define WM8994_AIF2_TRI_SHIFT                       15  /* AIF2_TRI */
2798 #define WM8994_AIF2_TRI_WIDTH                        1  /* AIF2_TRI */
2799 #define WM8994_AIF2_MSTR                        0x4000  /* AIF2_MSTR */
2800 #define WM8994_AIF2_MSTR_MASK                   0x4000  /* AIF2_MSTR */
2801 #define WM8994_AIF2_MSTR_SHIFT                      14  /* AIF2_MSTR */
2802 #define WM8994_AIF2_MSTR_WIDTH                       1  /* AIF2_MSTR */
2803 #define WM8994_AIF2_CLK_FRC                     0x2000  /* AIF2_CLK_FRC */
2804 #define WM8994_AIF2_CLK_FRC_MASK                0x2000  /* AIF2_CLK_FRC */
2805 #define WM8994_AIF2_CLK_FRC_SHIFT                   13  /* AIF2_CLK_FRC */
2806 #define WM8994_AIF2_CLK_FRC_WIDTH                    1  /* AIF2_CLK_FRC */
2807 #define WM8994_AIF2_LRCLK_FRC                   0x1000  /* AIF2_LRCLK_FRC */
2808 #define WM8994_AIF2_LRCLK_FRC_MASK              0x1000  /* AIF2_LRCLK_FRC */
2809 #define WM8994_AIF2_LRCLK_FRC_SHIFT                 12  /* AIF2_LRCLK_FRC */
2810 #define WM8994_AIF2_LRCLK_FRC_WIDTH                  1  /* AIF2_LRCLK_FRC */
2811 
2812 /*
2813  * R787 (0x313) - AIF2 BCLK
2814  */
2815 #define WM8994_AIF2_BCLK_DIV_MASK               0x01F0  /* AIF2_BCLK_DIV - [8:4] */
2816 #define WM8994_AIF2_BCLK_DIV_SHIFT                   4  /* AIF2_BCLK_DIV - [8:4] */
2817 #define WM8994_AIF2_BCLK_DIV_WIDTH                   5  /* AIF2_BCLK_DIV - [8:4] */
2818 
2819 /*
2820  * R788 (0x314) - AIF2ADC LRCLK
2821  */
2822 #define WM8994_AIF2ADC_LRCLK_DIR                0x0800  /* AIF2ADC_LRCLK_DIR */
2823 #define WM8994_AIF2ADC_LRCLK_DIR_MASK           0x0800  /* AIF2ADC_LRCLK_DIR */
2824 #define WM8994_AIF2ADC_LRCLK_DIR_SHIFT              11  /* AIF2ADC_LRCLK_DIR */
2825 #define WM8994_AIF2ADC_LRCLK_DIR_WIDTH               1  /* AIF2ADC_LRCLK_DIR */
2826 #define WM8994_AIF2ADC_RATE_MASK                0x07FF  /* AIF2ADC_RATE - [10:0] */
2827 #define WM8994_AIF2ADC_RATE_SHIFT                    0  /* AIF2ADC_RATE - [10:0] */
2828 #define WM8994_AIF2ADC_RATE_WIDTH                   11  /* AIF2ADC_RATE - [10:0] */
2829 
2830 /*
2831  * R789 (0x315) - AIF2DAC LRCLK
2832  */
2833 #define WM8994_AIF2DAC_LRCLK_DIR                0x0800  /* AIF2DAC_LRCLK_DIR */
2834 #define WM8994_AIF2DAC_LRCLK_DIR_MASK           0x0800  /* AIF2DAC_LRCLK_DIR */
2835 #define WM8994_AIF2DAC_LRCLK_DIR_SHIFT              11  /* AIF2DAC_LRCLK_DIR */
2836 #define WM8994_AIF2DAC_LRCLK_DIR_WIDTH               1  /* AIF2DAC_LRCLK_DIR */
2837 #define WM8994_AIF2DAC_RATE_MASK                0x07FF  /* AIF2DAC_RATE - [10:0] */
2838 #define WM8994_AIF2DAC_RATE_SHIFT                    0  /* AIF2DAC_RATE - [10:0] */
2839 #define WM8994_AIF2DAC_RATE_WIDTH                   11  /* AIF2DAC_RATE - [10:0] */
2840 
2841 /*
2842  * R790 (0x316) - AIF2DAC Data
2843  */
2844 #define WM8994_AIF2DACL_DAT_INV                 0x0002  /* AIF2DACL_DAT_INV */
2845 #define WM8994_AIF2DACL_DAT_INV_MASK            0x0002  /* AIF2DACL_DAT_INV */
2846 #define WM8994_AIF2DACL_DAT_INV_SHIFT                1  /* AIF2DACL_DAT_INV */
2847 #define WM8994_AIF2DACL_DAT_INV_WIDTH                1  /* AIF2DACL_DAT_INV */
2848 #define WM8994_AIF2DACR_DAT_INV                 0x0001  /* AIF2DACR_DAT_INV */
2849 #define WM8994_AIF2DACR_DAT_INV_MASK            0x0001  /* AIF2DACR_DAT_INV */
2850 #define WM8994_AIF2DACR_DAT_INV_SHIFT                0  /* AIF2DACR_DAT_INV */
2851 #define WM8994_AIF2DACR_DAT_INV_WIDTH                1  /* AIF2DACR_DAT_INV */
2852 
2853 /*
2854  * R791 (0x317) - AIF2ADC Data
2855  */
2856 #define WM8994_AIF2ADCL_DAT_INV                 0x0002  /* AIF2ADCL_DAT_INV */
2857 #define WM8994_AIF2ADCL_DAT_INV_MASK            0x0002  /* AIF2ADCL_DAT_INV */
2858 #define WM8994_AIF2ADCL_DAT_INV_SHIFT                1  /* AIF2ADCL_DAT_INV */
2859 #define WM8994_AIF2ADCL_DAT_INV_WIDTH                1  /* AIF2ADCL_DAT_INV */
2860 #define WM8994_AIF2ADCR_DAT_INV                 0x0001  /* AIF2ADCR_DAT_INV */
2861 #define WM8994_AIF2ADCR_DAT_INV_MASK            0x0001  /* AIF2ADCR_DAT_INV */
2862 #define WM8994_AIF2ADCR_DAT_INV_SHIFT                0  /* AIF2ADCR_DAT_INV */
2863 #define WM8994_AIF2ADCR_DAT_INV_WIDTH                1  /* AIF2ADCR_DAT_INV */
2864 
2865 /*
2866  * R800 (0x320) - AIF3 Control (1)
2867  */
2868 #define WM8958_AIF3_LRCLK_INV                   0x0080  /* AIF3_LRCLK_INV */
2869 #define WM8958_AIF3_LRCLK_INV_MASK              0x0080  /* AIF3_LRCLK_INV */
2870 #define WM8958_AIF3_LRCLK_INV_SHIFT                  7  /* AIF3_LRCLK_INV */
2871 #define WM8958_AIF3_LRCLK_INV_WIDTH                  1  /* AIF3_LRCLK_INV */
2872 #define WM8958_AIF3_WL_MASK                     0x0060  /* AIF3_WL - [6:5] */
2873 #define WM8958_AIF3_WL_SHIFT                         5  /* AIF3_WL - [6:5] */
2874 #define WM8958_AIF3_WL_WIDTH                         2  /* AIF3_WL - [6:5] */
2875 #define WM8958_AIF3_FMT_MASK                    0x0018  /* AIF3_FMT - [4:3] */
2876 #define WM8958_AIF3_FMT_SHIFT                        3  /* AIF3_FMT - [4:3] */
2877 #define WM8958_AIF3_FMT_WIDTH                        2  /* AIF3_FMT - [4:3] */
2878 
2879 /*
2880  * R801 (0x321) - AIF3 Control (2)
2881  */
2882 #define WM8958_AIF3DAC_BOOST_MASK               0x0C00  /* AIF3DAC_BOOST - [11:10] */
2883 #define WM8958_AIF3DAC_BOOST_SHIFT                  10  /* AIF3DAC_BOOST - [11:10] */
2884 #define WM8958_AIF3DAC_BOOST_WIDTH                   2  /* AIF3DAC_BOOST - [11:10] */
2885 #define WM8958_AIF3DAC_COMP                     0x0010  /* AIF3DAC_COMP */
2886 #define WM8958_AIF3DAC_COMP_MASK                0x0010  /* AIF3DAC_COMP */
2887 #define WM8958_AIF3DAC_COMP_SHIFT                    4  /* AIF3DAC_COMP */
2888 #define WM8958_AIF3DAC_COMP_WIDTH                    1  /* AIF3DAC_COMP */
2889 #define WM8958_AIF3DAC_COMPMODE                 0x0008  /* AIF3DAC_COMPMODE */
2890 #define WM8958_AIF3DAC_COMPMODE_MASK            0x0008  /* AIF3DAC_COMPMODE */
2891 #define WM8958_AIF3DAC_COMPMODE_SHIFT                3  /* AIF3DAC_COMPMODE */
2892 #define WM8958_AIF3DAC_COMPMODE_WIDTH                1  /* AIF3DAC_COMPMODE */
2893 #define WM8958_AIF3ADC_COMP                     0x0004  /* AIF3ADC_COMP */
2894 #define WM8958_AIF3ADC_COMP_MASK                0x0004  /* AIF3ADC_COMP */
2895 #define WM8958_AIF3ADC_COMP_SHIFT                    2  /* AIF3ADC_COMP */
2896 #define WM8958_AIF3ADC_COMP_WIDTH                    1  /* AIF3ADC_COMP */
2897 #define WM8958_AIF3ADC_COMPMODE                 0x0002  /* AIF3ADC_COMPMODE */
2898 #define WM8958_AIF3ADC_COMPMODE_MASK            0x0002  /* AIF3ADC_COMPMODE */
2899 #define WM8958_AIF3ADC_COMPMODE_SHIFT                1  /* AIF3ADC_COMPMODE */
2900 #define WM8958_AIF3ADC_COMPMODE_WIDTH                1  /* AIF3ADC_COMPMODE */
2901 #define WM8958_AIF3_LOOPBACK                    0x0001  /* AIF3_LOOPBACK */
2902 #define WM8958_AIF3_LOOPBACK_MASK               0x0001  /* AIF3_LOOPBACK */
2903 #define WM8958_AIF3_LOOPBACK_SHIFT                   0  /* AIF3_LOOPBACK */
2904 #define WM8958_AIF3_LOOPBACK_WIDTH                   1  /* AIF3_LOOPBACK */
2905 
2906 /*
2907  * R802 (0x322) - AIF3DAC Data
2908  */
2909 #define WM8958_AIF3DAC_DAT_INV                  0x0001  /* AIF3DAC_DAT_INV */
2910 #define WM8958_AIF3DAC_DAT_INV_MASK             0x0001  /* AIF3DAC_DAT_INV */
2911 #define WM8958_AIF3DAC_DAT_INV_SHIFT                 0  /* AIF3DAC_DAT_INV */
2912 #define WM8958_AIF3DAC_DAT_INV_WIDTH                 1  /* AIF3DAC_DAT_INV */
2913 
2914 /*
2915  * R803 (0x323) - AIF3ADC Data
2916  */
2917 #define WM8958_AIF3ADC_DAT_INV                  0x0001  /* AIF3ADC_DAT_INV */
2918 #define WM8958_AIF3ADC_DAT_INV_MASK             0x0001  /* AIF3ADC_DAT_INV */
2919 #define WM8958_AIF3ADC_DAT_INV_SHIFT                 0  /* AIF3ADC_DAT_INV */
2920 #define WM8958_AIF3ADC_DAT_INV_WIDTH                 1  /* AIF3ADC_DAT_INV */
2921 
2922 /*
2923  * R1024 (0x400) - AIF1 ADC1 Left Volume
2924  */
2925 #define WM8994_AIF1ADC1_VU                      0x0100  /* AIF1ADC1_VU */
2926 #define WM8994_AIF1ADC1_VU_MASK                 0x0100  /* AIF1ADC1_VU */
2927 #define WM8994_AIF1ADC1_VU_SHIFT                     8  /* AIF1ADC1_VU */
2928 #define WM8994_AIF1ADC1_VU_WIDTH                     1  /* AIF1ADC1_VU */
2929 #define WM8994_AIF1ADC1L_VOL_MASK               0x00FF  /* AIF1ADC1L_VOL - [7:0] */
2930 #define WM8994_AIF1ADC1L_VOL_SHIFT                   0  /* AIF1ADC1L_VOL - [7:0] */
2931 #define WM8994_AIF1ADC1L_VOL_WIDTH                   8  /* AIF1ADC1L_VOL - [7:0] */
2932 
2933 /*
2934  * R1025 (0x401) - AIF1 ADC1 Right Volume
2935  */
2936 #define WM8994_AIF1ADC1_VU                      0x0100  /* AIF1ADC1_VU */
2937 #define WM8994_AIF1ADC1_VU_MASK                 0x0100  /* AIF1ADC1_VU */
2938 #define WM8994_AIF1ADC1_VU_SHIFT                     8  /* AIF1ADC1_VU */
2939 #define WM8994_AIF1ADC1_VU_WIDTH                     1  /* AIF1ADC1_VU */
2940 #define WM8994_AIF1ADC1R_VOL_MASK               0x00FF  /* AIF1ADC1R_VOL - [7:0] */
2941 #define WM8994_AIF1ADC1R_VOL_SHIFT                   0  /* AIF1ADC1R_VOL - [7:0] */
2942 #define WM8994_AIF1ADC1R_VOL_WIDTH                   8  /* AIF1ADC1R_VOL - [7:0] */
2943 
2944 /*
2945  * R1026 (0x402) - AIF1 DAC1 Left Volume
2946  */
2947 #define WM8994_AIF1DAC1_VU                      0x0100  /* AIF1DAC1_VU */
2948 #define WM8994_AIF1DAC1_VU_MASK                 0x0100  /* AIF1DAC1_VU */
2949 #define WM8994_AIF1DAC1_VU_SHIFT                     8  /* AIF1DAC1_VU */
2950 #define WM8994_AIF1DAC1_VU_WIDTH                     1  /* AIF1DAC1_VU */
2951 #define WM8994_AIF1DAC1L_VOL_MASK               0x00FF  /* AIF1DAC1L_VOL - [7:0] */
2952 #define WM8994_AIF1DAC1L_VOL_SHIFT                   0  /* AIF1DAC1L_VOL - [7:0] */
2953 #define WM8994_AIF1DAC1L_VOL_WIDTH                   8  /* AIF1DAC1L_VOL - [7:0] */
2954 
2955 /*
2956  * R1027 (0x403) - AIF1 DAC1 Right Volume
2957  */
2958 #define WM8994_AIF1DAC1_VU                      0x0100  /* AIF1DAC1_VU */
2959 #define WM8994_AIF1DAC1_VU_MASK                 0x0100  /* AIF1DAC1_VU */
2960 #define WM8994_AIF1DAC1_VU_SHIFT                     8  /* AIF1DAC1_VU */
2961 #define WM8994_AIF1DAC1_VU_WIDTH                     1  /* AIF1DAC1_VU */
2962 #define WM8994_AIF1DAC1R_VOL_MASK               0x00FF  /* AIF1DAC1R_VOL - [7:0] */
2963 #define WM8994_AIF1DAC1R_VOL_SHIFT                   0  /* AIF1DAC1R_VOL - [7:0] */
2964 #define WM8994_AIF1DAC1R_VOL_WIDTH                   8  /* AIF1DAC1R_VOL - [7:0] */
2965 
2966 /*
2967  * R1028 (0x404) - AIF1 ADC2 Left Volume
2968  */
2969 #define WM8994_AIF1ADC2_VU                      0x0100  /* AIF1ADC2_VU */
2970 #define WM8994_AIF1ADC2_VU_MASK                 0x0100  /* AIF1ADC2_VU */
2971 #define WM8994_AIF1ADC2_VU_SHIFT                     8  /* AIF1ADC2_VU */
2972 #define WM8994_AIF1ADC2_VU_WIDTH                     1  /* AIF1ADC2_VU */
2973 #define WM8994_AIF1ADC2L_VOL_MASK               0x00FF  /* AIF1ADC2L_VOL - [7:0] */
2974 #define WM8994_AIF1ADC2L_VOL_SHIFT                   0  /* AIF1ADC2L_VOL - [7:0] */
2975 #define WM8994_AIF1ADC2L_VOL_WIDTH                   8  /* AIF1ADC2L_VOL - [7:0] */
2976 
2977 /*
2978  * R1029 (0x405) - AIF1 ADC2 Right Volume
2979  */
2980 #define WM8994_AIF1ADC2_VU                      0x0100  /* AIF1ADC2_VU */
2981 #define WM8994_AIF1ADC2_VU_MASK                 0x0100  /* AIF1ADC2_VU */
2982 #define WM8994_AIF1ADC2_VU_SHIFT                     8  /* AIF1ADC2_VU */
2983 #define WM8994_AIF1ADC2_VU_WIDTH                     1  /* AIF1ADC2_VU */
2984 #define WM8994_AIF1ADC2R_VOL_MASK               0x00FF  /* AIF1ADC2R_VOL - [7:0] */
2985 #define WM8994_AIF1ADC2R_VOL_SHIFT                   0  /* AIF1ADC2R_VOL - [7:0] */
2986 #define WM8994_AIF1ADC2R_VOL_WIDTH                   8  /* AIF1ADC2R_VOL - [7:0] */
2987 
2988 /*
2989  * R1030 (0x406) - AIF1 DAC2 Left Volume
2990  */
2991 #define WM8994_AIF1DAC2_VU                      0x0100  /* AIF1DAC2_VU */
2992 #define WM8994_AIF1DAC2_VU_MASK                 0x0100  /* AIF1DAC2_VU */
2993 #define WM8994_AIF1DAC2_VU_SHIFT                     8  /* AIF1DAC2_VU */
2994 #define WM8994_AIF1DAC2_VU_WIDTH                     1  /* AIF1DAC2_VU */
2995 #define WM8994_AIF1DAC2L_VOL_MASK               0x00FF  /* AIF1DAC2L_VOL - [7:0] */
2996 #define WM8994_AIF1DAC2L_VOL_SHIFT                   0  /* AIF1DAC2L_VOL - [7:0] */
2997 #define WM8994_AIF1DAC2L_VOL_WIDTH                   8  /* AIF1DAC2L_VOL - [7:0] */
2998 
2999 /*
3000  * R1031 (0x407) - AIF1 DAC2 Right Volume
3001  */
3002 #define WM8994_AIF1DAC2_VU                      0x0100  /* AIF1DAC2_VU */
3003 #define WM8994_AIF1DAC2_VU_MASK                 0x0100  /* AIF1DAC2_VU */
3004 #define WM8994_AIF1DAC2_VU_SHIFT                     8  /* AIF1DAC2_VU */
3005 #define WM8994_AIF1DAC2_VU_WIDTH                     1  /* AIF1DAC2_VU */
3006 #define WM8994_AIF1DAC2R_VOL_MASK               0x00FF  /* AIF1DAC2R_VOL - [7:0] */
3007 #define WM8994_AIF1DAC2R_VOL_SHIFT                   0  /* AIF1DAC2R_VOL - [7:0] */
3008 #define WM8994_AIF1DAC2R_VOL_WIDTH                   8  /* AIF1DAC2R_VOL - [7:0] */
3009 
3010 /*
3011  * R1040 (0x410) - AIF1 ADC1 Filters
3012  */
3013 #define WM8994_AIF1ADC_4FS                      0x8000  /* AIF1ADC_4FS */
3014 #define WM8994_AIF1ADC_4FS_MASK                 0x8000  /* AIF1ADC_4FS */
3015 #define WM8994_AIF1ADC_4FS_SHIFT                    15  /* AIF1ADC_4FS */
3016 #define WM8994_AIF1ADC_4FS_WIDTH                     1  /* AIF1ADC_4FS */
3017 #define WM8994_AIF1ADC1_HPF_CUT_MASK            0x6000  /* AIF1ADC1_HPF_CUT - [14:13] */
3018 #define WM8994_AIF1ADC1_HPF_CUT_SHIFT               13  /* AIF1ADC1_HPF_CUT - [14:13] */
3019 #define WM8994_AIF1ADC1_HPF_CUT_WIDTH                2  /* AIF1ADC1_HPF_CUT - [14:13] */
3020 #define WM8994_AIF1ADC1L_HPF                    0x1000  /* AIF1ADC1L_HPF */
3021 #define WM8994_AIF1ADC1L_HPF_MASK               0x1000  /* AIF1ADC1L_HPF */
3022 #define WM8994_AIF1ADC1L_HPF_SHIFT                  12  /* AIF1ADC1L_HPF */
3023 #define WM8994_AIF1ADC1L_HPF_WIDTH                   1  /* AIF1ADC1L_HPF */
3024 #define WM8994_AIF1ADC1R_HPF                    0x0800  /* AIF1ADC1R_HPF */
3025 #define WM8994_AIF1ADC1R_HPF_MASK               0x0800  /* AIF1ADC1R_HPF */
3026 #define WM8994_AIF1ADC1R_HPF_SHIFT                  11  /* AIF1ADC1R_HPF */
3027 #define WM8994_AIF1ADC1R_HPF_WIDTH                   1  /* AIF1ADC1R_HPF */
3028 
3029 /*
3030  * R1041 (0x411) - AIF1 ADC2 Filters
3031  */
3032 #define WM8994_AIF1ADC2_HPF_CUT_MASK            0x6000  /* AIF1ADC2_HPF_CUT - [14:13] */
3033 #define WM8994_AIF1ADC2_HPF_CUT_SHIFT               13  /* AIF1ADC2_HPF_CUT - [14:13] */
3034 #define WM8994_AIF1ADC2_HPF_CUT_WIDTH                2  /* AIF1ADC2_HPF_CUT - [14:13] */
3035 #define WM8994_AIF1ADC2L_HPF                    0x1000  /* AIF1ADC2L_HPF */
3036 #define WM8994_AIF1ADC2L_HPF_MASK               0x1000  /* AIF1ADC2L_HPF */
3037 #define WM8994_AIF1ADC2L_HPF_SHIFT                  12  /* AIF1ADC2L_HPF */
3038 #define WM8994_AIF1ADC2L_HPF_WIDTH                   1  /* AIF1ADC2L_HPF */
3039 #define WM8994_AIF1ADC2R_HPF                    0x0800  /* AIF1ADC2R_HPF */
3040 #define WM8994_AIF1ADC2R_HPF_MASK               0x0800  /* AIF1ADC2R_HPF */
3041 #define WM8994_AIF1ADC2R_HPF_SHIFT                  11  /* AIF1ADC2R_HPF */
3042 #define WM8994_AIF1ADC2R_HPF_WIDTH                   1  /* AIF1ADC2R_HPF */
3043 
3044 /*
3045  * R1056 (0x420) - AIF1 DAC1 Filters (1)
3046  */
3047 #define WM8994_AIF1DAC1_MUTE                    0x0200  /* AIF1DAC1_MUTE */
3048 #define WM8994_AIF1DAC1_MUTE_MASK               0x0200  /* AIF1DAC1_MUTE */
3049 #define WM8994_AIF1DAC1_MUTE_SHIFT                   9  /* AIF1DAC1_MUTE */
3050 #define WM8994_AIF1DAC1_MUTE_WIDTH                   1  /* AIF1DAC1_MUTE */
3051 #define WM8994_AIF1DAC1_MONO                    0x0080  /* AIF1DAC1_MONO */
3052 #define WM8994_AIF1DAC1_MONO_MASK               0x0080  /* AIF1DAC1_MONO */
3053 #define WM8994_AIF1DAC1_MONO_SHIFT                   7  /* AIF1DAC1_MONO */
3054 #define WM8994_AIF1DAC1_MONO_WIDTH                   1  /* AIF1DAC1_MONO */
3055 #define WM8994_AIF1DAC1_MUTERATE                0x0020  /* AIF1DAC1_MUTERATE */
3056 #define WM8994_AIF1DAC1_MUTERATE_MASK           0x0020  /* AIF1DAC1_MUTERATE */
3057 #define WM8994_AIF1DAC1_MUTERATE_SHIFT               5  /* AIF1DAC1_MUTERATE */
3058 #define WM8994_AIF1DAC1_MUTERATE_WIDTH               1  /* AIF1DAC1_MUTERATE */
3059 #define WM8994_AIF1DAC1_UNMUTE_RAMP             0x0010  /* AIF1DAC1_UNMUTE_RAMP */
3060 #define WM8994_AIF1DAC1_UNMUTE_RAMP_MASK        0x0010  /* AIF1DAC1_UNMUTE_RAMP */
3061 #define WM8994_AIF1DAC1_UNMUTE_RAMP_SHIFT            4  /* AIF1DAC1_UNMUTE_RAMP */
3062 #define WM8994_AIF1DAC1_UNMUTE_RAMP_WIDTH            1  /* AIF1DAC1_UNMUTE_RAMP */
3063 #define WM8994_AIF1DAC1_DEEMP_MASK              0x0006  /* AIF1DAC1_DEEMP - [2:1] */
3064 #define WM8994_AIF1DAC1_DEEMP_SHIFT                  1  /* AIF1DAC1_DEEMP - [2:1] */
3065 #define WM8994_AIF1DAC1_DEEMP_WIDTH                  2  /* AIF1DAC1_DEEMP - [2:1] */
3066 
3067 /*
3068  * R1057 (0x421) - AIF1 DAC1 Filters (2)
3069  */
3070 #define WM8994_AIF1DAC1_3D_GAIN_MASK            0x3E00  /* AIF1DAC1_3D_GAIN - [13:9] */
3071 #define WM8994_AIF1DAC1_3D_GAIN_SHIFT                9  /* AIF1DAC1_3D_GAIN - [13:9] */
3072 #define WM8994_AIF1DAC1_3D_GAIN_WIDTH                5  /* AIF1DAC1_3D_GAIN - [13:9] */
3073 #define WM8994_AIF1DAC1_3D_ENA                  0x0100  /* AIF1DAC1_3D_ENA */
3074 #define WM8994_AIF1DAC1_3D_ENA_MASK             0x0100  /* AIF1DAC1_3D_ENA */
3075 #define WM8994_AIF1DAC1_3D_ENA_SHIFT                 8  /* AIF1DAC1_3D_ENA */
3076 #define WM8994_AIF1DAC1_3D_ENA_WIDTH                 1  /* AIF1DAC1_3D_ENA */
3077 
3078 /*
3079  * R1058 (0x422) - AIF1 DAC2 Filters (1)
3080  */
3081 #define WM8994_AIF1DAC2_MUTE                    0x0200  /* AIF1DAC2_MUTE */
3082 #define WM8994_AIF1DAC2_MUTE_MASK               0x0200  /* AIF1DAC2_MUTE */
3083 #define WM8994_AIF1DAC2_MUTE_SHIFT                   9  /* AIF1DAC2_MUTE */
3084 #define WM8994_AIF1DAC2_MUTE_WIDTH                   1  /* AIF1DAC2_MUTE */
3085 #define WM8994_AIF1DAC2_MONO                    0x0080  /* AIF1DAC2_MONO */
3086 #define WM8994_AIF1DAC2_MONO_MASK               0x0080  /* AIF1DAC2_MONO */
3087 #define WM8994_AIF1DAC2_MONO_SHIFT                   7  /* AIF1DAC2_MONO */
3088 #define WM8994_AIF1DAC2_MONO_WIDTH                   1  /* AIF1DAC2_MONO */
3089 #define WM8994_AIF1DAC2_MUTERATE                0x0020  /* AIF1DAC2_MUTERATE */
3090 #define WM8994_AIF1DAC2_MUTERATE_MASK           0x0020  /* AIF1DAC2_MUTERATE */
3091 #define WM8994_AIF1DAC2_MUTERATE_SHIFT               5  /* AIF1DAC2_MUTERATE */
3092 #define WM8994_AIF1DAC2_MUTERATE_WIDTH               1  /* AIF1DAC2_MUTERATE */
3093 #define WM8994_AIF1DAC2_UNMUTE_RAMP             0x0010  /* AIF1DAC2_UNMUTE_RAMP */
3094 #define WM8994_AIF1DAC2_UNMUTE_RAMP_MASK        0x0010  /* AIF1DAC2_UNMUTE_RAMP */
3095 #define WM8994_AIF1DAC2_UNMUTE_RAMP_SHIFT            4  /* AIF1DAC2_UNMUTE_RAMP */
3096 #define WM8994_AIF1DAC2_UNMUTE_RAMP_WIDTH            1  /* AIF1DAC2_UNMUTE_RAMP */
3097 #define WM8994_AIF1DAC2_DEEMP_MASK              0x0006  /* AIF1DAC2_DEEMP - [2:1] */
3098 #define WM8994_AIF1DAC2_DEEMP_SHIFT                  1  /* AIF1DAC2_DEEMP - [2:1] */
3099 #define WM8994_AIF1DAC2_DEEMP_WIDTH                  2  /* AIF1DAC2_DEEMP - [2:1] */
3100 
3101 /*
3102  * R1059 (0x423) - AIF1 DAC2 Filters (2)
3103  */
3104 #define WM8994_AIF1DAC2_3D_GAIN_MASK            0x3E00  /* AIF1DAC2_3D_GAIN - [13:9] */
3105 #define WM8994_AIF1DAC2_3D_GAIN_SHIFT                9  /* AIF1DAC2_3D_GAIN - [13:9] */
3106 #define WM8994_AIF1DAC2_3D_GAIN_WIDTH                5  /* AIF1DAC2_3D_GAIN - [13:9] */
3107 #define WM8994_AIF1DAC2_3D_ENA                  0x0100  /* AIF1DAC2_3D_ENA */
3108 #define WM8994_AIF1DAC2_3D_ENA_MASK             0x0100  /* AIF1DAC2_3D_ENA */
3109 #define WM8994_AIF1DAC2_3D_ENA_SHIFT                 8  /* AIF1DAC2_3D_ENA */
3110 #define WM8994_AIF1DAC2_3D_ENA_WIDTH                 1  /* AIF1DAC2_3D_ENA */
3111 
3112 /*
3113  * R1072 (0x430) - AIF1 DAC1 Noise Gate
3114  */
3115 #define WM8958_AIF1DAC1_NG_HLD_MASK             0x0060  /* AIF1DAC1_NG_HLD - [6:5] */
3116 #define WM8958_AIF1DAC1_NG_HLD_SHIFT                 5  /* AIF1DAC1_NG_HLD - [6:5] */
3117 #define WM8958_AIF1DAC1_NG_HLD_WIDTH                 2  /* AIF1DAC1_NG_HLD - [6:5] */
3118 #define WM8958_AIF1DAC1_NG_THR_MASK             0x000E  /* AIF1DAC1_NG_THR - [3:1] */
3119 #define WM8958_AIF1DAC1_NG_THR_SHIFT                 1  /* AIF1DAC1_NG_THR - [3:1] */
3120 #define WM8958_AIF1DAC1_NG_THR_WIDTH                 3  /* AIF1DAC1_NG_THR - [3:1] */
3121 #define WM8958_AIF1DAC1_NG_ENA                  0x0001  /* AIF1DAC1_NG_ENA */
3122 #define WM8958_AIF1DAC1_NG_ENA_MASK             0x0001  /* AIF1DAC1_NG_ENA */
3123 #define WM8958_AIF1DAC1_NG_ENA_SHIFT                 0  /* AIF1DAC1_NG_ENA */
3124 #define WM8958_AIF1DAC1_NG_ENA_WIDTH                 1  /* AIF1DAC1_NG_ENA */
3125 
3126 /*
3127  * R1073 (0x431) - AIF1 DAC2 Noise Gate
3128  */
3129 #define WM8958_AIF1DAC2_NG_HLD_MASK             0x0060  /* AIF1DAC2_NG_HLD - [6:5] */
3130 #define WM8958_AIF1DAC2_NG_HLD_SHIFT                 5  /* AIF1DAC2_NG_HLD - [6:5] */
3131 #define WM8958_AIF1DAC2_NG_HLD_WIDTH                 2  /* AIF1DAC2_NG_HLD - [6:5] */
3132 #define WM8958_AIF1DAC2_NG_THR_MASK             0x000E  /* AIF1DAC2_NG_THR - [3:1] */
3133 #define WM8958_AIF1DAC2_NG_THR_SHIFT                 1  /* AIF1DAC2_NG_THR - [3:1] */
3134 #define WM8958_AIF1DAC2_NG_THR_WIDTH                 3  /* AIF1DAC2_NG_THR - [3:1] */
3135 #define WM8958_AIF1DAC2_NG_ENA                  0x0001  /* AIF1DAC2_NG_ENA */
3136 #define WM8958_AIF1DAC2_NG_ENA_MASK             0x0001  /* AIF1DAC2_NG_ENA */
3137 #define WM8958_AIF1DAC2_NG_ENA_SHIFT                 0  /* AIF1DAC2_NG_ENA */
3138 #define WM8958_AIF1DAC2_NG_ENA_WIDTH                 1  /* AIF1DAC2_NG_ENA */
3139 
3140 /*
3141  * R1088 (0x440) - AIF1 DRC1 (1)
3142  */
3143 #define WM8994_AIF1DRC1_SIG_DET_RMS_MASK        0xF800  /* AIF1DRC1_SIG_DET_RMS - [15:11] */
3144 #define WM8994_AIF1DRC1_SIG_DET_RMS_SHIFT           11  /* AIF1DRC1_SIG_DET_RMS - [15:11] */
3145 #define WM8994_AIF1DRC1_SIG_DET_RMS_WIDTH            5  /* AIF1DRC1_SIG_DET_RMS - [15:11] */
3146 #define WM8994_AIF1DRC1_SIG_DET_PK_MASK         0x0600  /* AIF1DRC1_SIG_DET_PK - [10:9] */
3147 #define WM8994_AIF1DRC1_SIG_DET_PK_SHIFT             9  /* AIF1DRC1_SIG_DET_PK - [10:9] */
3148 #define WM8994_AIF1DRC1_SIG_DET_PK_WIDTH             2  /* AIF1DRC1_SIG_DET_PK - [10:9] */
3149 #define WM8994_AIF1DRC1_NG_ENA                  0x0100  /* AIF1DRC1_NG_ENA */
3150 #define WM8994_AIF1DRC1_NG_ENA_MASK             0x0100  /* AIF1DRC1_NG_ENA */
3151 #define WM8994_AIF1DRC1_NG_ENA_SHIFT                 8  /* AIF1DRC1_NG_ENA */
3152 #define WM8994_AIF1DRC1_NG_ENA_WIDTH                 1  /* AIF1DRC1_NG_ENA */
3153 #define WM8994_AIF1DRC1_SIG_DET_MODE            0x0080  /* AIF1DRC1_SIG_DET_MODE */
3154 #define WM8994_AIF1DRC1_SIG_DET_MODE_MASK       0x0080  /* AIF1DRC1_SIG_DET_MODE */
3155 #define WM8994_AIF1DRC1_SIG_DET_MODE_SHIFT           7  /* AIF1DRC1_SIG_DET_MODE */
3156 #define WM8994_AIF1DRC1_SIG_DET_MODE_WIDTH           1  /* AIF1DRC1_SIG_DET_MODE */
3157 #define WM8994_AIF1DRC1_SIG_DET                 0x0040  /* AIF1DRC1_SIG_DET */
3158 #define WM8994_AIF1DRC1_SIG_DET_MASK            0x0040  /* AIF1DRC1_SIG_DET */
3159 #define WM8994_AIF1DRC1_SIG_DET_SHIFT                6  /* AIF1DRC1_SIG_DET */
3160 #define WM8994_AIF1DRC1_SIG_DET_WIDTH                1  /* AIF1DRC1_SIG_DET */
3161 #define WM8994_AIF1DRC1_KNEE2_OP_ENA            0x0020  /* AIF1DRC1_KNEE2_OP_ENA */
3162 #define WM8994_AIF1DRC1_KNEE2_OP_ENA_MASK       0x0020  /* AIF1DRC1_KNEE2_OP_ENA */
3163 #define WM8994_AIF1DRC1_KNEE2_OP_ENA_SHIFT           5  /* AIF1DRC1_KNEE2_OP_ENA */
3164 #define WM8994_AIF1DRC1_KNEE2_OP_ENA_WIDTH           1  /* AIF1DRC1_KNEE2_OP_ENA */
3165 #define WM8994_AIF1DRC1_QR                      0x0010  /* AIF1DRC1_QR */
3166 #define WM8994_AIF1DRC1_QR_MASK                 0x0010  /* AIF1DRC1_QR */
3167 #define WM8994_AIF1DRC1_QR_SHIFT                     4  /* AIF1DRC1_QR */
3168 #define WM8994_AIF1DRC1_QR_WIDTH                     1  /* AIF1DRC1_QR */
3169 #define WM8994_AIF1DRC1_ANTICLIP                0x0008  /* AIF1DRC1_ANTICLIP */
3170 #define WM8994_AIF1DRC1_ANTICLIP_MASK           0x0008  /* AIF1DRC1_ANTICLIP */
3171 #define WM8994_AIF1DRC1_ANTICLIP_SHIFT               3  /* AIF1DRC1_ANTICLIP */
3172 #define WM8994_AIF1DRC1_ANTICLIP_WIDTH               1  /* AIF1DRC1_ANTICLIP */
3173 #define WM8994_AIF1DAC1_DRC_ENA                 0x0004  /* AIF1DAC1_DRC_ENA */
3174 #define WM8994_AIF1DAC1_DRC_ENA_MASK            0x0004  /* AIF1DAC1_DRC_ENA */
3175 #define WM8994_AIF1DAC1_DRC_ENA_SHIFT                2  /* AIF1DAC1_DRC_ENA */
3176 #define WM8994_AIF1DAC1_DRC_ENA_WIDTH                1  /* AIF1DAC1_DRC_ENA */
3177 #define WM8994_AIF1ADC1L_DRC_ENA                0x0002  /* AIF1ADC1L_DRC_ENA */
3178 #define WM8994_AIF1ADC1L_DRC_ENA_MASK           0x0002  /* AIF1ADC1L_DRC_ENA */
3179 #define WM8994_AIF1ADC1L_DRC_ENA_SHIFT               1  /* AIF1ADC1L_DRC_ENA */
3180 #define WM8994_AIF1ADC1L_DRC_ENA_WIDTH               1  /* AIF1ADC1L_DRC_ENA */
3181 #define WM8994_AIF1ADC1R_DRC_ENA                0x0001  /* AIF1ADC1R_DRC_ENA */
3182 #define WM8994_AIF1ADC1R_DRC_ENA_MASK           0x0001  /* AIF1ADC1R_DRC_ENA */
3183 #define WM8994_AIF1ADC1R_DRC_ENA_SHIFT               0  /* AIF1ADC1R_DRC_ENA */
3184 #define WM8994_AIF1ADC1R_DRC_ENA_WIDTH               1  /* AIF1ADC1R_DRC_ENA */
3185 
3186 /*
3187  * R1089 (0x441) - AIF1 DRC1 (2)
3188  */
3189 #define WM8994_AIF1DRC1_ATK_MASK                0x1E00  /* AIF1DRC1_ATK - [12:9] */
3190 #define WM8994_AIF1DRC1_ATK_SHIFT                    9  /* AIF1DRC1_ATK - [12:9] */
3191 #define WM8994_AIF1DRC1_ATK_WIDTH                    4  /* AIF1DRC1_ATK - [12:9] */
3192 #define WM8994_AIF1DRC1_DCY_MASK                0x01E0  /* AIF1DRC1_DCY - [8:5] */
3193 #define WM8994_AIF1DRC1_DCY_SHIFT                    5  /* AIF1DRC1_DCY - [8:5] */
3194 #define WM8994_AIF1DRC1_DCY_WIDTH                    4  /* AIF1DRC1_DCY - [8:5] */
3195 #define WM8994_AIF1DRC1_MINGAIN_MASK            0x001C  /* AIF1DRC1_MINGAIN - [4:2] */
3196 #define WM8994_AIF1DRC1_MINGAIN_SHIFT                2  /* AIF1DRC1_MINGAIN - [4:2] */
3197 #define WM8994_AIF1DRC1_MINGAIN_WIDTH                3  /* AIF1DRC1_MINGAIN - [4:2] */
3198 #define WM8994_AIF1DRC1_MAXGAIN_MASK            0x0003  /* AIF1DRC1_MAXGAIN - [1:0] */
3199 #define WM8994_AIF1DRC1_MAXGAIN_SHIFT                0  /* AIF1DRC1_MAXGAIN - [1:0] */
3200 #define WM8994_AIF1DRC1_MAXGAIN_WIDTH                2  /* AIF1DRC1_MAXGAIN - [1:0] */
3201 
3202 /*
3203  * R1090 (0x442) - AIF1 DRC1 (3)
3204  */
3205 #define WM8994_AIF1DRC1_NG_MINGAIN_MASK         0xF000  /* AIF1DRC1_NG_MINGAIN - [15:12] */
3206 #define WM8994_AIF1DRC1_NG_MINGAIN_SHIFT            12  /* AIF1DRC1_NG_MINGAIN - [15:12] */
3207 #define WM8994_AIF1DRC1_NG_MINGAIN_WIDTH             4  /* AIF1DRC1_NG_MINGAIN - [15:12] */
3208 #define WM8994_AIF1DRC1_NG_EXP_MASK             0x0C00  /* AIF1DRC1_NG_EXP - [11:10] */
3209 #define WM8994_AIF1DRC1_NG_EXP_SHIFT                10  /* AIF1DRC1_NG_EXP - [11:10] */
3210 #define WM8994_AIF1DRC1_NG_EXP_WIDTH                 2  /* AIF1DRC1_NG_EXP - [11:10] */
3211 #define WM8994_AIF1DRC1_QR_THR_MASK             0x0300  /* AIF1DRC1_QR_THR - [9:8] */
3212 #define WM8994_AIF1DRC1_QR_THR_SHIFT                 8  /* AIF1DRC1_QR_THR - [9:8] */
3213 #define WM8994_AIF1DRC1_QR_THR_WIDTH                 2  /* AIF1DRC1_QR_THR - [9:8] */
3214 #define WM8994_AIF1DRC1_QR_DCY_MASK             0x00C0  /* AIF1DRC1_QR_DCY - [7:6] */
3215 #define WM8994_AIF1DRC1_QR_DCY_SHIFT                 6  /* AIF1DRC1_QR_DCY - [7:6] */
3216 #define WM8994_AIF1DRC1_QR_DCY_WIDTH                 2  /* AIF1DRC1_QR_DCY - [7:6] */
3217 #define WM8994_AIF1DRC1_HI_COMP_MASK            0x0038  /* AIF1DRC1_HI_COMP - [5:3] */
3218 #define WM8994_AIF1DRC1_HI_COMP_SHIFT                3  /* AIF1DRC1_HI_COMP - [5:3] */
3219 #define WM8994_AIF1DRC1_HI_COMP_WIDTH                3  /* AIF1DRC1_HI_COMP - [5:3] */
3220 #define WM8994_AIF1DRC1_LO_COMP_MASK            0x0007  /* AIF1DRC1_LO_COMP - [2:0] */
3221 #define WM8994_AIF1DRC1_LO_COMP_SHIFT                0  /* AIF1DRC1_LO_COMP - [2:0] */
3222 #define WM8994_AIF1DRC1_LO_COMP_WIDTH                3  /* AIF1DRC1_LO_COMP - [2:0] */
3223 
3224 /*
3225  * R1091 (0x443) - AIF1 DRC1 (4)
3226  */
3227 #define WM8994_AIF1DRC1_KNEE_IP_MASK            0x07E0  /* AIF1DRC1_KNEE_IP - [10:5] */
3228 #define WM8994_AIF1DRC1_KNEE_IP_SHIFT                5  /* AIF1DRC1_KNEE_IP - [10:5] */
3229 #define WM8994_AIF1DRC1_KNEE_IP_WIDTH                6  /* AIF1DRC1_KNEE_IP - [10:5] */
3230 #define WM8994_AIF1DRC1_KNEE_OP_MASK            0x001F  /* AIF1DRC1_KNEE_OP - [4:0] */
3231 #define WM8994_AIF1DRC1_KNEE_OP_SHIFT                0  /* AIF1DRC1_KNEE_OP - [4:0] */
3232 #define WM8994_AIF1DRC1_KNEE_OP_WIDTH                5  /* AIF1DRC1_KNEE_OP - [4:0] */
3233 
3234 /*
3235  * R1092 (0x444) - AIF1 DRC1 (5)
3236  */
3237 #define WM8994_AIF1DRC1_KNEE2_IP_MASK           0x03E0  /* AIF1DRC1_KNEE2_IP - [9:5] */
3238 #define WM8994_AIF1DRC1_KNEE2_IP_SHIFT               5  /* AIF1DRC1_KNEE2_IP - [9:5] */
3239 #define WM8994_AIF1DRC1_KNEE2_IP_WIDTH               5  /* AIF1DRC1_KNEE2_IP - [9:5] */
3240 #define WM8994_AIF1DRC1_KNEE2_OP_MASK           0x001F  /* AIF1DRC1_KNEE2_OP - [4:0] */
3241 #define WM8994_AIF1DRC1_KNEE2_OP_SHIFT               0  /* AIF1DRC1_KNEE2_OP - [4:0] */
3242 #define WM8994_AIF1DRC1_KNEE2_OP_WIDTH               5  /* AIF1DRC1_KNEE2_OP - [4:0] */
3243 
3244 /*
3245  * R1104 (0x450) - AIF1 DRC2 (1)
3246  */
3247 #define WM8994_AIF1DRC2_SIG_DET_RMS_MASK        0xF800  /* AIF1DRC2_SIG_DET_RMS - [15:11] */
3248 #define WM8994_AIF1DRC2_SIG_DET_RMS_SHIFT           11  /* AIF1DRC2_SIG_DET_RMS - [15:11] */
3249 #define WM8994_AIF1DRC2_SIG_DET_RMS_WIDTH            5  /* AIF1DRC2_SIG_DET_RMS - [15:11] */
3250 #define WM8994_AIF1DRC2_SIG_DET_PK_MASK         0x0600  /* AIF1DRC2_SIG_DET_PK - [10:9] */
3251 #define WM8994_AIF1DRC2_SIG_DET_PK_SHIFT             9  /* AIF1DRC2_SIG_DET_PK - [10:9] */
3252 #define WM8994_AIF1DRC2_SIG_DET_PK_WIDTH             2  /* AIF1DRC2_SIG_DET_PK - [10:9] */
3253 #define WM8994_AIF1DRC2_NG_ENA                  0x0100  /* AIF1DRC2_NG_ENA */
3254 #define WM8994_AIF1DRC2_NG_ENA_MASK             0x0100  /* AIF1DRC2_NG_ENA */
3255 #define WM8994_AIF1DRC2_NG_ENA_SHIFT                 8  /* AIF1DRC2_NG_ENA */
3256 #define WM8994_AIF1DRC2_NG_ENA_WIDTH                 1  /* AIF1DRC2_NG_ENA */
3257 #define WM8994_AIF1DRC2_SIG_DET_MODE            0x0080  /* AIF1DRC2_SIG_DET_MODE */
3258 #define WM8994_AIF1DRC2_SIG_DET_MODE_MASK       0x0080  /* AIF1DRC2_SIG_DET_MODE */
3259 #define WM8994_AIF1DRC2_SIG_DET_MODE_SHIFT           7  /* AIF1DRC2_SIG_DET_MODE */
3260 #define WM8994_AIF1DRC2_SIG_DET_MODE_WIDTH           1  /* AIF1DRC2_SIG_DET_MODE */
3261 #define WM8994_AIF1DRC2_SIG_DET                 0x0040  /* AIF1DRC2_SIG_DET */
3262 #define WM8994_AIF1DRC2_SIG_DET_MASK            0x0040  /* AIF1DRC2_SIG_DET */
3263 #define WM8994_AIF1DRC2_SIG_DET_SHIFT                6  /* AIF1DRC2_SIG_DET */
3264 #define WM8994_AIF1DRC2_SIG_DET_WIDTH                1  /* AIF1DRC2_SIG_DET */
3265 #define WM8994_AIF1DRC2_KNEE2_OP_ENA            0x0020  /* AIF1DRC2_KNEE2_OP_ENA */
3266 #define WM8994_AIF1DRC2_KNEE2_OP_ENA_MASK       0x0020  /* AIF1DRC2_KNEE2_OP_ENA */
3267 #define WM8994_AIF1DRC2_KNEE2_OP_ENA_SHIFT           5  /* AIF1DRC2_KNEE2_OP_ENA */
3268 #define WM8994_AIF1DRC2_KNEE2_OP_ENA_WIDTH           1  /* AIF1DRC2_KNEE2_OP_ENA */
3269 #define WM8994_AIF1DRC2_QR                      0x0010  /* AIF1DRC2_QR */
3270 #define WM8994_AIF1DRC2_QR_MASK                 0x0010  /* AIF1DRC2_QR */
3271 #define WM8994_AIF1DRC2_QR_SHIFT                     4  /* AIF1DRC2_QR */
3272 #define WM8994_AIF1DRC2_QR_WIDTH                     1  /* AIF1DRC2_QR */
3273 #define WM8994_AIF1DRC2_ANTICLIP                0x0008  /* AIF1DRC2_ANTICLIP */
3274 #define WM8994_AIF1DRC2_ANTICLIP_MASK           0x0008  /* AIF1DRC2_ANTICLIP */
3275 #define WM8994_AIF1DRC2_ANTICLIP_SHIFT               3  /* AIF1DRC2_ANTICLIP */
3276 #define WM8994_AIF1DRC2_ANTICLIP_WIDTH               1  /* AIF1DRC2_ANTICLIP */
3277 #define WM8994_AIF1DAC2_DRC_ENA                 0x0004  /* AIF1DAC2_DRC_ENA */
3278 #define WM8994_AIF1DAC2_DRC_ENA_MASK            0x0004  /* AIF1DAC2_DRC_ENA */
3279 #define WM8994_AIF1DAC2_DRC_ENA_SHIFT                2  /* AIF1DAC2_DRC_ENA */
3280 #define WM8994_AIF1DAC2_DRC_ENA_WIDTH                1  /* AIF1DAC2_DRC_ENA */
3281 #define WM8994_AIF1ADC2L_DRC_ENA                0x0002  /* AIF1ADC2L_DRC_ENA */
3282 #define WM8994_AIF1ADC2L_DRC_ENA_MASK           0x0002  /* AIF1ADC2L_DRC_ENA */
3283 #define WM8994_AIF1ADC2L_DRC_ENA_SHIFT               1  /* AIF1ADC2L_DRC_ENA */
3284 #define WM8994_AIF1ADC2L_DRC_ENA_WIDTH               1  /* AIF1ADC2L_DRC_ENA */
3285 #define WM8994_AIF1ADC2R_DRC_ENA                0x0001  /* AIF1ADC2R_DRC_ENA */
3286 #define WM8994_AIF1ADC2R_DRC_ENA_MASK           0x0001  /* AIF1ADC2R_DRC_ENA */
3287 #define WM8994_AIF1ADC2R_DRC_ENA_SHIFT               0  /* AIF1ADC2R_DRC_ENA */
3288 #define WM8994_AIF1ADC2R_DRC_ENA_WIDTH               1  /* AIF1ADC2R_DRC_ENA */
3289 
3290 /*
3291  * R1105 (0x451) - AIF1 DRC2 (2)
3292  */
3293 #define WM8994_AIF1DRC2_ATK_MASK                0x1E00  /* AIF1DRC2_ATK - [12:9] */
3294 #define WM8994_AIF1DRC2_ATK_SHIFT                    9  /* AIF1DRC2_ATK - [12:9] */
3295 #define WM8994_AIF1DRC2_ATK_WIDTH                    4  /* AIF1DRC2_ATK - [12:9] */
3296 #define WM8994_AIF1DRC2_DCY_MASK                0x01E0  /* AIF1DRC2_DCY - [8:5] */
3297 #define WM8994_AIF1DRC2_DCY_SHIFT                    5  /* AIF1DRC2_DCY - [8:5] */
3298 #define WM8994_AIF1DRC2_DCY_WIDTH                    4  /* AIF1DRC2_DCY - [8:5] */
3299 #define WM8994_AIF1DRC2_MINGAIN_MASK            0x001C  /* AIF1DRC2_MINGAIN - [4:2] */
3300 #define WM8994_AIF1DRC2_MINGAIN_SHIFT                2  /* AIF1DRC2_MINGAIN - [4:2] */
3301 #define WM8994_AIF1DRC2_MINGAIN_WIDTH                3  /* AIF1DRC2_MINGAIN - [4:2] */
3302 #define WM8994_AIF1DRC2_MAXGAIN_MASK            0x0003  /* AIF1DRC2_MAXGAIN - [1:0] */
3303 #define WM8994_AIF1DRC2_MAXGAIN_SHIFT                0  /* AIF1DRC2_MAXGAIN - [1:0] */
3304 #define WM8994_AIF1DRC2_MAXGAIN_WIDTH                2  /* AIF1DRC2_MAXGAIN - [1:0] */
3305 
3306 /*
3307  * R1106 (0x452) - AIF1 DRC2 (3)
3308  */
3309 #define WM8994_AIF1DRC2_NG_MINGAIN_MASK         0xF000  /* AIF1DRC2_NG_MINGAIN - [15:12] */
3310 #define WM8994_AIF1DRC2_NG_MINGAIN_SHIFT            12  /* AIF1DRC2_NG_MINGAIN - [15:12] */
3311 #define WM8994_AIF1DRC2_NG_MINGAIN_WIDTH             4  /* AIF1DRC2_NG_MINGAIN - [15:12] */
3312 #define WM8994_AIF1DRC2_NG_EXP_MASK             0x0C00  /* AIF1DRC2_NG_EXP - [11:10] */
3313 #define WM8994_AIF1DRC2_NG_EXP_SHIFT                10  /* AIF1DRC2_NG_EXP - [11:10] */
3314 #define WM8994_AIF1DRC2_NG_EXP_WIDTH                 2  /* AIF1DRC2_NG_EXP - [11:10] */
3315 #define WM8994_AIF1DRC2_QR_THR_MASK             0x0300  /* AIF1DRC2_QR_THR - [9:8] */
3316 #define WM8994_AIF1DRC2_QR_THR_SHIFT                 8  /* AIF1DRC2_QR_THR - [9:8] */
3317 #define WM8994_AIF1DRC2_QR_THR_WIDTH                 2  /* AIF1DRC2_QR_THR - [9:8] */
3318 #define WM8994_AIF1DRC2_QR_DCY_MASK             0x00C0  /* AIF1DRC2_QR_DCY - [7:6] */
3319 #define WM8994_AIF1DRC2_QR_DCY_SHIFT                 6  /* AIF1DRC2_QR_DCY - [7:6] */
3320 #define WM8994_AIF1DRC2_QR_DCY_WIDTH                 2  /* AIF1DRC2_QR_DCY - [7:6] */
3321 #define WM8994_AIF1DRC2_HI_COMP_MASK            0x0038  /* AIF1DRC2_HI_COMP - [5:3] */
3322 #define WM8994_AIF1DRC2_HI_COMP_SHIFT                3  /* AIF1DRC2_HI_COMP - [5:3] */
3323 #define WM8994_AIF1DRC2_HI_COMP_WIDTH                3  /* AIF1DRC2_HI_COMP - [5:3] */
3324 #define WM8994_AIF1DRC2_LO_COMP_MASK            0x0007  /* AIF1DRC2_LO_COMP - [2:0] */
3325 #define WM8994_AIF1DRC2_LO_COMP_SHIFT                0  /* AIF1DRC2_LO_COMP - [2:0] */
3326 #define WM8994_AIF1DRC2_LO_COMP_WIDTH                3  /* AIF1DRC2_LO_COMP - [2:0] */
3327 
3328 /*
3329  * R1107 (0x453) - AIF1 DRC2 (4)
3330  */
3331 #define WM8994_AIF1DRC2_KNEE_IP_MASK            0x07E0  /* AIF1DRC2_KNEE_IP - [10:5] */
3332 #define WM8994_AIF1DRC2_KNEE_IP_SHIFT                5  /* AIF1DRC2_KNEE_IP - [10:5] */
3333 #define WM8994_AIF1DRC2_KNEE_IP_WIDTH                6  /* AIF1DRC2_KNEE_IP - [10:5] */
3334 #define WM8994_AIF1DRC2_KNEE_OP_MASK            0x001F  /* AIF1DRC2_KNEE_OP - [4:0] */
3335 #define WM8994_AIF1DRC2_KNEE_OP_SHIFT                0  /* AIF1DRC2_KNEE_OP - [4:0] */
3336 #define WM8994_AIF1DRC2_KNEE_OP_WIDTH                5  /* AIF1DRC2_KNEE_OP - [4:0] */
3337 
3338 /*
3339  * R1108 (0x454) - AIF1 DRC2 (5)
3340  */
3341 #define WM8994_AIF1DRC2_KNEE2_IP_MASK           0x03E0  /* AIF1DRC2_KNEE2_IP - [9:5] */
3342 #define WM8994_AIF1DRC2_KNEE2_IP_SHIFT               5  /* AIF1DRC2_KNEE2_IP - [9:5] */
3343 #define WM8994_AIF1DRC2_KNEE2_IP_WIDTH               5  /* AIF1DRC2_KNEE2_IP - [9:5] */
3344 #define WM8994_AIF1DRC2_KNEE2_OP_MASK           0x001F  /* AIF1DRC2_KNEE2_OP - [4:0] */
3345 #define WM8994_AIF1DRC2_KNEE2_OP_SHIFT               0  /* AIF1DRC2_KNEE2_OP - [4:0] */
3346 #define WM8994_AIF1DRC2_KNEE2_OP_WIDTH               5  /* AIF1DRC2_KNEE2_OP - [4:0] */
3347 
3348 /*
3349  * R1152 (0x480) - AIF1 DAC1 EQ Gains (1)
3350  */
3351 #define WM8994_AIF1DAC1_EQ_B1_GAIN_MASK         0xF800  /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
3352 #define WM8994_AIF1DAC1_EQ_B1_GAIN_SHIFT            11  /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
3353 #define WM8994_AIF1DAC1_EQ_B1_GAIN_WIDTH             5  /* AIF1DAC1_EQ_B1_GAIN - [15:11] */
3354 #define WM8994_AIF1DAC1_EQ_B2_GAIN_MASK         0x07C0  /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
3355 #define WM8994_AIF1DAC1_EQ_B2_GAIN_SHIFT             6  /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
3356 #define WM8994_AIF1DAC1_EQ_B2_GAIN_WIDTH             5  /* AIF1DAC1_EQ_B2_GAIN - [10:6] */
3357 #define WM8994_AIF1DAC1_EQ_B3_GAIN_MASK         0x003E  /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
3358 #define WM8994_AIF1DAC1_EQ_B3_GAIN_SHIFT             1  /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
3359 #define WM8994_AIF1DAC1_EQ_B3_GAIN_WIDTH             5  /* AIF1DAC1_EQ_B3_GAIN - [5:1] */
3360 #define WM8994_AIF1DAC1_EQ_ENA                  0x0001  /* AIF1DAC1_EQ_ENA */
3361 #define WM8994_AIF1DAC1_EQ_ENA_MASK             0x0001  /* AIF1DAC1_EQ_ENA */
3362 #define WM8994_AIF1DAC1_EQ_ENA_SHIFT                 0  /* AIF1DAC1_EQ_ENA */
3363 #define WM8994_AIF1DAC1_EQ_ENA_WIDTH                 1  /* AIF1DAC1_EQ_ENA */
3364 
3365 /*
3366  * R1153 (0x481) - AIF1 DAC1 EQ Gains (2)
3367  */
3368 #define WM8994_AIF1DAC1_EQ_B4_GAIN_MASK         0xF800  /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
3369 #define WM8994_AIF1DAC1_EQ_B4_GAIN_SHIFT            11  /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
3370 #define WM8994_AIF1DAC1_EQ_B4_GAIN_WIDTH             5  /* AIF1DAC1_EQ_B4_GAIN - [15:11] */
3371 #define WM8994_AIF1DAC1_EQ_B5_GAIN_MASK         0x07C0  /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
3372 #define WM8994_AIF1DAC1_EQ_B5_GAIN_SHIFT             6  /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
3373 #define WM8994_AIF1DAC1_EQ_B5_GAIN_WIDTH             5  /* AIF1DAC1_EQ_B5_GAIN - [10:6] */
3374 
3375 /*
3376  * R1154 (0x482) - AIF1 DAC1 EQ Band 1 A
3377  */
3378 #define WM8994_AIF1DAC1_EQ_B1_A_MASK            0xFFFF  /* AIF1DAC1_EQ_B1_A - [15:0] */
3379 #define WM8994_AIF1DAC1_EQ_B1_A_SHIFT                0  /* AIF1DAC1_EQ_B1_A - [15:0] */
3380 #define WM8994_AIF1DAC1_EQ_B1_A_WIDTH               16  /* AIF1DAC1_EQ_B1_A - [15:0] */
3381 
3382 /*
3383  * R1155 (0x483) - AIF1 DAC1 EQ Band 1 B
3384  */
3385 #define WM8994_AIF1DAC1_EQ_B1_B_MASK            0xFFFF  /* AIF1DAC1_EQ_B1_B - [15:0] */
3386 #define WM8994_AIF1DAC1_EQ_B1_B_SHIFT                0  /* AIF1DAC1_EQ_B1_B - [15:0] */
3387 #define WM8994_AIF1DAC1_EQ_B1_B_WIDTH               16  /* AIF1DAC1_EQ_B1_B - [15:0] */
3388 
3389 /*
3390  * R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG
3391  */
3392 #define WM8994_AIF1DAC1_EQ_B1_PG_MASK           0xFFFF  /* AIF1DAC1_EQ_B1_PG - [15:0] */
3393 #define WM8994_AIF1DAC1_EQ_B1_PG_SHIFT               0  /* AIF1DAC1_EQ_B1_PG - [15:0] */
3394 #define WM8994_AIF1DAC1_EQ_B1_PG_WIDTH              16  /* AIF1DAC1_EQ_B1_PG - [15:0] */
3395 
3396 /*
3397  * R1157 (0x485) - AIF1 DAC1 EQ Band 2 A
3398  */
3399 #define WM8994_AIF1DAC1_EQ_B2_A_MASK            0xFFFF  /* AIF1DAC1_EQ_B2_A - [15:0] */
3400 #define WM8994_AIF1DAC1_EQ_B2_A_SHIFT                0  /* AIF1DAC1_EQ_B2_A - [15:0] */
3401 #define WM8994_AIF1DAC1_EQ_B2_A_WIDTH               16  /* AIF1DAC1_EQ_B2_A - [15:0] */
3402 
3403 /*
3404  * R1158 (0x486) - AIF1 DAC1 EQ Band 2 B
3405  */
3406 #define WM8994_AIF1DAC1_EQ_B2_B_MASK            0xFFFF  /* AIF1DAC1_EQ_B2_B - [15:0] */
3407 #define WM8994_AIF1DAC1_EQ_B2_B_SHIFT                0  /* AIF1DAC1_EQ_B2_B - [15:0] */
3408 #define WM8994_AIF1DAC1_EQ_B2_B_WIDTH               16  /* AIF1DAC1_EQ_B2_B - [15:0] */
3409 
3410 /*
3411  * R1159 (0x487) - AIF1 DAC1 EQ Band 2 C
3412  */
3413 #define WM8994_AIF1DAC1_EQ_B2_C_MASK            0xFFFF  /* AIF1DAC1_EQ_B2_C - [15:0] */
3414 #define WM8994_AIF1DAC1_EQ_B2_C_SHIFT                0  /* AIF1DAC1_EQ_B2_C - [15:0] */
3415 #define WM8994_AIF1DAC1_EQ_B2_C_WIDTH               16  /* AIF1DAC1_EQ_B2_C - [15:0] */
3416 
3417 /*
3418  * R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG
3419  */
3420 #define WM8994_AIF1DAC1_EQ_B2_PG_MASK           0xFFFF  /* AIF1DAC1_EQ_B2_PG - [15:0] */
3421 #define WM8994_AIF1DAC1_EQ_B2_PG_SHIFT               0  /* AIF1DAC1_EQ_B2_PG - [15:0] */
3422 #define WM8994_AIF1DAC1_EQ_B2_PG_WIDTH              16  /* AIF1DAC1_EQ_B2_PG - [15:0] */
3423 
3424 /*
3425  * R1161 (0x489) - AIF1 DAC1 EQ Band 3 A
3426  */
3427 #define WM8994_AIF1DAC1_EQ_B3_A_MASK            0xFFFF  /* AIF1DAC1_EQ_B3_A - [15:0] */
3428 #define WM8994_AIF1DAC1_EQ_B3_A_SHIFT                0  /* AIF1DAC1_EQ_B3_A - [15:0] */
3429 #define WM8994_AIF1DAC1_EQ_B3_A_WIDTH               16  /* AIF1DAC1_EQ_B3_A - [15:0] */
3430 
3431 /*
3432  * R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B
3433  */
3434 #define WM8994_AIF1DAC1_EQ_B3_B_MASK            0xFFFF  /* AIF1DAC1_EQ_B3_B - [15:0] */
3435 #define WM8994_AIF1DAC1_EQ_B3_B_SHIFT                0  /* AIF1DAC1_EQ_B3_B - [15:0] */
3436 #define WM8994_AIF1DAC1_EQ_B3_B_WIDTH               16  /* AIF1DAC1_EQ_B3_B - [15:0] */
3437 
3438 /*
3439  * R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C
3440  */
3441 #define WM8994_AIF1DAC1_EQ_B3_C_MASK            0xFFFF  /* AIF1DAC1_EQ_B3_C - [15:0] */
3442 #define WM8994_AIF1DAC1_EQ_B3_C_SHIFT                0  /* AIF1DAC1_EQ_B3_C - [15:0] */
3443 #define WM8994_AIF1DAC1_EQ_B3_C_WIDTH               16  /* AIF1DAC1_EQ_B3_C - [15:0] */
3444 
3445 /*
3446  * R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG
3447  */
3448 #define WM8994_AIF1DAC1_EQ_B3_PG_MASK           0xFFFF  /* AIF1DAC1_EQ_B3_PG - [15:0] */
3449 #define WM8994_AIF1DAC1_EQ_B3_PG_SHIFT               0  /* AIF1DAC1_EQ_B3_PG - [15:0] */
3450 #define WM8994_AIF1DAC1_EQ_B3_PG_WIDTH              16  /* AIF1DAC1_EQ_B3_PG - [15:0] */
3451 
3452 /*
3453  * R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A
3454  */
3455 #define WM8994_AIF1DAC1_EQ_B4_A_MASK            0xFFFF  /* AIF1DAC1_EQ_B4_A - [15:0] */
3456 #define WM8994_AIF1DAC1_EQ_B4_A_SHIFT                0  /* AIF1DAC1_EQ_B4_A - [15:0] */
3457 #define WM8994_AIF1DAC1_EQ_B4_A_WIDTH               16  /* AIF1DAC1_EQ_B4_A - [15:0] */
3458 
3459 /*
3460  * R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B
3461  */
3462 #define WM8994_AIF1DAC1_EQ_B4_B_MASK            0xFFFF  /* AIF1DAC1_EQ_B4_B - [15:0] */
3463 #define WM8994_AIF1DAC1_EQ_B4_B_SHIFT                0  /* AIF1DAC1_EQ_B4_B - [15:0] */
3464 #define WM8994_AIF1DAC1_EQ_B4_B_WIDTH               16  /* AIF1DAC1_EQ_B4_B - [15:0] */
3465 
3466 /*
3467  * R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C
3468  */
3469 #define WM8994_AIF1DAC1_EQ_B4_C_MASK            0xFFFF  /* AIF1DAC1_EQ_B4_C - [15:0] */
3470 #define WM8994_AIF1DAC1_EQ_B4_C_SHIFT                0  /* AIF1DAC1_EQ_B4_C - [15:0] */
3471 #define WM8994_AIF1DAC1_EQ_B4_C_WIDTH               16  /* AIF1DAC1_EQ_B4_C - [15:0] */
3472 
3473 /*
3474  * R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG
3475  */
3476 #define WM8994_AIF1DAC1_EQ_B4_PG_MASK           0xFFFF  /* AIF1DAC1_EQ_B4_PG - [15:0] */
3477 #define WM8994_AIF1DAC1_EQ_B4_PG_SHIFT               0  /* AIF1DAC1_EQ_B4_PG - [15:0] */
3478 #define WM8994_AIF1DAC1_EQ_B4_PG_WIDTH              16  /* AIF1DAC1_EQ_B4_PG - [15:0] */
3479 
3480 /*
3481  * R1169 (0x491) - AIF1 DAC1 EQ Band 5 A
3482  */
3483 #define WM8994_AIF1DAC1_EQ_B5_A_MASK            0xFFFF  /* AIF1DAC1_EQ_B5_A - [15:0] */
3484 #define WM8994_AIF1DAC1_EQ_B5_A_SHIFT                0  /* AIF1DAC1_EQ_B5_A - [15:0] */
3485 #define WM8994_AIF1DAC1_EQ_B5_A_WIDTH               16  /* AIF1DAC1_EQ_B5_A - [15:0] */
3486 
3487 /*
3488  * R1170 (0x492) - AIF1 DAC1 EQ Band 5 B
3489  */
3490 #define WM8994_AIF1DAC1_EQ_B5_B_MASK            0xFFFF  /* AIF1DAC1_EQ_B5_B - [15:0] */
3491 #define WM8994_AIF1DAC1_EQ_B5_B_SHIFT                0  /* AIF1DAC1_EQ_B5_B - [15:0] */
3492 #define WM8994_AIF1DAC1_EQ_B5_B_WIDTH               16  /* AIF1DAC1_EQ_B5_B - [15:0] */
3493 
3494 /*
3495  * R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG
3496  */
3497 #define WM8994_AIF1DAC1_EQ_B5_PG_MASK           0xFFFF  /* AIF1DAC1_EQ_B5_PG - [15:0] */
3498 #define WM8994_AIF1DAC1_EQ_B5_PG_SHIFT               0  /* AIF1DAC1_EQ_B5_PG - [15:0] */
3499 #define WM8994_AIF1DAC1_EQ_B5_PG_WIDTH              16  /* AIF1DAC1_EQ_B5_PG - [15:0] */
3500 
3501 /*
3502  * R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1)
3503  */
3504 #define WM8994_AIF1DAC2_EQ_B1_GAIN_MASK         0xF800  /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
3505 #define WM8994_AIF1DAC2_EQ_B1_GAIN_SHIFT            11  /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
3506 #define WM8994_AIF1DAC2_EQ_B1_GAIN_WIDTH             5  /* AIF1DAC2_EQ_B1_GAIN - [15:11] */
3507 #define WM8994_AIF1DAC2_EQ_B2_GAIN_MASK         0x07C0  /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
3508 #define WM8994_AIF1DAC2_EQ_B2_GAIN_SHIFT             6  /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
3509 #define WM8994_AIF1DAC2_EQ_B2_GAIN_WIDTH             5  /* AIF1DAC2_EQ_B2_GAIN - [10:6] */
3510 #define WM8994_AIF1DAC2_EQ_B3_GAIN_MASK         0x003E  /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
3511 #define WM8994_AIF1DAC2_EQ_B3_GAIN_SHIFT             1  /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
3512 #define WM8994_AIF1DAC2_EQ_B3_GAIN_WIDTH             5  /* AIF1DAC2_EQ_B3_GAIN - [5:1] */
3513 #define WM8994_AIF1DAC2_EQ_ENA                  0x0001  /* AIF1DAC2_EQ_ENA */
3514 #define WM8994_AIF1DAC2_EQ_ENA_MASK             0x0001  /* AIF1DAC2_EQ_ENA */
3515 #define WM8994_AIF1DAC2_EQ_ENA_SHIFT                 0  /* AIF1DAC2_EQ_ENA */
3516 #define WM8994_AIF1DAC2_EQ_ENA_WIDTH                 1  /* AIF1DAC2_EQ_ENA */
3517 
3518 /*
3519  * R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2)
3520  */
3521 #define WM8994_AIF1DAC2_EQ_B4_GAIN_MASK         0xF800  /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
3522 #define WM8994_AIF1DAC2_EQ_B4_GAIN_SHIFT            11  /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
3523 #define WM8994_AIF1DAC2_EQ_B4_GAIN_WIDTH             5  /* AIF1DAC2_EQ_B4_GAIN - [15:11] */
3524 #define WM8994_AIF1DAC2_EQ_B5_GAIN_MASK         0x07C0  /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
3525 #define WM8994_AIF1DAC2_EQ_B5_GAIN_SHIFT             6  /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
3526 #define WM8994_AIF1DAC2_EQ_B5_GAIN_WIDTH             5  /* AIF1DAC2_EQ_B5_GAIN - [10:6] */
3527 
3528 /*
3529  * R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A
3530  */
3531 #define WM8994_AIF1DAC2_EQ_B1_A_MASK            0xFFFF  /* AIF1DAC2_EQ_B1_A - [15:0] */
3532 #define WM8994_AIF1DAC2_EQ_B1_A_SHIFT                0  /* AIF1DAC2_EQ_B1_A - [15:0] */
3533 #define WM8994_AIF1DAC2_EQ_B1_A_WIDTH               16  /* AIF1DAC2_EQ_B1_A - [15:0] */
3534 
3535 /*
3536  * R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B
3537  */
3538 #define WM8994_AIF1DAC2_EQ_B1_B_MASK            0xFFFF  /* AIF1DAC2_EQ_B1_B - [15:0] */
3539 #define WM8994_AIF1DAC2_EQ_B1_B_SHIFT                0  /* AIF1DAC2_EQ_B1_B - [15:0] */
3540 #define WM8994_AIF1DAC2_EQ_B1_B_WIDTH               16  /* AIF1DAC2_EQ_B1_B - [15:0] */
3541 
3542 /*
3543  * R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG
3544  */
3545 #define WM8994_AIF1DAC2_EQ_B1_PG_MASK           0xFFFF  /* AIF1DAC2_EQ_B1_PG - [15:0] */
3546 #define WM8994_AIF1DAC2_EQ_B1_PG_SHIFT               0  /* AIF1DAC2_EQ_B1_PG - [15:0] */
3547 #define WM8994_AIF1DAC2_EQ_B1_PG_WIDTH              16  /* AIF1DAC2_EQ_B1_PG - [15:0] */
3548 
3549 /*
3550  * R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A
3551  */
3552 #define WM8994_AIF1DAC2_EQ_B2_A_MASK            0xFFFF  /* AIF1DAC2_EQ_B2_A - [15:0] */
3553 #define WM8994_AIF1DAC2_EQ_B2_A_SHIFT                0  /* AIF1DAC2_EQ_B2_A - [15:0] */
3554 #define WM8994_AIF1DAC2_EQ_B2_A_WIDTH               16  /* AIF1DAC2_EQ_B2_A - [15:0] */
3555 
3556 /*
3557  * R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B
3558  */
3559 #define WM8994_AIF1DAC2_EQ_B2_B_MASK            0xFFFF  /* AIF1DAC2_EQ_B2_B - [15:0] */
3560 #define WM8994_AIF1DAC2_EQ_B2_B_SHIFT                0  /* AIF1DAC2_EQ_B2_B - [15:0] */
3561 #define WM8994_AIF1DAC2_EQ_B2_B_WIDTH               16  /* AIF1DAC2_EQ_B2_B - [15:0] */
3562 
3563 /*
3564  * R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C
3565  */
3566 #define WM8994_AIF1DAC2_EQ_B2_C_MASK            0xFFFF  /* AIF1DAC2_EQ_B2_C - [15:0] */
3567 #define WM8994_AIF1DAC2_EQ_B2_C_SHIFT                0  /* AIF1DAC2_EQ_B2_C - [15:0] */
3568 #define WM8994_AIF1DAC2_EQ_B2_C_WIDTH               16  /* AIF1DAC2_EQ_B2_C - [15:0] */
3569 
3570 /*
3571  * R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG
3572  */
3573 #define WM8994_AIF1DAC2_EQ_B2_PG_MASK           0xFFFF  /* AIF1DAC2_EQ_B2_PG - [15:0] */
3574 #define WM8994_AIF1DAC2_EQ_B2_PG_SHIFT               0  /* AIF1DAC2_EQ_B2_PG - [15:0] */
3575 #define WM8994_AIF1DAC2_EQ_B2_PG_WIDTH              16  /* AIF1DAC2_EQ_B2_PG - [15:0] */
3576 
3577 /*
3578  * R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A
3579  */
3580 #define WM8994_AIF1DAC2_EQ_B3_A_MASK            0xFFFF  /* AIF1DAC2_EQ_B3_A - [15:0] */
3581 #define WM8994_AIF1DAC2_EQ_B3_A_SHIFT                0  /* AIF1DAC2_EQ_B3_A - [15:0] */
3582 #define WM8994_AIF1DAC2_EQ_B3_A_WIDTH               16  /* AIF1DAC2_EQ_B3_A - [15:0] */
3583 
3584 /*
3585  * R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B
3586  */
3587 #define WM8994_AIF1DAC2_EQ_B3_B_MASK            0xFFFF  /* AIF1DAC2_EQ_B3_B - [15:0] */
3588 #define WM8994_AIF1DAC2_EQ_B3_B_SHIFT                0  /* AIF1DAC2_EQ_B3_B - [15:0] */
3589 #define WM8994_AIF1DAC2_EQ_B3_B_WIDTH               16  /* AIF1DAC2_EQ_B3_B - [15:0] */
3590 
3591 /*
3592  * R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C
3593  */
3594 #define WM8994_AIF1DAC2_EQ_B3_C_MASK            0xFFFF  /* AIF1DAC2_EQ_B3_C - [15:0] */
3595 #define WM8994_AIF1DAC2_EQ_B3_C_SHIFT                0  /* AIF1DAC2_EQ_B3_C - [15:0] */
3596 #define WM8994_AIF1DAC2_EQ_B3_C_WIDTH               16  /* AIF1DAC2_EQ_B3_C - [15:0] */
3597 
3598 /*
3599  * R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG
3600  */
3601 #define WM8994_AIF1DAC2_EQ_B3_PG_MASK           0xFFFF  /* AIF1DAC2_EQ_B3_PG - [15:0] */
3602 #define WM8994_AIF1DAC2_EQ_B3_PG_SHIFT               0  /* AIF1DAC2_EQ_B3_PG - [15:0] */
3603 #define WM8994_AIF1DAC2_EQ_B3_PG_WIDTH              16  /* AIF1DAC2_EQ_B3_PG - [15:0] */
3604 
3605 /*
3606  * R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A
3607  */
3608 #define WM8994_AIF1DAC2_EQ_B4_A_MASK            0xFFFF  /* AIF1DAC2_EQ_B4_A - [15:0] */
3609 #define WM8994_AIF1DAC2_EQ_B4_A_SHIFT                0  /* AIF1DAC2_EQ_B4_A - [15:0] */
3610 #define WM8994_AIF1DAC2_EQ_B4_A_WIDTH               16  /* AIF1DAC2_EQ_B4_A - [15:0] */
3611 
3612 /*
3613  * R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B
3614  */
3615 #define WM8994_AIF1DAC2_EQ_B4_B_MASK            0xFFFF  /* AIF1DAC2_EQ_B4_B - [15:0] */
3616 #define WM8994_AIF1DAC2_EQ_B4_B_SHIFT                0  /* AIF1DAC2_EQ_B4_B - [15:0] */
3617 #define WM8994_AIF1DAC2_EQ_B4_B_WIDTH               16  /* AIF1DAC2_EQ_B4_B - [15:0] */
3618 
3619 /*
3620  * R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C
3621  */
3622 #define WM8994_AIF1DAC2_EQ_B4_C_MASK            0xFFFF  /* AIF1DAC2_EQ_B4_C - [15:0] */
3623 #define WM8994_AIF1DAC2_EQ_B4_C_SHIFT                0  /* AIF1DAC2_EQ_B4_C - [15:0] */
3624 #define WM8994_AIF1DAC2_EQ_B4_C_WIDTH               16  /* AIF1DAC2_EQ_B4_C - [15:0] */
3625 
3626 /*
3627  * R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG
3628  */
3629 #define WM8994_AIF1DAC2_EQ_B4_PG_MASK           0xFFFF  /* AIF1DAC2_EQ_B4_PG - [15:0] */
3630 #define WM8994_AIF1DAC2_EQ_B4_PG_SHIFT               0  /* AIF1DAC2_EQ_B4_PG - [15:0] */
3631 #define WM8994_AIF1DAC2_EQ_B4_PG_WIDTH              16  /* AIF1DAC2_EQ_B4_PG - [15:0] */
3632 
3633 /*
3634  * R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A
3635  */
3636 #define WM8994_AIF1DAC2_EQ_B5_A_MASK            0xFFFF  /* AIF1DAC2_EQ_B5_A - [15:0] */
3637 #define WM8994_AIF1DAC2_EQ_B5_A_SHIFT                0  /* AIF1DAC2_EQ_B5_A - [15:0] */
3638 #define WM8994_AIF1DAC2_EQ_B5_A_WIDTH               16  /* AIF1DAC2_EQ_B5_A - [15:0] */
3639 
3640 /*
3641  * R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B
3642  */
3643 #define WM8994_AIF1DAC2_EQ_B5_B_MASK            0xFFFF  /* AIF1DAC2_EQ_B5_B - [15:0] */
3644 #define WM8994_AIF1DAC2_EQ_B5_B_SHIFT                0  /* AIF1DAC2_EQ_B5_B - [15:0] */
3645 #define WM8994_AIF1DAC2_EQ_B5_B_WIDTH               16  /* AIF1DAC2_EQ_B5_B - [15:0] */
3646 
3647 /*
3648  * R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG
3649  */
3650 #define WM8994_AIF1DAC2_EQ_B5_PG_MASK           0xFFFF  /* AIF1DAC2_EQ_B5_PG - [15:0] */
3651 #define WM8994_AIF1DAC2_EQ_B5_PG_SHIFT               0  /* AIF1DAC2_EQ_B5_PG - [15:0] */
3652 #define WM8994_AIF1DAC2_EQ_B5_PG_WIDTH              16  /* AIF1DAC2_EQ_B5_PG - [15:0] */
3653 
3654 /*
3655  * R1280 (0x500) - AIF2 ADC Left Volume
3656  */
3657 #define WM8994_AIF2ADC_VU                       0x0100  /* AIF2ADC_VU */
3658 #define WM8994_AIF2ADC_VU_MASK                  0x0100  /* AIF2ADC_VU */
3659 #define WM8994_AIF2ADC_VU_SHIFT                      8  /* AIF2ADC_VU */
3660 #define WM8994_AIF2ADC_VU_WIDTH                      1  /* AIF2ADC_VU */
3661 #define WM8994_AIF2ADCL_VOL_MASK                0x00FF  /* AIF2ADCL_VOL - [7:0] */
3662 #define WM8994_AIF2ADCL_VOL_SHIFT                    0  /* AIF2ADCL_VOL - [7:0] */
3663 #define WM8994_AIF2ADCL_VOL_WIDTH                    8  /* AIF2ADCL_VOL - [7:0] */
3664 
3665 /*
3666  * R1281 (0x501) - AIF2 ADC Right Volume
3667  */
3668 #define WM8994_AIF2ADC_VU                       0x0100  /* AIF2ADC_VU */
3669 #define WM8994_AIF2ADC_VU_MASK                  0x0100  /* AIF2ADC_VU */
3670 #define WM8994_AIF2ADC_VU_SHIFT                      8  /* AIF2ADC_VU */
3671 #define WM8994_AIF2ADC_VU_WIDTH                      1  /* AIF2ADC_VU */
3672 #define WM8994_AIF2ADCR_VOL_MASK                0x00FF  /* AIF2ADCR_VOL - [7:0] */
3673 #define WM8994_AIF2ADCR_VOL_SHIFT                    0  /* AIF2ADCR_VOL - [7:0] */
3674 #define WM8994_AIF2ADCR_VOL_WIDTH                    8  /* AIF2ADCR_VOL - [7:0] */
3675 
3676 /*
3677  * R1282 (0x502) - AIF2 DAC Left Volume
3678  */
3679 #define WM8994_AIF2DAC_VU                       0x0100  /* AIF2DAC_VU */
3680 #define WM8994_AIF2DAC_VU_MASK                  0x0100  /* AIF2DAC_VU */
3681 #define WM8994_AIF2DAC_VU_SHIFT                      8  /* AIF2DAC_VU */
3682 #define WM8994_AIF2DAC_VU_WIDTH                      1  /* AIF2DAC_VU */
3683 #define WM8994_AIF2DACL_VOL_MASK                0x00FF  /* AIF2DACL_VOL - [7:0] */
3684 #define WM8994_AIF2DACL_VOL_SHIFT                    0  /* AIF2DACL_VOL - [7:0] */
3685 #define WM8994_AIF2DACL_VOL_WIDTH                    8  /* AIF2DACL_VOL - [7:0] */
3686 
3687 /*
3688  * R1283 (0x503) - AIF2 DAC Right Volume
3689  */
3690 #define WM8994_AIF2DAC_VU                       0x0100  /* AIF2DAC_VU */
3691 #define WM8994_AIF2DAC_VU_MASK                  0x0100  /* AIF2DAC_VU */
3692 #define WM8994_AIF2DAC_VU_SHIFT                      8  /* AIF2DAC_VU */
3693 #define WM8994_AIF2DAC_VU_WIDTH                      1  /* AIF2DAC_VU */
3694 #define WM8994_AIF2DACR_VOL_MASK                0x00FF  /* AIF2DACR_VOL - [7:0] */
3695 #define WM8994_AIF2DACR_VOL_SHIFT                    0  /* AIF2DACR_VOL - [7:0] */
3696 #define WM8994_AIF2DACR_VOL_WIDTH                    8  /* AIF2DACR_VOL - [7:0] */
3697 
3698 /*
3699  * R1296 (0x510) - AIF2 ADC Filters
3700  */
3701 #define WM8994_AIF2ADC_4FS                      0x8000  /* AIF2ADC_4FS */
3702 #define WM8994_AIF2ADC_4FS_MASK                 0x8000  /* AIF2ADC_4FS */
3703 #define WM8994_AIF2ADC_4FS_SHIFT                    15  /* AIF2ADC_4FS */
3704 #define WM8994_AIF2ADC_4FS_WIDTH                     1  /* AIF2ADC_4FS */
3705 #define WM8994_AIF2ADC_HPF_CUT_MASK             0x6000  /* AIF2ADC_HPF_CUT - [14:13] */
3706 #define WM8994_AIF2ADC_HPF_CUT_SHIFT                13  /* AIF2ADC_HPF_CUT - [14:13] */
3707 #define WM8994_AIF2ADC_HPF_CUT_WIDTH                 2  /* AIF2ADC_HPF_CUT - [14:13] */
3708 #define WM8994_AIF2ADCL_HPF                     0x1000  /* AIF2ADCL_HPF */
3709 #define WM8994_AIF2ADCL_HPF_MASK                0x1000  /* AIF2ADCL_HPF */
3710 #define WM8994_AIF2ADCL_HPF_SHIFT                   12  /* AIF2ADCL_HPF */
3711 #define WM8994_AIF2ADCL_HPF_WIDTH                    1  /* AIF2ADCL_HPF */
3712 #define WM8994_AIF2ADCR_HPF                     0x0800  /* AIF2ADCR_HPF */
3713 #define WM8994_AIF2ADCR_HPF_MASK                0x0800  /* AIF2ADCR_HPF */
3714 #define WM8994_AIF2ADCR_HPF_SHIFT                   11  /* AIF2ADCR_HPF */
3715 #define WM8994_AIF2ADCR_HPF_WIDTH                    1  /* AIF2ADCR_HPF */
3716 
3717 /*
3718  * R1312 (0x520) - AIF2 DAC Filters (1)
3719  */
3720 #define WM8994_AIF2DAC_MUTE                     0x0200  /* AIF2DAC_MUTE */
3721 #define WM8994_AIF2DAC_MUTE_MASK                0x0200  /* AIF2DAC_MUTE */
3722 #define WM8994_AIF2DAC_MUTE_SHIFT                    9  /* AIF2DAC_MUTE */
3723 #define WM8994_AIF2DAC_MUTE_WIDTH                    1  /* AIF2DAC_MUTE */
3724 #define WM8994_AIF2DAC_MONO                     0x0080  /* AIF2DAC_MONO */
3725 #define WM8994_AIF2DAC_MONO_MASK                0x0080  /* AIF2DAC_MONO */
3726 #define WM8994_AIF2DAC_MONO_SHIFT                    7  /* AIF2DAC_MONO */
3727 #define WM8994_AIF2DAC_MONO_WIDTH                    1  /* AIF2DAC_MONO */
3728 #define WM8994_AIF2DAC_MUTERATE                 0x0020  /* AIF2DAC_MUTERATE */
3729 #define WM8994_AIF2DAC_MUTERATE_MASK            0x0020  /* AIF2DAC_MUTERATE */
3730 #define WM8994_AIF2DAC_MUTERATE_SHIFT                5  /* AIF2DAC_MUTERATE */
3731 #define WM8994_AIF2DAC_MUTERATE_WIDTH                1  /* AIF2DAC_MUTERATE */
3732 #define WM8994_AIF2DAC_UNMUTE_RAMP              0x0010  /* AIF2DAC_UNMUTE_RAMP */
3733 #define WM8994_AIF2DAC_UNMUTE_RAMP_MASK         0x0010  /* AIF2DAC_UNMUTE_RAMP */
3734 #define WM8994_AIF2DAC_UNMUTE_RAMP_SHIFT             4  /* AIF2DAC_UNMUTE_RAMP */
3735 #define WM8994_AIF2DAC_UNMUTE_RAMP_WIDTH             1  /* AIF2DAC_UNMUTE_RAMP */
3736 #define WM8994_AIF2DAC_DEEMP_MASK               0x0006  /* AIF2DAC_DEEMP - [2:1] */
3737 #define WM8994_AIF2DAC_DEEMP_SHIFT                   1  /* AIF2DAC_DEEMP - [2:1] */
3738 #define WM8994_AIF2DAC_DEEMP_WIDTH                   2  /* AIF2DAC_DEEMP - [2:1] */
3739 
3740 /*
3741  * R1313 (0x521) - AIF2 DAC Filters (2)
3742  */
3743 #define WM8994_AIF2DAC_3D_GAIN_MASK             0x3E00  /* AIF2DAC_3D_GAIN - [13:9] */
3744 #define WM8994_AIF2DAC_3D_GAIN_SHIFT                 9  /* AIF2DAC_3D_GAIN - [13:9] */
3745 #define WM8994_AIF2DAC_3D_GAIN_WIDTH                 5  /* AIF2DAC_3D_GAIN - [13:9] */
3746 #define WM8994_AIF2DAC_3D_ENA                   0x0100  /* AIF2DAC_3D_ENA */
3747 #define WM8994_AIF2DAC_3D_ENA_MASK              0x0100  /* AIF2DAC_3D_ENA */
3748 #define WM8994_AIF2DAC_3D_ENA_SHIFT                  8  /* AIF2DAC_3D_ENA */
3749 #define WM8994_AIF2DAC_3D_ENA_WIDTH                  1  /* AIF2DAC_3D_ENA */
3750 
3751 /*
3752  * R1328 (0x530) - AIF2 DAC Noise Gate
3753  */
3754 #define WM8958_AIF2DAC_NG_HLD_MASK              0x0060  /* AIF2DAC_NG_HLD - [6:5] */
3755 #define WM8958_AIF2DAC_NG_HLD_SHIFT                  5  /* AIF2DAC_NG_HLD - [6:5] */
3756 #define WM8958_AIF2DAC_NG_HLD_WIDTH                  2  /* AIF2DAC_NG_HLD - [6:5] */
3757 #define WM8958_AIF2DAC_NG_THR_MASK              0x000E  /* AIF2DAC_NG_THR - [3:1] */
3758 #define WM8958_AIF2DAC_NG_THR_SHIFT                  1  /* AIF2DAC_NG_THR - [3:1] */
3759 #define WM8958_AIF2DAC_NG_THR_WIDTH                  3  /* AIF2DAC_NG_THR - [3:1] */
3760 #define WM8958_AIF2DAC_NG_ENA                   0x0001  /* AIF2DAC_NG_ENA */
3761 #define WM8958_AIF2DAC_NG_ENA_MASK              0x0001  /* AIF2DAC_NG_ENA */
3762 #define WM8958_AIF2DAC_NG_ENA_SHIFT                  0  /* AIF2DAC_NG_ENA */
3763 #define WM8958_AIF2DAC_NG_ENA_WIDTH                  1  /* AIF2DAC_NG_ENA */
3764 
3765 /*
3766  * R1344 (0x540) - AIF2 DRC (1)
3767  */
3768 #define WM8994_AIF2DRC_SIG_DET_RMS_MASK         0xF800  /* AIF2DRC_SIG_DET_RMS - [15:11] */
3769 #define WM8994_AIF2DRC_SIG_DET_RMS_SHIFT            11  /* AIF2DRC_SIG_DET_RMS - [15:11] */
3770 #define WM8994_AIF2DRC_SIG_DET_RMS_WIDTH             5  /* AIF2DRC_SIG_DET_RMS - [15:11] */
3771 #define WM8994_AIF2DRC_SIG_DET_PK_MASK          0x0600  /* AIF2DRC_SIG_DET_PK - [10:9] */
3772 #define WM8994_AIF2DRC_SIG_DET_PK_SHIFT              9  /* AIF2DRC_SIG_DET_PK - [10:9] */
3773 #define WM8994_AIF2DRC_SIG_DET_PK_WIDTH              2  /* AIF2DRC_SIG_DET_PK - [10:9] */
3774 #define WM8994_AIF2DRC_NG_ENA                   0x0100  /* AIF2DRC_NG_ENA */
3775 #define WM8994_AIF2DRC_NG_ENA_MASK              0x0100  /* AIF2DRC_NG_ENA */
3776 #define WM8994_AIF2DRC_NG_ENA_SHIFT                  8  /* AIF2DRC_NG_ENA */
3777 #define WM8994_AIF2DRC_NG_ENA_WIDTH                  1  /* AIF2DRC_NG_ENA */
3778 #define WM8994_AIF2DRC_SIG_DET_MODE             0x0080  /* AIF2DRC_SIG_DET_MODE */
3779 #define WM8994_AIF2DRC_SIG_DET_MODE_MASK        0x0080  /* AIF2DRC_SIG_DET_MODE */
3780 #define WM8994_AIF2DRC_SIG_DET_MODE_SHIFT            7  /* AIF2DRC_SIG_DET_MODE */
3781 #define WM8994_AIF2DRC_SIG_DET_MODE_WIDTH            1  /* AIF2DRC_SIG_DET_MODE */
3782 #define WM8994_AIF2DRC_SIG_DET                  0x0040  /* AIF2DRC_SIG_DET */
3783 #define WM8994_AIF2DRC_SIG_DET_MASK             0x0040  /* AIF2DRC_SIG_DET */
3784 #define WM8994_AIF2DRC_SIG_DET_SHIFT                 6  /* AIF2DRC_SIG_DET */
3785 #define WM8994_AIF2DRC_SIG_DET_WIDTH                 1  /* AIF2DRC_SIG_DET */
3786 #define WM8994_AIF2DRC_KNEE2_OP_ENA             0x0020  /* AIF2DRC_KNEE2_OP_ENA */
3787 #define WM8994_AIF2DRC_KNEE2_OP_ENA_MASK        0x0020  /* AIF2DRC_KNEE2_OP_ENA */
3788 #define WM8994_AIF2DRC_KNEE2_OP_ENA_SHIFT            5  /* AIF2DRC_KNEE2_OP_ENA */
3789 #define WM8994_AIF2DRC_KNEE2_OP_ENA_WIDTH            1  /* AIF2DRC_KNEE2_OP_ENA */
3790 #define WM8994_AIF2DRC_QR                       0x0010  /* AIF2DRC_QR */
3791 #define WM8994_AIF2DRC_QR_MASK                  0x0010  /* AIF2DRC_QR */
3792 #define WM8994_AIF2DRC_QR_SHIFT                      4  /* AIF2DRC_QR */
3793 #define WM8994_AIF2DRC_QR_WIDTH                      1  /* AIF2DRC_QR */
3794 #define WM8994_AIF2DRC_ANTICLIP                 0x0008  /* AIF2DRC_ANTICLIP */
3795 #define WM8994_AIF2DRC_ANTICLIP_MASK            0x0008  /* AIF2DRC_ANTICLIP */
3796 #define WM8994_AIF2DRC_ANTICLIP_SHIFT                3  /* AIF2DRC_ANTICLIP */
3797 #define WM8994_AIF2DRC_ANTICLIP_WIDTH                1  /* AIF2DRC_ANTICLIP */
3798 #define WM8994_AIF2DAC_DRC_ENA                  0x0004  /* AIF2DAC_DRC_ENA */
3799 #define WM8994_AIF2DAC_DRC_ENA_MASK             0x0004  /* AIF2DAC_DRC_ENA */
3800 #define WM8994_AIF2DAC_DRC_ENA_SHIFT                 2  /* AIF2DAC_DRC_ENA */
3801 #define WM8994_AIF2DAC_DRC_ENA_WIDTH                 1  /* AIF2DAC_DRC_ENA */
3802 #define WM8994_AIF2ADCL_DRC_ENA                 0x0002  /* AIF2ADCL_DRC_ENA */
3803 #define WM8994_AIF2ADCL_DRC_ENA_MASK            0x0002  /* AIF2ADCL_DRC_ENA */
3804 #define WM8994_AIF2ADCL_DRC_ENA_SHIFT                1  /* AIF2ADCL_DRC_ENA */
3805 #define WM8994_AIF2ADCL_DRC_ENA_WIDTH                1  /* AIF2ADCL_DRC_ENA */
3806 #define WM8994_AIF2ADCR_DRC_ENA                 0x0001  /* AIF2ADCR_DRC_ENA */
3807 #define WM8994_AIF2ADCR_DRC_ENA_MASK            0x0001  /* AIF2ADCR_DRC_ENA */
3808 #define WM8994_AIF2ADCR_DRC_ENA_SHIFT                0  /* AIF2ADCR_DRC_ENA */
3809 #define WM8994_AIF2ADCR_DRC_ENA_WIDTH                1  /* AIF2ADCR_DRC_ENA */
3810 
3811 /*
3812  * R1345 (0x541) - AIF2 DRC (2)
3813  */
3814 #define WM8994_AIF2DRC_ATK_MASK                 0x1E00  /* AIF2DRC_ATK - [12:9] */
3815 #define WM8994_AIF2DRC_ATK_SHIFT                     9  /* AIF2DRC_ATK - [12:9] */
3816 #define WM8994_AIF2DRC_ATK_WIDTH                     4  /* AIF2DRC_ATK - [12:9] */
3817 #define WM8994_AIF2DRC_DCY_MASK                 0x01E0  /* AIF2DRC_DCY - [8:5] */
3818 #define WM8994_AIF2DRC_DCY_SHIFT                     5  /* AIF2DRC_DCY - [8:5] */
3819 #define WM8994_AIF2DRC_DCY_WIDTH                     4  /* AIF2DRC_DCY - [8:5] */
3820 #define WM8994_AIF2DRC_MINGAIN_MASK             0x001C  /* AIF2DRC_MINGAIN - [4:2] */
3821 #define WM8994_AIF2DRC_MINGAIN_SHIFT                 2  /* AIF2DRC_MINGAIN - [4:2] */
3822 #define WM8994_AIF2DRC_MINGAIN_WIDTH                 3  /* AIF2DRC_MINGAIN - [4:2] */
3823 #define WM8994_AIF2DRC_MAXGAIN_MASK             0x0003  /* AIF2DRC_MAXGAIN - [1:0] */
3824 #define WM8994_AIF2DRC_MAXGAIN_SHIFT                 0  /* AIF2DRC_MAXGAIN - [1:0] */
3825 #define WM8994_AIF2DRC_MAXGAIN_WIDTH                 2  /* AIF2DRC_MAXGAIN - [1:0] */
3826 
3827 /*
3828  * R1346 (0x542) - AIF2 DRC (3)
3829  */
3830 #define WM8994_AIF2DRC_NG_MINGAIN_MASK          0xF000  /* AIF2DRC_NG_MINGAIN - [15:12] */
3831 #define WM8994_AIF2DRC_NG_MINGAIN_SHIFT             12  /* AIF2DRC_NG_MINGAIN - [15:12] */
3832 #define WM8994_AIF2DRC_NG_MINGAIN_WIDTH              4  /* AIF2DRC_NG_MINGAIN - [15:12] */
3833 #define WM8994_AIF2DRC_NG_EXP_MASK              0x0C00  /* AIF2DRC_NG_EXP - [11:10] */
3834 #define WM8994_AIF2DRC_NG_EXP_SHIFT                 10  /* AIF2DRC_NG_EXP - [11:10] */
3835 #define WM8994_AIF2DRC_NG_EXP_WIDTH                  2  /* AIF2DRC_NG_EXP - [11:10] */
3836 #define WM8994_AIF2DRC_QR_THR_MASK              0x0300  /* AIF2DRC_QR_THR - [9:8] */
3837 #define WM8994_AIF2DRC_QR_THR_SHIFT                  8  /* AIF2DRC_QR_THR - [9:8] */
3838 #define WM8994_AIF2DRC_QR_THR_WIDTH                  2  /* AIF2DRC_QR_THR - [9:8] */
3839 #define WM8994_AIF2DRC_QR_DCY_MASK              0x00C0  /* AIF2DRC_QR_DCY - [7:6] */
3840 #define WM8994_AIF2DRC_QR_DCY_SHIFT                  6  /* AIF2DRC_QR_DCY - [7:6] */
3841 #define WM8994_AIF2DRC_QR_DCY_WIDTH                  2  /* AIF2DRC_QR_DCY - [7:6] */
3842 #define WM8994_AIF2DRC_HI_COMP_MASK             0x0038  /* AIF2DRC_HI_COMP - [5:3] */
3843 #define WM8994_AIF2DRC_HI_COMP_SHIFT                 3  /* AIF2DRC_HI_COMP - [5:3] */
3844 #define WM8994_AIF2DRC_HI_COMP_WIDTH                 3  /* AIF2DRC_HI_COMP - [5:3] */
3845 #define WM8994_AIF2DRC_LO_COMP_MASK             0x0007  /* AIF2DRC_LO_COMP - [2:0] */
3846 #define WM8994_AIF2DRC_LO_COMP_SHIFT                 0  /* AIF2DRC_LO_COMP - [2:0] */
3847 #define WM8994_AIF2DRC_LO_COMP_WIDTH                 3  /* AIF2DRC_LO_COMP - [2:0] */
3848 
3849 /*
3850  * R1347 (0x543) - AIF2 DRC (4)
3851  */
3852 #define WM8994_AIF2DRC_KNEE_IP_MASK             0x07E0  /* AIF2DRC_KNEE_IP - [10:5] */
3853 #define WM8994_AIF2DRC_KNEE_IP_SHIFT                 5  /* AIF2DRC_KNEE_IP - [10:5] */
3854 #define WM8994_AIF2DRC_KNEE_IP_WIDTH                 6  /* AIF2DRC_KNEE_IP - [10:5] */
3855 #define WM8994_AIF2DRC_KNEE_OP_MASK             0x001F  /* AIF2DRC_KNEE_OP - [4:0] */
3856 #define WM8994_AIF2DRC_KNEE_OP_SHIFT                 0  /* AIF2DRC_KNEE_OP - [4:0] */
3857 #define WM8994_AIF2DRC_KNEE_OP_WIDTH                 5  /* AIF2DRC_KNEE_OP - [4:0] */
3858 
3859 /*
3860  * R1348 (0x544) - AIF2 DRC (5)
3861  */
3862 #define WM8994_AIF2DRC_KNEE2_IP_MASK            0x03E0  /* AIF2DRC_KNEE2_IP - [9:5] */
3863 #define WM8994_AIF2DRC_KNEE2_IP_SHIFT                5  /* AIF2DRC_KNEE2_IP - [9:5] */
3864 #define WM8994_AIF2DRC_KNEE2_IP_WIDTH                5  /* AIF2DRC_KNEE2_IP - [9:5] */
3865 #define WM8994_AIF2DRC_KNEE2_OP_MASK            0x001F  /* AIF2DRC_KNEE2_OP - [4:0] */
3866 #define WM8994_AIF2DRC_KNEE2_OP_SHIFT                0  /* AIF2DRC_KNEE2_OP - [4:0] */
3867 #define WM8994_AIF2DRC_KNEE2_OP_WIDTH                5  /* AIF2DRC_KNEE2_OP - [4:0] */
3868 
3869 /*
3870  * R1408 (0x580) - AIF2 EQ Gains (1)
3871  */
3872 #define WM8994_AIF2DAC_EQ_B1_GAIN_MASK          0xF800  /* AIF2DAC_EQ_B1_GAIN - [15:11] */
3873 #define WM8994_AIF2DAC_EQ_B1_GAIN_SHIFT             11  /* AIF2DAC_EQ_B1_GAIN - [15:11] */
3874 #define WM8994_AIF2DAC_EQ_B1_GAIN_WIDTH              5  /* AIF2DAC_EQ_B1_GAIN - [15:11] */
3875 #define WM8994_AIF2DAC_EQ_B2_GAIN_MASK          0x07C0  /* AIF2DAC_EQ_B2_GAIN - [10:6] */
3876 #define WM8994_AIF2DAC_EQ_B2_GAIN_SHIFT              6  /* AIF2DAC_EQ_B2_GAIN - [10:6] */
3877 #define WM8994_AIF2DAC_EQ_B2_GAIN_WIDTH              5  /* AIF2DAC_EQ_B2_GAIN - [10:6] */
3878 #define WM8994_AIF2DAC_EQ_B3_GAIN_MASK          0x003E  /* AIF2DAC_EQ_B3_GAIN - [5:1] */
3879 #define WM8994_AIF2DAC_EQ_B3_GAIN_SHIFT              1  /* AIF2DAC_EQ_B3_GAIN - [5:1] */
3880 #define WM8994_AIF2DAC_EQ_B3_GAIN_WIDTH              5  /* AIF2DAC_EQ_B3_GAIN - [5:1] */
3881 #define WM8994_AIF2DAC_EQ_ENA                   0x0001  /* AIF2DAC_EQ_ENA */
3882 #define WM8994_AIF2DAC_EQ_ENA_MASK              0x0001  /* AIF2DAC_EQ_ENA */
3883 #define WM8994_AIF2DAC_EQ_ENA_SHIFT                  0  /* AIF2DAC_EQ_ENA */
3884 #define WM8994_AIF2DAC_EQ_ENA_WIDTH                  1  /* AIF2DAC_EQ_ENA */
3885 
3886 /*
3887  * R1409 (0x581) - AIF2 EQ Gains (2)
3888  */
3889 #define WM8994_AIF2DAC_EQ_B4_GAIN_MASK          0xF800  /* AIF2DAC_EQ_B4_GAIN - [15:11] */
3890 #define WM8994_AIF2DAC_EQ_B4_GAIN_SHIFT             11  /* AIF2DAC_EQ_B4_GAIN - [15:11] */
3891 #define WM8994_AIF2DAC_EQ_B4_GAIN_WIDTH              5  /* AIF2DAC_EQ_B4_GAIN - [15:11] */
3892 #define WM8994_AIF2DAC_EQ_B5_GAIN_MASK          0x07C0  /* AIF2DAC_EQ_B5_GAIN - [10:6] */
3893 #define WM8994_AIF2DAC_EQ_B5_GAIN_SHIFT              6  /* AIF2DAC_EQ_B5_GAIN - [10:6] */
3894 #define WM8994_AIF2DAC_EQ_B5_GAIN_WIDTH              5  /* AIF2DAC_EQ_B5_GAIN - [10:6] */
3895 
3896 /*
3897  * R1410 (0x582) - AIF2 EQ Band 1 A
3898  */
3899 #define WM8994_AIF2DAC_EQ_B1_A_MASK             0xFFFF  /* AIF2DAC_EQ_B1_A - [15:0] */
3900 #define WM8994_AIF2DAC_EQ_B1_A_SHIFT                 0  /* AIF2DAC_EQ_B1_A - [15:0] */
3901 #define WM8994_AIF2DAC_EQ_B1_A_WIDTH                16  /* AIF2DAC_EQ_B1_A - [15:0] */
3902 
3903 /*
3904  * R1411 (0x583) - AIF2 EQ Band 1 B
3905  */
3906 #define WM8994_AIF2DAC_EQ_B1_B_MASK             0xFFFF  /* AIF2DAC_EQ_B1_B - [15:0] */
3907 #define WM8994_AIF2DAC_EQ_B1_B_SHIFT                 0  /* AIF2DAC_EQ_B1_B - [15:0] */
3908 #define WM8994_AIF2DAC_EQ_B1_B_WIDTH                16  /* AIF2DAC_EQ_B1_B - [15:0] */
3909 
3910 /*
3911  * R1412 (0x584) - AIF2 EQ Band 1 PG
3912  */
3913 #define WM8994_AIF2DAC_EQ_B1_PG_MASK            0xFFFF  /* AIF2DAC_EQ_B1_PG - [15:0] */
3914 #define WM8994_AIF2DAC_EQ_B1_PG_SHIFT                0  /* AIF2DAC_EQ_B1_PG - [15:0] */
3915 #define WM8994_AIF2DAC_EQ_B1_PG_WIDTH               16  /* AIF2DAC_EQ_B1_PG - [15:0] */
3916 
3917 /*
3918  * R1413 (0x585) - AIF2 EQ Band 2 A
3919  */
3920 #define WM8994_AIF2DAC_EQ_B2_A_MASK             0xFFFF  /* AIF2DAC_EQ_B2_A - [15:0] */
3921 #define WM8994_AIF2DAC_EQ_B2_A_SHIFT                 0  /* AIF2DAC_EQ_B2_A - [15:0] */
3922 #define WM8994_AIF2DAC_EQ_B2_A_WIDTH                16  /* AIF2DAC_EQ_B2_A - [15:0] */
3923 
3924 /*
3925  * R1414 (0x586) - AIF2 EQ Band 2 B
3926  */
3927 #define WM8994_AIF2DAC_EQ_B2_B_MASK             0xFFFF  /* AIF2DAC_EQ_B2_B - [15:0] */
3928 #define WM8994_AIF2DAC_EQ_B2_B_SHIFT                 0  /* AIF2DAC_EQ_B2_B - [15:0] */
3929 #define WM8994_AIF2DAC_EQ_B2_B_WIDTH                16  /* AIF2DAC_EQ_B2_B - [15:0] */
3930 
3931 /*
3932  * R1415 (0x587) - AIF2 EQ Band 2 C
3933  */
3934 #define WM8994_AIF2DAC_EQ_B2_C_MASK             0xFFFF  /* AIF2DAC_EQ_B2_C - [15:0] */
3935 #define WM8994_AIF2DAC_EQ_B2_C_SHIFT                 0  /* AIF2DAC_EQ_B2_C - [15:0] */
3936 #define WM8994_AIF2DAC_EQ_B2_C_WIDTH                16  /* AIF2DAC_EQ_B2_C - [15:0] */
3937 
3938 /*
3939  * R1416 (0x588) - AIF2 EQ Band 2 PG
3940  */
3941 #define WM8994_AIF2DAC_EQ_B2_PG_MASK            0xFFFF  /* AIF2DAC_EQ_B2_PG - [15:0] */
3942 #define WM8994_AIF2DAC_EQ_B2_PG_SHIFT                0  /* AIF2DAC_EQ_B2_PG - [15:0] */
3943 #define WM8994_AIF2DAC_EQ_B2_PG_WIDTH               16  /* AIF2DAC_EQ_B2_PG - [15:0] */
3944 
3945 /*
3946  * R1417 (0x589) - AIF2 EQ Band 3 A
3947  */
3948 #define WM8994_AIF2DAC_EQ_B3_A_MASK             0xFFFF  /* AIF2DAC_EQ_B3_A - [15:0] */
3949 #define WM8994_AIF2DAC_EQ_B3_A_SHIFT                 0  /* AIF2DAC_EQ_B3_A - [15:0] */
3950 #define WM8994_AIF2DAC_EQ_B3_A_WIDTH                16  /* AIF2DAC_EQ_B3_A - [15:0] */
3951 
3952 /*
3953  * R1418 (0x58A) - AIF2 EQ Band 3 B
3954  */
3955 #define WM8994_AIF2DAC_EQ_B3_B_MASK             0xFFFF  /* AIF2DAC_EQ_B3_B - [15:0] */
3956 #define WM8994_AIF2DAC_EQ_B3_B_SHIFT                 0  /* AIF2DAC_EQ_B3_B - [15:0] */
3957 #define WM8994_AIF2DAC_EQ_B3_B_WIDTH                16  /* AIF2DAC_EQ_B3_B - [15:0] */
3958 
3959 /*
3960  * R1419 (0x58B) - AIF2 EQ Band 3 C
3961  */
3962 #define WM8994_AIF2DAC_EQ_B3_C_MASK             0xFFFF  /* AIF2DAC_EQ_B3_C - [15:0] */
3963 #define WM8994_AIF2DAC_EQ_B3_C_SHIFT                 0  /* AIF2DAC_EQ_B3_C - [15:0] */
3964 #define WM8994_AIF2DAC_EQ_B3_C_WIDTH                16  /* AIF2DAC_EQ_B3_C - [15:0] */
3965 
3966 /*
3967  * R1420 (0x58C) - AIF2 EQ Band 3 PG
3968  */
3969 #define WM8994_AIF2DAC_EQ_B3_PG_MASK            0xFFFF  /* AIF2DAC_EQ_B3_PG - [15:0] */
3970 #define WM8994_AIF2DAC_EQ_B3_PG_SHIFT                0  /* AIF2DAC_EQ_B3_PG - [15:0] */
3971 #define WM8994_AIF2DAC_EQ_B3_PG_WIDTH               16  /* AIF2DAC_EQ_B3_PG - [15:0] */
3972 
3973 /*
3974  * R1421 (0x58D) - AIF2 EQ Band 4 A
3975  */
3976 #define WM8994_AIF2DAC_EQ_B4_A_MASK             0xFFFF  /* AIF2DAC_EQ_B4_A - [15:0] */
3977 #define WM8994_AIF2DAC_EQ_B4_A_SHIFT                 0  /* AIF2DAC_EQ_B4_A - [15:0] */
3978 #define WM8994_AIF2DAC_EQ_B4_A_WIDTH                16  /* AIF2DAC_EQ_B4_A - [15:0] */
3979 
3980 /*
3981  * R1422 (0x58E) - AIF2 EQ Band 4 B
3982  */
3983 #define WM8994_AIF2DAC_EQ_B4_B_MASK             0xFFFF  /* AIF2DAC_EQ_B4_B - [15:0] */
3984 #define WM8994_AIF2DAC_EQ_B4_B_SHIFT                 0  /* AIF2DAC_EQ_B4_B - [15:0] */
3985 #define WM8994_AIF2DAC_EQ_B4_B_WIDTH                16  /* AIF2DAC_EQ_B4_B - [15:0] */
3986 
3987 /*
3988  * R1423 (0x58F) - AIF2 EQ Band 4 C
3989  */
3990 #define WM8994_AIF2DAC_EQ_B4_C_MASK             0xFFFF  /* AIF2DAC_EQ_B4_C - [15:0] */
3991 #define WM8994_AIF2DAC_EQ_B4_C_SHIFT                 0  /* AIF2DAC_EQ_B4_C - [15:0] */
3992 #define WM8994_AIF2DAC_EQ_B4_C_WIDTH                16  /* AIF2DAC_EQ_B4_C - [15:0] */
3993 
3994 /*
3995  * R1424 (0x590) - AIF2 EQ Band 4 PG
3996  */
3997 #define WM8994_AIF2DAC_EQ_B4_PG_MASK            0xFFFF  /* AIF2DAC_EQ_B4_PG - [15:0] */
3998 #define WM8994_AIF2DAC_EQ_B4_PG_SHIFT                0  /* AIF2DAC_EQ_B4_PG - [15:0] */
3999 #define WM8994_AIF2DAC_EQ_B4_PG_WIDTH               16  /* AIF2DAC_EQ_B4_PG - [15:0] */
4000 
4001 /*
4002  * R1425 (0x591) - AIF2 EQ Band 5 A
4003  */
4004 #define WM8994_AIF2DAC_EQ_B5_A_MASK             0xFFFF  /* AIF2DAC_EQ_B5_A - [15:0] */
4005 #define WM8994_AIF2DAC_EQ_B5_A_SHIFT                 0  /* AIF2DAC_EQ_B5_A - [15:0] */
4006 #define WM8994_AIF2DAC_EQ_B5_A_WIDTH                16  /* AIF2DAC_EQ_B5_A - [15:0] */
4007 
4008 /*
4009  * R1426 (0x592) - AIF2 EQ Band 5 B
4010  */
4011 #define WM8994_AIF2DAC_EQ_B5_B_MASK             0xFFFF  /* AIF2DAC_EQ_B5_B - [15:0] */
4012 #define WM8994_AIF2DAC_EQ_B5_B_SHIFT                 0  /* AIF2DAC_EQ_B5_B - [15:0] */
4013 #define WM8994_AIF2DAC_EQ_B5_B_WIDTH                16  /* AIF2DAC_EQ_B5_B - [15:0] */
4014 
4015 /*
4016  * R1427 (0x593) - AIF2 EQ Band 5 PG
4017  */
4018 #define WM8994_AIF2DAC_EQ_B5_PG_MASK            0xFFFF  /* AIF2DAC_EQ_B5_PG - [15:0] */
4019 #define WM8994_AIF2DAC_EQ_B5_PG_SHIFT                0  /* AIF2DAC_EQ_B5_PG - [15:0] */
4020 #define WM8994_AIF2DAC_EQ_B5_PG_WIDTH               16  /* AIF2DAC_EQ_B5_PG - [15:0] */
4021 
4022 /*
4023  * R1536 (0x600) - DAC1 Mixer Volumes
4024  */
4025 #define WM8994_ADCR_DAC1_VOL_MASK               0x01E0  /* ADCR_DAC1_VOL - [8:5] */
4026 #define WM8994_ADCR_DAC1_VOL_SHIFT                   5  /* ADCR_DAC1_VOL - [8:5] */
4027 #define WM8994_ADCR_DAC1_VOL_WIDTH                   4  /* ADCR_DAC1_VOL - [8:5] */
4028 #define WM8994_ADCL_DAC1_VOL_MASK               0x000F  /* ADCL_DAC1_VOL - [3:0] */
4029 #define WM8994_ADCL_DAC1_VOL_SHIFT                   0  /* ADCL_DAC1_VOL - [3:0] */
4030 #define WM8994_ADCL_DAC1_VOL_WIDTH                   4  /* ADCL_DAC1_VOL - [3:0] */
4031 
4032 /*
4033  * R1537 (0x601) - DAC1 Left Mixer Routing
4034  */
4035 #define WM8994_ADCR_TO_DAC1L                    0x0020  /* ADCR_TO_DAC1L */
4036 #define WM8994_ADCR_TO_DAC1L_MASK               0x0020  /* ADCR_TO_DAC1L */
4037 #define WM8994_ADCR_TO_DAC1L_SHIFT                   5  /* ADCR_TO_DAC1L */
4038 #define WM8994_ADCR_TO_DAC1L_WIDTH                   1  /* ADCR_TO_DAC1L */
4039 #define WM8994_ADCL_TO_DAC1L                    0x0010  /* ADCL_TO_DAC1L */
4040 #define WM8994_ADCL_TO_DAC1L_MASK               0x0010  /* ADCL_TO_DAC1L */
4041 #define WM8994_ADCL_TO_DAC1L_SHIFT                   4  /* ADCL_TO_DAC1L */
4042 #define WM8994_ADCL_TO_DAC1L_WIDTH                   1  /* ADCL_TO_DAC1L */
4043 #define WM8994_AIF2DACL_TO_DAC1L                0x0004  /* AIF2DACL_TO_DAC1L */
4044 #define WM8994_AIF2DACL_TO_DAC1L_MASK           0x0004  /* AIF2DACL_TO_DAC1L */
4045 #define WM8994_AIF2DACL_TO_DAC1L_SHIFT               2  /* AIF2DACL_TO_DAC1L */
4046 #define WM8994_AIF2DACL_TO_DAC1L_WIDTH               1  /* AIF2DACL_TO_DAC1L */
4047 #define WM8994_AIF1DAC2L_TO_DAC1L               0x0002  /* AIF1DAC2L_TO_DAC1L */
4048 #define WM8994_AIF1DAC2L_TO_DAC1L_MASK          0x0002  /* AIF1DAC2L_TO_DAC1L */
4049 #define WM8994_AIF1DAC2L_TO_DAC1L_SHIFT              1  /* AIF1DAC2L_TO_DAC1L */
4050 #define WM8994_AIF1DAC2L_TO_DAC1L_WIDTH              1  /* AIF1DAC2L_TO_DAC1L */
4051 #define WM8994_AIF1DAC1L_TO_DAC1L               0x0001  /* AIF1DAC1L_TO_DAC1L */
4052 #define WM8994_AIF1DAC1L_TO_DAC1L_MASK          0x0001  /* AIF1DAC1L_TO_DAC1L */
4053 #define WM8994_AIF1DAC1L_TO_DAC1L_SHIFT              0  /* AIF1DAC1L_TO_DAC1L */
4054 #define WM8994_AIF1DAC1L_TO_DAC1L_WIDTH              1  /* AIF1DAC1L_TO_DAC1L */
4055 
4056 /*
4057  * R1538 (0x602) - DAC1 Right Mixer Routing
4058  */
4059 #define WM8994_ADCR_TO_DAC1R                    0x0020  /* ADCR_TO_DAC1R */
4060 #define WM8994_ADCR_TO_DAC1R_MASK               0x0020  /* ADCR_TO_DAC1R */
4061 #define WM8994_ADCR_TO_DAC1R_SHIFT                   5  /* ADCR_TO_DAC1R */
4062 #define WM8994_ADCR_TO_DAC1R_WIDTH                   1  /* ADCR_TO_DAC1R */
4063 #define WM8994_ADCL_TO_DAC1R                    0x0010  /* ADCL_TO_DAC1R */
4064 #define WM8994_ADCL_TO_DAC1R_MASK               0x0010  /* ADCL_TO_DAC1R */
4065 #define WM8994_ADCL_TO_DAC1R_SHIFT                   4  /* ADCL_TO_DAC1R */
4066 #define WM8994_ADCL_TO_DAC1R_WIDTH                   1  /* ADCL_TO_DAC1R */
4067 #define WM8994_AIF2DACR_TO_DAC1R                0x0004  /* AIF2DACR_TO_DAC1R */
4068 #define WM8994_AIF2DACR_TO_DAC1R_MASK           0x0004  /* AIF2DACR_TO_DAC1R */
4069 #define WM8994_AIF2DACR_TO_DAC1R_SHIFT               2  /* AIF2DACR_TO_DAC1R */
4070 #define WM8994_AIF2DACR_TO_DAC1R_WIDTH               1  /* AIF2DACR_TO_DAC1R */
4071 #define WM8994_AIF1DAC2R_TO_DAC1R               0x0002  /* AIF1DAC2R_TO_DAC1R */
4072 #define WM8994_AIF1DAC2R_TO_DAC1R_MASK          0x0002  /* AIF1DAC2R_TO_DAC1R */
4073 #define WM8994_AIF1DAC2R_TO_DAC1R_SHIFT              1  /* AIF1DAC2R_TO_DAC1R */
4074 #define WM8994_AIF1DAC2R_TO_DAC1R_WIDTH              1  /* AIF1DAC2R_TO_DAC1R */
4075 #define WM8994_AIF1DAC1R_TO_DAC1R               0x0001  /* AIF1DAC1R_TO_DAC1R */
4076 #define WM8994_AIF1DAC1R_TO_DAC1R_MASK          0x0001  /* AIF1DAC1R_TO_DAC1R */
4077 #define WM8994_AIF1DAC1R_TO_DAC1R_SHIFT              0  /* AIF1DAC1R_TO_DAC1R */
4078 #define WM8994_AIF1DAC1R_TO_DAC1R_WIDTH              1  /* AIF1DAC1R_TO_DAC1R */
4079 
4080 /*
4081  * R1539 (0x603) - DAC2 Mixer Volumes
4082  */
4083 #define WM8994_ADCR_DAC2_VOL_MASK               0x01E0  /* ADCR_DAC2_VOL - [8:5] */
4084 #define WM8994_ADCR_DAC2_VOL_SHIFT                   5  /* ADCR_DAC2_VOL - [8:5] */
4085 #define WM8994_ADCR_DAC2_VOL_WIDTH                   4  /* ADCR_DAC2_VOL - [8:5] */
4086 #define WM8994_ADCL_DAC2_VOL_MASK               0x000F  /* ADCL_DAC2_VOL - [3:0] */
4087 #define WM8994_ADCL_DAC2_VOL_SHIFT                   0  /* ADCL_DAC2_VOL - [3:0] */
4088 #define WM8994_ADCL_DAC2_VOL_WIDTH                   4  /* ADCL_DAC2_VOL - [3:0] */
4089 
4090 /*
4091  * R1540 (0x604) - DAC2 Left Mixer Routing
4092  */
4093 #define WM8994_ADCR_TO_DAC2L                    0x0020  /* ADCR_TO_DAC2L */
4094 #define WM8994_ADCR_TO_DAC2L_MASK               0x0020  /* ADCR_TO_DAC2L */
4095 #define WM8994_ADCR_TO_DAC2L_SHIFT                   5  /* ADCR_TO_DAC2L */
4096 #define WM8994_ADCR_TO_DAC2L_WIDTH                   1  /* ADCR_TO_DAC2L */
4097 #define WM8994_ADCL_TO_DAC2L                    0x0010  /* ADCL_TO_DAC2L */
4098 #define WM8994_ADCL_TO_DAC2L_MASK               0x0010  /* ADCL_TO_DAC2L */
4099 #define WM8994_ADCL_TO_DAC2L_SHIFT                   4  /* ADCL_TO_DAC2L */
4100 #define WM8994_ADCL_TO_DAC2L_WIDTH                   1  /* ADCL_TO_DAC2L */
4101 #define WM8994_AIF2DACL_TO_DAC2L                0x0004  /* AIF2DACL_TO_DAC2L */
4102 #define WM8994_AIF2DACL_TO_DAC2L_MASK           0x0004  /* AIF2DACL_TO_DAC2L */
4103 #define WM8994_AIF2DACL_TO_DAC2L_SHIFT               2  /* AIF2DACL_TO_DAC2L */
4104 #define WM8994_AIF2DACL_TO_DAC2L_WIDTH               1  /* AIF2DACL_TO_DAC2L */
4105 #define WM8994_AIF1DAC2L_TO_DAC2L               0x0002  /* AIF1DAC2L_TO_DAC2L */
4106 #define WM8994_AIF1DAC2L_TO_DAC2L_MASK          0x0002  /* AIF1DAC2L_TO_DAC2L */
4107 #define WM8994_AIF1DAC2L_TO_DAC2L_SHIFT              1  /* AIF1DAC2L_TO_DAC2L */
4108 #define WM8994_AIF1DAC2L_TO_DAC2L_WIDTH              1  /* AIF1DAC2L_TO_DAC2L */
4109 #define WM8994_AIF1DAC1L_TO_DAC2L               0x0001  /* AIF1DAC1L_TO_DAC2L */
4110 #define WM8994_AIF1DAC1L_TO_DAC2L_MASK          0x0001  /* AIF1DAC1L_TO_DAC2L */
4111 #define WM8994_AIF1DAC1L_TO_DAC2L_SHIFT              0  /* AIF1DAC1L_TO_DAC2L */
4112 #define WM8994_AIF1DAC1L_TO_DAC2L_WIDTH              1  /* AIF1DAC1L_TO_DAC2L */
4113 
4114 /*
4115  * R1541 (0x605) - DAC2 Right Mixer Routing
4116  */
4117 #define WM8994_ADCR_TO_DAC2R                    0x0020  /* ADCR_TO_DAC2R */
4118 #define WM8994_ADCR_TO_DAC2R_MASK               0x0020  /* ADCR_TO_DAC2R */
4119 #define WM8994_ADCR_TO_DAC2R_SHIFT                   5  /* ADCR_TO_DAC2R */
4120 #define WM8994_ADCR_TO_DAC2R_WIDTH                   1  /* ADCR_TO_DAC2R */
4121 #define WM8994_ADCL_TO_DAC2R                    0x0010  /* ADCL_TO_DAC2R */
4122 #define WM8994_ADCL_TO_DAC2R_MASK               0x0010  /* ADCL_TO_DAC2R */
4123 #define WM8994_ADCL_TO_DAC2R_SHIFT                   4  /* ADCL_TO_DAC2R */
4124 #define WM8994_ADCL_TO_DAC2R_WIDTH                   1  /* ADCL_TO_DAC2R */
4125 #define WM8994_AIF2DACR_TO_DAC2R                0x0004  /* AIF2DACR_TO_DAC2R */
4126 #define WM8994_AIF2DACR_TO_DAC2R_MASK           0x0004  /* AIF2DACR_TO_DAC2R */
4127 #define WM8994_AIF2DACR_TO_DAC2R_SHIFT               2  /* AIF2DACR_TO_DAC2R */
4128 #define WM8994_AIF2DACR_TO_DAC2R_WIDTH               1  /* AIF2DACR_TO_DAC2R */
4129 #define WM8994_AIF1DAC2R_TO_DAC2R               0x0002  /* AIF1DAC2R_TO_DAC2R */
4130 #define WM8994_AIF1DAC2R_TO_DAC2R_MASK          0x0002  /* AIF1DAC2R_TO_DAC2R */
4131 #define WM8994_AIF1DAC2R_TO_DAC2R_SHIFT              1  /* AIF1DAC2R_TO_DAC2R */
4132 #define WM8994_AIF1DAC2R_TO_DAC2R_WIDTH              1  /* AIF1DAC2R_TO_DAC2R */
4133 #define WM8994_AIF1DAC1R_TO_DAC2R               0x0001  /* AIF1DAC1R_TO_DAC2R */
4134 #define WM8994_AIF1DAC1R_TO_DAC2R_MASK          0x0001  /* AIF1DAC1R_TO_DAC2R */
4135 #define WM8994_AIF1DAC1R_TO_DAC2R_SHIFT              0  /* AIF1DAC1R_TO_DAC2R */
4136 #define WM8994_AIF1DAC1R_TO_DAC2R_WIDTH              1  /* AIF1DAC1R_TO_DAC2R */
4137 
4138 /*
4139  * R1542 (0x606) - AIF1 ADC1 Left Mixer Routing
4140  */
4141 #define WM8994_ADC1L_TO_AIF1ADC1L               0x0002  /* ADC1L_TO_AIF1ADC1L */
4142 #define WM8994_ADC1L_TO_AIF1ADC1L_MASK          0x0002  /* ADC1L_TO_AIF1ADC1L */
4143 #define WM8994_ADC1L_TO_AIF1ADC1L_SHIFT              1  /* ADC1L_TO_AIF1ADC1L */
4144 #define WM8994_ADC1L_TO_AIF1ADC1L_WIDTH              1  /* ADC1L_TO_AIF1ADC1L */
4145 #define WM8994_AIF2DACL_TO_AIF1ADC1L            0x0001  /* AIF2DACL_TO_AIF1ADC1L */
4146 #define WM8994_AIF2DACL_TO_AIF1ADC1L_MASK       0x0001  /* AIF2DACL_TO_AIF1ADC1L */
4147 #define WM8994_AIF2DACL_TO_AIF1ADC1L_SHIFT           0  /* AIF2DACL_TO_AIF1ADC1L */
4148 #define WM8994_AIF2DACL_TO_AIF1ADC1L_WIDTH           1  /* AIF2DACL_TO_AIF1ADC1L */
4149 
4150 /*
4151  * R1543 (0x607) - AIF1 ADC1 Right Mixer Routing
4152  */
4153 #define WM8994_ADC1R_TO_AIF1ADC1R               0x0002  /* ADC1R_TO_AIF1ADC1R */
4154 #define WM8994_ADC1R_TO_AIF1ADC1R_MASK          0x0002  /* ADC1R_TO_AIF1ADC1R */
4155 #define WM8994_ADC1R_TO_AIF1ADC1R_SHIFT              1  /* ADC1R_TO_AIF1ADC1R */
4156 #define WM8994_ADC1R_TO_AIF1ADC1R_WIDTH              1  /* ADC1R_TO_AIF1ADC1R */
4157 #define WM8994_AIF2DACR_TO_AIF1ADC1R            0x0001  /* AIF2DACR_TO_AIF1ADC1R */
4158 #define WM8994_AIF2DACR_TO_AIF1ADC1R_MASK       0x0001  /* AIF2DACR_TO_AIF1ADC1R */
4159 #define WM8994_AIF2DACR_TO_AIF1ADC1R_SHIFT           0  /* AIF2DACR_TO_AIF1ADC1R */
4160 #define WM8994_AIF2DACR_TO_AIF1ADC1R_WIDTH           1  /* AIF2DACR_TO_AIF1ADC1R */
4161 
4162 /*
4163  * R1544 (0x608) - AIF1 ADC2 Left Mixer Routing
4164  */
4165 #define WM8994_ADC2L_TO_AIF1ADC2L               0x0002  /* ADC2L_TO_AIF1ADC2L */
4166 #define WM8994_ADC2L_TO_AIF1ADC2L_MASK          0x0002  /* ADC2L_TO_AIF1ADC2L */
4167 #define WM8994_ADC2L_TO_AIF1ADC2L_SHIFT              1  /* ADC2L_TO_AIF1ADC2L */
4168 #define WM8994_ADC2L_TO_AIF1ADC2L_WIDTH              1  /* ADC2L_TO_AIF1ADC2L */
4169 #define WM8994_AIF2DACL_TO_AIF1ADC2L            0x0001  /* AIF2DACL_TO_AIF1ADC2L */
4170 #define WM8994_AIF2DACL_TO_AIF1ADC2L_MASK       0x0001  /* AIF2DACL_TO_AIF1ADC2L */
4171 #define WM8994_AIF2DACL_TO_AIF1ADC2L_SHIFT           0  /* AIF2DACL_TO_AIF1ADC2L */
4172 #define WM8994_AIF2DACL_TO_AIF1ADC2L_WIDTH           1  /* AIF2DACL_TO_AIF1ADC2L */
4173 
4174 /*
4175  * R1545 (0x609) - AIF1 ADC2 Right mixer Routing
4176  */
4177 #define WM8994_ADC2R_TO_AIF1ADC2R               0x0002  /* ADC2R_TO_AIF1ADC2R */
4178 #define WM8994_ADC2R_TO_AIF1ADC2R_MASK          0x0002  /* ADC2R_TO_AIF1ADC2R */
4179 #define WM8994_ADC2R_TO_AIF1ADC2R_SHIFT              1  /* ADC2R_TO_AIF1ADC2R */
4180 #define WM8994_ADC2R_TO_AIF1ADC2R_WIDTH              1  /* ADC2R_TO_AIF1ADC2R */
4181 #define WM8994_AIF2DACR_TO_AIF1ADC2R            0x0001  /* AIF2DACR_TO_AIF1ADC2R */
4182 #define WM8994_AIF2DACR_TO_AIF1ADC2R_MASK       0x0001  /* AIF2DACR_TO_AIF1ADC2R */
4183 #define WM8994_AIF2DACR_TO_AIF1ADC2R_SHIFT           0  /* AIF2DACR_TO_AIF1ADC2R */
4184 #define WM8994_AIF2DACR_TO_AIF1ADC2R_WIDTH           1  /* AIF2DACR_TO_AIF1ADC2R */
4185 
4186 /*
4187  * R1552 (0x610) - DAC1 Left Volume
4188  */
4189 #define WM8994_DAC1L_MUTE                       0x0200  /* DAC1L_MUTE */
4190 #define WM8994_DAC1L_MUTE_MASK                  0x0200  /* DAC1L_MUTE */
4191 #define WM8994_DAC1L_MUTE_SHIFT                      9  /* DAC1L_MUTE */
4192 #define WM8994_DAC1L_MUTE_WIDTH                      1  /* DAC1L_MUTE */
4193 #define WM8994_DAC1_VU                          0x0100  /* DAC1_VU */
4194 #define WM8994_DAC1_VU_MASK                     0x0100  /* DAC1_VU */
4195 #define WM8994_DAC1_VU_SHIFT                         8  /* DAC1_VU */
4196 #define WM8994_DAC1_VU_WIDTH                         1  /* DAC1_VU */
4197 #define WM8994_DAC1L_VOL_MASK                   0x00FF  /* DAC1L_VOL - [7:0] */
4198 #define WM8994_DAC1L_VOL_SHIFT                       0  /* DAC1L_VOL - [7:0] */
4199 #define WM8994_DAC1L_VOL_WIDTH                       8  /* DAC1L_VOL - [7:0] */
4200 
4201 /*
4202  * R1553 (0x611) - DAC1 Right Volume
4203  */
4204 #define WM8994_DAC1R_MUTE                       0x0200  /* DAC1R_MUTE */
4205 #define WM8994_DAC1R_MUTE_MASK                  0x0200  /* DAC1R_MUTE */
4206 #define WM8994_DAC1R_MUTE_SHIFT                      9  /* DAC1R_MUTE */
4207 #define WM8994_DAC1R_MUTE_WIDTH                      1  /* DAC1R_MUTE */
4208 #define WM8994_DAC1_VU                          0x0100  /* DAC1_VU */
4209 #define WM8994_DAC1_VU_MASK                     0x0100  /* DAC1_VU */
4210 #define WM8994_DAC1_VU_SHIFT                         8  /* DAC1_VU */
4211 #define WM8994_DAC1_VU_WIDTH                         1  /* DAC1_VU */
4212 #define WM8994_DAC1R_VOL_MASK                   0x00FF  /* DAC1R_VOL - [7:0] */
4213 #define WM8994_DAC1R_VOL_SHIFT                       0  /* DAC1R_VOL - [7:0] */
4214 #define WM8994_DAC1R_VOL_WIDTH                       8  /* DAC1R_VOL - [7:0] */
4215 
4216 /*
4217  * R1554 (0x612) - DAC2 Left Volume
4218  */
4219 #define WM8994_DAC2L_MUTE                       0x0200  /* DAC2L_MUTE */
4220 #define WM8994_DAC2L_MUTE_MASK                  0x0200  /* DAC2L_MUTE */
4221 #define WM8994_DAC2L_MUTE_SHIFT                      9  /* DAC2L_MUTE */
4222 #define WM8994_DAC2L_MUTE_WIDTH                      1  /* DAC2L_MUTE */
4223 #define WM8994_DAC2_VU                          0x0100  /* DAC2_VU */
4224 #define WM8994_DAC2_VU_MASK                     0x0100  /* DAC2_VU */
4225 #define WM8994_DAC2_VU_SHIFT                         8  /* DAC2_VU */
4226 #define WM8994_DAC2_VU_WIDTH                         1  /* DAC2_VU */
4227 #define WM8994_DAC2L_VOL_MASK                   0x00FF  /* DAC2L_VOL - [7:0] */
4228 #define WM8994_DAC2L_VOL_SHIFT                       0  /* DAC2L_VOL - [7:0] */
4229 #define WM8994_DAC2L_VOL_WIDTH                       8  /* DAC2L_VOL - [7:0] */
4230 
4231 /*
4232  * R1555 (0x613) - DAC2 Right Volume
4233  */
4234 #define WM8994_DAC2R_MUTE                       0x0200  /* DAC2R_MUTE */
4235 #define WM8994_DAC2R_MUTE_MASK                  0x0200  /* DAC2R_MUTE */
4236 #define WM8994_DAC2R_MUTE_SHIFT                      9  /* DAC2R_MUTE */
4237 #define WM8994_DAC2R_MUTE_WIDTH                      1  /* DAC2R_MUTE */
4238 #define WM8994_DAC2_VU                          0x0100  /* DAC2_VU */
4239 #define WM8994_DAC2_VU_MASK                     0x0100  /* DAC2_VU */
4240 #define WM8994_DAC2_VU_SHIFT                         8  /* DAC2_VU */
4241 #define WM8994_DAC2_VU_WIDTH                         1  /* DAC2_VU */
4242 #define WM8994_DAC2R_VOL_MASK                   0x00FF  /* DAC2R_VOL - [7:0] */
4243 #define WM8994_DAC2R_VOL_SHIFT                       0  /* DAC2R_VOL - [7:0] */
4244 #define WM8994_DAC2R_VOL_WIDTH                       8  /* DAC2R_VOL - [7:0] */
4245 
4246 /*
4247  * R1556 (0x614) - DAC Softmute
4248  */
4249 #define WM8994_DAC_SOFTMUTEMODE                 0x0002  /* DAC_SOFTMUTEMODE */
4250 #define WM8994_DAC_SOFTMUTEMODE_MASK            0x0002  /* DAC_SOFTMUTEMODE */
4251 #define WM8994_DAC_SOFTMUTEMODE_SHIFT                1  /* DAC_SOFTMUTEMODE */
4252 #define WM8994_DAC_SOFTMUTEMODE_WIDTH                1  /* DAC_SOFTMUTEMODE */
4253 #define WM8994_DAC_MUTERATE                     0x0001  /* DAC_MUTERATE */
4254 #define WM8994_DAC_MUTERATE_MASK                0x0001  /* DAC_MUTERATE */
4255 #define WM8994_DAC_MUTERATE_SHIFT                    0  /* DAC_MUTERATE */
4256 #define WM8994_DAC_MUTERATE_WIDTH                    1  /* DAC_MUTERATE */
4257 
4258 /*
4259  * R1568 (0x620) - Oversampling
4260  */
4261 #define WM8994_ADC_OSR128                       0x0002  /* ADC_OSR128 */
4262 #define WM8994_ADC_OSR128_MASK                  0x0002  /* ADC_OSR128 */
4263 #define WM8994_ADC_OSR128_SHIFT                      1  /* ADC_OSR128 */
4264 #define WM8994_ADC_OSR128_WIDTH                      1  /* ADC_OSR128 */
4265 #define WM8994_DAC_OSR128                       0x0001  /* DAC_OSR128 */
4266 #define WM8994_DAC_OSR128_MASK                  0x0001  /* DAC_OSR128 */
4267 #define WM8994_DAC_OSR128_SHIFT                      0  /* DAC_OSR128 */
4268 #define WM8994_DAC_OSR128_WIDTH                      1  /* DAC_OSR128 */
4269 
4270 /*
4271  * R1569 (0x621) - Sidetone
4272  */
4273 #define WM8994_ST_HPF_CUT_MASK                  0x0380  /* ST_HPF_CUT - [9:7] */
4274 #define WM8994_ST_HPF_CUT_SHIFT                      7  /* ST_HPF_CUT - [9:7] */
4275 #define WM8994_ST_HPF_CUT_WIDTH                      3  /* ST_HPF_CUT - [9:7] */
4276 #define WM8994_ST_HPF                           0x0040  /* ST_HPF */
4277 #define WM8994_ST_HPF_MASK                      0x0040  /* ST_HPF */
4278 #define WM8994_ST_HPF_SHIFT                          6  /* ST_HPF */
4279 #define WM8994_ST_HPF_WIDTH                          1  /* ST_HPF */
4280 #define WM8994_STR_SEL                          0x0002  /* STR_SEL */
4281 #define WM8994_STR_SEL_MASK                     0x0002  /* STR_SEL */
4282 #define WM8994_STR_SEL_SHIFT                         1  /* STR_SEL */
4283 #define WM8994_STR_SEL_WIDTH                         1  /* STR_SEL */
4284 #define WM8994_STL_SEL                          0x0001  /* STL_SEL */
4285 #define WM8994_STL_SEL_MASK                     0x0001  /* STL_SEL */
4286 #define WM8994_STL_SEL_SHIFT                         0  /* STL_SEL */
4287 #define WM8994_STL_SEL_WIDTH                         1  /* STL_SEL */
4288 
4289 /*
4290  * R1797 (0x705) - JACKDET Ctrl
4291  */
4292 #define WM1811_JACKDET_DB                       0x0100  /* JACKDET_DB */
4293 #define WM1811_JACKDET_DB_MASK                  0x0100  /* JACKDET_DB */
4294 #define WM1811_JACKDET_DB_SHIFT                      8  /* JACKDET_DB */
4295 #define WM1811_JACKDET_DB_WIDTH                      1  /* JACKDET_DB */
4296 #define WM1811_JACKDET_LVL                      0x0040  /* JACKDET_LVL */
4297 #define WM1811_JACKDET_LVL_MASK                 0x0040  /* JACKDET_LVL */
4298 #define WM1811_JACKDET_LVL_SHIFT                     6  /* JACKDET_LVL */
4299 #define WM1811_JACKDET_LVL_WIDTH                     1  /* JACKDET_LVL */
4300 
4301 /*
4302  * R1824 (0x720) - Pull Control (1)
4303  */
4304 #define WM8994_DMICDAT2_PU                      0x0800  /* DMICDAT2_PU */
4305 #define WM8994_DMICDAT2_PU_MASK                 0x0800  /* DMICDAT2_PU */
4306 #define WM8994_DMICDAT2_PU_SHIFT                    11  /* DMICDAT2_PU */
4307 #define WM8994_DMICDAT2_PU_WIDTH                     1  /* DMICDAT2_PU */
4308 #define WM8994_DMICDAT2_PD                      0x0400  /* DMICDAT2_PD */
4309 #define WM8994_DMICDAT2_PD_MASK                 0x0400  /* DMICDAT2_PD */
4310 #define WM8994_DMICDAT2_PD_SHIFT                    10  /* DMICDAT2_PD */
4311 #define WM8994_DMICDAT2_PD_WIDTH                     1  /* DMICDAT2_PD */
4312 #define WM8994_DMICDAT1_PU                      0x0200  /* DMICDAT1_PU */
4313 #define WM8994_DMICDAT1_PU_MASK                 0x0200  /* DMICDAT1_PU */
4314 #define WM8994_DMICDAT1_PU_SHIFT                     9  /* DMICDAT1_PU */
4315 #define WM8994_DMICDAT1_PU_WIDTH                     1  /* DMICDAT1_PU */
4316 #define WM8994_DMICDAT1_PD                      0x0100  /* DMICDAT1_PD */
4317 #define WM8994_DMICDAT1_PD_MASK                 0x0100  /* DMICDAT1_PD */
4318 #define WM8994_DMICDAT1_PD_SHIFT                     8  /* DMICDAT1_PD */
4319 #define WM8994_DMICDAT1_PD_WIDTH                     1  /* DMICDAT1_PD */
4320 #define WM8994_MCLK1_PU                         0x0080  /* MCLK1_PU */
4321 #define WM8994_MCLK1_PU_MASK                    0x0080  /* MCLK1_PU */
4322 #define WM8994_MCLK1_PU_SHIFT                        7  /* MCLK1_PU */
4323 #define WM8994_MCLK1_PU_WIDTH                        1  /* MCLK1_PU */
4324 #define WM8994_MCLK1_PD                         0x0040  /* MCLK1_PD */
4325 #define WM8994_MCLK1_PD_MASK                    0x0040  /* MCLK1_PD */
4326 #define WM8994_MCLK1_PD_SHIFT                        6  /* MCLK1_PD */
4327 #define WM8994_MCLK1_PD_WIDTH                        1  /* MCLK1_PD */
4328 #define WM8994_DACDAT1_PU                       0x0020  /* DACDAT1_PU */
4329 #define WM8994_DACDAT1_PU_MASK                  0x0020  /* DACDAT1_PU */
4330 #define WM8994_DACDAT1_PU_SHIFT                      5  /* DACDAT1_PU */
4331 #define WM8994_DACDAT1_PU_WIDTH                      1  /* DACDAT1_PU */
4332 #define WM8994_DACDAT1_PD                       0x0010  /* DACDAT1_PD */
4333 #define WM8994_DACDAT1_PD_MASK                  0x0010  /* DACDAT1_PD */
4334 #define WM8994_DACDAT1_PD_SHIFT                      4  /* DACDAT1_PD */
4335 #define WM8994_DACDAT1_PD_WIDTH                      1  /* DACDAT1_PD */
4336 #define WM8994_DACLRCLK1_PU                     0x0008  /* DACLRCLK1_PU */
4337 #define WM8994_DACLRCLK1_PU_MASK                0x0008  /* DACLRCLK1_PU */
4338 #define WM8994_DACLRCLK1_PU_SHIFT                    3  /* DACLRCLK1_PU */
4339 #define WM8994_DACLRCLK1_PU_WIDTH                    1  /* DACLRCLK1_PU */
4340 #define WM8994_DACLRCLK1_PD                     0x0004  /* DACLRCLK1_PD */
4341 #define WM8994_DACLRCLK1_PD_MASK                0x0004  /* DACLRCLK1_PD */
4342 #define WM8994_DACLRCLK1_PD_SHIFT                    2  /* DACLRCLK1_PD */
4343 #define WM8994_DACLRCLK1_PD_WIDTH                    1  /* DACLRCLK1_PD */
4344 #define WM8994_BCLK1_PU                         0x0002  /* BCLK1_PU */
4345 #define WM8994_BCLK1_PU_MASK                    0x0002  /* BCLK1_PU */
4346 #define WM8994_BCLK1_PU_SHIFT                        1  /* BCLK1_PU */
4347 #define WM8994_BCLK1_PU_WIDTH                        1  /* BCLK1_PU */
4348 #define WM8994_BCLK1_PD                         0x0001  /* BCLK1_PD */
4349 #define WM8994_BCLK1_PD_MASK                    0x0001  /* BCLK1_PD */
4350 #define WM8994_BCLK1_PD_SHIFT                        0  /* BCLK1_PD */
4351 #define WM8994_BCLK1_PD_WIDTH                        1  /* BCLK1_PD */
4352 
4353 /*
4354  * R1825 (0x721) - Pull Control (2)
4355  */
4356 #define WM8994_CSNADDR_PD                       0x0100  /* CSNADDR_PD */
4357 #define WM8994_CSNADDR_PD_MASK                  0x0100  /* CSNADDR_PD */
4358 #define WM8994_CSNADDR_PD_SHIFT                      8  /* CSNADDR_PD */
4359 #define WM8994_CSNADDR_PD_WIDTH                      1  /* CSNADDR_PD */
4360 #define WM8994_LDO2ENA_PD                       0x0040  /* LDO2ENA_PD */
4361 #define WM8994_LDO2ENA_PD_MASK                  0x0040  /* LDO2ENA_PD */
4362 #define WM8994_LDO2ENA_PD_SHIFT                      6  /* LDO2ENA_PD */
4363 #define WM8994_LDO2ENA_PD_WIDTH                      1  /* LDO2ENA_PD */
4364 #define WM8994_LDO1ENA_PD                       0x0010  /* LDO1ENA_PD */
4365 #define WM8994_LDO1ENA_PD_MASK                  0x0010  /* LDO1ENA_PD */
4366 #define WM8994_LDO1ENA_PD_SHIFT                      4  /* LDO1ENA_PD */
4367 #define WM8994_LDO1ENA_PD_WIDTH                      1  /* LDO1ENA_PD */
4368 #define WM8994_CIFMODE_PD                       0x0004  /* CIFMODE_PD */
4369 #define WM8994_CIFMODE_PD_MASK                  0x0004  /* CIFMODE_PD */
4370 #define WM8994_CIFMODE_PD_SHIFT                      2  /* CIFMODE_PD */
4371 #define WM8994_CIFMODE_PD_WIDTH                      1  /* CIFMODE_PD */
4372 #define WM8994_SPKMODE_PU                       0x0002  /* SPKMODE_PU */
4373 #define WM8994_SPKMODE_PU_MASK                  0x0002  /* SPKMODE_PU */
4374 #define WM8994_SPKMODE_PU_SHIFT                      1  /* SPKMODE_PU */
4375 #define WM8994_SPKMODE_PU_WIDTH                      1  /* SPKMODE_PU */
4376 
4377 /*
4378  * R1840 (0x730) - Interrupt Status 1
4379  */
4380 #define WM8994_GP11_EINT                        0x0400  /* GP11_EINT */
4381 #define WM8994_GP11_EINT_MASK                   0x0400  /* GP11_EINT */
4382 #define WM8994_GP11_EINT_SHIFT                      10  /* GP11_EINT */
4383 #define WM8994_GP11_EINT_WIDTH                       1  /* GP11_EINT */
4384 #define WM8994_GP10_EINT                        0x0200  /* GP10_EINT */
4385 #define WM8994_GP10_EINT_MASK                   0x0200  /* GP10_EINT */
4386 #define WM8994_GP10_EINT_SHIFT                       9  /* GP10_EINT */
4387 #define WM8994_GP10_EINT_WIDTH                       1  /* GP10_EINT */
4388 #define WM8994_GP9_EINT                         0x0100  /* GP9_EINT */
4389 #define WM8994_GP9_EINT_MASK                    0x0100  /* GP9_EINT */
4390 #define WM8994_GP9_EINT_SHIFT                        8  /* GP9_EINT */
4391 #define WM8994_GP9_EINT_WIDTH                        1  /* GP9_EINT */
4392 #define WM8994_GP8_EINT                         0x0080  /* GP8_EINT */
4393 #define WM8994_GP8_EINT_MASK                    0x0080  /* GP8_EINT */
4394 #define WM8994_GP8_EINT_SHIFT                        7  /* GP8_EINT */
4395 #define WM8994_GP8_EINT_WIDTH                        1  /* GP8_EINT */
4396 #define WM8994_GP7_EINT                         0x0040  /* GP7_EINT */
4397 #define WM8994_GP7_EINT_MASK                    0x0040  /* GP7_EINT */
4398 #define WM8994_GP7_EINT_SHIFT                        6  /* GP7_EINT */
4399 #define WM8994_GP7_EINT_WIDTH                        1  /* GP7_EINT */
4400 #define WM8994_GP6_EINT                         0x0020  /* GP6_EINT */
4401 #define WM8994_GP6_EINT_MASK                    0x0020  /* GP6_EINT */
4402 #define WM8994_GP6_EINT_SHIFT                        5  /* GP6_EINT */
4403 #define WM8994_GP6_EINT_WIDTH                        1  /* GP6_EINT */
4404 #define WM8994_GP5_EINT                         0x0010  /* GP5_EINT */
4405 #define WM8994_GP5_EINT_MASK                    0x0010  /* GP5_EINT */
4406 #define WM8994_GP5_EINT_SHIFT                        4  /* GP5_EINT */
4407 #define WM8994_GP5_EINT_WIDTH                        1  /* GP5_EINT */
4408 #define WM8994_GP4_EINT                         0x0008  /* GP4_EINT */
4409 #define WM8994_GP4_EINT_MASK                    0x0008  /* GP4_EINT */
4410 #define WM8994_GP4_EINT_SHIFT                        3  /* GP4_EINT */
4411 #define WM8994_GP4_EINT_WIDTH                        1  /* GP4_EINT */
4412 #define WM8994_GP3_EINT                         0x0004  /* GP3_EINT */
4413 #define WM8994_GP3_EINT_MASK                    0x0004  /* GP3_EINT */
4414 #define WM8994_GP3_EINT_SHIFT                        2  /* GP3_EINT */
4415 #define WM8994_GP3_EINT_WIDTH                        1  /* GP3_EINT */
4416 #define WM8994_GP2_EINT                         0x0002  /* GP2_EINT */
4417 #define WM8994_GP2_EINT_MASK                    0x0002  /* GP2_EINT */
4418 #define WM8994_GP2_EINT_SHIFT                        1  /* GP2_EINT */
4419 #define WM8994_GP2_EINT_WIDTH                        1  /* GP2_EINT */
4420 #define WM8994_GP1_EINT                         0x0001  /* GP1_EINT */
4421 #define WM8994_GP1_EINT_MASK                    0x0001  /* GP1_EINT */
4422 #define WM8994_GP1_EINT_SHIFT                        0  /* GP1_EINT */
4423 #define WM8994_GP1_EINT_WIDTH                        1  /* GP1_EINT */
4424 
4425 /*
4426  * R1841 (0x731) - Interrupt Status 2
4427  */
4428 #define WM8994_TEMP_WARN_EINT                   0x8000  /* TEMP_WARN_EINT */
4429 #define WM8994_TEMP_WARN_EINT_MASK              0x8000  /* TEMP_WARN_EINT */
4430 #define WM8994_TEMP_WARN_EINT_SHIFT                 15  /* TEMP_WARN_EINT */
4431 #define WM8994_TEMP_WARN_EINT_WIDTH                  1  /* TEMP_WARN_EINT */
4432 #define WM8994_DCS_DONE_EINT                    0x4000  /* DCS_DONE_EINT */
4433 #define WM8994_DCS_DONE_EINT_MASK               0x4000  /* DCS_DONE_EINT */
4434 #define WM8994_DCS_DONE_EINT_SHIFT                  14  /* DCS_DONE_EINT */
4435 #define WM8994_DCS_DONE_EINT_WIDTH                   1  /* DCS_DONE_EINT */
4436 #define WM8994_WSEQ_DONE_EINT                   0x2000  /* WSEQ_DONE_EINT */
4437 #define WM8994_WSEQ_DONE_EINT_MASK              0x2000  /* WSEQ_DONE_EINT */
4438 #define WM8994_WSEQ_DONE_EINT_SHIFT                 13  /* WSEQ_DONE_EINT */
4439 #define WM8994_WSEQ_DONE_EINT_WIDTH                  1  /* WSEQ_DONE_EINT */
4440 #define WM8994_FIFOS_ERR_EINT                   0x1000  /* FIFOS_ERR_EINT */
4441 #define WM8994_FIFOS_ERR_EINT_MASK              0x1000  /* FIFOS_ERR_EINT */
4442 #define WM8994_FIFOS_ERR_EINT_SHIFT                 12  /* FIFOS_ERR_EINT */
4443 #define WM8994_FIFOS_ERR_EINT_WIDTH                  1  /* FIFOS_ERR_EINT */
4444 #define WM8994_AIF2DRC_SIG_DET_EINT             0x0800  /* AIF2DRC_SIG_DET_EINT */
4445 #define WM8994_AIF2DRC_SIG_DET_EINT_MASK        0x0800  /* AIF2DRC_SIG_DET_EINT */
4446 #define WM8994_AIF2DRC_SIG_DET_EINT_SHIFT           11  /* AIF2DRC_SIG_DET_EINT */
4447 #define WM8994_AIF2DRC_SIG_DET_EINT_WIDTH            1  /* AIF2DRC_SIG_DET_EINT */
4448 #define WM8994_AIF1DRC2_SIG_DET_EINT            0x0400  /* AIF1DRC2_SIG_DET_EINT */
4449 #define WM8994_AIF1DRC2_SIG_DET_EINT_MASK       0x0400  /* AIF1DRC2_SIG_DET_EINT */
4450 #define WM8994_AIF1DRC2_SIG_DET_EINT_SHIFT          10  /* AIF1DRC2_SIG_DET_EINT */
4451 #define WM8994_AIF1DRC2_SIG_DET_EINT_WIDTH           1  /* AIF1DRC2_SIG_DET_EINT */
4452 #define WM8994_AIF1DRC1_SIG_DET_EINT            0x0200  /* AIF1DRC1_SIG_DET_EINT */
4453 #define WM8994_AIF1DRC1_SIG_DET_EINT_MASK       0x0200  /* AIF1DRC1_SIG_DET_EINT */
4454 #define WM8994_AIF1DRC1_SIG_DET_EINT_SHIFT           9  /* AIF1DRC1_SIG_DET_EINT */
4455 #define WM8994_AIF1DRC1_SIG_DET_EINT_WIDTH           1  /* AIF1DRC1_SIG_DET_EINT */
4456 #define WM8994_SRC2_LOCK_EINT                   0x0100  /* SRC2_LOCK_EINT */
4457 #define WM8994_SRC2_LOCK_EINT_MASK              0x0100  /* SRC2_LOCK_EINT */
4458 #define WM8994_SRC2_LOCK_EINT_SHIFT                  8  /* SRC2_LOCK_EINT */
4459 #define WM8994_SRC2_LOCK_EINT_WIDTH                  1  /* SRC2_LOCK_EINT */
4460 #define WM8994_SRC1_LOCK_EINT                   0x0080  /* SRC1_LOCK_EINT */
4461 #define WM8994_SRC1_LOCK_EINT_MASK              0x0080  /* SRC1_LOCK_EINT */
4462 #define WM8994_SRC1_LOCK_EINT_SHIFT                  7  /* SRC1_LOCK_EINT */
4463 #define WM8994_SRC1_LOCK_EINT_WIDTH                  1  /* SRC1_LOCK_EINT */
4464 #define WM8994_FLL2_LOCK_EINT                   0x0040  /* FLL2_LOCK_EINT */
4465 #define WM8994_FLL2_LOCK_EINT_MASK              0x0040  /* FLL2_LOCK_EINT */
4466 #define WM8994_FLL2_LOCK_EINT_SHIFT                  6  /* FLL2_LOCK_EINT */
4467 #define WM8994_FLL2_LOCK_EINT_WIDTH                  1  /* FLL2_LOCK_EINT */
4468 #define WM8994_FLL1_LOCK_EINT                   0x0020  /* FLL1_LOCK_EINT */
4469 #define WM8994_FLL1_LOCK_EINT_MASK              0x0020  /* FLL1_LOCK_EINT */
4470 #define WM8994_FLL1_LOCK_EINT_SHIFT                  5  /* FLL1_LOCK_EINT */
4471 #define WM8994_FLL1_LOCK_EINT_WIDTH                  1  /* FLL1_LOCK_EINT */
4472 #define WM8994_MIC2_SHRT_EINT                   0x0010  /* MIC2_SHRT_EINT */
4473 #define WM8994_MIC2_SHRT_EINT_MASK              0x0010  /* MIC2_SHRT_EINT */
4474 #define WM8994_MIC2_SHRT_EINT_SHIFT                  4  /* MIC2_SHRT_EINT */
4475 #define WM8994_MIC2_SHRT_EINT_WIDTH                  1  /* MIC2_SHRT_EINT */
4476 #define WM8994_MIC2_DET_EINT                    0x0008  /* MIC2_DET_EINT */
4477 #define WM8994_MIC2_DET_EINT_MASK               0x0008  /* MIC2_DET_EINT */
4478 #define WM8994_MIC2_DET_EINT_SHIFT                   3  /* MIC2_DET_EINT */
4479 #define WM8994_MIC2_DET_EINT_WIDTH                   1  /* MIC2_DET_EINT */
4480 #define WM8994_MIC1_SHRT_EINT                   0x0004  /* MIC1_SHRT_EINT */
4481 #define WM8994_MIC1_SHRT_EINT_MASK              0x0004  /* MIC1_SHRT_EINT */
4482 #define WM8994_MIC1_SHRT_EINT_SHIFT                  2  /* MIC1_SHRT_EINT */
4483 #define WM8994_MIC1_SHRT_EINT_WIDTH                  1  /* MIC1_SHRT_EINT */
4484 #define WM8994_MIC1_DET_EINT                    0x0002  /* MIC1_DET_EINT */
4485 #define WM8994_MIC1_DET_EINT_MASK               0x0002  /* MIC1_DET_EINT */
4486 #define WM8994_MIC1_DET_EINT_SHIFT                   1  /* MIC1_DET_EINT */
4487 #define WM8994_MIC1_DET_EINT_WIDTH                   1  /* MIC1_DET_EINT */
4488 #define WM8994_TEMP_SHUT_EINT                   0x0001  /* TEMP_SHUT_EINT */
4489 #define WM8994_TEMP_SHUT_EINT_MASK              0x0001  /* TEMP_SHUT_EINT */
4490 #define WM8994_TEMP_SHUT_EINT_SHIFT                  0  /* TEMP_SHUT_EINT */
4491 #define WM8994_TEMP_SHUT_EINT_WIDTH                  1  /* TEMP_SHUT_EINT */
4492 
4493 /*
4494  * R1842 (0x732) - Interrupt Raw Status 2
4495  */
4496 #define WM8994_TEMP_WARN_STS                    0x8000  /* TEMP_WARN_STS */
4497 #define WM8994_TEMP_WARN_STS_MASK               0x8000  /* TEMP_WARN_STS */
4498 #define WM8994_TEMP_WARN_STS_SHIFT                  15  /* TEMP_WARN_STS */
4499 #define WM8994_TEMP_WARN_STS_WIDTH                   1  /* TEMP_WARN_STS */
4500 #define WM8994_DCS_DONE_STS                     0x4000  /* DCS_DONE_STS */
4501 #define WM8994_DCS_DONE_STS_MASK                0x4000  /* DCS_DONE_STS */
4502 #define WM8994_DCS_DONE_STS_SHIFT                   14  /* DCS_DONE_STS */
4503 #define WM8994_DCS_DONE_STS_WIDTH                    1  /* DCS_DONE_STS */
4504 #define WM8994_WSEQ_DONE_STS                    0x2000  /* WSEQ_DONE_STS */
4505 #define WM8994_WSEQ_DONE_STS_MASK               0x2000  /* WSEQ_DONE_STS */
4506 #define WM8994_WSEQ_DONE_STS_SHIFT                  13  /* WSEQ_DONE_STS */
4507 #define WM8994_WSEQ_DONE_STS_WIDTH                   1  /* WSEQ_DONE_STS */
4508 #define WM8994_FIFOS_ERR_STS                    0x1000  /* FIFOS_ERR_STS */
4509 #define WM8994_FIFOS_ERR_STS_MASK               0x1000  /* FIFOS_ERR_STS */
4510 #define WM8994_FIFOS_ERR_STS_SHIFT                  12  /* FIFOS_ERR_STS */
4511 #define WM8994_FIFOS_ERR_STS_WIDTH                   1  /* FIFOS_ERR_STS */
4512 #define WM8994_AIF2DRC_SIG_DET_STS              0x0800  /* AIF2DRC_SIG_DET_STS */
4513 #define WM8994_AIF2DRC_SIG_DET_STS_MASK         0x0800  /* AIF2DRC_SIG_DET_STS */
4514 #define WM8994_AIF2DRC_SIG_DET_STS_SHIFT            11  /* AIF2DRC_SIG_DET_STS */
4515 #define WM8994_AIF2DRC_SIG_DET_STS_WIDTH             1  /* AIF2DRC_SIG_DET_STS */
4516 #define WM8994_AIF1DRC2_SIG_DET_STS             0x0400  /* AIF1DRC2_SIG_DET_STS */
4517 #define WM8994_AIF1DRC2_SIG_DET_STS_MASK        0x0400  /* AIF1DRC2_SIG_DET_STS */
4518 #define WM8994_AIF1DRC2_SIG_DET_STS_SHIFT           10  /* AIF1DRC2_SIG_DET_STS */
4519 #define WM8994_AIF1DRC2_SIG_DET_STS_WIDTH            1  /* AIF1DRC2_SIG_DET_STS */
4520 #define WM8994_AIF1DRC1_SIG_DET_STS             0x0200  /* AIF1DRC1_SIG_DET_STS */
4521 #define WM8994_AIF1DRC1_SIG_DET_STS_MASK        0x0200  /* AIF1DRC1_SIG_DET_STS */
4522 #define WM8994_AIF1DRC1_SIG_DET_STS_SHIFT            9  /* AIF1DRC1_SIG_DET_STS */
4523 #define WM8994_AIF1DRC1_SIG_DET_STS_WIDTH            1  /* AIF1DRC1_SIG_DET_STS */
4524 #define WM8994_SRC2_LOCK_STS                    0x0100  /* SRC2_LOCK_STS */
4525 #define WM8994_SRC2_LOCK_STS_MASK               0x0100  /* SRC2_LOCK_STS */
4526 #define WM8994_SRC2_LOCK_STS_SHIFT                   8  /* SRC2_LOCK_STS */
4527 #define WM8994_SRC2_LOCK_STS_WIDTH                   1  /* SRC2_LOCK_STS */
4528 #define WM8994_SRC1_LOCK_STS                    0x0080  /* SRC1_LOCK_STS */
4529 #define WM8994_SRC1_LOCK_STS_MASK               0x0080  /* SRC1_LOCK_STS */
4530 #define WM8994_SRC1_LOCK_STS_SHIFT                   7  /* SRC1_LOCK_STS */
4531 #define WM8994_SRC1_LOCK_STS_WIDTH                   1  /* SRC1_LOCK_STS */
4532 #define WM8994_FLL2_LOCK_STS                    0x0040  /* FLL2_LOCK_STS */
4533 #define WM8994_FLL2_LOCK_STS_MASK               0x0040  /* FLL2_LOCK_STS */
4534 #define WM8994_FLL2_LOCK_STS_SHIFT                   6  /* FLL2_LOCK_STS */
4535 #define WM8994_FLL2_LOCK_STS_WIDTH                   1  /* FLL2_LOCK_STS */
4536 #define WM8994_FLL1_LOCK_STS                    0x0020  /* FLL1_LOCK_STS */
4537 #define WM8994_FLL1_LOCK_STS_MASK               0x0020  /* FLL1_LOCK_STS */
4538 #define WM8994_FLL1_LOCK_STS_SHIFT                   5  /* FLL1_LOCK_STS */
4539 #define WM8994_FLL1_LOCK_STS_WIDTH                   1  /* FLL1_LOCK_STS */
4540 #define WM8994_MIC2_SHRT_STS                    0x0010  /* MIC2_SHRT_STS */
4541 #define WM8994_MIC2_SHRT_STS_MASK               0x0010  /* MIC2_SHRT_STS */
4542 #define WM8994_MIC2_SHRT_STS_SHIFT                   4  /* MIC2_SHRT_STS */
4543 #define WM8994_MIC2_SHRT_STS_WIDTH                   1  /* MIC2_SHRT_STS */
4544 #define WM8994_MIC2_DET_STS                     0x0008  /* MIC2_DET_STS */
4545 #define WM8994_MIC2_DET_STS_MASK                0x0008  /* MIC2_DET_STS */
4546 #define WM8994_MIC2_DET_STS_SHIFT                    3  /* MIC2_DET_STS */
4547 #define WM8994_MIC2_DET_STS_WIDTH                    1  /* MIC2_DET_STS */
4548 #define WM8994_MIC1_SHRT_STS                    0x0004  /* MIC1_SHRT_STS */
4549 #define WM8994_MIC1_SHRT_STS_MASK               0x0004  /* MIC1_SHRT_STS */
4550 #define WM8994_MIC1_SHRT_STS_SHIFT                   2  /* MIC1_SHRT_STS */
4551 #define WM8994_MIC1_SHRT_STS_WIDTH                   1  /* MIC1_SHRT_STS */
4552 #define WM8994_MIC1_DET_STS                     0x0002  /* MIC1_DET_STS */
4553 #define WM8994_MIC1_DET_STS_MASK                0x0002  /* MIC1_DET_STS */
4554 #define WM8994_MIC1_DET_STS_SHIFT                    1  /* MIC1_DET_STS */
4555 #define WM8994_MIC1_DET_STS_WIDTH                    1  /* MIC1_DET_STS */
4556 #define WM8994_TEMP_SHUT_STS                    0x0001  /* TEMP_SHUT_STS */
4557 #define WM8994_TEMP_SHUT_STS_MASK               0x0001  /* TEMP_SHUT_STS */
4558 #define WM8994_TEMP_SHUT_STS_SHIFT                   0  /* TEMP_SHUT_STS */
4559 #define WM8994_TEMP_SHUT_STS_WIDTH                   1  /* TEMP_SHUT_STS */
4560 
4561 /*
4562  * R1848 (0x738) - Interrupt Status 1 Mask
4563  */
4564 #define WM8994_IM_GP11_EINT                     0x0400  /* IM_GP11_EINT */
4565 #define WM8994_IM_GP11_EINT_MASK                0x0400  /* IM_GP11_EINT */
4566 #define WM8994_IM_GP11_EINT_SHIFT                   10  /* IM_GP11_EINT */
4567 #define WM8994_IM_GP11_EINT_WIDTH                    1  /* IM_GP11_EINT */
4568 #define WM8994_IM_GP10_EINT                     0x0200  /* IM_GP10_EINT */
4569 #define WM8994_IM_GP10_EINT_MASK                0x0200  /* IM_GP10_EINT */
4570 #define WM8994_IM_GP10_EINT_SHIFT                    9  /* IM_GP10_EINT */
4571 #define WM8994_IM_GP10_EINT_WIDTH                    1  /* IM_GP10_EINT */
4572 #define WM8994_IM_GP9_EINT                      0x0100  /* IM_GP9_EINT */
4573 #define WM8994_IM_GP9_EINT_MASK                 0x0100  /* IM_GP9_EINT */
4574 #define WM8994_IM_GP9_EINT_SHIFT                     8  /* IM_GP9_EINT */
4575 #define WM8994_IM_GP9_EINT_WIDTH                     1  /* IM_GP9_EINT */
4576 #define WM8994_IM_GP8_EINT                      0x0080  /* IM_GP8_EINT */
4577 #define WM8994_IM_GP8_EINT_MASK                 0x0080  /* IM_GP8_EINT */
4578 #define WM8994_IM_GP8_EINT_SHIFT                     7  /* IM_GP8_EINT */
4579 #define WM8994_IM_GP8_EINT_WIDTH                     1  /* IM_GP8_EINT */
4580 #define WM8994_IM_GP7_EINT                      0x0040  /* IM_GP7_EINT */
4581 #define WM8994_IM_GP7_EINT_MASK                 0x0040  /* IM_GP7_EINT */
4582 #define WM8994_IM_GP7_EINT_SHIFT                     6  /* IM_GP7_EINT */
4583 #define WM8994_IM_GP7_EINT_WIDTH                     1  /* IM_GP7_EINT */
4584 #define WM8994_IM_GP6_EINT                      0x0020  /* IM_GP6_EINT */
4585 #define WM8994_IM_GP6_EINT_MASK                 0x0020  /* IM_GP6_EINT */
4586 #define WM8994_IM_GP6_EINT_SHIFT                     5  /* IM_GP6_EINT */
4587 #define WM8994_IM_GP6_EINT_WIDTH                     1  /* IM_GP6_EINT */
4588 #define WM8994_IM_GP5_EINT                      0x0010  /* IM_GP5_EINT */
4589 #define WM8994_IM_GP5_EINT_MASK                 0x0010  /* IM_GP5_EINT */
4590 #define WM8994_IM_GP5_EINT_SHIFT                     4  /* IM_GP5_EINT */
4591 #define WM8994_IM_GP5_EINT_WIDTH                     1  /* IM_GP5_EINT */
4592 #define WM8994_IM_GP4_EINT                      0x0008  /* IM_GP4_EINT */
4593 #define WM8994_IM_GP4_EINT_MASK                 0x0008  /* IM_GP4_EINT */
4594 #define WM8994_IM_GP4_EINT_SHIFT                     3  /* IM_GP4_EINT */
4595 #define WM8994_IM_GP4_EINT_WIDTH                     1  /* IM_GP4_EINT */
4596 #define WM8994_IM_GP3_EINT                      0x0004  /* IM_GP3_EINT */
4597 #define WM8994_IM_GP3_EINT_MASK                 0x0004  /* IM_GP3_EINT */
4598 #define WM8994_IM_GP3_EINT_SHIFT                     2  /* IM_GP3_EINT */
4599 #define WM8994_IM_GP3_EINT_WIDTH                     1  /* IM_GP3_EINT */
4600 #define WM8994_IM_GP2_EINT                      0x0002  /* IM_GP2_EINT */
4601 #define WM8994_IM_GP2_EINT_MASK                 0x0002  /* IM_GP2_EINT */
4602 #define WM8994_IM_GP2_EINT_SHIFT                     1  /* IM_GP2_EINT */
4603 #define WM8994_IM_GP2_EINT_WIDTH                     1  /* IM_GP2_EINT */
4604 #define WM8994_IM_GP1_EINT                      0x0001  /* IM_GP1_EINT */
4605 #define WM8994_IM_GP1_EINT_MASK                 0x0001  /* IM_GP1_EINT */
4606 #define WM8994_IM_GP1_EINT_SHIFT                     0  /* IM_GP1_EINT */
4607 #define WM8994_IM_GP1_EINT_WIDTH                     1  /* IM_GP1_EINT */
4608 
4609 /*
4610  * R1849 (0x739) - Interrupt Status 2 Mask
4611  */
4612 #define WM8994_IM_TEMP_WARN_EINT                0x8000  /* IM_TEMP_WARN_EINT */
4613 #define WM8994_IM_TEMP_WARN_EINT_MASK           0x8000  /* IM_TEMP_WARN_EINT */
4614 #define WM8994_IM_TEMP_WARN_EINT_SHIFT              15  /* IM_TEMP_WARN_EINT */
4615 #define WM8994_IM_TEMP_WARN_EINT_WIDTH               1  /* IM_TEMP_WARN_EINT */
4616 #define WM8994_IM_DCS_DONE_EINT                 0x4000  /* IM_DCS_DONE_EINT */
4617 #define WM8994_IM_DCS_DONE_EINT_MASK            0x4000  /* IM_DCS_DONE_EINT */
4618 #define WM8994_IM_DCS_DONE_EINT_SHIFT               14  /* IM_DCS_DONE_EINT */
4619 #define WM8994_IM_DCS_DONE_EINT_WIDTH                1  /* IM_DCS_DONE_EINT */
4620 #define WM8994_IM_WSEQ_DONE_EINT                0x2000  /* IM_WSEQ_DONE_EINT */
4621 #define WM8994_IM_WSEQ_DONE_EINT_MASK           0x2000  /* IM_WSEQ_DONE_EINT */
4622 #define WM8994_IM_WSEQ_DONE_EINT_SHIFT              13  /* IM_WSEQ_DONE_EINT */
4623 #define WM8994_IM_WSEQ_DONE_EINT_WIDTH               1  /* IM_WSEQ_DONE_EINT */
4624 #define WM8994_IM_FIFOS_ERR_EINT                0x1000  /* IM_FIFOS_ERR_EINT */
4625 #define WM8994_IM_FIFOS_ERR_EINT_MASK           0x1000  /* IM_FIFOS_ERR_EINT */
4626 #define WM8994_IM_FIFOS_ERR_EINT_SHIFT              12  /* IM_FIFOS_ERR_EINT */
4627 #define WM8994_IM_FIFOS_ERR_EINT_WIDTH               1  /* IM_FIFOS_ERR_EINT */
4628 #define WM8994_IM_AIF2DRC_SIG_DET_EINT          0x0800  /* IM_AIF2DRC_SIG_DET_EINT */
4629 #define WM8994_IM_AIF2DRC_SIG_DET_EINT_MASK     0x0800  /* IM_AIF2DRC_SIG_DET_EINT */
4630 #define WM8994_IM_AIF2DRC_SIG_DET_EINT_SHIFT        11  /* IM_AIF2DRC_SIG_DET_EINT */
4631 #define WM8994_IM_AIF2DRC_SIG_DET_EINT_WIDTH         1  /* IM_AIF2DRC_SIG_DET_EINT */
4632 #define WM8994_IM_AIF1DRC2_SIG_DET_EINT         0x0400  /* IM_AIF1DRC2_SIG_DET_EINT */
4633 #define WM8994_IM_AIF1DRC2_SIG_DET_EINT_MASK    0x0400  /* IM_AIF1DRC2_SIG_DET_EINT */
4634 #define WM8994_IM_AIF1DRC2_SIG_DET_EINT_SHIFT       10  /* IM_AIF1DRC2_SIG_DET_EINT */
4635 #define WM8994_IM_AIF1DRC2_SIG_DET_EINT_WIDTH        1  /* IM_AIF1DRC2_SIG_DET_EINT */
4636 #define WM8994_IM_AIF1DRC1_SIG_DET_EINT         0x0200  /* IM_AIF1DRC1_SIG_DET_EINT */
4637 #define WM8994_IM_AIF1DRC1_SIG_DET_EINT_MASK    0x0200  /* IM_AIF1DRC1_SIG_DET_EINT */
4638 #define WM8994_IM_AIF1DRC1_SIG_DET_EINT_SHIFT        9  /* IM_AIF1DRC1_SIG_DET_EINT */
4639 #define WM8994_IM_AIF1DRC1_SIG_DET_EINT_WIDTH        1  /* IM_AIF1DRC1_SIG_DET_EINT */
4640 #define WM8994_IM_SRC2_LOCK_EINT                0x0100  /* IM_SRC2_LOCK_EINT */
4641 #define WM8994_IM_SRC2_LOCK_EINT_MASK           0x0100  /* IM_SRC2_LOCK_EINT */
4642 #define WM8994_IM_SRC2_LOCK_EINT_SHIFT               8  /* IM_SRC2_LOCK_EINT */
4643 #define WM8994_IM_SRC2_LOCK_EINT_WIDTH               1  /* IM_SRC2_LOCK_EINT */
4644 #define WM8994_IM_SRC1_LOCK_EINT                0x0080  /* IM_SRC1_LOCK_EINT */
4645 #define WM8994_IM_SRC1_LOCK_EINT_MASK           0x0080  /* IM_SRC1_LOCK_EINT */
4646 #define WM8994_IM_SRC1_LOCK_EINT_SHIFT               7  /* IM_SRC1_LOCK_EINT */
4647 #define WM8994_IM_SRC1_LOCK_EINT_WIDTH               1  /* IM_SRC1_LOCK_EINT */
4648 #define WM8994_IM_FLL2_LOCK_EINT                0x0040  /* IM_FLL2_LOCK_EINT */
4649 #define WM8994_IM_FLL2_LOCK_EINT_MASK           0x0040  /* IM_FLL2_LOCK_EINT */
4650 #define WM8994_IM_FLL2_LOCK_EINT_SHIFT               6  /* IM_FLL2_LOCK_EINT */
4651 #define WM8994_IM_FLL2_LOCK_EINT_WIDTH               1  /* IM_FLL2_LOCK_EINT */
4652 #define WM8994_IM_FLL1_LOCK_EINT                0x0020  /* IM_FLL1_LOCK_EINT */
4653 #define WM8994_IM_FLL1_LOCK_EINT_MASK           0x0020  /* IM_FLL1_LOCK_EINT */
4654 #define WM8994_IM_FLL1_LOCK_EINT_SHIFT               5  /* IM_FLL1_LOCK_EINT */
4655 #define WM8994_IM_FLL1_LOCK_EINT_WIDTH               1  /* IM_FLL1_LOCK_EINT */
4656 #define WM8994_IM_MIC2_SHRT_EINT                0x0010  /* IM_MIC2_SHRT_EINT */
4657 #define WM8994_IM_MIC2_SHRT_EINT_MASK           0x0010  /* IM_MIC2_SHRT_EINT */
4658 #define WM8994_IM_MIC2_SHRT_EINT_SHIFT               4  /* IM_MIC2_SHRT_EINT */
4659 #define WM8994_IM_MIC2_SHRT_EINT_WIDTH               1  /* IM_MIC2_SHRT_EINT */
4660 #define WM8994_IM_MIC2_DET_EINT                 0x0008  /* IM_MIC2_DET_EINT */
4661 #define WM8994_IM_MIC2_DET_EINT_MASK            0x0008  /* IM_MIC2_DET_EINT */
4662 #define WM8994_IM_MIC2_DET_EINT_SHIFT                3  /* IM_MIC2_DET_EINT */
4663 #define WM8994_IM_MIC2_DET_EINT_WIDTH                1  /* IM_MIC2_DET_EINT */
4664 #define WM8994_IM_MIC1_SHRT_EINT                0x0004  /* IM_MIC1_SHRT_EINT */
4665 #define WM8994_IM_MIC1_SHRT_EINT_MASK           0x0004  /* IM_MIC1_SHRT_EINT */
4666 #define WM8994_IM_MIC1_SHRT_EINT_SHIFT               2  /* IM_MIC1_SHRT_EINT */
4667 #define WM8994_IM_MIC1_SHRT_EINT_WIDTH               1  /* IM_MIC1_SHRT_EINT */
4668 #define WM8994_IM_MIC1_DET_EINT                 0x0002  /* IM_MIC1_DET_EINT */
4669 #define WM8994_IM_MIC1_DET_EINT_MASK            0x0002  /* IM_MIC1_DET_EINT */
4670 #define WM8994_IM_MIC1_DET_EINT_SHIFT                1  /* IM_MIC1_DET_EINT */
4671 #define WM8994_IM_MIC1_DET_EINT_WIDTH                1  /* IM_MIC1_DET_EINT */
4672 #define WM8994_IM_TEMP_SHUT_EINT                0x0001  /* IM_TEMP_SHUT_EINT */
4673 #define WM8994_IM_TEMP_SHUT_EINT_MASK           0x0001  /* IM_TEMP_SHUT_EINT */
4674 #define WM8994_IM_TEMP_SHUT_EINT_SHIFT               0  /* IM_TEMP_SHUT_EINT */
4675 #define WM8994_IM_TEMP_SHUT_EINT_WIDTH               1  /* IM_TEMP_SHUT_EINT */
4676 
4677 /*
4678  * R1856 (0x740) - Interrupt Control
4679  */
4680 #define WM8994_IM_IRQ                           0x0001  /* IM_IRQ */
4681 #define WM8994_IM_IRQ_MASK                      0x0001  /* IM_IRQ */
4682 #define WM8994_IM_IRQ_SHIFT                          0  /* IM_IRQ */
4683 #define WM8994_IM_IRQ_WIDTH                          1  /* IM_IRQ */
4684 
4685 /*
4686  * R1864 (0x748) - IRQ Debounce
4687  */
4688 #define WM8994_TEMP_WARN_DB                     0x0020  /* TEMP_WARN_DB */
4689 #define WM8994_TEMP_WARN_DB_MASK                0x0020  /* TEMP_WARN_DB */
4690 #define WM8994_TEMP_WARN_DB_SHIFT                    5  /* TEMP_WARN_DB */
4691 #define WM8994_TEMP_WARN_DB_WIDTH                    1  /* TEMP_WARN_DB */
4692 #define WM8994_MIC2_SHRT_DB                     0x0010  /* MIC2_SHRT_DB */
4693 #define WM8994_MIC2_SHRT_DB_MASK                0x0010  /* MIC2_SHRT_DB */
4694 #define WM8994_MIC2_SHRT_DB_SHIFT                    4  /* MIC2_SHRT_DB */
4695 #define WM8994_MIC2_SHRT_DB_WIDTH                    1  /* MIC2_SHRT_DB */
4696 #define WM8994_MIC2_DET_DB                      0x0008  /* MIC2_DET_DB */
4697 #define WM8994_MIC2_DET_DB_MASK                 0x0008  /* MIC2_DET_DB */
4698 #define WM8994_MIC2_DET_DB_SHIFT                     3  /* MIC2_DET_DB */
4699 #define WM8994_MIC2_DET_DB_WIDTH                     1  /* MIC2_DET_DB */
4700 #define WM8994_MIC1_SHRT_DB                     0x0004  /* MIC1_SHRT_DB */
4701 #define WM8994_MIC1_SHRT_DB_MASK                0x0004  /* MIC1_SHRT_DB */
4702 #define WM8994_MIC1_SHRT_DB_SHIFT                    2  /* MIC1_SHRT_DB */
4703 #define WM8994_MIC1_SHRT_DB_WIDTH                    1  /* MIC1_SHRT_DB */
4704 #define WM8994_MIC1_DET_DB                      0x0002  /* MIC1_DET_DB */
4705 #define WM8994_MIC1_DET_DB_MASK                 0x0002  /* MIC1_DET_DB */
4706 #define WM8994_MIC1_DET_DB_SHIFT                     1  /* MIC1_DET_DB */
4707 #define WM8994_MIC1_DET_DB_WIDTH                     1  /* MIC1_DET_DB */
4708 #define WM8994_TEMP_SHUT_DB                     0x0001  /* TEMP_SHUT_DB */
4709 #define WM8994_TEMP_SHUT_DB_MASK                0x0001  /* TEMP_SHUT_DB */
4710 #define WM8994_TEMP_SHUT_DB_SHIFT                    0  /* TEMP_SHUT_DB */
4711 #define WM8994_TEMP_SHUT_DB_WIDTH                    1  /* TEMP_SHUT_DB */
4712 
4713 /*
4714  * R2304 (0x900) - DSP2_Program
4715  */
4716 #define WM8958_DSP2_ENA                         0x0001  /* DSP2_ENA */
4717 #define WM8958_DSP2_ENA_MASK                    0x0001  /* DSP2_ENA */
4718 #define WM8958_DSP2_ENA_SHIFT                        0  /* DSP2_ENA */
4719 #define WM8958_DSP2_ENA_WIDTH                        1  /* DSP2_ENA */
4720 
4721 /*
4722  * R2305 (0x901) - DSP2_Config
4723  */
4724 #define WM8958_MBC_SEL_MASK                     0x0030  /* MBC_SEL - [5:4] */
4725 #define WM8958_MBC_SEL_SHIFT                         4  /* MBC_SEL - [5:4] */
4726 #define WM8958_MBC_SEL_WIDTH                         2  /* MBC_SEL - [5:4] */
4727 #define WM8958_MBC_ENA                          0x0001  /* MBC_ENA */
4728 #define WM8958_MBC_ENA_MASK                     0x0001  /* MBC_ENA */
4729 #define WM8958_MBC_ENA_SHIFT                         0  /* MBC_ENA */
4730 #define WM8958_MBC_ENA_WIDTH                         1  /* MBC_ENA */
4731 
4732 /*
4733  * R2560 (0xA00) - DSP2_MagicNum
4734  */
4735 #define WM8958_DSP2_MAGIC_NUM_MASK              0xFFFF  /* DSP2_MAGIC_NUM - [15:0] */
4736 #define WM8958_DSP2_MAGIC_NUM_SHIFT                  0  /* DSP2_MAGIC_NUM - [15:0] */
4737 #define WM8958_DSP2_MAGIC_NUM_WIDTH                 16  /* DSP2_MAGIC_NUM - [15:0] */
4738 
4739 /*
4740  * R2561 (0xA01) - DSP2_ReleaseYear
4741  */
4742 #define WM8958_DSP2_RELEASE_YEAR_MASK           0xFFFF  /* DSP2_RELEASE_YEAR - [15:0] */
4743 #define WM8958_DSP2_RELEASE_YEAR_SHIFT               0  /* DSP2_RELEASE_YEAR - [15:0] */
4744 #define WM8958_DSP2_RELEASE_YEAR_WIDTH              16  /* DSP2_RELEASE_YEAR - [15:0] */
4745 
4746 /*
4747  * R2562 (0xA02) - DSP2_ReleaseMonthDay
4748  */
4749 #define WM8958_DSP2_RELEASE_MONTH_MASK          0xFF00  /* DSP2_RELEASE_MONTH - [15:8] */
4750 #define WM8958_DSP2_RELEASE_MONTH_SHIFT              8  /* DSP2_RELEASE_MONTH - [15:8] */
4751 #define WM8958_DSP2_RELEASE_MONTH_WIDTH              8  /* DSP2_RELEASE_MONTH - [15:8] */
4752 #define WM8958_DSP2_RELEASE_DAY_MASK            0x00FF  /* DSP2_RELEASE_DAY - [7:0] */
4753 #define WM8958_DSP2_RELEASE_DAY_SHIFT                0  /* DSP2_RELEASE_DAY - [7:0] */
4754 #define WM8958_DSP2_RELEASE_DAY_WIDTH                8  /* DSP2_RELEASE_DAY - [7:0] */
4755 
4756 /*
4757  * R2563 (0xA03) - DSP2_ReleaseTime
4758  */
4759 #define WM8958_DSP2_RELEASE_HOURS_MASK          0xFF00  /* DSP2_RELEASE_HOURS - [15:8] */
4760 #define WM8958_DSP2_RELEASE_HOURS_SHIFT              8  /* DSP2_RELEASE_HOURS - [15:8] */
4761 #define WM8958_DSP2_RELEASE_HOURS_WIDTH              8  /* DSP2_RELEASE_HOURS - [15:8] */
4762 #define WM8958_DSP2_RELEASE_MINS_MASK           0x00FF  /* DSP2_RELEASE_MINS - [7:0] */
4763 #define WM8958_DSP2_RELEASE_MINS_SHIFT               0  /* DSP2_RELEASE_MINS - [7:0] */
4764 #define WM8958_DSP2_RELEASE_MINS_WIDTH               8  /* DSP2_RELEASE_MINS - [7:0] */
4765 
4766 /*
4767  * R2564 (0xA04) - DSP2_VerMajMin
4768  */
4769 #define WM8958_DSP2_MAJOR_VER_MASK              0xFF00  /* DSP2_MAJOR_VER - [15:8] */
4770 #define WM8958_DSP2_MAJOR_VER_SHIFT                  8  /* DSP2_MAJOR_VER - [15:8] */
4771 #define WM8958_DSP2_MAJOR_VER_WIDTH                  8  /* DSP2_MAJOR_VER - [15:8] */
4772 #define WM8958_DSP2_MINOR_VER_MASK              0x00FF  /* DSP2_MINOR_VER - [7:0] */
4773 #define WM8958_DSP2_MINOR_VER_SHIFT                  0  /* DSP2_MINOR_VER - [7:0] */
4774 #define WM8958_DSP2_MINOR_VER_WIDTH                  8  /* DSP2_MINOR_VER - [7:0] */
4775 
4776 /*
4777  * R2565 (0xA05) - DSP2_VerBuild
4778  */
4779 #define WM8958_DSP2_BUILD_VER_MASK              0xFFFF  /* DSP2_BUILD_VER - [15:0] */
4780 #define WM8958_DSP2_BUILD_VER_SHIFT                  0  /* DSP2_BUILD_VER - [15:0] */
4781 #define WM8958_DSP2_BUILD_VER_WIDTH                 16  /* DSP2_BUILD_VER - [15:0] */
4782 
4783 /*
4784  * R2573 (0xA0D) - DSP2_ExecControl
4785  */
4786 #define WM8958_DSP2_STOPC                       0x0020  /* DSP2_STOPC */
4787 #define WM8958_DSP2_STOPC_MASK                  0x0020  /* DSP2_STOPC */
4788 #define WM8958_DSP2_STOPC_SHIFT                      5  /* DSP2_STOPC */
4789 #define WM8958_DSP2_STOPC_WIDTH                      1  /* DSP2_STOPC */
4790 #define WM8958_DSP2_STOPS                       0x0010  /* DSP2_STOPS */
4791 #define WM8958_DSP2_STOPS_MASK                  0x0010  /* DSP2_STOPS */
4792 #define WM8958_DSP2_STOPS_SHIFT                      4  /* DSP2_STOPS */
4793 #define WM8958_DSP2_STOPS_WIDTH                      1  /* DSP2_STOPS */
4794 #define WM8958_DSP2_STOPI                       0x0008  /* DSP2_STOPI */
4795 #define WM8958_DSP2_STOPI_MASK                  0x0008  /* DSP2_STOPI */
4796 #define WM8958_DSP2_STOPI_SHIFT                      3  /* DSP2_STOPI */
4797 #define WM8958_DSP2_STOPI_WIDTH                      1  /* DSP2_STOPI */
4798 #define WM8958_DSP2_STOP                        0x0004  /* DSP2_STOP */
4799 #define WM8958_DSP2_STOP_MASK                   0x0004  /* DSP2_STOP */
4800 #define WM8958_DSP2_STOP_SHIFT                       2  /* DSP2_STOP */
4801 #define WM8958_DSP2_STOP_WIDTH                       1  /* DSP2_STOP */
4802 #define WM8958_DSP2_RUNR                        0x0002  /* DSP2_RUNR */
4803 #define WM8958_DSP2_RUNR_MASK                   0x0002  /* DSP2_RUNR */
4804 #define WM8958_DSP2_RUNR_SHIFT                       1  /* DSP2_RUNR */
4805 #define WM8958_DSP2_RUNR_WIDTH                       1  /* DSP2_RUNR */
4806 #define WM8958_DSP2_RUN                         0x0001  /* DSP2_RUN */
4807 #define WM8958_DSP2_RUN_MASK                    0x0001  /* DSP2_RUN */
4808 #define WM8958_DSP2_RUN_SHIFT                        0  /* DSP2_RUN */
4809 #define WM8958_DSP2_RUN_WIDTH                        1  /* DSP2_RUN */
4810 
4811 #endif
4812