1 #ifndef LINUX_BCMA_DRIVER_CC_H_ 2 #define LINUX_BCMA_DRIVER_CC_H_ 3 4 /** ChipCommon core registers. **/ 5 #define BCMA_CC_ID 0x0000 6 #define BCMA_CC_ID_ID 0x0000FFFF 7 #define BCMA_CC_ID_ID_SHIFT 0 8 #define BCMA_CC_ID_REV 0x000F0000 9 #define BCMA_CC_ID_REV_SHIFT 16 10 #define BCMA_CC_ID_PKG 0x00F00000 11 #define BCMA_CC_ID_PKG_SHIFT 20 12 #define BCMA_CC_ID_NRCORES 0x0F000000 13 #define BCMA_CC_ID_NRCORES_SHIFT 24 14 #define BCMA_CC_ID_TYPE 0xF0000000 15 #define BCMA_CC_ID_TYPE_SHIFT 28 16 #define BCMA_CC_CAP 0x0004 /* Capabilities */ 17 #define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */ 18 #define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */ 19 #define BCMA_CC_CAP_UARTCLK 0x00000018 /* UART clock select */ 20 #define BCMA_CC_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */ 21 #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */ 22 #define BCMA_CC_CAP_EXTBUS 0x000000C0 /* External buses present */ 23 #define BCMA_CC_CAP_FLASHT 0x00000700 /* Flash Type */ 24 #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */ 25 #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */ 26 #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */ 27 #define BCMA_CC_FLASHT_NFLASH 0x00000200 28 #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */ 29 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */ 30 #define BCMA_PLLTYPE_NONE 0x00000000 31 #define BCMA_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */ 32 #define BCMA_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */ 33 #define BCMA_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */ 34 #define BCMA_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */ 35 #define BCMA_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */ 36 #define BCMA_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */ 37 #define BCMA_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */ 38 #define BCMA_CC_CAP_PCTL 0x00040000 /* Power Control */ 39 #define BCMA_CC_CAP_OTPS 0x00380000 /* OTP size */ 40 #define BCMA_CC_CAP_OTPS_SHIFT 19 41 #define BCMA_CC_CAP_OTPS_BASE 5 42 #define BCMA_CC_CAP_JTAGM 0x00400000 /* JTAG master present */ 43 #define BCMA_CC_CAP_BROM 0x00800000 /* Internal boot ROM active */ 44 #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */ 45 #define BCMA_CC_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */ 46 #define BCMA_CC_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */ 47 #define BCMA_CC_CAP_SPROM 0x40000000 /* SPROM present */ 48 #define BCMA_CC_CORECTL 0x0008 49 #define BCMA_CC_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ 50 #define BCMA_CC_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ 51 #define BCMA_CC_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */ 52 #define BCMA_CC_BIST 0x000C 53 #define BCMA_CC_OTPS 0x0010 /* OTP status */ 54 #define BCMA_CC_OTPS_PROGFAIL 0x80000000 55 #define BCMA_CC_OTPS_PROTECT 0x00000007 56 #define BCMA_CC_OTPS_HW_PROTECT 0x00000001 57 #define BCMA_CC_OTPS_SW_PROTECT 0x00000002 58 #define BCMA_CC_OTPS_CID_PROTECT 0x00000004 59 #define BCMA_CC_OTPS_GU_PROG_IND 0x00000F00 /* General Use programmed indication */ 60 #define BCMA_CC_OTPS_GU_PROG_IND_SHIFT 8 61 #define BCMA_CC_OTPS_GU_PROG_HW 0x00000100 /* HW region programmed */ 62 #define BCMA_CC_OTPC 0x0014 /* OTP control */ 63 #define BCMA_CC_OTPC_RECWAIT 0xFF000000 64 #define BCMA_CC_OTPC_PROGWAIT 0x00FFFF00 65 #define BCMA_CC_OTPC_PRW_SHIFT 8 66 #define BCMA_CC_OTPC_MAXFAIL 0x00000038 67 #define BCMA_CC_OTPC_VSEL 0x00000006 68 #define BCMA_CC_OTPC_SELVL 0x00000001 69 #define BCMA_CC_OTPP 0x0018 /* OTP prog */ 70 #define BCMA_CC_OTPP_COL 0x000000FF 71 #define BCMA_CC_OTPP_ROW 0x0000FF00 72 #define BCMA_CC_OTPP_ROW_SHIFT 8 73 #define BCMA_CC_OTPP_READERR 0x10000000 74 #define BCMA_CC_OTPP_VALUE 0x20000000 75 #define BCMA_CC_OTPP_READ 0x40000000 76 #define BCMA_CC_OTPP_START 0x80000000 77 #define BCMA_CC_OTPP_BUSY 0x80000000 78 #define BCMA_CC_OTPL 0x001C /* OTP layout */ 79 #define BCMA_CC_OTPL_GURGN_OFFSET 0x00000FFF /* offset of general use region */ 80 #define BCMA_CC_IRQSTAT 0x0020 81 #define BCMA_CC_IRQMASK 0x0024 82 #define BCMA_CC_IRQ_GPIO 0x00000001 /* gpio intr */ 83 #define BCMA_CC_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */ 84 #define BCMA_CC_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */ 85 #define BCMA_CC_CHIPCTL 0x0028 /* Rev >= 11 only */ 86 #define BCMA_CC_CHIPSTAT 0x002C /* Rev >= 11 only */ 87 #define BCMA_CC_CHIPST_4313_SPROM_PRESENT 1 88 #define BCMA_CC_CHIPST_4313_OTP_PRESENT 2 89 #define BCMA_CC_CHIPST_4331_SPROM_PRESENT 2 90 #define BCMA_CC_CHIPST_4331_OTP_PRESENT 4 91 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */ 92 #define BCMA_CC_JCMD_START 0x80000000 93 #define BCMA_CC_JCMD_BUSY 0x80000000 94 #define BCMA_CC_JCMD_PAUSE 0x40000000 95 #define BCMA_CC_JCMD0_ACC_MASK 0x0000F000 96 #define BCMA_CC_JCMD0_ACC_IRDR 0x00000000 97 #define BCMA_CC_JCMD0_ACC_DR 0x00001000 98 #define BCMA_CC_JCMD0_ACC_IR 0x00002000 99 #define BCMA_CC_JCMD0_ACC_RESET 0x00003000 100 #define BCMA_CC_JCMD0_ACC_IRPDR 0x00004000 101 #define BCMA_CC_JCMD0_ACC_PDR 0x00005000 102 #define BCMA_CC_JCMD0_IRW_MASK 0x00000F00 103 #define BCMA_CC_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */ 104 #define BCMA_CC_JCMD_ACC_IRDR 0x00000000 105 #define BCMA_CC_JCMD_ACC_DR 0x00010000 106 #define BCMA_CC_JCMD_ACC_IR 0x00020000 107 #define BCMA_CC_JCMD_ACC_RESET 0x00030000 108 #define BCMA_CC_JCMD_ACC_IRPDR 0x00040000 109 #define BCMA_CC_JCMD_ACC_PDR 0x00050000 110 #define BCMA_CC_JCMD_IRW_MASK 0x00001F00 111 #define BCMA_CC_JCMD_IRW_SHIFT 8 112 #define BCMA_CC_JCMD_DRW_MASK 0x0000003F 113 #define BCMA_CC_JIR 0x0034 /* Rev >= 10 only */ 114 #define BCMA_CC_JDR 0x0038 /* Rev >= 10 only */ 115 #define BCMA_CC_JCTL 0x003C /* Rev >= 10 only */ 116 #define BCMA_CC_JCTL_FORCE_CLK 4 /* Force clock */ 117 #define BCMA_CC_JCTL_EXT_EN 2 /* Enable external targets */ 118 #define BCMA_CC_JCTL_EN 1 /* Enable Jtag master */ 119 #define BCMA_CC_FLASHCTL 0x0040 120 #define BCMA_CC_FLASHCTL_START 0x80000000 121 #define BCMA_CC_FLASHCTL_BUSY BCMA_CC_FLASHCTL_START 122 #define BCMA_CC_FLASHADDR 0x0044 123 #define BCMA_CC_FLASHDATA 0x0048 124 #define BCMA_CC_BCAST_ADDR 0x0050 125 #define BCMA_CC_BCAST_DATA 0x0054 126 #define BCMA_CC_GPIOPULLUP 0x0058 /* Rev >= 20 only */ 127 #define BCMA_CC_GPIOPULLDOWN 0x005C /* Rev >= 20 only */ 128 #define BCMA_CC_GPIOIN 0x0060 129 #define BCMA_CC_GPIOOUT 0x0064 130 #define BCMA_CC_GPIOOUTEN 0x0068 131 #define BCMA_CC_GPIOCTL 0x006C 132 #define BCMA_CC_GPIOPOL 0x0070 133 #define BCMA_CC_GPIOIRQ 0x0074 134 #define BCMA_CC_WATCHDOG 0x0080 135 #define BCMA_CC_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */ 136 #define BCMA_CC_GPIOTIMER_OFFTIME 0x0000FFFF 137 #define BCMA_CC_GPIOTIMER_OFFTIME_SHIFT 0 138 #define BCMA_CC_GPIOTIMER_ONTIME 0xFFFF0000 139 #define BCMA_CC_GPIOTIMER_ONTIME_SHIFT 16 140 #define BCMA_CC_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */ 141 #define BCMA_CC_CLOCK_N 0x0090 142 #define BCMA_CC_CLOCK_SB 0x0094 143 #define BCMA_CC_CLOCK_PCI 0x0098 144 #define BCMA_CC_CLOCK_M2 0x009C 145 #define BCMA_CC_CLOCK_MIPS 0x00A0 146 #define BCMA_CC_CLKDIV 0x00A4 /* Rev >= 3 only */ 147 #define BCMA_CC_CLKDIV_SFLASH 0x0F000000 148 #define BCMA_CC_CLKDIV_SFLASH_SHIFT 24 149 #define BCMA_CC_CLKDIV_OTP 0x000F0000 150 #define BCMA_CC_CLKDIV_OTP_SHIFT 16 151 #define BCMA_CC_CLKDIV_JTAG 0x00000F00 152 #define BCMA_CC_CLKDIV_JTAG_SHIFT 8 153 #define BCMA_CC_CLKDIV_UART 0x000000FF 154 #define BCMA_CC_CAP_EXT 0x00AC /* Capabilities */ 155 #define BCMA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */ 156 #define BCMA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */ 157 #define BCMA_CC_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */ 158 #define BCMA_CC_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */ 159 #define BCMA_CC_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */ 160 #define BCMA_CC_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */ 161 #define BCMA_CC_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */ 162 #define BCMA_CC_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ 163 #define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */ 164 #define BCMA_CC_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */ 165 #define BCMA_CC_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */ 166 #define BCMA_CC_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */ 167 #define BCMA_CC_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ 168 #define BCMA_CC_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ 169 #define BCMA_CC_SLOWCLKCTL_CLKDIV_SHIFT 16 170 #define BCMA_CC_SYSCLKCTL 0x00C0 /* Rev >= 3 only */ 171 #define BCMA_CC_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */ 172 #define BCMA_CC_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */ 173 #define BCMA_CC_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */ 174 #define BCMA_CC_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */ 175 #define BCMA_CC_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */ 176 #define BCMA_CC_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */ 177 #define BCMA_CC_SYSCLKCTL_CLKDIV_SHIFT 16 178 #define BCMA_CC_CLKSTSTR 0x00C4 /* Rev >= 3 only */ 179 #define BCMA_CC_EROM 0x00FC 180 #define BCMA_CC_PCMCIA_CFG 0x0100 181 #define BCMA_CC_PCMCIA_MEMWAIT 0x0104 182 #define BCMA_CC_PCMCIA_ATTRWAIT 0x0108 183 #define BCMA_CC_PCMCIA_IOWAIT 0x010C 184 #define BCMA_CC_IDE_CFG 0x0110 185 #define BCMA_CC_IDE_MEMWAIT 0x0114 186 #define BCMA_CC_IDE_ATTRWAIT 0x0118 187 #define BCMA_CC_IDE_IOWAIT 0x011C 188 #define BCMA_CC_PROG_CFG 0x0120 189 #define BCMA_CC_PROG_WAITCNT 0x0124 190 #define BCMA_CC_FLASH_CFG 0x0128 191 #define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ 192 #define BCMA_CC_FLASH_WAITCNT 0x012C 193 #define BCMA_CC_SROM_CONTROL 0x0190 194 #define BCMA_CC_SROM_CONTROL_START 0x80000000 195 #define BCMA_CC_SROM_CONTROL_BUSY 0x80000000 196 #define BCMA_CC_SROM_CONTROL_OPCODE 0x60000000 197 #define BCMA_CC_SROM_CONTROL_OP_READ 0x00000000 198 #define BCMA_CC_SROM_CONTROL_OP_WRITE 0x20000000 199 #define BCMA_CC_SROM_CONTROL_OP_WRDIS 0x40000000 200 #define BCMA_CC_SROM_CONTROL_OP_WREN 0x60000000 201 #define BCMA_CC_SROM_CONTROL_OTPSEL 0x00000010 202 #define BCMA_CC_SROM_CONTROL_LOCK 0x00000008 203 #define BCMA_CC_SROM_CONTROL_SIZE_MASK 0x00000006 204 #define BCMA_CC_SROM_CONTROL_SIZE_1K 0x00000000 205 #define BCMA_CC_SROM_CONTROL_SIZE_4K 0x00000002 206 #define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004 207 #define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1 208 #define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001 209 /* 0x1E0 is defined as shared BCMA_CLKCTLST */ 210 #define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ 211 #define BCMA_CC_UART0_DATA 0x0300 212 #define BCMA_CC_UART0_IMR 0x0304 213 #define BCMA_CC_UART0_FCR 0x0308 214 #define BCMA_CC_UART0_LCR 0x030C 215 #define BCMA_CC_UART0_MCR 0x0310 216 #define BCMA_CC_UART0_LSR 0x0314 217 #define BCMA_CC_UART0_MSR 0x0318 218 #define BCMA_CC_UART0_SCRATCH 0x031C 219 #define BCMA_CC_UART1_DATA 0x0400 220 #define BCMA_CC_UART1_IMR 0x0404 221 #define BCMA_CC_UART1_FCR 0x0408 222 #define BCMA_CC_UART1_LCR 0x040C 223 #define BCMA_CC_UART1_MCR 0x0410 224 #define BCMA_CC_UART1_LSR 0x0414 225 #define BCMA_CC_UART1_MSR 0x0418 226 #define BCMA_CC_UART1_SCRATCH 0x041C 227 /* PMU registers (rev >= 20) */ 228 #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */ 229 #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */ 230 #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16 231 #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400 232 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */ 233 #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */ 234 #define BCMA_CC_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */ 235 #define BCMA_CC_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */ 236 #define BCMA_CC_PMU_CTL_XTALFREQ_SHIFT 2 237 #define BCMA_CC_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */ 238 #define BCMA_CC_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */ 239 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */ 240 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */ 241 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */ 242 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */ 243 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */ 244 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */ 245 #define BCMA_CC_PMU_STAT_HAVEHT 0x00000004 /* HT available */ 246 #define BCMA_CC_PMU_STAT_RESINIT 0x00000003 /* Res init */ 247 #define BCMA_CC_PMU_RES_STAT 0x060C /* PMU res status */ 248 #define BCMA_CC_PMU_RES_PEND 0x0610 /* PMU res pending */ 249 #define BCMA_CC_PMU_TIMER 0x0614 /* PMU timer */ 250 #define BCMA_CC_PMU_MINRES_MSK 0x0618 /* PMU min res mask */ 251 #define BCMA_CC_PMU_MAXRES_MSK 0x061C /* PMU max res mask */ 252 #define BCMA_CC_PMU_RES_TABSEL 0x0620 /* PMU res table sel */ 253 #define BCMA_CC_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */ 254 #define BCMA_CC_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */ 255 #define BCMA_CC_PMU_RES_TIMER 0x062C /* PMU res timer */ 256 #define BCMA_CC_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */ 257 #define BCMA_CC_PMU_WATCHDOG 0x0634 /* PMU watchdog */ 258 #define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */ 259 #define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */ 260 #define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */ 261 #define BCMA_CC_CHIPCTL_ADDR 0x0650 262 #define BCMA_CC_CHIPCTL_DATA 0x0654 263 #define BCMA_CC_REGCTL_ADDR 0x0658 264 #define BCMA_CC_REGCTL_DATA 0x065C 265 #define BCMA_CC_PLLCTL_ADDR 0x0660 266 #define BCMA_CC_PLLCTL_DATA 0x0664 267 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */ 268 269 /* Divider allocation in 4716/47162/5356 */ 270 #define BCMA_CC_PMU5_MAINPLL_CPU 1 271 #define BCMA_CC_PMU5_MAINPLL_MEM 2 272 #define BCMA_CC_PMU5_MAINPLL_SSB 3 273 274 /* PLL usage in 4716/47162 */ 275 #define BCMA_CC_PMU4716_MAINPLL_PLL0 12 276 277 /* PLL usage in 5356/5357 */ 278 #define BCMA_CC_PMU5356_MAINPLL_PLL0 0 279 #define BCMA_CC_PMU5357_MAINPLL_PLL0 0 280 281 /* 4706 PMU */ 282 #define BCMA_CC_PMU4706_MAINPLL_PLL0 0 283 284 /* ALP clock on pre-PMU chips */ 285 #define BCMA_CC_PMU_ALP_CLOCK 20000000 286 /* HT clock for systems with PMU-enabled chipcommon */ 287 #define BCMA_CC_PMU_HT_CLOCK 80000000 288 289 /* PMU rev 5 (& 6) */ 290 #define BCMA_CC_PPL_P1P2_OFF 0 291 #define BCMA_CC_PPL_P1_MASK 0x0f000000 292 #define BCMA_CC_PPL_P1_SHIFT 24 293 #define BCMA_CC_PPL_P2_MASK 0x00f00000 294 #define BCMA_CC_PPL_P2_SHIFT 20 295 #define BCMA_CC_PPL_M14_OFF 1 296 #define BCMA_CC_PPL_MDIV_MASK 0x000000ff 297 #define BCMA_CC_PPL_MDIV_WIDTH 8 298 #define BCMA_CC_PPL_NM5_OFF 2 299 #define BCMA_CC_PPL_NDIV_MASK 0xfff00000 300 #define BCMA_CC_PPL_NDIV_SHIFT 20 301 #define BCMA_CC_PPL_FMAB_OFF 3 302 #define BCMA_CC_PPL_MRAT_MASK 0xf0000000 303 #define BCMA_CC_PPL_MRAT_SHIFT 28 304 #define BCMA_CC_PPL_ABRAT_MASK 0x08000000 305 #define BCMA_CC_PPL_ABRAT_SHIFT 27 306 #define BCMA_CC_PPL_FDIV_MASK 0x07ffffff 307 #define BCMA_CC_PPL_PLLCTL_OFF 4 308 #define BCMA_CC_PPL_PCHI_OFF 5 309 #define BCMA_CC_PPL_PCHI_MASK 0x0000003f 310 311 /* BCM4331 ChipControl numbers. */ 312 #define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */ 313 #define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */ 314 #define BCMA_CHIPCTL_4331_EXT_LNA BIT(2) /* 0 disable */ 315 #define BCMA_CHIPCTL_4331_SPROM_GPIO13_15 BIT(3) /* sprom/gpio13-15 mux */ 316 #define BCMA_CHIPCTL_4331_EXTPA_EN BIT(4) /* 0 ext pa disable, 1 ext pa enabled */ 317 #define BCMA_CHIPCTL_4331_GPIOCLK_ON_SPROMCS BIT(5) /* set drive out GPIO_CLK on sprom_cs pin */ 318 #define BCMA_CHIPCTL_4331_PCIE_MDIO_ON_SPROMCS BIT(6) /* use sprom_cs pin as PCIE mdio interface */ 319 #define BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5 BIT(7) /* aband extpa will be at gpio2/5 and sprom_dout */ 320 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXCLKEN BIT(8) /* override core control on pipe_AuxClkEnable */ 321 #define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */ 322 #define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */ 323 #define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */ 324 #define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */ 325 #define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */ 326 327 /* Data for the PMU, if available. 328 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU) 329 */ 330 struct bcma_chipcommon_pmu { 331 u8 rev; /* PMU revision */ 332 u32 crystalfreq; /* The active crystal frequency (in kHz) */ 333 }; 334 335 #ifdef CONFIG_BCMA_DRIVER_MIPS 336 struct bcma_pflash { 337 u8 buswidth; 338 u32 window; 339 u32 window_size; 340 }; 341 342 struct bcma_serial_port { 343 void *regs; 344 unsigned long clockspeed; 345 unsigned int irq; 346 unsigned int baud_base; 347 unsigned int reg_shift; 348 }; 349 #endif /* CONFIG_BCMA_DRIVER_MIPS */ 350 351 struct bcma_drv_cc { 352 struct bcma_device *core; 353 u32 status; 354 u32 capabilities; 355 u32 capabilities_ext; 356 u8 setup_done:1; 357 /* Fast Powerup Delay constant */ 358 u16 fast_pwrup_delay; 359 struct bcma_chipcommon_pmu pmu; 360 #ifdef CONFIG_BCMA_DRIVER_MIPS 361 struct bcma_pflash pflash; 362 363 int nr_serial_ports; 364 struct bcma_serial_port serial_ports[4]; 365 #endif /* CONFIG_BCMA_DRIVER_MIPS */ 366 }; 367 368 /* Register access */ 369 #define bcma_cc_read32(cc, offset) \ 370 bcma_read32((cc)->core, offset) 371 #define bcma_cc_write32(cc, offset, val) \ 372 bcma_write32((cc)->core, offset, val) 373 374 #define bcma_cc_mask32(cc, offset, mask) \ 375 bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) & (mask)) 376 #define bcma_cc_set32(cc, offset, set) \ 377 bcma_cc_write32(cc, offset, bcma_cc_read32(cc, offset) | (set)) 378 #define bcma_cc_maskset32(cc, offset, mask, set) \ 379 bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set)) 380 381 extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc); 382 383 extern void bcma_chipco_suspend(struct bcma_drv_cc *cc); 384 extern void bcma_chipco_resume(struct bcma_drv_cc *cc); 385 386 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable); 387 388 extern void bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, 389 u32 ticks); 390 391 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value); 392 393 u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask); 394 395 /* Chipcommon GPIO pin access. */ 396 u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask); 397 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value); 398 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value); 399 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value); 400 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value); 401 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value); 402 403 /* PMU support */ 404 extern void bcma_pmu_init(struct bcma_drv_cc *cc); 405 406 extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, 407 u32 value); 408 extern void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, 409 u32 mask, u32 set); 410 extern void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc, 411 u32 offset, u32 mask, u32 set); 412 extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, 413 u32 offset, u32 mask, u32 set); 414 415 #endif /* LINUX_BCMA_DRIVER_CC_H_ */ 416