1 /*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 /*
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
29 *
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
41 *
42 * Cycle bit rules:
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
47 *
48 * Producer rules:
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
52 * cycle state).
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
56 *
57 * Consumer rules:
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
65 */
66
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
69 #include "xhci.h"
70
71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
72 struct xhci_virt_device *virt_dev,
73 struct xhci_event_cmd *event);
74
75 /*
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
77 * address of the TRB.
78 */
xhci_trb_virt_to_dma(struct xhci_segment * seg,union xhci_trb * trb)79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
80 union xhci_trb *trb)
81 {
82 unsigned long segment_offset;
83
84 if (!seg || !trb || trb < seg->trbs)
85 return 0;
86 /* offset in TRBs */
87 segment_offset = trb - seg->trbs;
88 if (segment_offset > TRBS_PER_SEGMENT)
89 return 0;
90 return seg->dma + (segment_offset * sizeof(*trb));
91 }
92
93 /* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
95 */
last_trb_on_last_seg(struct xhci_hcd * xhci,struct xhci_ring * ring,struct xhci_segment * seg,union xhci_trb * trb)96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
97 struct xhci_segment *seg, union xhci_trb *trb)
98 {
99 if (ring == xhci->event_ring)
100 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
101 (seg->next == xhci->event_ring->first_seg);
102 else
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
104 }
105
106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
108 * event seg?
109 */
last_trb(struct xhci_hcd * xhci,struct xhci_ring * ring,struct xhci_segment * seg,union xhci_trb * trb)110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
111 struct xhci_segment *seg, union xhci_trb *trb)
112 {
113 if (ring == xhci->event_ring)
114 return trb == &seg->trbs[TRBS_PER_SEGMENT];
115 else
116 return TRB_TYPE_LINK_LE32(trb->link.control);
117 }
118
enqueue_is_link_trb(struct xhci_ring * ring)119 static int enqueue_is_link_trb(struct xhci_ring *ring)
120 {
121 struct xhci_link_trb *link = &ring->enqueue->link;
122 return TRB_TYPE_LINK_LE32(link->control);
123 }
124
xhci_find_next_enqueue(struct xhci_ring * ring)125 union xhci_trb *xhci_find_next_enqueue(struct xhci_ring *ring)
126 {
127 /* Enqueue pointer can be left pointing to the link TRB,
128 * we must handle that
129 */
130 if (TRB_TYPE_LINK_LE32(ring->enqueue->link.control))
131 return ring->enq_seg->next->trbs;
132 return ring->enqueue;
133 }
134
135 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
136 * TRB is in a new segment. This does not skip over link TRBs, and it does not
137 * effect the ring dequeue or enqueue pointers.
138 */
next_trb(struct xhci_hcd * xhci,struct xhci_ring * ring,struct xhci_segment ** seg,union xhci_trb ** trb)139 static void next_trb(struct xhci_hcd *xhci,
140 struct xhci_ring *ring,
141 struct xhci_segment **seg,
142 union xhci_trb **trb)
143 {
144 if (last_trb(xhci, ring, *seg, *trb)) {
145 *seg = (*seg)->next;
146 *trb = ((*seg)->trbs);
147 } else {
148 (*trb)++;
149 }
150 }
151
152 /*
153 * See Cycle bit rules. SW is the consumer for the event ring only.
154 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
155 */
inc_deq(struct xhci_hcd * xhci,struct xhci_ring * ring)156 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
157 {
158 unsigned long long addr;
159
160 ring->deq_updates++;
161
162 /*
163 * If this is not event ring, and the dequeue pointer
164 * is not on a link TRB, there is one more usable TRB
165 */
166 if (ring->type != TYPE_EVENT &&
167 !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
168 ring->num_trbs_free++;
169
170 do {
171 /*
172 * Update the dequeue pointer further if that was a link TRB or
173 * we're at the end of an event ring segment (which doesn't have
174 * link TRBS)
175 */
176 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
177 if (ring->type == TYPE_EVENT &&
178 last_trb_on_last_seg(xhci, ring,
179 ring->deq_seg, ring->dequeue)) {
180 ring->cycle_state = (ring->cycle_state ? 0 : 1);
181 }
182 ring->deq_seg = ring->deq_seg->next;
183 ring->dequeue = ring->deq_seg->trbs;
184 } else {
185 ring->dequeue++;
186 }
187 } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
188
189 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
190 }
191
192 /*
193 * See Cycle bit rules. SW is the consumer for the event ring only.
194 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
195 *
196 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
197 * chain bit is set), then set the chain bit in all the following link TRBs.
198 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
199 * have their chain bit cleared (so that each Link TRB is a separate TD).
200 *
201 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
202 * set, but other sections talk about dealing with the chain bit set. This was
203 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
204 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
205 *
206 * @more_trbs_coming: Will you enqueue more TRBs before calling
207 * prepare_transfer()?
208 */
inc_enq(struct xhci_hcd * xhci,struct xhci_ring * ring,bool more_trbs_coming)209 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
210 bool more_trbs_coming)
211 {
212 u32 chain;
213 union xhci_trb *next;
214 unsigned long long addr;
215
216 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
217 /* If this is not event ring, there is one less usable TRB */
218 if (ring->type != TYPE_EVENT &&
219 !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
220 ring->num_trbs_free--;
221 next = ++(ring->enqueue);
222
223 ring->enq_updates++;
224 /* Update the dequeue pointer further if that was a link TRB or we're at
225 * the end of an event ring segment (which doesn't have link TRBS)
226 */
227 while (last_trb(xhci, ring, ring->enq_seg, next)) {
228 if (ring->type != TYPE_EVENT) {
229 /*
230 * If the caller doesn't plan on enqueueing more
231 * TDs before ringing the doorbell, then we
232 * don't want to give the link TRB to the
233 * hardware just yet. We'll give the link TRB
234 * back in prepare_ring() just before we enqueue
235 * the TD at the top of the ring.
236 */
237 if (!chain && !more_trbs_coming)
238 break;
239
240 /* If we're not dealing with 0.95 hardware or
241 * isoc rings on AMD 0.96 host,
242 * carry over the chain bit of the previous TRB
243 * (which may mean the chain bit is cleared).
244 */
245 if (!(ring->type == TYPE_ISOC &&
246 (xhci->quirks & XHCI_AMD_0x96_HOST))
247 && !xhci_link_trb_quirk(xhci)) {
248 next->link.control &=
249 cpu_to_le32(~TRB_CHAIN);
250 next->link.control |=
251 cpu_to_le32(chain);
252 }
253 /* Give this link TRB to the hardware */
254 wmb();
255 next->link.control ^= cpu_to_le32(TRB_CYCLE);
256
257 /* Toggle the cycle bit after the last ring segment. */
258 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
259 ring->cycle_state = (ring->cycle_state ? 0 : 1);
260 }
261 }
262 ring->enq_seg = ring->enq_seg->next;
263 ring->enqueue = ring->enq_seg->trbs;
264 next = ring->enqueue;
265 }
266 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
267 }
268
269 /*
270 * Check to see if there's room to enqueue num_trbs on the ring and make sure
271 * enqueue pointer will not advance into dequeue segment. See rules above.
272 */
room_on_ring(struct xhci_hcd * xhci,struct xhci_ring * ring,unsigned int num_trbs)273 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
274 unsigned int num_trbs)
275 {
276 int num_trbs_in_deq_seg;
277
278 if (ring->num_trbs_free < num_trbs)
279 return 0;
280
281 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
282 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
283 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
284 return 0;
285 }
286
287 return 1;
288 }
289
290 /* Ring the host controller doorbell after placing a command on the ring */
xhci_ring_cmd_db(struct xhci_hcd * xhci)291 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
292 {
293 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
294 return;
295
296 xhci_dbg(xhci, "// Ding dong!\n");
297 xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
298 /* Flush PCI posted writes */
299 xhci_readl(xhci, &xhci->dba->doorbell[0]);
300 }
301
xhci_abort_cmd_ring(struct xhci_hcd * xhci)302 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
303 {
304 u64 temp_64;
305 int ret;
306
307 xhci_dbg(xhci, "Abort command ring\n");
308
309 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
310 xhci_dbg(xhci, "The command ring isn't running, "
311 "Have the command ring been stopped?\n");
312 return 0;
313 }
314
315 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
316 if (!(temp_64 & CMD_RING_RUNNING)) {
317 xhci_dbg(xhci, "Command ring had been stopped\n");
318 return 0;
319 }
320 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
321 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
322 &xhci->op_regs->cmd_ring);
323
324 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
325 * time the completion od all xHCI commands, including
326 * the Command Abort operation. If software doesn't see
327 * CRR negated in a timely manner (e.g. longer than 5
328 * seconds), then it should assume that the there are
329 * larger problems with the xHC and assert HCRST.
330 */
331 ret = handshake(xhci, &xhci->op_regs->cmd_ring,
332 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
333 if (ret < 0) {
334 xhci_err(xhci, "Stopped the command ring failed, "
335 "maybe the host is dead\n");
336 xhci->xhc_state |= XHCI_STATE_DYING;
337 xhci_quiesce(xhci);
338 xhci_halt(xhci);
339 return -ESHUTDOWN;
340 }
341
342 return 0;
343 }
344
xhci_queue_cd(struct xhci_hcd * xhci,struct xhci_command * command,union xhci_trb * cmd_trb)345 static int xhci_queue_cd(struct xhci_hcd *xhci,
346 struct xhci_command *command,
347 union xhci_trb *cmd_trb)
348 {
349 struct xhci_cd *cd;
350 cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
351 if (!cd)
352 return -ENOMEM;
353 INIT_LIST_HEAD(&cd->cancel_cmd_list);
354
355 cd->command = command;
356 cd->cmd_trb = cmd_trb;
357 list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
358
359 return 0;
360 }
361
362 /*
363 * Cancel the command which has issue.
364 *
365 * Some commands may hang due to waiting for acknowledgement from
366 * usb device. It is outside of the xHC's ability to control and
367 * will cause the command ring is blocked. When it occurs software
368 * should intervene to recover the command ring.
369 * See Section 4.6.1.1 and 4.6.1.2
370 */
xhci_cancel_cmd(struct xhci_hcd * xhci,struct xhci_command * command,union xhci_trb * cmd_trb)371 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
372 union xhci_trb *cmd_trb)
373 {
374 int retval = 0;
375 unsigned long flags;
376
377 spin_lock_irqsave(&xhci->lock, flags);
378
379 if (xhci->xhc_state & XHCI_STATE_DYING) {
380 xhci_warn(xhci, "Abort the command ring,"
381 " but the xHCI is dead.\n");
382 retval = -ESHUTDOWN;
383 goto fail;
384 }
385
386 /* queue the cmd desriptor to cancel_cmd_list */
387 retval = xhci_queue_cd(xhci, command, cmd_trb);
388 if (retval) {
389 xhci_warn(xhci, "Queuing command descriptor failed.\n");
390 goto fail;
391 }
392
393 /* abort command ring */
394 retval = xhci_abort_cmd_ring(xhci);
395 if (retval) {
396 xhci_err(xhci, "Abort command ring failed\n");
397 if (unlikely(retval == -ESHUTDOWN)) {
398 spin_unlock_irqrestore(&xhci->lock, flags);
399 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
400 xhci_dbg(xhci, "xHCI host controller is dead.\n");
401 return retval;
402 }
403 }
404
405 fail:
406 spin_unlock_irqrestore(&xhci->lock, flags);
407 return retval;
408 }
409
xhci_ring_ep_doorbell(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index,unsigned int stream_id)410 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
411 unsigned int slot_id,
412 unsigned int ep_index,
413 unsigned int stream_id)
414 {
415 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
416 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
417 unsigned int ep_state = ep->ep_state;
418
419 /* Don't ring the doorbell for this endpoint if there are pending
420 * cancellations because we don't want to interrupt processing.
421 * We don't want to restart any stream rings if there's a set dequeue
422 * pointer command pending because the device can choose to start any
423 * stream once the endpoint is on the HW schedule.
424 * FIXME - check all the stream rings for pending cancellations.
425 */
426 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
427 (ep_state & EP_HALTED))
428 return;
429 xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
430 /* The CPU has better things to do at this point than wait for a
431 * write-posting flush. It'll get there soon enough.
432 */
433 }
434
435 /* Ring the doorbell for any rings with pending URBs */
ring_doorbell_for_active_rings(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index)436 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
437 unsigned int slot_id,
438 unsigned int ep_index)
439 {
440 unsigned int stream_id;
441 struct xhci_virt_ep *ep;
442
443 ep = &xhci->devs[slot_id]->eps[ep_index];
444
445 /* A ring has pending URBs if its TD list is not empty */
446 if (!(ep->ep_state & EP_HAS_STREAMS)) {
447 if (ep->ring && !(list_empty(&ep->ring->td_list)))
448 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
449 return;
450 }
451
452 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
453 stream_id++) {
454 struct xhci_stream_info *stream_info = ep->stream_info;
455 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
456 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
457 stream_id);
458 }
459 }
460
461 /*
462 * Find the segment that trb is in. Start searching in start_seg.
463 * If we must move past a segment that has a link TRB with a toggle cycle state
464 * bit set, then we will toggle the value pointed at by cycle_state.
465 */
find_trb_seg(struct xhci_segment * start_seg,union xhci_trb * trb,int * cycle_state)466 static struct xhci_segment *find_trb_seg(
467 struct xhci_segment *start_seg,
468 union xhci_trb *trb, int *cycle_state)
469 {
470 struct xhci_segment *cur_seg = start_seg;
471 struct xhci_generic_trb *generic_trb;
472
473 while (cur_seg->trbs > trb ||
474 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
475 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
476 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
477 *cycle_state ^= 0x1;
478 cur_seg = cur_seg->next;
479 if (cur_seg == start_seg)
480 /* Looped over the entire list. Oops! */
481 return NULL;
482 }
483 return cur_seg;
484 }
485
486
xhci_triad_to_transfer_ring(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index,unsigned int stream_id)487 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
488 unsigned int slot_id, unsigned int ep_index,
489 unsigned int stream_id)
490 {
491 struct xhci_virt_ep *ep;
492
493 ep = &xhci->devs[slot_id]->eps[ep_index];
494 /* Common case: no streams */
495 if (!(ep->ep_state & EP_HAS_STREAMS))
496 return ep->ring;
497
498 if (stream_id == 0) {
499 xhci_warn(xhci,
500 "WARN: Slot ID %u, ep index %u has streams, "
501 "but URB has no stream ID.\n",
502 slot_id, ep_index);
503 return NULL;
504 }
505
506 if (stream_id < ep->stream_info->num_streams)
507 return ep->stream_info->stream_rings[stream_id];
508
509 xhci_warn(xhci,
510 "WARN: Slot ID %u, ep index %u has "
511 "stream IDs 1 to %u allocated, "
512 "but stream ID %u is requested.\n",
513 slot_id, ep_index,
514 ep->stream_info->num_streams - 1,
515 stream_id);
516 return NULL;
517 }
518
519 /* Get the right ring for the given URB.
520 * If the endpoint supports streams, boundary check the URB's stream ID.
521 * If the endpoint doesn't support streams, return the singular endpoint ring.
522 */
xhci_urb_to_transfer_ring(struct xhci_hcd * xhci,struct urb * urb)523 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
524 struct urb *urb)
525 {
526 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
527 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
528 }
529
530 /*
531 * Move the xHC's endpoint ring dequeue pointer past cur_td.
532 * Record the new state of the xHC's endpoint ring dequeue segment,
533 * dequeue pointer, and new consumer cycle state in state.
534 * Update our internal representation of the ring's dequeue pointer.
535 *
536 * We do this in three jumps:
537 * - First we update our new ring state to be the same as when the xHC stopped.
538 * - Then we traverse the ring to find the segment that contains
539 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
540 * any link TRBs with the toggle cycle bit set.
541 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
542 * if we've moved it past a link TRB with the toggle cycle bit set.
543 *
544 * Some of the uses of xhci_generic_trb are grotty, but if they're done
545 * with correct __le32 accesses they should work fine. Only users of this are
546 * in here.
547 */
xhci_find_new_dequeue_state(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index,unsigned int stream_id,struct xhci_td * cur_td,struct xhci_dequeue_state * state)548 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
549 unsigned int slot_id, unsigned int ep_index,
550 unsigned int stream_id, struct xhci_td *cur_td,
551 struct xhci_dequeue_state *state)
552 {
553 struct xhci_virt_device *dev = xhci->devs[slot_id];
554 struct xhci_ring *ep_ring;
555 struct xhci_generic_trb *trb;
556 struct xhci_ep_ctx *ep_ctx;
557 dma_addr_t addr;
558
559 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
560 ep_index, stream_id);
561 if (!ep_ring) {
562 xhci_warn(xhci, "WARN can't find new dequeue state "
563 "for invalid stream ID %u.\n",
564 stream_id);
565 return;
566 }
567 state->new_cycle_state = 0;
568 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
569 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
570 dev->eps[ep_index].stopped_trb,
571 &state->new_cycle_state);
572 if (!state->new_deq_seg) {
573 WARN_ON(1);
574 return;
575 }
576
577 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
578 xhci_dbg(xhci, "Finding endpoint context\n");
579 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
580 state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
581
582 state->new_deq_ptr = cur_td->last_trb;
583 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
584 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
585 state->new_deq_ptr,
586 &state->new_cycle_state);
587 if (!state->new_deq_seg) {
588 WARN_ON(1);
589 return;
590 }
591
592 trb = &state->new_deq_ptr->generic;
593 if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
594 (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
595 state->new_cycle_state ^= 0x1;
596 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
597
598 /*
599 * If there is only one segment in a ring, find_trb_seg()'s while loop
600 * will not run, and it will return before it has a chance to see if it
601 * needs to toggle the cycle bit. It can't tell if the stalled transfer
602 * ended just before the link TRB on a one-segment ring, or if the TD
603 * wrapped around the top of the ring, because it doesn't have the TD in
604 * question. Look for the one-segment case where stalled TRB's address
605 * is greater than the new dequeue pointer address.
606 */
607 if (ep_ring->first_seg == ep_ring->first_seg->next &&
608 state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
609 state->new_cycle_state ^= 0x1;
610 xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
611
612 /* Don't update the ring cycle state for the producer (us). */
613 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
614 state->new_deq_seg);
615 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
616 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
617 (unsigned long long) addr);
618 }
619
620 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
621 * (The last TRB actually points to the ring enqueue pointer, which is not part
622 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
623 */
td_to_noop(struct xhci_hcd * xhci,struct xhci_ring * ep_ring,struct xhci_td * cur_td,bool flip_cycle)624 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
625 struct xhci_td *cur_td, bool flip_cycle)
626 {
627 struct xhci_segment *cur_seg;
628 union xhci_trb *cur_trb;
629
630 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
631 true;
632 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
633 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
634 /* Unchain any chained Link TRBs, but
635 * leave the pointers intact.
636 */
637 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
638 /* Flip the cycle bit (link TRBs can't be the first
639 * or last TRB).
640 */
641 if (flip_cycle)
642 cur_trb->generic.field[3] ^=
643 cpu_to_le32(TRB_CYCLE);
644 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
645 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
646 "in seg %p (0x%llx dma)\n",
647 cur_trb,
648 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
649 cur_seg,
650 (unsigned long long)cur_seg->dma);
651 } else {
652 cur_trb->generic.field[0] = 0;
653 cur_trb->generic.field[1] = 0;
654 cur_trb->generic.field[2] = 0;
655 /* Preserve only the cycle bit of this TRB */
656 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
657 /* Flip the cycle bit except on the first or last TRB */
658 if (flip_cycle && cur_trb != cur_td->first_trb &&
659 cur_trb != cur_td->last_trb)
660 cur_trb->generic.field[3] ^=
661 cpu_to_le32(TRB_CYCLE);
662 cur_trb->generic.field[3] |= cpu_to_le32(
663 TRB_TYPE(TRB_TR_NOOP));
664 xhci_dbg(xhci, "TRB to noop at offset 0x%llx\n",
665 (unsigned long long)
666 xhci_trb_virt_to_dma(cur_seg, cur_trb));
667 }
668 if (cur_trb == cur_td->last_trb)
669 break;
670 }
671 }
672
673 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
674 unsigned int ep_index, unsigned int stream_id,
675 struct xhci_segment *deq_seg,
676 union xhci_trb *deq_ptr, u32 cycle_state);
677
xhci_queue_new_dequeue_state(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index,unsigned int stream_id,struct xhci_dequeue_state * deq_state)678 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
679 unsigned int slot_id, unsigned int ep_index,
680 unsigned int stream_id,
681 struct xhci_dequeue_state *deq_state)
682 {
683 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
684
685 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
686 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
687 deq_state->new_deq_seg,
688 (unsigned long long)deq_state->new_deq_seg->dma,
689 deq_state->new_deq_ptr,
690 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
691 deq_state->new_cycle_state);
692 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
693 deq_state->new_deq_seg,
694 deq_state->new_deq_ptr,
695 (u32) deq_state->new_cycle_state);
696 /* Stop the TD queueing code from ringing the doorbell until
697 * this command completes. The HC won't set the dequeue pointer
698 * if the ring is running, and ringing the doorbell starts the
699 * ring running.
700 */
701 ep->ep_state |= SET_DEQ_PENDING;
702 }
703
xhci_stop_watchdog_timer_in_irq(struct xhci_hcd * xhci,struct xhci_virt_ep * ep)704 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
705 struct xhci_virt_ep *ep)
706 {
707 ep->ep_state &= ~EP_HALT_PENDING;
708 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
709 * timer is running on another CPU, we don't decrement stop_cmds_pending
710 * (since we didn't successfully stop the watchdog timer).
711 */
712 if (del_timer(&ep->stop_cmd_timer))
713 ep->stop_cmds_pending--;
714 }
715
716 /* Must be called with xhci->lock held in interrupt context */
xhci_giveback_urb_in_irq(struct xhci_hcd * xhci,struct xhci_td * cur_td,int status,char * adjective)717 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
718 struct xhci_td *cur_td, int status, char *adjective)
719 {
720 struct usb_hcd *hcd;
721 struct urb *urb;
722 struct urb_priv *urb_priv;
723
724 urb = cur_td->urb;
725 urb_priv = urb->hcpriv;
726 urb_priv->td_cnt++;
727 hcd = bus_to_hcd(urb->dev->bus);
728
729 /* Only giveback urb when this is the last td in urb */
730 if (urb_priv->td_cnt == urb_priv->length) {
731 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
732 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
733 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
734 if (xhci->quirks & XHCI_AMD_PLL_FIX)
735 usb_amd_quirk_pll_enable();
736 }
737 }
738 usb_hcd_unlink_urb_from_ep(hcd, urb);
739
740 spin_unlock(&xhci->lock);
741 usb_hcd_giveback_urb(hcd, urb, status);
742 xhci_urb_free_priv(xhci, urb_priv);
743 spin_lock(&xhci->lock);
744 }
745 }
746
747 /*
748 * When we get a command completion for a Stop Endpoint Command, we need to
749 * unlink any cancelled TDs from the ring. There are two ways to do that:
750 *
751 * 1. If the HW was in the middle of processing the TD that needs to be
752 * cancelled, then we must move the ring's dequeue pointer past the last TRB
753 * in the TD with a Set Dequeue Pointer Command.
754 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
755 * bit cleared) so that the HW will skip over them.
756 */
handle_stopped_endpoint(struct xhci_hcd * xhci,union xhci_trb * trb,struct xhci_event_cmd * event)757 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
758 union xhci_trb *trb, struct xhci_event_cmd *event)
759 {
760 unsigned int slot_id;
761 unsigned int ep_index;
762 struct xhci_virt_device *virt_dev;
763 struct xhci_ring *ep_ring;
764 struct xhci_virt_ep *ep;
765 struct list_head *entry;
766 struct xhci_td *cur_td = NULL;
767 struct xhci_td *last_unlinked_td;
768
769 struct xhci_dequeue_state deq_state;
770
771 if (unlikely(TRB_TO_SUSPEND_PORT(
772 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
773 slot_id = TRB_TO_SLOT_ID(
774 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
775 virt_dev = xhci->devs[slot_id];
776 if (virt_dev)
777 handle_cmd_in_cmd_wait_list(xhci, virt_dev,
778 event);
779 else
780 xhci_warn(xhci, "Stop endpoint command "
781 "completion for disabled slot %u\n",
782 slot_id);
783 return;
784 }
785
786 memset(&deq_state, 0, sizeof(deq_state));
787 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
788 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
789 ep = &xhci->devs[slot_id]->eps[ep_index];
790
791 if (list_empty(&ep->cancelled_td_list)) {
792 xhci_stop_watchdog_timer_in_irq(xhci, ep);
793 ep->stopped_td = NULL;
794 ep->stopped_trb = NULL;
795 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
796 return;
797 }
798
799 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
800 * We have the xHCI lock, so nothing can modify this list until we drop
801 * it. We're also in the event handler, so we can't get re-interrupted
802 * if another Stop Endpoint command completes
803 */
804 list_for_each(entry, &ep->cancelled_td_list) {
805 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
806 xhci_dbg(xhci, "Removing canceled TD starting at 0x%llx (dma).\n",
807 (unsigned long long)xhci_trb_virt_to_dma(
808 cur_td->start_seg, cur_td->first_trb));
809 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
810 if (!ep_ring) {
811 /* This shouldn't happen unless a driver is mucking
812 * with the stream ID after submission. This will
813 * leave the TD on the hardware ring, and the hardware
814 * will try to execute it, and may access a buffer
815 * that has already been freed. In the best case, the
816 * hardware will execute it, and the event handler will
817 * ignore the completion event for that TD, since it was
818 * removed from the td_list for that endpoint. In
819 * short, don't muck with the stream ID after
820 * submission.
821 */
822 xhci_warn(xhci, "WARN Cancelled URB %p "
823 "has invalid stream ID %u.\n",
824 cur_td->urb,
825 cur_td->urb->stream_id);
826 goto remove_finished_td;
827 }
828 /*
829 * If we stopped on the TD we need to cancel, then we have to
830 * move the xHC endpoint ring dequeue pointer past this TD.
831 */
832 if (cur_td == ep->stopped_td)
833 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
834 cur_td->urb->stream_id,
835 cur_td, &deq_state);
836 else
837 td_to_noop(xhci, ep_ring, cur_td, false);
838 remove_finished_td:
839 /*
840 * The event handler won't see a completion for this TD anymore,
841 * so remove it from the endpoint ring's TD list. Keep it in
842 * the cancelled TD list for URB completion later.
843 */
844 list_del_init(&cur_td->td_list);
845 }
846 last_unlinked_td = cur_td;
847 xhci_stop_watchdog_timer_in_irq(xhci, ep);
848
849 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
850 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
851 xhci_queue_new_dequeue_state(xhci,
852 slot_id, ep_index,
853 ep->stopped_td->urb->stream_id,
854 &deq_state);
855 xhci_ring_cmd_db(xhci);
856 } else {
857 /* Otherwise ring the doorbell(s) to restart queued transfers */
858 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
859 }
860
861 /* Clear stopped_td and stopped_trb if endpoint is not halted */
862 if (!(ep->ep_state & EP_HALTED)) {
863 ep->stopped_td = NULL;
864 ep->stopped_trb = NULL;
865 }
866
867 /*
868 * Drop the lock and complete the URBs in the cancelled TD list.
869 * New TDs to be cancelled might be added to the end of the list before
870 * we can complete all the URBs for the TDs we already unlinked.
871 * So stop when we've completed the URB for the last TD we unlinked.
872 */
873 do {
874 cur_td = list_entry(ep->cancelled_td_list.next,
875 struct xhci_td, cancelled_td_list);
876 list_del_init(&cur_td->cancelled_td_list);
877
878 /* Clean up the cancelled URB */
879 /* Doesn't matter what we pass for status, since the core will
880 * just overwrite it (because the URB has been unlinked).
881 */
882 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
883
884 /* Stop processing the cancelled list if the watchdog timer is
885 * running.
886 */
887 if (xhci->xhc_state & XHCI_STATE_DYING)
888 return;
889 } while (cur_td != last_unlinked_td);
890
891 /* Return to the event handler with xhci->lock re-acquired */
892 }
893
894 /* Watchdog timer function for when a stop endpoint command fails to complete.
895 * In this case, we assume the host controller is broken or dying or dead. The
896 * host may still be completing some other events, so we have to be careful to
897 * let the event ring handler and the URB dequeueing/enqueueing functions know
898 * through xhci->state.
899 *
900 * The timer may also fire if the host takes a very long time to respond to the
901 * command, and the stop endpoint command completion handler cannot delete the
902 * timer before the timer function is called. Another endpoint cancellation may
903 * sneak in before the timer function can grab the lock, and that may queue
904 * another stop endpoint command and add the timer back. So we cannot use a
905 * simple flag to say whether there is a pending stop endpoint command for a
906 * particular endpoint.
907 *
908 * Instead we use a combination of that flag and a counter for the number of
909 * pending stop endpoint commands. If the timer is the tail end of the last
910 * stop endpoint command, and the endpoint's command is still pending, we assume
911 * the host is dying.
912 */
xhci_stop_endpoint_command_watchdog(unsigned long arg)913 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
914 {
915 struct xhci_hcd *xhci;
916 struct xhci_virt_ep *ep;
917 struct xhci_virt_ep *temp_ep;
918 struct xhci_ring *ring;
919 struct xhci_td *cur_td;
920 int ret, i, j;
921 unsigned long flags;
922
923 ep = (struct xhci_virt_ep *) arg;
924 xhci = ep->xhci;
925
926 spin_lock_irqsave(&xhci->lock, flags);
927
928 ep->stop_cmds_pending--;
929 if (xhci->xhc_state & XHCI_STATE_DYING) {
930 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
931 "xHCI as DYING, exiting.\n");
932 spin_unlock_irqrestore(&xhci->lock, flags);
933 return;
934 }
935 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
936 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
937 "exiting.\n");
938 spin_unlock_irqrestore(&xhci->lock, flags);
939 return;
940 }
941
942 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
943 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
944 /* Oops, HC is dead or dying or at least not responding to the stop
945 * endpoint command.
946 */
947 xhci->xhc_state |= XHCI_STATE_DYING;
948 /* Disable interrupts from the host controller and start halting it */
949 xhci_quiesce(xhci);
950 spin_unlock_irqrestore(&xhci->lock, flags);
951
952 ret = xhci_halt(xhci);
953
954 spin_lock_irqsave(&xhci->lock, flags);
955 if (ret < 0) {
956 /* This is bad; the host is not responding to commands and it's
957 * not allowing itself to be halted. At least interrupts are
958 * disabled. If we call usb_hc_died(), it will attempt to
959 * disconnect all device drivers under this host. Those
960 * disconnect() methods will wait for all URBs to be unlinked,
961 * so we must complete them.
962 */
963 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
964 xhci_warn(xhci, "Completing active URBs anyway.\n");
965 /* We could turn all TDs on the rings to no-ops. This won't
966 * help if the host has cached part of the ring, and is slow if
967 * we want to preserve the cycle bit. Skip it and hope the host
968 * doesn't touch the memory.
969 */
970 }
971 for (i = 0; i < MAX_HC_SLOTS; i++) {
972 if (!xhci->devs[i])
973 continue;
974 for (j = 0; j < 31; j++) {
975 temp_ep = &xhci->devs[i]->eps[j];
976 ring = temp_ep->ring;
977 if (!ring)
978 continue;
979 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
980 "ep index %u\n", i, j);
981 while (!list_empty(&ring->td_list)) {
982 cur_td = list_first_entry(&ring->td_list,
983 struct xhci_td,
984 td_list);
985 list_del_init(&cur_td->td_list);
986 if (!list_empty(&cur_td->cancelled_td_list))
987 list_del_init(&cur_td->cancelled_td_list);
988 xhci_giveback_urb_in_irq(xhci, cur_td,
989 -ESHUTDOWN, "killed");
990 }
991 while (!list_empty(&temp_ep->cancelled_td_list)) {
992 cur_td = list_first_entry(
993 &temp_ep->cancelled_td_list,
994 struct xhci_td,
995 cancelled_td_list);
996 list_del_init(&cur_td->cancelled_td_list);
997 xhci_giveback_urb_in_irq(xhci, cur_td,
998 -ESHUTDOWN, "killed");
999 }
1000 }
1001 }
1002 spin_unlock_irqrestore(&xhci->lock, flags);
1003 xhci_dbg(xhci, "Calling usb_hc_died()\n");
1004 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1005 xhci_dbg(xhci, "xHCI host controller is dead.\n");
1006 }
1007
1008
update_ring_for_set_deq_completion(struct xhci_hcd * xhci,struct xhci_virt_device * dev,struct xhci_ring * ep_ring,unsigned int ep_index)1009 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1010 struct xhci_virt_device *dev,
1011 struct xhci_ring *ep_ring,
1012 unsigned int ep_index)
1013 {
1014 union xhci_trb *dequeue_temp;
1015 int num_trbs_free_temp;
1016 bool revert = false;
1017
1018 num_trbs_free_temp = ep_ring->num_trbs_free;
1019 dequeue_temp = ep_ring->dequeue;
1020
1021 /* If we get two back-to-back stalls, and the first stalled transfer
1022 * ends just before a link TRB, the dequeue pointer will be left on
1023 * the link TRB by the code in the while loop. So we have to update
1024 * the dequeue pointer one segment further, or we'll jump off
1025 * the segment into la-la-land.
1026 */
1027 if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
1028 ep_ring->deq_seg = ep_ring->deq_seg->next;
1029 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1030 }
1031
1032 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1033 /* We have more usable TRBs */
1034 ep_ring->num_trbs_free++;
1035 ep_ring->dequeue++;
1036 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
1037 ep_ring->dequeue)) {
1038 if (ep_ring->dequeue ==
1039 dev->eps[ep_index].queued_deq_ptr)
1040 break;
1041 ep_ring->deq_seg = ep_ring->deq_seg->next;
1042 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1043 }
1044 if (ep_ring->dequeue == dequeue_temp) {
1045 revert = true;
1046 break;
1047 }
1048 }
1049
1050 if (revert) {
1051 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1052 ep_ring->num_trbs_free = num_trbs_free_temp;
1053 }
1054 }
1055
1056 /*
1057 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1058 * we need to clear the set deq pending flag in the endpoint ring state, so that
1059 * the TD queueing code can ring the doorbell again. We also need to ring the
1060 * endpoint doorbell to restart the ring, but only if there aren't more
1061 * cancellations pending.
1062 */
handle_set_deq_completion(struct xhci_hcd * xhci,struct xhci_event_cmd * event,union xhci_trb * trb)1063 static void handle_set_deq_completion(struct xhci_hcd *xhci,
1064 struct xhci_event_cmd *event,
1065 union xhci_trb *trb)
1066 {
1067 unsigned int slot_id;
1068 unsigned int ep_index;
1069 unsigned int stream_id;
1070 struct xhci_ring *ep_ring;
1071 struct xhci_virt_device *dev;
1072 struct xhci_ep_ctx *ep_ctx;
1073 struct xhci_slot_ctx *slot_ctx;
1074
1075 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1076 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1077 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1078 dev = xhci->devs[slot_id];
1079
1080 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1081 if (!ep_ring) {
1082 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1083 "freed stream ID %u\n",
1084 stream_id);
1085 /* XXX: Harmless??? */
1086 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1087 return;
1088 }
1089
1090 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1091 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1092
1093 if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
1094 unsigned int ep_state;
1095 unsigned int slot_state;
1096
1097 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
1098 case COMP_TRB_ERR:
1099 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1100 "of stream ID configuration\n");
1101 break;
1102 case COMP_CTX_STATE:
1103 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1104 "to incorrect slot or ep state.\n");
1105 ep_state = le32_to_cpu(ep_ctx->ep_info);
1106 ep_state &= EP_STATE_MASK;
1107 slot_state = le32_to_cpu(slot_ctx->dev_state);
1108 slot_state = GET_SLOT_STATE(slot_state);
1109 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
1110 slot_state, ep_state);
1111 break;
1112 case COMP_EBADSLT:
1113 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1114 "slot %u was not enabled.\n", slot_id);
1115 break;
1116 default:
1117 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1118 "completion code of %u.\n",
1119 GET_COMP_CODE(le32_to_cpu(event->status)));
1120 break;
1121 }
1122 /* OK what do we do now? The endpoint state is hosed, and we
1123 * should never get to this point if the synchronization between
1124 * queueing, and endpoint state are correct. This might happen
1125 * if the device gets disconnected after we've finished
1126 * cancelling URBs, which might not be an error...
1127 */
1128 } else {
1129 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1130 le64_to_cpu(ep_ctx->deq));
1131 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1132 dev->eps[ep_index].queued_deq_ptr) ==
1133 (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1134 /* Update the ring's dequeue segment and dequeue pointer
1135 * to reflect the new position.
1136 */
1137 update_ring_for_set_deq_completion(xhci, dev,
1138 ep_ring, ep_index);
1139 } else {
1140 xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1141 "Ptr command & xHCI internal state.\n");
1142 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1143 dev->eps[ep_index].queued_deq_seg,
1144 dev->eps[ep_index].queued_deq_ptr);
1145 }
1146 }
1147
1148 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1149 dev->eps[ep_index].queued_deq_seg = NULL;
1150 dev->eps[ep_index].queued_deq_ptr = NULL;
1151 /* Restart any rings with pending URBs */
1152 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1153 }
1154
handle_reset_ep_completion(struct xhci_hcd * xhci,struct xhci_event_cmd * event,union xhci_trb * trb)1155 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1156 struct xhci_event_cmd *event,
1157 union xhci_trb *trb)
1158 {
1159 int slot_id;
1160 unsigned int ep_index;
1161
1162 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1163 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1164 /* This command will only fail if the endpoint wasn't halted,
1165 * but we don't care.
1166 */
1167 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1168 GET_COMP_CODE(le32_to_cpu(event->status)));
1169
1170 /* HW with the reset endpoint quirk needs to have a configure endpoint
1171 * command complete before the endpoint can be used. Queue that here
1172 * because the HW can't handle two commands being queued in a row.
1173 */
1174 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1175 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1176 xhci_queue_configure_endpoint(xhci,
1177 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1178 false);
1179 xhci_ring_cmd_db(xhci);
1180 } else {
1181 /* Clear our internal halted state and restart the ring(s) */
1182 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1183 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1184 }
1185 }
1186
1187 /* Complete the command and detele it from the devcie's command queue.
1188 */
xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd * xhci,struct xhci_command * command,u32 status)1189 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1190 struct xhci_command *command, u32 status)
1191 {
1192 command->status = status;
1193 list_del(&command->cmd_list);
1194 if (command->completion)
1195 complete(command->completion);
1196 else
1197 xhci_free_command(xhci, command);
1198 }
1199
1200
1201 /* Check to see if a command in the device's command queue matches this one.
1202 * Signal the completion or free the command, and return 1. Return 0 if the
1203 * completed command isn't at the head of the command list.
1204 */
handle_cmd_in_cmd_wait_list(struct xhci_hcd * xhci,struct xhci_virt_device * virt_dev,struct xhci_event_cmd * event)1205 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1206 struct xhci_virt_device *virt_dev,
1207 struct xhci_event_cmd *event)
1208 {
1209 struct xhci_command *command;
1210
1211 if (list_empty(&virt_dev->cmd_list))
1212 return 0;
1213
1214 command = list_entry(virt_dev->cmd_list.next,
1215 struct xhci_command, cmd_list);
1216 if (xhci->cmd_ring->dequeue != command->command_trb)
1217 return 0;
1218
1219 xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1220 GET_COMP_CODE(le32_to_cpu(event->status)));
1221 return 1;
1222 }
1223
1224 /*
1225 * Finding the command trb need to be cancelled and modifying it to
1226 * NO OP command. And if the command is in device's command wait
1227 * list, finishing and freeing it.
1228 *
1229 * If we can't find the command trb, we think it had already been
1230 * executed.
1231 */
xhci_cmd_to_noop(struct xhci_hcd * xhci,struct xhci_cd * cur_cd)1232 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1233 {
1234 struct xhci_segment *cur_seg;
1235 union xhci_trb *cmd_trb;
1236 u32 cycle_state;
1237
1238 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1239 return;
1240
1241 /* find the current segment of command ring */
1242 cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1243 xhci->cmd_ring->dequeue, &cycle_state);
1244
1245 if (!cur_seg) {
1246 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1247 xhci->cmd_ring->dequeue,
1248 (unsigned long long)
1249 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1250 xhci->cmd_ring->dequeue));
1251 xhci_debug_ring(xhci, xhci->cmd_ring);
1252 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1253 return;
1254 }
1255
1256 /* find the command trb matched by cd from command ring */
1257 for (cmd_trb = xhci->cmd_ring->dequeue;
1258 cmd_trb != xhci->cmd_ring->enqueue;
1259 next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1260 /* If the trb is link trb, continue */
1261 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1262 continue;
1263
1264 if (cur_cd->cmd_trb == cmd_trb) {
1265
1266 /* If the command in device's command list, we should
1267 * finish it and free the command structure.
1268 */
1269 if (cur_cd->command)
1270 xhci_complete_cmd_in_cmd_wait_list(xhci,
1271 cur_cd->command, COMP_CMD_STOP);
1272
1273 /* get cycle state from the origin command trb */
1274 cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1275 & TRB_CYCLE;
1276
1277 /* modify the command trb to NO OP command */
1278 cmd_trb->generic.field[0] = 0;
1279 cmd_trb->generic.field[1] = 0;
1280 cmd_trb->generic.field[2] = 0;
1281 cmd_trb->generic.field[3] = cpu_to_le32(
1282 TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1283 break;
1284 }
1285 }
1286 }
1287
xhci_cancel_cmd_in_cd_list(struct xhci_hcd * xhci)1288 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1289 {
1290 struct xhci_cd *cur_cd, *next_cd;
1291
1292 if (list_empty(&xhci->cancel_cmd_list))
1293 return;
1294
1295 list_for_each_entry_safe(cur_cd, next_cd,
1296 &xhci->cancel_cmd_list, cancel_cmd_list) {
1297 xhci_cmd_to_noop(xhci, cur_cd);
1298 list_del(&cur_cd->cancel_cmd_list);
1299 kfree(cur_cd);
1300 }
1301 }
1302
1303 /*
1304 * traversing the cancel_cmd_list. If the command descriptor according
1305 * to cmd_trb is found, the function free it and return 1, otherwise
1306 * return 0.
1307 */
xhci_search_cmd_trb_in_cd_list(struct xhci_hcd * xhci,union xhci_trb * cmd_trb)1308 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1309 union xhci_trb *cmd_trb)
1310 {
1311 struct xhci_cd *cur_cd, *next_cd;
1312
1313 if (list_empty(&xhci->cancel_cmd_list))
1314 return 0;
1315
1316 list_for_each_entry_safe(cur_cd, next_cd,
1317 &xhci->cancel_cmd_list, cancel_cmd_list) {
1318 if (cur_cd->cmd_trb == cmd_trb) {
1319 if (cur_cd->command)
1320 xhci_complete_cmd_in_cmd_wait_list(xhci,
1321 cur_cd->command, COMP_CMD_STOP);
1322 list_del(&cur_cd->cancel_cmd_list);
1323 kfree(cur_cd);
1324 return 1;
1325 }
1326 }
1327
1328 return 0;
1329 }
1330
1331 /*
1332 * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1333 * trb pointed by the command ring dequeue pointer is the trb we want to
1334 * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1335 * traverse the cancel_cmd_list to trun the all of the commands according
1336 * to command descriptor to NO-OP trb.
1337 */
handle_stopped_cmd_ring(struct xhci_hcd * xhci,int cmd_trb_comp_code)1338 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1339 int cmd_trb_comp_code)
1340 {
1341 int cur_trb_is_good = 0;
1342
1343 /* Searching the cmd trb pointed by the command ring dequeue
1344 * pointer in command descriptor list. If it is found, free it.
1345 */
1346 cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1347 xhci->cmd_ring->dequeue);
1348
1349 if (cmd_trb_comp_code == COMP_CMD_ABORT)
1350 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1351 else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1352 /* traversing the cancel_cmd_list and canceling
1353 * the command according to command descriptor
1354 */
1355 xhci_cancel_cmd_in_cd_list(xhci);
1356
1357 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1358 /*
1359 * ring command ring doorbell again to restart the
1360 * command ring
1361 */
1362 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1363 xhci_ring_cmd_db(xhci);
1364 }
1365 return cur_trb_is_good;
1366 }
1367
handle_cmd_completion(struct xhci_hcd * xhci,struct xhci_event_cmd * event)1368 static void handle_cmd_completion(struct xhci_hcd *xhci,
1369 struct xhci_event_cmd *event)
1370 {
1371 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1372 u64 cmd_dma;
1373 dma_addr_t cmd_dequeue_dma;
1374 struct xhci_input_control_ctx *ctrl_ctx;
1375 struct xhci_virt_device *virt_dev;
1376 unsigned int ep_index;
1377 struct xhci_ring *ep_ring;
1378 unsigned int ep_state;
1379
1380 cmd_dma = le64_to_cpu(event->cmd_trb);
1381 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1382 xhci->cmd_ring->dequeue);
1383 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1384 if (cmd_dequeue_dma == 0) {
1385 xhci->error_bitmask |= 1 << 4;
1386 return;
1387 }
1388 /* Does the DMA address match our internal dequeue pointer address? */
1389 if (cmd_dma != (u64) cmd_dequeue_dma) {
1390 xhci->error_bitmask |= 1 << 5;
1391 return;
1392 }
1393
1394 if ((GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_ABORT) ||
1395 (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_STOP)) {
1396 /* If the return value is 0, we think the trb pointed by
1397 * command ring dequeue pointer is a good trb. The good
1398 * trb means we don't want to cancel the trb, but it have
1399 * been stopped by host. So we should handle it normally.
1400 * Otherwise, driver should invoke inc_deq() and return.
1401 */
1402 if (handle_stopped_cmd_ring(xhci,
1403 GET_COMP_CODE(le32_to_cpu(event->status)))) {
1404 inc_deq(xhci, xhci->cmd_ring);
1405 return;
1406 }
1407 /* There is no command to handle if we get a stop event when the
1408 * command ring is empty, event->cmd_trb points to the next
1409 * unset command
1410 */
1411 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1412 return;
1413 }
1414
1415 switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1416 & TRB_TYPE_BITMASK) {
1417 case TRB_TYPE(TRB_ENABLE_SLOT):
1418 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1419 xhci->slot_id = slot_id;
1420 else
1421 xhci->slot_id = 0;
1422 complete(&xhci->addr_dev);
1423 break;
1424 case TRB_TYPE(TRB_DISABLE_SLOT):
1425 if (xhci->devs[slot_id]) {
1426 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1427 /* Delete default control endpoint resources */
1428 xhci_free_device_endpoint_resources(xhci,
1429 xhci->devs[slot_id], true);
1430 xhci_free_virt_device(xhci, slot_id);
1431 }
1432 break;
1433 case TRB_TYPE(TRB_CONFIG_EP):
1434 virt_dev = xhci->devs[slot_id];
1435 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1436 break;
1437 /*
1438 * Configure endpoint commands can come from the USB core
1439 * configuration or alt setting changes, or because the HW
1440 * needed an extra configure endpoint command after a reset
1441 * endpoint command or streams were being configured.
1442 * If the command was for a halted endpoint, the xHCI driver
1443 * is not waiting on the configure endpoint command.
1444 */
1445 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1446 virt_dev->in_ctx);
1447 /* Input ctx add_flags are the endpoint index plus one */
1448 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1449 /* A usb_set_interface() call directly after clearing a halted
1450 * condition may race on this quirky hardware. Not worth
1451 * worrying about, since this is prototype hardware. Not sure
1452 * if this will work for streams, but streams support was
1453 * untested on this prototype.
1454 */
1455 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1456 ep_index != (unsigned int) -1 &&
1457 le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1458 le32_to_cpu(ctrl_ctx->drop_flags)) {
1459 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1460 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1461 if (!(ep_state & EP_HALTED))
1462 goto bandwidth_change;
1463 xhci_dbg(xhci, "Completed config ep cmd - "
1464 "last ep index = %d, state = %d\n",
1465 ep_index, ep_state);
1466 /* Clear internal halted state and restart ring(s) */
1467 xhci->devs[slot_id]->eps[ep_index].ep_state &=
1468 ~EP_HALTED;
1469 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1470 break;
1471 }
1472 bandwidth_change:
1473 xhci_dbg(xhci, "Completed config ep cmd\n");
1474 xhci->devs[slot_id]->cmd_status =
1475 GET_COMP_CODE(le32_to_cpu(event->status));
1476 complete(&xhci->devs[slot_id]->cmd_completion);
1477 break;
1478 case TRB_TYPE(TRB_EVAL_CONTEXT):
1479 virt_dev = xhci->devs[slot_id];
1480 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1481 break;
1482 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1483 complete(&xhci->devs[slot_id]->cmd_completion);
1484 break;
1485 case TRB_TYPE(TRB_ADDR_DEV):
1486 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1487 complete(&xhci->addr_dev);
1488 break;
1489 case TRB_TYPE(TRB_STOP_RING):
1490 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1491 break;
1492 case TRB_TYPE(TRB_SET_DEQ):
1493 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1494 break;
1495 case TRB_TYPE(TRB_CMD_NOOP):
1496 break;
1497 case TRB_TYPE(TRB_RESET_EP):
1498 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1499 break;
1500 case TRB_TYPE(TRB_RESET_DEV):
1501 xhci_dbg(xhci, "Completed reset device command.\n");
1502 slot_id = TRB_TO_SLOT_ID(
1503 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1504 virt_dev = xhci->devs[slot_id];
1505 if (virt_dev)
1506 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1507 else
1508 xhci_warn(xhci, "Reset device command completion "
1509 "for disabled slot %u\n", slot_id);
1510 break;
1511 case TRB_TYPE(TRB_NEC_GET_FW):
1512 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1513 xhci->error_bitmask |= 1 << 6;
1514 break;
1515 }
1516 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1517 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1518 NEC_FW_MINOR(le32_to_cpu(event->status)));
1519 break;
1520 default:
1521 /* Skip over unknown commands on the event ring */
1522 xhci->error_bitmask |= 1 << 6;
1523 break;
1524 }
1525 inc_deq(xhci, xhci->cmd_ring);
1526 }
1527
handle_vendor_event(struct xhci_hcd * xhci,union xhci_trb * event)1528 static void handle_vendor_event(struct xhci_hcd *xhci,
1529 union xhci_trb *event)
1530 {
1531 u32 trb_type;
1532
1533 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1534 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1535 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1536 handle_cmd_completion(xhci, &event->event_cmd);
1537 }
1538
1539 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1540 * port registers -- USB 3.0 and USB 2.0).
1541 *
1542 * Returns a zero-based port number, which is suitable for indexing into each of
1543 * the split roothubs' port arrays and bus state arrays.
1544 * Add one to it in order to call xhci_find_slot_id_by_port.
1545 */
find_faked_portnum_from_hw_portnum(struct usb_hcd * hcd,struct xhci_hcd * xhci,u32 port_id)1546 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1547 struct xhci_hcd *xhci, u32 port_id)
1548 {
1549 unsigned int i;
1550 unsigned int num_similar_speed_ports = 0;
1551
1552 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1553 * and usb2_ports are 0-based indexes. Count the number of similar
1554 * speed ports, up to 1 port before this port.
1555 */
1556 for (i = 0; i < (port_id - 1); i++) {
1557 u8 port_speed = xhci->port_array[i];
1558
1559 /*
1560 * Skip ports that don't have known speeds, or have duplicate
1561 * Extended Capabilities port speed entries.
1562 */
1563 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1564 continue;
1565
1566 /*
1567 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1568 * 1.1 ports are under the USB 2.0 hub. If the port speed
1569 * matches the device speed, it's a similar speed port.
1570 */
1571 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1572 num_similar_speed_ports++;
1573 }
1574 return num_similar_speed_ports;
1575 }
1576
handle_device_notification(struct xhci_hcd * xhci,union xhci_trb * event)1577 static void handle_device_notification(struct xhci_hcd *xhci,
1578 union xhci_trb *event)
1579 {
1580 u32 slot_id;
1581 struct usb_device *udev;
1582
1583 slot_id = TRB_TO_SLOT_ID(event->generic.field[3]);
1584 if (!xhci->devs[slot_id]) {
1585 xhci_warn(xhci, "Device Notification event for "
1586 "unused slot %u\n", slot_id);
1587 return;
1588 }
1589
1590 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1591 slot_id);
1592 udev = xhci->devs[slot_id]->udev;
1593 if (udev && udev->parent)
1594 usb_wakeup_notification(udev->parent, udev->portnum);
1595 }
1596
handle_port_status(struct xhci_hcd * xhci,union xhci_trb * event)1597 static void handle_port_status(struct xhci_hcd *xhci,
1598 union xhci_trb *event)
1599 {
1600 struct usb_hcd *hcd;
1601 u32 port_id;
1602 u32 temp, temp1;
1603 int max_ports;
1604 int slot_id;
1605 unsigned int faked_port_index;
1606 u8 major_revision;
1607 struct xhci_bus_state *bus_state;
1608 __le32 __iomem **port_array;
1609 bool bogus_port_status = false;
1610
1611 /* Port status change events always have a successful completion code */
1612 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1613 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1614 xhci->error_bitmask |= 1 << 8;
1615 }
1616 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1617 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1618
1619 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1620 if ((port_id <= 0) || (port_id > max_ports)) {
1621 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1622 bogus_port_status = true;
1623 goto cleanup;
1624 }
1625
1626 /* Figure out which usb_hcd this port is attached to:
1627 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1628 */
1629 major_revision = xhci->port_array[port_id - 1];
1630 if (major_revision == 0) {
1631 xhci_warn(xhci, "Event for port %u not in "
1632 "Extended Capabilities, ignoring.\n",
1633 port_id);
1634 bogus_port_status = true;
1635 goto cleanup;
1636 }
1637 if (major_revision == DUPLICATE_ENTRY) {
1638 xhci_warn(xhci, "Event for port %u duplicated in"
1639 "Extended Capabilities, ignoring.\n",
1640 port_id);
1641 bogus_port_status = true;
1642 goto cleanup;
1643 }
1644
1645 /*
1646 * Hardware port IDs reported by a Port Status Change Event include USB
1647 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1648 * resume event, but we first need to translate the hardware port ID
1649 * into the index into the ports on the correct split roothub, and the
1650 * correct bus_state structure.
1651 */
1652 /* Find the right roothub. */
1653 hcd = xhci_to_hcd(xhci);
1654 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1655 hcd = xhci->shared_hcd;
1656 bus_state = &xhci->bus_state[hcd_index(hcd)];
1657 if (hcd->speed == HCD_USB3)
1658 port_array = xhci->usb3_ports;
1659 else
1660 port_array = xhci->usb2_ports;
1661 /* Find the faked port hub number */
1662 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1663 port_id);
1664
1665 temp = xhci_readl(xhci, port_array[faked_port_index]);
1666 if (hcd->state == HC_STATE_SUSPENDED) {
1667 xhci_dbg(xhci, "resume root hub\n");
1668 usb_hcd_resume_root_hub(hcd);
1669 }
1670
1671 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1672 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1673
1674 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1675 if (!(temp1 & CMD_RUN)) {
1676 xhci_warn(xhci, "xHC is not running.\n");
1677 goto cleanup;
1678 }
1679
1680 if (DEV_SUPERSPEED(temp)) {
1681 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1682 /* Set a flag to say the port signaled remote wakeup,
1683 * so we can tell the difference between the end of
1684 * device and host initiated resume.
1685 */
1686 bus_state->port_remote_wakeup |= 1 << faked_port_index;
1687 xhci_test_and_clear_bit(xhci, port_array,
1688 faked_port_index, PORT_PLC);
1689 xhci_set_link_state(xhci, port_array, faked_port_index,
1690 XDEV_U0);
1691 /* Need to wait until the next link state change
1692 * indicates the device is actually in U0.
1693 */
1694 bogus_port_status = true;
1695 goto cleanup;
1696 } else {
1697 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1698 bus_state->resume_done[faked_port_index] = jiffies +
1699 msecs_to_jiffies(20);
1700 set_bit(faked_port_index, &bus_state->resuming_ports);
1701 mod_timer(&hcd->rh_timer,
1702 bus_state->resume_done[faked_port_index]);
1703 /* Do the rest in GetPortStatus */
1704 }
1705 }
1706
1707 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1708 DEV_SUPERSPEED(temp)) {
1709 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1710 /* We've just brought the device into U0 through either the
1711 * Resume state after a device remote wakeup, or through the
1712 * U3Exit state after a host-initiated resume. If it's a device
1713 * initiated remote wake, don't pass up the link state change,
1714 * so the roothub behavior is consistent with external
1715 * USB 3.0 hub behavior.
1716 */
1717 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1718 faked_port_index + 1);
1719 if (slot_id && xhci->devs[slot_id])
1720 xhci_ring_device(xhci, slot_id);
1721 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1722 bus_state->port_remote_wakeup &=
1723 ~(1 << faked_port_index);
1724 xhci_test_and_clear_bit(xhci, port_array,
1725 faked_port_index, PORT_PLC);
1726 usb_wakeup_notification(hcd->self.root_hub,
1727 faked_port_index + 1);
1728 bogus_port_status = true;
1729 goto cleanup;
1730 }
1731 }
1732
1733 if (hcd->speed != HCD_USB3)
1734 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1735 PORT_PLC);
1736
1737 cleanup:
1738 /* Update event ring dequeue pointer before dropping the lock */
1739 inc_deq(xhci, xhci->event_ring);
1740
1741 /* Don't make the USB core poll the roothub if we got a bad port status
1742 * change event. Besides, at that point we can't tell which roothub
1743 * (USB 2.0 or USB 3.0) to kick.
1744 */
1745 if (bogus_port_status)
1746 return;
1747
1748 /*
1749 * xHCI port-status-change events occur when the "or" of all the
1750 * status-change bits in the portsc register changes from 0 to 1.
1751 * New status changes won't cause an event if any other change
1752 * bits are still set. When an event occurs, switch over to
1753 * polling to avoid losing status changes.
1754 */
1755 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1756 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1757 spin_unlock(&xhci->lock);
1758 /* Pass this up to the core */
1759 usb_hcd_poll_rh_status(hcd);
1760 spin_lock(&xhci->lock);
1761 }
1762
1763 /*
1764 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1765 * at end_trb, which may be in another segment. If the suspect DMA address is a
1766 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1767 * returns 0.
1768 */
trb_in_td(struct xhci_segment * start_seg,union xhci_trb * start_trb,union xhci_trb * end_trb,dma_addr_t suspect_dma)1769 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1770 union xhci_trb *start_trb,
1771 union xhci_trb *end_trb,
1772 dma_addr_t suspect_dma)
1773 {
1774 dma_addr_t start_dma;
1775 dma_addr_t end_seg_dma;
1776 dma_addr_t end_trb_dma;
1777 struct xhci_segment *cur_seg;
1778
1779 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1780 cur_seg = start_seg;
1781
1782 do {
1783 if (start_dma == 0)
1784 return NULL;
1785 /* We may get an event for a Link TRB in the middle of a TD */
1786 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1787 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1788 /* If the end TRB isn't in this segment, this is set to 0 */
1789 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1790
1791 if (end_trb_dma > 0) {
1792 /* The end TRB is in this segment, so suspect should be here */
1793 if (start_dma <= end_trb_dma) {
1794 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1795 return cur_seg;
1796 } else {
1797 /* Case for one segment with
1798 * a TD wrapped around to the top
1799 */
1800 if ((suspect_dma >= start_dma &&
1801 suspect_dma <= end_seg_dma) ||
1802 (suspect_dma >= cur_seg->dma &&
1803 suspect_dma <= end_trb_dma))
1804 return cur_seg;
1805 }
1806 return NULL;
1807 } else {
1808 /* Might still be somewhere in this segment */
1809 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1810 return cur_seg;
1811 }
1812 cur_seg = cur_seg->next;
1813 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1814 } while (cur_seg != start_seg);
1815
1816 return NULL;
1817 }
1818
xhci_cleanup_halted_endpoint(struct xhci_hcd * xhci,unsigned int slot_id,unsigned int ep_index,unsigned int stream_id,struct xhci_td * td,union xhci_trb * event_trb)1819 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1820 unsigned int slot_id, unsigned int ep_index,
1821 unsigned int stream_id,
1822 struct xhci_td *td, union xhci_trb *event_trb)
1823 {
1824 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1825 ep->ep_state |= EP_HALTED;
1826 ep->stopped_td = td;
1827 ep->stopped_trb = event_trb;
1828 ep->stopped_stream = stream_id;
1829
1830 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1831 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1832
1833 ep->stopped_td = NULL;
1834 ep->stopped_trb = NULL;
1835 ep->stopped_stream = 0;
1836
1837 xhci_ring_cmd_db(xhci);
1838 }
1839
1840 /* Check if an error has halted the endpoint ring. The class driver will
1841 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1842 * However, a babble and other errors also halt the endpoint ring, and the class
1843 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1844 * Ring Dequeue Pointer command manually.
1845 */
xhci_requires_manual_halt_cleanup(struct xhci_hcd * xhci,struct xhci_ep_ctx * ep_ctx,unsigned int trb_comp_code)1846 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1847 struct xhci_ep_ctx *ep_ctx,
1848 unsigned int trb_comp_code)
1849 {
1850 /* TRB completion codes that may require a manual halt cleanup */
1851 if (trb_comp_code == COMP_TX_ERR ||
1852 trb_comp_code == COMP_BABBLE ||
1853 trb_comp_code == COMP_SPLIT_ERR)
1854 /* The 0.96 spec says a babbling control endpoint
1855 * is not halted. The 0.96 spec says it is. Some HW
1856 * claims to be 0.95 compliant, but it halts the control
1857 * endpoint anyway. Check if a babble halted the
1858 * endpoint.
1859 */
1860 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1861 cpu_to_le32(EP_STATE_HALTED))
1862 return 1;
1863
1864 return 0;
1865 }
1866
xhci_is_vendor_info_code(struct xhci_hcd * xhci,unsigned int trb_comp_code)1867 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1868 {
1869 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1870 /* Vendor defined "informational" completion code,
1871 * treat as not-an-error.
1872 */
1873 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1874 trb_comp_code);
1875 xhci_dbg(xhci, "Treating code as success.\n");
1876 return 1;
1877 }
1878 return 0;
1879 }
1880
1881 /*
1882 * Finish the td processing, remove the td from td list;
1883 * Return 1 if the urb can be given back.
1884 */
finish_td(struct xhci_hcd * xhci,struct xhci_td * td,union xhci_trb * event_trb,struct xhci_transfer_event * event,struct xhci_virt_ep * ep,int * status,bool skip)1885 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1886 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1887 struct xhci_virt_ep *ep, int *status, bool skip)
1888 {
1889 struct xhci_virt_device *xdev;
1890 struct xhci_ring *ep_ring;
1891 unsigned int slot_id;
1892 int ep_index;
1893 struct urb *urb = NULL;
1894 struct xhci_ep_ctx *ep_ctx;
1895 int ret = 0;
1896 struct urb_priv *urb_priv;
1897 u32 trb_comp_code;
1898
1899 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1900 xdev = xhci->devs[slot_id];
1901 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1902 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1903 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1904 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1905
1906 if (skip)
1907 goto td_cleanup;
1908
1909 if (trb_comp_code == COMP_STOP_INVAL ||
1910 trb_comp_code == COMP_STOP) {
1911 /* The Endpoint Stop Command completion will take care of any
1912 * stopped TDs. A stopped TD may be restarted, so don't update
1913 * the ring dequeue pointer or take this TD off any lists yet.
1914 */
1915 ep->stopped_td = td;
1916 ep->stopped_trb = event_trb;
1917 return 0;
1918 } else {
1919 if (trb_comp_code == COMP_STALL) {
1920 /* The transfer is completed from the driver's
1921 * perspective, but we need to issue a set dequeue
1922 * command for this stalled endpoint to move the dequeue
1923 * pointer past the TD. We can't do that here because
1924 * the halt condition must be cleared first. Let the
1925 * USB class driver clear the stall later.
1926 */
1927 ep->stopped_td = td;
1928 ep->stopped_trb = event_trb;
1929 ep->stopped_stream = ep_ring->stream_id;
1930 } else if (xhci_requires_manual_halt_cleanup(xhci,
1931 ep_ctx, trb_comp_code)) {
1932 /* Other types of errors halt the endpoint, but the
1933 * class driver doesn't call usb_reset_endpoint() unless
1934 * the error is -EPIPE. Clear the halted status in the
1935 * xHCI hardware manually.
1936 */
1937 xhci_cleanup_halted_endpoint(xhci,
1938 slot_id, ep_index, ep_ring->stream_id,
1939 td, event_trb);
1940 } else {
1941 /* Update ring dequeue pointer */
1942 while (ep_ring->dequeue != td->last_trb)
1943 inc_deq(xhci, ep_ring);
1944 inc_deq(xhci, ep_ring);
1945 }
1946
1947 td_cleanup:
1948 /* Clean up the endpoint's TD list */
1949 urb = td->urb;
1950 urb_priv = urb->hcpriv;
1951
1952 /* Do one last check of the actual transfer length.
1953 * If the host controller said we transferred more data than
1954 * the buffer length, urb->actual_length will be a very big
1955 * number (since it's unsigned). Play it safe and say we didn't
1956 * transfer anything.
1957 */
1958 if (urb->actual_length > urb->transfer_buffer_length) {
1959 xhci_warn(xhci, "URB transfer length is wrong, "
1960 "xHC issue? req. len = %u, "
1961 "act. len = %u\n",
1962 urb->transfer_buffer_length,
1963 urb->actual_length);
1964 urb->actual_length = 0;
1965 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1966 *status = -EREMOTEIO;
1967 else
1968 *status = 0;
1969 }
1970 list_del_init(&td->td_list);
1971 /* Was this TD slated to be cancelled but completed anyway? */
1972 if (!list_empty(&td->cancelled_td_list))
1973 list_del_init(&td->cancelled_td_list);
1974
1975 urb_priv->td_cnt++;
1976 /* Giveback the urb when all the tds are completed */
1977 if (urb_priv->td_cnt == urb_priv->length) {
1978 ret = 1;
1979 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1980 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1981 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1982 == 0) {
1983 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1984 usb_amd_quirk_pll_enable();
1985 }
1986 }
1987 }
1988 }
1989
1990 return ret;
1991 }
1992
1993 /*
1994 * Process control tds, update urb status and actual_length.
1995 */
process_ctrl_td(struct xhci_hcd * xhci,struct xhci_td * td,union xhci_trb * event_trb,struct xhci_transfer_event * event,struct xhci_virt_ep * ep,int * status)1996 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1997 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1998 struct xhci_virt_ep *ep, int *status)
1999 {
2000 struct xhci_virt_device *xdev;
2001 struct xhci_ring *ep_ring;
2002 unsigned int slot_id;
2003 int ep_index;
2004 struct xhci_ep_ctx *ep_ctx;
2005 u32 trb_comp_code;
2006
2007 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2008 xdev = xhci->devs[slot_id];
2009 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2010 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2011 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2012 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2013
2014 switch (trb_comp_code) {
2015 case COMP_SUCCESS:
2016 if (event_trb == ep_ring->dequeue) {
2017 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
2018 "without IOC set??\n");
2019 *status = -ESHUTDOWN;
2020 } else if (event_trb != td->last_trb) {
2021 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
2022 "without IOC set??\n");
2023 *status = -ESHUTDOWN;
2024 } else {
2025 *status = 0;
2026 }
2027 break;
2028 case COMP_SHORT_TX:
2029 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2030 *status = -EREMOTEIO;
2031 else
2032 *status = 0;
2033 break;
2034 case COMP_STOP_INVAL:
2035 case COMP_STOP:
2036 return finish_td(xhci, td, event_trb, event, ep, status, false);
2037 default:
2038 if (!xhci_requires_manual_halt_cleanup(xhci,
2039 ep_ctx, trb_comp_code))
2040 break;
2041 xhci_dbg(xhci, "TRB error code %u, "
2042 "halted endpoint index = %u\n",
2043 trb_comp_code, ep_index);
2044 /* else fall through */
2045 case COMP_STALL:
2046 /* Did we transfer part of the data (middle) phase? */
2047 if (event_trb != ep_ring->dequeue &&
2048 event_trb != td->last_trb)
2049 td->urb->actual_length =
2050 td->urb->transfer_buffer_length -
2051 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2052 else
2053 td->urb->actual_length = 0;
2054
2055 xhci_cleanup_halted_endpoint(xhci,
2056 slot_id, ep_index, 0, td, event_trb);
2057 return finish_td(xhci, td, event_trb, event, ep, status, true);
2058 }
2059 /*
2060 * Did we transfer any data, despite the errors that might have
2061 * happened? I.e. did we get past the setup stage?
2062 */
2063 if (event_trb != ep_ring->dequeue) {
2064 /* The event was for the status stage */
2065 if (event_trb == td->last_trb) {
2066 if (td->urb->actual_length != 0) {
2067 /* Don't overwrite a previously set error code
2068 */
2069 if ((*status == -EINPROGRESS || *status == 0) &&
2070 (td->urb->transfer_flags
2071 & URB_SHORT_NOT_OK))
2072 /* Did we already see a short data
2073 * stage? */
2074 *status = -EREMOTEIO;
2075 } else {
2076 td->urb->actual_length =
2077 td->urb->transfer_buffer_length;
2078 }
2079 } else {
2080 /* Maybe the event was for the data stage? */
2081 td->urb->actual_length =
2082 td->urb->transfer_buffer_length -
2083 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2084 xhci_dbg(xhci, "Waiting for status "
2085 "stage event\n");
2086 return 0;
2087 }
2088 }
2089
2090 return finish_td(xhci, td, event_trb, event, ep, status, false);
2091 }
2092
2093 /*
2094 * Process isochronous tds, update urb packet status and actual_length.
2095 */
process_isoc_td(struct xhci_hcd * xhci,struct xhci_td * td,union xhci_trb * event_trb,struct xhci_transfer_event * event,struct xhci_virt_ep * ep,int * status)2096 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2097 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2098 struct xhci_virt_ep *ep, int *status)
2099 {
2100 struct xhci_ring *ep_ring;
2101 struct urb_priv *urb_priv;
2102 int idx;
2103 int len = 0;
2104 union xhci_trb *cur_trb;
2105 struct xhci_segment *cur_seg;
2106 struct usb_iso_packet_descriptor *frame;
2107 u32 trb_comp_code;
2108 bool skip_td = false;
2109
2110 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2111 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2112 urb_priv = td->urb->hcpriv;
2113 idx = urb_priv->td_cnt;
2114 frame = &td->urb->iso_frame_desc[idx];
2115
2116 /* handle completion code */
2117 switch (trb_comp_code) {
2118 case COMP_SUCCESS:
2119 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2120 frame->status = 0;
2121 break;
2122 }
2123 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2124 trb_comp_code = COMP_SHORT_TX;
2125 case COMP_SHORT_TX:
2126 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2127 -EREMOTEIO : 0;
2128 break;
2129 case COMP_BW_OVER:
2130 frame->status = -ECOMM;
2131 skip_td = true;
2132 break;
2133 case COMP_BUFF_OVER:
2134 case COMP_BABBLE:
2135 frame->status = -EOVERFLOW;
2136 skip_td = true;
2137 break;
2138 case COMP_DEV_ERR:
2139 case COMP_STALL:
2140 case COMP_TX_ERR:
2141 frame->status = -EPROTO;
2142 skip_td = true;
2143 break;
2144 case COMP_STOP:
2145 case COMP_STOP_INVAL:
2146 break;
2147 default:
2148 frame->status = -1;
2149 break;
2150 }
2151
2152 if (trb_comp_code == COMP_SUCCESS || skip_td) {
2153 frame->actual_length = frame->length;
2154 td->urb->actual_length += frame->length;
2155 } else {
2156 for (cur_trb = ep_ring->dequeue,
2157 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2158 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2159 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2160 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2161 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2162 }
2163 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2164 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2165
2166 if (trb_comp_code != COMP_STOP_INVAL) {
2167 frame->actual_length = len;
2168 td->urb->actual_length += len;
2169 }
2170 }
2171
2172 return finish_td(xhci, td, event_trb, event, ep, status, false);
2173 }
2174
skip_isoc_td(struct xhci_hcd * xhci,struct xhci_td * td,struct xhci_transfer_event * event,struct xhci_virt_ep * ep,int * status)2175 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2176 struct xhci_transfer_event *event,
2177 struct xhci_virt_ep *ep, int *status)
2178 {
2179 struct xhci_ring *ep_ring;
2180 struct urb_priv *urb_priv;
2181 struct usb_iso_packet_descriptor *frame;
2182 int idx;
2183
2184 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2185 urb_priv = td->urb->hcpriv;
2186 idx = urb_priv->td_cnt;
2187 frame = &td->urb->iso_frame_desc[idx];
2188
2189 /* The transfer is partly done. */
2190 frame->status = -EXDEV;
2191
2192 /* calc actual length */
2193 frame->actual_length = 0;
2194
2195 /* Update ring dequeue pointer */
2196 while (ep_ring->dequeue != td->last_trb)
2197 inc_deq(xhci, ep_ring);
2198 inc_deq(xhci, ep_ring);
2199
2200 return finish_td(xhci, td, NULL, event, ep, status, true);
2201 }
2202
2203 /*
2204 * Process bulk and interrupt tds, update urb status and actual_length.
2205 */
process_bulk_intr_td(struct xhci_hcd * xhci,struct xhci_td * td,union xhci_trb * event_trb,struct xhci_transfer_event * event,struct xhci_virt_ep * ep,int * status)2206 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2207 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2208 struct xhci_virt_ep *ep, int *status)
2209 {
2210 struct xhci_ring *ep_ring;
2211 union xhci_trb *cur_trb;
2212 struct xhci_segment *cur_seg;
2213 u32 trb_comp_code;
2214
2215 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2216 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2217
2218 switch (trb_comp_code) {
2219 case COMP_SUCCESS:
2220 /* Double check that the HW transferred everything. */
2221 if (event_trb != td->last_trb ||
2222 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2223 xhci_warn(xhci, "WARN Successful completion "
2224 "on short TX\n");
2225 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2226 *status = -EREMOTEIO;
2227 else
2228 *status = 0;
2229 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2230 trb_comp_code = COMP_SHORT_TX;
2231 } else {
2232 *status = 0;
2233 }
2234 break;
2235 case COMP_SHORT_TX:
2236 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2237 *status = -EREMOTEIO;
2238 else
2239 *status = 0;
2240 break;
2241 default:
2242 /* Others already handled above */
2243 break;
2244 }
2245 if (trb_comp_code == COMP_SHORT_TX)
2246 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2247 "%d bytes untransferred\n",
2248 td->urb->ep->desc.bEndpointAddress,
2249 td->urb->transfer_buffer_length,
2250 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2251 /* Fast path - was this the last TRB in the TD for this URB? */
2252 if (event_trb == td->last_trb) {
2253 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2254 td->urb->actual_length =
2255 td->urb->transfer_buffer_length -
2256 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2257 if (td->urb->transfer_buffer_length <
2258 td->urb->actual_length) {
2259 xhci_warn(xhci, "HC gave bad length "
2260 "of %d bytes left\n",
2261 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2262 td->urb->actual_length = 0;
2263 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2264 *status = -EREMOTEIO;
2265 else
2266 *status = 0;
2267 }
2268 /* Don't overwrite a previously set error code */
2269 if (*status == -EINPROGRESS) {
2270 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2271 *status = -EREMOTEIO;
2272 else
2273 *status = 0;
2274 }
2275 } else {
2276 td->urb->actual_length =
2277 td->urb->transfer_buffer_length;
2278 /* Ignore a short packet completion if the
2279 * untransferred length was zero.
2280 */
2281 if (*status == -EREMOTEIO)
2282 *status = 0;
2283 }
2284 } else {
2285 /* Slow path - walk the list, starting from the dequeue
2286 * pointer, to get the actual length transferred.
2287 */
2288 td->urb->actual_length = 0;
2289 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2290 cur_trb != event_trb;
2291 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2292 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2293 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2294 td->urb->actual_length +=
2295 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2296 }
2297 /* If the ring didn't stop on a Link or No-op TRB, add
2298 * in the actual bytes transferred from the Normal TRB
2299 */
2300 if (trb_comp_code != COMP_STOP_INVAL)
2301 td->urb->actual_length +=
2302 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2303 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2304 }
2305
2306 return finish_td(xhci, td, event_trb, event, ep, status, false);
2307 }
2308
2309 /*
2310 * If this function returns an error condition, it means it got a Transfer
2311 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2312 * At this point, the host controller is probably hosed and should be reset.
2313 */
handle_tx_event(struct xhci_hcd * xhci,struct xhci_transfer_event * event)2314 static int handle_tx_event(struct xhci_hcd *xhci,
2315 struct xhci_transfer_event *event)
2316 {
2317 struct xhci_virt_device *xdev;
2318 struct xhci_virt_ep *ep;
2319 struct xhci_ring *ep_ring;
2320 unsigned int slot_id;
2321 int ep_index;
2322 struct xhci_td *td = NULL;
2323 dma_addr_t event_dma;
2324 struct xhci_segment *event_seg;
2325 union xhci_trb *event_trb;
2326 struct urb *urb = NULL;
2327 int status = -EINPROGRESS;
2328 struct urb_priv *urb_priv;
2329 struct xhci_ep_ctx *ep_ctx;
2330 struct list_head *tmp;
2331 u32 trb_comp_code;
2332 int ret = 0;
2333 int td_num = 0;
2334
2335 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2336 xdev = xhci->devs[slot_id];
2337 if (!xdev) {
2338 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2339 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2340 (unsigned long long) xhci_trb_virt_to_dma(
2341 xhci->event_ring->deq_seg,
2342 xhci->event_ring->dequeue),
2343 lower_32_bits(le64_to_cpu(event->buffer)),
2344 upper_32_bits(le64_to_cpu(event->buffer)),
2345 le32_to_cpu(event->transfer_len),
2346 le32_to_cpu(event->flags));
2347 xhci_dbg(xhci, "Event ring:\n");
2348 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2349 return -ENODEV;
2350 }
2351
2352 /* Endpoint ID is 1 based, our index is zero based */
2353 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2354 ep = &xdev->eps[ep_index];
2355 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2356 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2357 if (!ep_ring ||
2358 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2359 EP_STATE_DISABLED) {
2360 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2361 "or incorrect stream ring\n");
2362 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2363 (unsigned long long) xhci_trb_virt_to_dma(
2364 xhci->event_ring->deq_seg,
2365 xhci->event_ring->dequeue),
2366 lower_32_bits(le64_to_cpu(event->buffer)),
2367 upper_32_bits(le64_to_cpu(event->buffer)),
2368 le32_to_cpu(event->transfer_len),
2369 le32_to_cpu(event->flags));
2370 xhci_dbg(xhci, "Event ring:\n");
2371 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2372 return -ENODEV;
2373 }
2374
2375 /* Count current td numbers if ep->skip is set */
2376 if (ep->skip) {
2377 list_for_each(tmp, &ep_ring->td_list)
2378 td_num++;
2379 }
2380
2381 event_dma = le64_to_cpu(event->buffer);
2382 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2383 /* Look for common error cases */
2384 switch (trb_comp_code) {
2385 /* Skip codes that require special handling depending on
2386 * transfer type
2387 */
2388 case COMP_SUCCESS:
2389 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2390 break;
2391 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2392 trb_comp_code = COMP_SHORT_TX;
2393 else
2394 xhci_warn(xhci, "WARN Successful completion on short TX: "
2395 "needs XHCI_TRUST_TX_LENGTH quirk?\n");
2396 case COMP_SHORT_TX:
2397 break;
2398 case COMP_STOP:
2399 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2400 break;
2401 case COMP_STOP_INVAL:
2402 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2403 break;
2404 case COMP_STALL:
2405 xhci_dbg(xhci, "Stalled endpoint\n");
2406 ep->ep_state |= EP_HALTED;
2407 status = -EPIPE;
2408 break;
2409 case COMP_TRB_ERR:
2410 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2411 status = -EILSEQ;
2412 break;
2413 case COMP_SPLIT_ERR:
2414 case COMP_TX_ERR:
2415 xhci_dbg(xhci, "Transfer error on endpoint\n");
2416 status = -EPROTO;
2417 break;
2418 case COMP_BABBLE:
2419 xhci_dbg(xhci, "Babble error on endpoint\n");
2420 status = -EOVERFLOW;
2421 break;
2422 case COMP_DB_ERR:
2423 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2424 status = -ENOSR;
2425 break;
2426 case COMP_BW_OVER:
2427 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2428 break;
2429 case COMP_BUFF_OVER:
2430 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2431 break;
2432 case COMP_UNDERRUN:
2433 /*
2434 * When the Isoch ring is empty, the xHC will generate
2435 * a Ring Overrun Event for IN Isoch endpoint or Ring
2436 * Underrun Event for OUT Isoch endpoint.
2437 */
2438 xhci_dbg(xhci, "underrun event on endpoint\n");
2439 if (!list_empty(&ep_ring->td_list))
2440 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2441 "still with TDs queued?\n",
2442 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2443 ep_index);
2444 goto cleanup;
2445 case COMP_OVERRUN:
2446 xhci_dbg(xhci, "overrun event on endpoint\n");
2447 if (!list_empty(&ep_ring->td_list))
2448 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2449 "still with TDs queued?\n",
2450 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2451 ep_index);
2452 goto cleanup;
2453 case COMP_DEV_ERR:
2454 xhci_warn(xhci, "WARN: detect an incompatible device");
2455 status = -EPROTO;
2456 break;
2457 case COMP_MISSED_INT:
2458 /*
2459 * When encounter missed service error, one or more isoc tds
2460 * may be missed by xHC.
2461 * Set skip flag of the ep_ring; Complete the missed tds as
2462 * short transfer when process the ep_ring next time.
2463 */
2464 ep->skip = true;
2465 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2466 goto cleanup;
2467 default:
2468 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2469 status = 0;
2470 break;
2471 }
2472 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2473 "busted\n");
2474 goto cleanup;
2475 }
2476
2477 do {
2478 /* This TRB should be in the TD at the head of this ring's
2479 * TD list.
2480 */
2481 if (list_empty(&ep_ring->td_list)) {
2482 /*
2483 * A stopped endpoint may generate an extra completion
2484 * event if the device was suspended. Don't print
2485 * warnings.
2486 */
2487 if (!(trb_comp_code == COMP_STOP ||
2488 trb_comp_code == COMP_STOP_INVAL)) {
2489 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2490 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2491 ep_index);
2492 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2493 (le32_to_cpu(event->flags) &
2494 TRB_TYPE_BITMASK)>>10);
2495 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2496 }
2497 if (ep->skip) {
2498 ep->skip = false;
2499 xhci_dbg(xhci, "td_list is empty while skip "
2500 "flag set. Clear skip flag.\n");
2501 }
2502 ret = 0;
2503 goto cleanup;
2504 }
2505
2506 /* We've skipped all the TDs on the ep ring when ep->skip set */
2507 if (ep->skip && td_num == 0) {
2508 ep->skip = false;
2509 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2510 "Clear skip flag.\n");
2511 ret = 0;
2512 goto cleanup;
2513 }
2514
2515 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2516 if (ep->skip)
2517 td_num--;
2518
2519 /* Is this a TRB in the currently executing TD? */
2520 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2521 td->last_trb, event_dma);
2522
2523 /*
2524 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2525 * is not in the current TD pointed by ep_ring->dequeue because
2526 * that the hardware dequeue pointer still at the previous TRB
2527 * of the current TD. The previous TRB maybe a Link TD or the
2528 * last TRB of the previous TD. The command completion handle
2529 * will take care the rest.
2530 */
2531 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2532 ret = 0;
2533 goto cleanup;
2534 }
2535
2536 if (!event_seg) {
2537 if (!ep->skip ||
2538 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2539 /* Some host controllers give a spurious
2540 * successful event after a short transfer.
2541 * Ignore it.
2542 */
2543 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2544 ep_ring->last_td_was_short) {
2545 ep_ring->last_td_was_short = false;
2546 ret = 0;
2547 goto cleanup;
2548 }
2549 /* HC is busted, give up! */
2550 xhci_err(xhci,
2551 "ERROR Transfer event TRB DMA ptr not "
2552 "part of current TD\n");
2553 return -ESHUTDOWN;
2554 }
2555
2556 ret = skip_isoc_td(xhci, td, event, ep, &status);
2557 goto cleanup;
2558 }
2559 if (trb_comp_code == COMP_SHORT_TX)
2560 ep_ring->last_td_was_short = true;
2561 else
2562 ep_ring->last_td_was_short = false;
2563
2564 if (ep->skip) {
2565 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2566 ep->skip = false;
2567 }
2568
2569 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2570 sizeof(*event_trb)];
2571 /*
2572 * No-op TRB should not trigger interrupts.
2573 * If event_trb is a no-op TRB, it means the
2574 * corresponding TD has been cancelled. Just ignore
2575 * the TD.
2576 */
2577 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2578 xhci_dbg(xhci,
2579 "event_trb is a no-op TRB. Skip it\n");
2580 goto cleanup;
2581 }
2582
2583 /* Now update the urb's actual_length and give back to
2584 * the core
2585 */
2586 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2587 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2588 &status);
2589 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2590 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2591 &status);
2592 else
2593 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2594 ep, &status);
2595
2596 cleanup:
2597 /*
2598 * Do not update event ring dequeue pointer if ep->skip is set.
2599 * Will roll back to continue process missed tds.
2600 */
2601 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2602 inc_deq(xhci, xhci->event_ring);
2603 }
2604
2605 if (ret) {
2606 urb = td->urb;
2607 urb_priv = urb->hcpriv;
2608 /* Leave the TD around for the reset endpoint function
2609 * to use(but only if it's not a control endpoint,
2610 * since we already queued the Set TR dequeue pointer
2611 * command for stalled control endpoints).
2612 */
2613 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2614 (trb_comp_code != COMP_STALL &&
2615 trb_comp_code != COMP_BABBLE))
2616 xhci_urb_free_priv(xhci, urb_priv);
2617 else
2618 kfree(urb_priv);
2619
2620 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2621 if ((urb->actual_length != urb->transfer_buffer_length &&
2622 (urb->transfer_flags &
2623 URB_SHORT_NOT_OK)) ||
2624 (status != 0 &&
2625 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2626 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2627 "expected = %x, status = %d\n",
2628 urb, urb->actual_length,
2629 urb->transfer_buffer_length,
2630 status);
2631 spin_unlock(&xhci->lock);
2632 /* EHCI, UHCI, and OHCI always unconditionally set the
2633 * urb->status of an isochronous endpoint to 0.
2634 */
2635 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2636 status = 0;
2637 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2638 spin_lock(&xhci->lock);
2639 }
2640
2641 /*
2642 * If ep->skip is set, it means there are missed tds on the
2643 * endpoint ring need to take care of.
2644 * Process them as short transfer until reach the td pointed by
2645 * the event.
2646 */
2647 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2648
2649 return 0;
2650 }
2651
2652 /*
2653 * This function handles all OS-owned events on the event ring. It may drop
2654 * xhci->lock between event processing (e.g. to pass up port status changes).
2655 * Returns >0 for "possibly more events to process" (caller should call again),
2656 * otherwise 0 if done. In future, <0 returns should indicate error code.
2657 */
xhci_handle_event(struct xhci_hcd * xhci)2658 static int xhci_handle_event(struct xhci_hcd *xhci)
2659 {
2660 union xhci_trb *event;
2661 int update_ptrs = 1;
2662 int ret;
2663
2664 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2665 xhci->error_bitmask |= 1 << 1;
2666 return 0;
2667 }
2668
2669 event = xhci->event_ring->dequeue;
2670 /* Does the HC or OS own the TRB? */
2671 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2672 xhci->event_ring->cycle_state) {
2673 xhci->error_bitmask |= 1 << 2;
2674 return 0;
2675 }
2676
2677 /*
2678 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2679 * speculative reads of the event's flags/data below.
2680 */
2681 rmb();
2682 /* FIXME: Handle more event types. */
2683 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2684 case TRB_TYPE(TRB_COMPLETION):
2685 handle_cmd_completion(xhci, &event->event_cmd);
2686 break;
2687 case TRB_TYPE(TRB_PORT_STATUS):
2688 handle_port_status(xhci, event);
2689 update_ptrs = 0;
2690 break;
2691 case TRB_TYPE(TRB_TRANSFER):
2692 ret = handle_tx_event(xhci, &event->trans_event);
2693 if (ret < 0)
2694 xhci->error_bitmask |= 1 << 9;
2695 else
2696 update_ptrs = 0;
2697 break;
2698 case TRB_TYPE(TRB_DEV_NOTE):
2699 handle_device_notification(xhci, event);
2700 break;
2701 default:
2702 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2703 TRB_TYPE(48))
2704 handle_vendor_event(xhci, event);
2705 else
2706 xhci->error_bitmask |= 1 << 3;
2707 }
2708 /* Any of the above functions may drop and re-acquire the lock, so check
2709 * to make sure a watchdog timer didn't mark the host as non-responsive.
2710 */
2711 if (xhci->xhc_state & XHCI_STATE_DYING) {
2712 xhci_dbg(xhci, "xHCI host dying, returning from "
2713 "event handler.\n");
2714 return 0;
2715 }
2716
2717 if (update_ptrs)
2718 /* Update SW event ring dequeue pointer */
2719 inc_deq(xhci, xhci->event_ring);
2720
2721 /* Are there more items on the event ring? Caller will call us again to
2722 * check.
2723 */
2724 return 1;
2725 }
2726
2727 /*
2728 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2729 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2730 * indicators of an event TRB error, but we check the status *first* to be safe.
2731 */
xhci_irq(struct usb_hcd * hcd)2732 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2733 {
2734 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2735 u32 status;
2736 union xhci_trb *trb;
2737 u64 temp_64;
2738 union xhci_trb *event_ring_deq;
2739 dma_addr_t deq;
2740
2741 spin_lock(&xhci->lock);
2742 trb = xhci->event_ring->dequeue;
2743 /* Check if the xHC generated the interrupt, or the irq is shared */
2744 status = xhci_readl(xhci, &xhci->op_regs->status);
2745 if (status == 0xffffffff)
2746 goto hw_died;
2747
2748 if (!(status & STS_EINT)) {
2749 spin_unlock(&xhci->lock);
2750 return IRQ_NONE;
2751 }
2752 if (status & STS_FATAL) {
2753 xhci_warn(xhci, "WARNING: Host System Error\n");
2754 xhci_halt(xhci);
2755 hw_died:
2756 spin_unlock(&xhci->lock);
2757 return -ESHUTDOWN;
2758 }
2759
2760 /*
2761 * Clear the op reg interrupt status first,
2762 * so we can receive interrupts from other MSI-X interrupters.
2763 * Write 1 to clear the interrupt status.
2764 */
2765 status |= STS_EINT;
2766 xhci_writel(xhci, status, &xhci->op_regs->status);
2767 /* FIXME when MSI-X is supported and there are multiple vectors */
2768 /* Clear the MSI-X event interrupt status */
2769
2770 if (hcd->irq) {
2771 u32 irq_pending;
2772 /* Acknowledge the PCI interrupt */
2773 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2774 irq_pending |= IMAN_IP;
2775 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2776 }
2777
2778 if (xhci->xhc_state & XHCI_STATE_DYING) {
2779 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2780 "Shouldn't IRQs be disabled?\n");
2781 /* Clear the event handler busy flag (RW1C);
2782 * the event ring should be empty.
2783 */
2784 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2785 xhci_write_64(xhci, temp_64 | ERST_EHB,
2786 &xhci->ir_set->erst_dequeue);
2787 spin_unlock(&xhci->lock);
2788
2789 return IRQ_HANDLED;
2790 }
2791
2792 event_ring_deq = xhci->event_ring->dequeue;
2793 /* FIXME this should be a delayed service routine
2794 * that clears the EHB.
2795 */
2796 while (xhci_handle_event(xhci) > 0) {}
2797
2798 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2799 /* If necessary, update the HW's version of the event ring deq ptr. */
2800 if (event_ring_deq != xhci->event_ring->dequeue) {
2801 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2802 xhci->event_ring->dequeue);
2803 if (deq == 0)
2804 xhci_warn(xhci, "WARN something wrong with SW event "
2805 "ring dequeue ptr.\n");
2806 /* Update HC event ring dequeue pointer */
2807 temp_64 &= ERST_PTR_MASK;
2808 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2809 }
2810
2811 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2812 temp_64 |= ERST_EHB;
2813 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2814
2815 spin_unlock(&xhci->lock);
2816
2817 return IRQ_HANDLED;
2818 }
2819
xhci_msi_irq(int irq,struct usb_hcd * hcd)2820 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2821 {
2822 return xhci_irq(hcd);
2823 }
2824
2825 /**** Endpoint Ring Operations ****/
2826
2827 /*
2828 * Generic function for queueing a TRB on a ring.
2829 * The caller must have checked to make sure there's room on the ring.
2830 *
2831 * @more_trbs_coming: Will you enqueue more TRBs before calling
2832 * prepare_transfer()?
2833 */
queue_trb(struct xhci_hcd * xhci,struct xhci_ring * ring,bool more_trbs_coming,u32 field1,u32 field2,u32 field3,u32 field4)2834 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2835 bool more_trbs_coming,
2836 u32 field1, u32 field2, u32 field3, u32 field4)
2837 {
2838 struct xhci_generic_trb *trb;
2839
2840 trb = &ring->enqueue->generic;
2841 trb->field[0] = cpu_to_le32(field1);
2842 trb->field[1] = cpu_to_le32(field2);
2843 trb->field[2] = cpu_to_le32(field3);
2844 trb->field[3] = cpu_to_le32(field4);
2845 inc_enq(xhci, ring, more_trbs_coming);
2846 }
2847
2848 /*
2849 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2850 * FIXME allocate segments if the ring is full.
2851 */
prepare_ring(struct xhci_hcd * xhci,struct xhci_ring * ep_ring,u32 ep_state,unsigned int num_trbs,gfp_t mem_flags)2852 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2853 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2854 {
2855 unsigned int num_trbs_needed;
2856
2857 /* Make sure the endpoint has been added to xHC schedule */
2858 switch (ep_state) {
2859 case EP_STATE_DISABLED:
2860 /*
2861 * USB core changed config/interfaces without notifying us,
2862 * or hardware is reporting the wrong state.
2863 */
2864 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2865 return -ENOENT;
2866 case EP_STATE_ERROR:
2867 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2868 /* FIXME event handling code for error needs to clear it */
2869 /* XXX not sure if this should be -ENOENT or not */
2870 return -EINVAL;
2871 case EP_STATE_HALTED:
2872 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2873 case EP_STATE_STOPPED:
2874 case EP_STATE_RUNNING:
2875 break;
2876 default:
2877 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2878 /*
2879 * FIXME issue Configure Endpoint command to try to get the HC
2880 * back into a known state.
2881 */
2882 return -EINVAL;
2883 }
2884
2885 while (1) {
2886 if (room_on_ring(xhci, ep_ring, num_trbs))
2887 break;
2888
2889 if (ep_ring == xhci->cmd_ring) {
2890 xhci_err(xhci, "Do not support expand command ring\n");
2891 return -ENOMEM;
2892 }
2893
2894 xhci_dbg(xhci, "ERROR no room on ep ring, "
2895 "try ring expansion\n");
2896 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2897 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2898 mem_flags)) {
2899 xhci_err(xhci, "Ring expansion failed\n");
2900 return -ENOMEM;
2901 }
2902 };
2903
2904 if (enqueue_is_link_trb(ep_ring)) {
2905 struct xhci_ring *ring = ep_ring;
2906 union xhci_trb *next;
2907
2908 next = ring->enqueue;
2909
2910 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2911 /* If we're not dealing with 0.95 hardware or isoc rings
2912 * on AMD 0.96 host, clear the chain bit.
2913 */
2914 if (!xhci_link_trb_quirk(xhci) &&
2915 !(ring->type == TYPE_ISOC &&
2916 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2917 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2918 else
2919 next->link.control |= cpu_to_le32(TRB_CHAIN);
2920
2921 wmb();
2922 next->link.control ^= cpu_to_le32(TRB_CYCLE);
2923
2924 /* Toggle the cycle bit after the last ring segment. */
2925 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2926 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2927 }
2928 ring->enq_seg = ring->enq_seg->next;
2929 ring->enqueue = ring->enq_seg->trbs;
2930 next = ring->enqueue;
2931 }
2932 }
2933
2934 return 0;
2935 }
2936
prepare_transfer(struct xhci_hcd * xhci,struct xhci_virt_device * xdev,unsigned int ep_index,unsigned int stream_id,unsigned int num_trbs,struct urb * urb,unsigned int td_index,gfp_t mem_flags)2937 static int prepare_transfer(struct xhci_hcd *xhci,
2938 struct xhci_virt_device *xdev,
2939 unsigned int ep_index,
2940 unsigned int stream_id,
2941 unsigned int num_trbs,
2942 struct urb *urb,
2943 unsigned int td_index,
2944 gfp_t mem_flags)
2945 {
2946 int ret;
2947 struct urb_priv *urb_priv;
2948 struct xhci_td *td;
2949 struct xhci_ring *ep_ring;
2950 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2951
2952 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2953 if (!ep_ring) {
2954 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2955 stream_id);
2956 return -EINVAL;
2957 }
2958
2959 ret = prepare_ring(xhci, ep_ring,
2960 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2961 num_trbs, mem_flags);
2962 if (ret)
2963 return ret;
2964
2965 urb_priv = urb->hcpriv;
2966 td = urb_priv->td[td_index];
2967
2968 INIT_LIST_HEAD(&td->td_list);
2969 INIT_LIST_HEAD(&td->cancelled_td_list);
2970
2971 if (td_index == 0) {
2972 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2973 if (unlikely(ret))
2974 return ret;
2975 }
2976
2977 td->urb = urb;
2978 /* Add this TD to the tail of the endpoint ring's TD list */
2979 list_add_tail(&td->td_list, &ep_ring->td_list);
2980 td->start_seg = ep_ring->enq_seg;
2981 td->first_trb = ep_ring->enqueue;
2982
2983 urb_priv->td[td_index] = td;
2984
2985 return 0;
2986 }
2987
count_sg_trbs_needed(struct xhci_hcd * xhci,struct urb * urb)2988 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2989 {
2990 int num_sgs, num_trbs, running_total, temp, i;
2991 struct scatterlist *sg;
2992
2993 sg = NULL;
2994 num_sgs = urb->num_mapped_sgs;
2995 temp = urb->transfer_buffer_length;
2996
2997 num_trbs = 0;
2998 for_each_sg(urb->sg, sg, num_sgs, i) {
2999 unsigned int len = sg_dma_len(sg);
3000
3001 /* Scatter gather list entries may cross 64KB boundaries */
3002 running_total = TRB_MAX_BUFF_SIZE -
3003 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
3004 running_total &= TRB_MAX_BUFF_SIZE - 1;
3005 if (running_total != 0)
3006 num_trbs++;
3007
3008 /* How many more 64KB chunks to transfer, how many more TRBs? */
3009 while (running_total < sg_dma_len(sg) && running_total < temp) {
3010 num_trbs++;
3011 running_total += TRB_MAX_BUFF_SIZE;
3012 }
3013 len = min_t(int, len, temp);
3014 temp -= len;
3015 if (temp == 0)
3016 break;
3017 }
3018 return num_trbs;
3019 }
3020
check_trb_math(struct urb * urb,int num_trbs,int running_total)3021 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
3022 {
3023 if (num_trbs != 0)
3024 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
3025 "TRBs, %d left\n", __func__,
3026 urb->ep->desc.bEndpointAddress, num_trbs);
3027 if (running_total != urb->transfer_buffer_length)
3028 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3029 "queued %#x (%d), asked for %#x (%d)\n",
3030 __func__,
3031 urb->ep->desc.bEndpointAddress,
3032 running_total, running_total,
3033 urb->transfer_buffer_length,
3034 urb->transfer_buffer_length);
3035 }
3036
giveback_first_trb(struct xhci_hcd * xhci,int slot_id,unsigned int ep_index,unsigned int stream_id,int start_cycle,struct xhci_generic_trb * start_trb)3037 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3038 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3039 struct xhci_generic_trb *start_trb)
3040 {
3041 /*
3042 * Pass all the TRBs to the hardware at once and make sure this write
3043 * isn't reordered.
3044 */
3045 wmb();
3046 if (start_cycle)
3047 start_trb->field[3] |= cpu_to_le32(start_cycle);
3048 else
3049 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3050 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3051 }
3052
3053 /*
3054 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3055 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3056 * (comprised of sg list entries) can take several service intervals to
3057 * transmit.
3058 */
xhci_queue_intr_tx(struct xhci_hcd * xhci,gfp_t mem_flags,struct urb * urb,int slot_id,unsigned int ep_index)3059 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3060 struct urb *urb, int slot_id, unsigned int ep_index)
3061 {
3062 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3063 xhci->devs[slot_id]->out_ctx, ep_index);
3064 int xhci_interval;
3065 int ep_interval;
3066
3067 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3068 ep_interval = urb->interval;
3069 /* Convert to microframes */
3070 if (urb->dev->speed == USB_SPEED_LOW ||
3071 urb->dev->speed == USB_SPEED_FULL)
3072 ep_interval *= 8;
3073 /* FIXME change this to a warning and a suggestion to use the new API
3074 * to set the polling interval (once the API is added).
3075 */
3076 if (xhci_interval != ep_interval) {
3077 if (printk_ratelimit())
3078 dev_dbg(&urb->dev->dev, "Driver uses different interval"
3079 " (%d microframe%s) than xHCI "
3080 "(%d microframe%s)\n",
3081 ep_interval,
3082 ep_interval == 1 ? "" : "s",
3083 xhci_interval,
3084 xhci_interval == 1 ? "" : "s");
3085 urb->interval = xhci_interval;
3086 /* Convert back to frames for LS/FS devices */
3087 if (urb->dev->speed == USB_SPEED_LOW ||
3088 urb->dev->speed == USB_SPEED_FULL)
3089 urb->interval /= 8;
3090 }
3091 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3092 }
3093
3094 /*
3095 * The TD size is the number of bytes remaining in the TD (including this TRB),
3096 * right shifted by 10.
3097 * It must fit in bits 21:17, so it can't be bigger than 31.
3098 */
xhci_td_remainder(unsigned int remainder)3099 static u32 xhci_td_remainder(unsigned int remainder)
3100 {
3101 u32 max = (1 << (21 - 17 + 1)) - 1;
3102
3103 if ((remainder >> 10) >= max)
3104 return max << 17;
3105 else
3106 return (remainder >> 10) << 17;
3107 }
3108
3109 /*
3110 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3111 * packets remaining in the TD (*not* including this TRB).
3112 *
3113 * Total TD packet count = total_packet_count =
3114 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3115 *
3116 * Packets transferred up to and including this TRB = packets_transferred =
3117 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3118 *
3119 * TD size = total_packet_count - packets_transferred
3120 *
3121 * It must fit in bits 21:17, so it can't be bigger than 31.
3122 * The last TRB in a TD must have the TD size set to zero.
3123 */
xhci_v1_0_td_remainder(int running_total,int trb_buff_len,unsigned int total_packet_count,struct urb * urb,unsigned int num_trbs_left)3124 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3125 unsigned int total_packet_count, struct urb *urb,
3126 unsigned int num_trbs_left)
3127 {
3128 int packets_transferred;
3129
3130 /* One TRB with a zero-length data packet. */
3131 if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3132 return 0;
3133
3134 /* All the TRB queueing functions don't count the current TRB in
3135 * running_total.
3136 */
3137 packets_transferred = (running_total + trb_buff_len) /
3138 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3139
3140 if ((total_packet_count - packets_transferred) > 31)
3141 return 31 << 17;
3142 return (total_packet_count - packets_transferred) << 17;
3143 }
3144
queue_bulk_sg_tx(struct xhci_hcd * xhci,gfp_t mem_flags,struct urb * urb,int slot_id,unsigned int ep_index)3145 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3146 struct urb *urb, int slot_id, unsigned int ep_index)
3147 {
3148 struct xhci_ring *ep_ring;
3149 unsigned int num_trbs;
3150 struct urb_priv *urb_priv;
3151 struct xhci_td *td;
3152 struct scatterlist *sg;
3153 int num_sgs;
3154 int trb_buff_len, this_sg_len, running_total;
3155 unsigned int total_packet_count;
3156 bool first_trb;
3157 u64 addr;
3158 bool more_trbs_coming;
3159
3160 struct xhci_generic_trb *start_trb;
3161 int start_cycle;
3162
3163 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3164 if (!ep_ring)
3165 return -EINVAL;
3166
3167 num_trbs = count_sg_trbs_needed(xhci, urb);
3168 num_sgs = urb->num_mapped_sgs;
3169 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3170 usb_endpoint_maxp(&urb->ep->desc));
3171
3172 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3173 ep_index, urb->stream_id,
3174 num_trbs, urb, 0, mem_flags);
3175 if (trb_buff_len < 0)
3176 return trb_buff_len;
3177
3178 urb_priv = urb->hcpriv;
3179 td = urb_priv->td[0];
3180
3181 /*
3182 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3183 * until we've finished creating all the other TRBs. The ring's cycle
3184 * state may change as we enqueue the other TRBs, so save it too.
3185 */
3186 start_trb = &ep_ring->enqueue->generic;
3187 start_cycle = ep_ring->cycle_state;
3188
3189 running_total = 0;
3190 /*
3191 * How much data is in the first TRB?
3192 *
3193 * There are three forces at work for TRB buffer pointers and lengths:
3194 * 1. We don't want to walk off the end of this sg-list entry buffer.
3195 * 2. The transfer length that the driver requested may be smaller than
3196 * the amount of memory allocated for this scatter-gather list.
3197 * 3. TRBs buffers can't cross 64KB boundaries.
3198 */
3199 sg = urb->sg;
3200 addr = (u64) sg_dma_address(sg);
3201 this_sg_len = sg_dma_len(sg);
3202 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3203 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3204 if (trb_buff_len > urb->transfer_buffer_length)
3205 trb_buff_len = urb->transfer_buffer_length;
3206
3207 first_trb = true;
3208 /* Queue the first TRB, even if it's zero-length */
3209 do {
3210 u32 field = 0;
3211 u32 length_field = 0;
3212 u32 remainder = 0;
3213
3214 /* Don't change the cycle bit of the first TRB until later */
3215 if (first_trb) {
3216 first_trb = false;
3217 if (start_cycle == 0)
3218 field |= 0x1;
3219 } else
3220 field |= ep_ring->cycle_state;
3221
3222 /* Chain all the TRBs together; clear the chain bit in the last
3223 * TRB to indicate it's the last TRB in the chain.
3224 */
3225 if (num_trbs > 1) {
3226 field |= TRB_CHAIN;
3227 } else {
3228 /* FIXME - add check for ZERO_PACKET flag before this */
3229 td->last_trb = ep_ring->enqueue;
3230 field |= TRB_IOC;
3231 }
3232
3233 /* Only set interrupt on short packet for IN endpoints */
3234 if (usb_urb_dir_in(urb))
3235 field |= TRB_ISP;
3236
3237 if (TRB_MAX_BUFF_SIZE -
3238 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3239 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3240 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3241 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3242 (unsigned int) addr + trb_buff_len);
3243 }
3244
3245 /* Set the TRB length, TD size, and interrupter fields. */
3246 if (xhci->hci_version < 0x100) {
3247 remainder = xhci_td_remainder(
3248 urb->transfer_buffer_length -
3249 running_total);
3250 } else {
3251 remainder = xhci_v1_0_td_remainder(running_total,
3252 trb_buff_len, total_packet_count, urb,
3253 num_trbs - 1);
3254 }
3255 length_field = TRB_LEN(trb_buff_len) |
3256 remainder |
3257 TRB_INTR_TARGET(0);
3258
3259 if (num_trbs > 1)
3260 more_trbs_coming = true;
3261 else
3262 more_trbs_coming = false;
3263 queue_trb(xhci, ep_ring, more_trbs_coming,
3264 lower_32_bits(addr),
3265 upper_32_bits(addr),
3266 length_field,
3267 field | TRB_TYPE(TRB_NORMAL));
3268 --num_trbs;
3269 running_total += trb_buff_len;
3270
3271 /* Calculate length for next transfer --
3272 * Are we done queueing all the TRBs for this sg entry?
3273 */
3274 this_sg_len -= trb_buff_len;
3275 if (this_sg_len == 0) {
3276 --num_sgs;
3277 if (num_sgs == 0)
3278 break;
3279 sg = sg_next(sg);
3280 addr = (u64) sg_dma_address(sg);
3281 this_sg_len = sg_dma_len(sg);
3282 } else {
3283 addr += trb_buff_len;
3284 }
3285
3286 trb_buff_len = TRB_MAX_BUFF_SIZE -
3287 (addr & (TRB_MAX_BUFF_SIZE - 1));
3288 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3289 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3290 trb_buff_len =
3291 urb->transfer_buffer_length - running_total;
3292 } while (running_total < urb->transfer_buffer_length);
3293
3294 check_trb_math(urb, num_trbs, running_total);
3295 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3296 start_cycle, start_trb);
3297 return 0;
3298 }
3299
3300 /* This is very similar to what ehci-q.c qtd_fill() does */
xhci_queue_bulk_tx(struct xhci_hcd * xhci,gfp_t mem_flags,struct urb * urb,int slot_id,unsigned int ep_index)3301 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3302 struct urb *urb, int slot_id, unsigned int ep_index)
3303 {
3304 struct xhci_ring *ep_ring;
3305 struct urb_priv *urb_priv;
3306 struct xhci_td *td;
3307 int num_trbs;
3308 struct xhci_generic_trb *start_trb;
3309 bool first_trb;
3310 bool more_trbs_coming;
3311 int start_cycle;
3312 u32 field, length_field;
3313
3314 int running_total, trb_buff_len, ret;
3315 unsigned int total_packet_count;
3316 u64 addr;
3317
3318 if (urb->num_sgs)
3319 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3320
3321 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3322 if (!ep_ring)
3323 return -EINVAL;
3324
3325 num_trbs = 0;
3326 /* How much data is (potentially) left before the 64KB boundary? */
3327 running_total = TRB_MAX_BUFF_SIZE -
3328 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3329 running_total &= TRB_MAX_BUFF_SIZE - 1;
3330
3331 /* If there's some data on this 64KB chunk, or we have to send a
3332 * zero-length transfer, we need at least one TRB
3333 */
3334 if (running_total != 0 || urb->transfer_buffer_length == 0)
3335 num_trbs++;
3336 /* How many more 64KB chunks to transfer, how many more TRBs? */
3337 while (running_total < urb->transfer_buffer_length) {
3338 num_trbs++;
3339 running_total += TRB_MAX_BUFF_SIZE;
3340 }
3341 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3342
3343 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3344 ep_index, urb->stream_id,
3345 num_trbs, urb, 0, mem_flags);
3346 if (ret < 0)
3347 return ret;
3348
3349 urb_priv = urb->hcpriv;
3350 td = urb_priv->td[0];
3351
3352 /*
3353 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3354 * until we've finished creating all the other TRBs. The ring's cycle
3355 * state may change as we enqueue the other TRBs, so save it too.
3356 */
3357 start_trb = &ep_ring->enqueue->generic;
3358 start_cycle = ep_ring->cycle_state;
3359
3360 running_total = 0;
3361 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3362 usb_endpoint_maxp(&urb->ep->desc));
3363 /* How much data is in the first TRB? */
3364 addr = (u64) urb->transfer_dma;
3365 trb_buff_len = TRB_MAX_BUFF_SIZE -
3366 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3367 if (trb_buff_len > urb->transfer_buffer_length)
3368 trb_buff_len = urb->transfer_buffer_length;
3369
3370 first_trb = true;
3371
3372 /* Queue the first TRB, even if it's zero-length */
3373 do {
3374 u32 remainder = 0;
3375 field = 0;
3376
3377 /* Don't change the cycle bit of the first TRB until later */
3378 if (first_trb) {
3379 first_trb = false;
3380 if (start_cycle == 0)
3381 field |= 0x1;
3382 } else
3383 field |= ep_ring->cycle_state;
3384
3385 /* Chain all the TRBs together; clear the chain bit in the last
3386 * TRB to indicate it's the last TRB in the chain.
3387 */
3388 if (num_trbs > 1) {
3389 field |= TRB_CHAIN;
3390 } else {
3391 /* FIXME - add check for ZERO_PACKET flag before this */
3392 td->last_trb = ep_ring->enqueue;
3393 field |= TRB_IOC;
3394 }
3395
3396 /* Only set interrupt on short packet for IN endpoints */
3397 if (usb_urb_dir_in(urb))
3398 field |= TRB_ISP;
3399
3400 /* Set the TRB length, TD size, and interrupter fields. */
3401 if (xhci->hci_version < 0x100) {
3402 remainder = xhci_td_remainder(
3403 urb->transfer_buffer_length -
3404 running_total);
3405 } else {
3406 remainder = xhci_v1_0_td_remainder(running_total,
3407 trb_buff_len, total_packet_count, urb,
3408 num_trbs - 1);
3409 }
3410 length_field = TRB_LEN(trb_buff_len) |
3411 remainder |
3412 TRB_INTR_TARGET(0);
3413
3414 if (num_trbs > 1)
3415 more_trbs_coming = true;
3416 else
3417 more_trbs_coming = false;
3418 queue_trb(xhci, ep_ring, more_trbs_coming,
3419 lower_32_bits(addr),
3420 upper_32_bits(addr),
3421 length_field,
3422 field | TRB_TYPE(TRB_NORMAL));
3423 --num_trbs;
3424 running_total += trb_buff_len;
3425
3426 /* Calculate length for next transfer */
3427 addr += trb_buff_len;
3428 trb_buff_len = urb->transfer_buffer_length - running_total;
3429 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3430 trb_buff_len = TRB_MAX_BUFF_SIZE;
3431 } while (running_total < urb->transfer_buffer_length);
3432
3433 check_trb_math(urb, num_trbs, running_total);
3434 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3435 start_cycle, start_trb);
3436 return 0;
3437 }
3438
3439 /* Caller must have locked xhci->lock */
xhci_queue_ctrl_tx(struct xhci_hcd * xhci,gfp_t mem_flags,struct urb * urb,int slot_id,unsigned int ep_index)3440 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3441 struct urb *urb, int slot_id, unsigned int ep_index)
3442 {
3443 struct xhci_ring *ep_ring;
3444 int num_trbs;
3445 int ret;
3446 struct usb_ctrlrequest *setup;
3447 struct xhci_generic_trb *start_trb;
3448 int start_cycle;
3449 u32 field, length_field;
3450 struct urb_priv *urb_priv;
3451 struct xhci_td *td;
3452
3453 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3454 if (!ep_ring)
3455 return -EINVAL;
3456
3457 /*
3458 * Need to copy setup packet into setup TRB, so we can't use the setup
3459 * DMA address.
3460 */
3461 if (!urb->setup_packet)
3462 return -EINVAL;
3463
3464 /* 1 TRB for setup, 1 for status */
3465 num_trbs = 2;
3466 /*
3467 * Don't need to check if we need additional event data and normal TRBs,
3468 * since data in control transfers will never get bigger than 16MB
3469 * XXX: can we get a buffer that crosses 64KB boundaries?
3470 */
3471 if (urb->transfer_buffer_length > 0)
3472 num_trbs++;
3473 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3474 ep_index, urb->stream_id,
3475 num_trbs, urb, 0, mem_flags);
3476 if (ret < 0)
3477 return ret;
3478
3479 urb_priv = urb->hcpriv;
3480 td = urb_priv->td[0];
3481
3482 /*
3483 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3484 * until we've finished creating all the other TRBs. The ring's cycle
3485 * state may change as we enqueue the other TRBs, so save it too.
3486 */
3487 start_trb = &ep_ring->enqueue->generic;
3488 start_cycle = ep_ring->cycle_state;
3489
3490 /* Queue setup TRB - see section 6.4.1.2.1 */
3491 /* FIXME better way to translate setup_packet into two u32 fields? */
3492 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3493 field = 0;
3494 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3495 if (start_cycle == 0)
3496 field |= 0x1;
3497
3498 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3499 if (xhci->hci_version == 0x100) {
3500 if (urb->transfer_buffer_length > 0) {
3501 if (setup->bRequestType & USB_DIR_IN)
3502 field |= TRB_TX_TYPE(TRB_DATA_IN);
3503 else
3504 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3505 }
3506 }
3507
3508 queue_trb(xhci, ep_ring, true,
3509 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3510 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3511 TRB_LEN(8) | TRB_INTR_TARGET(0),
3512 /* Immediate data in pointer */
3513 field);
3514
3515 /* If there's data, queue data TRBs */
3516 /* Only set interrupt on short packet for IN endpoints */
3517 if (usb_urb_dir_in(urb))
3518 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3519 else
3520 field = TRB_TYPE(TRB_DATA);
3521
3522 length_field = TRB_LEN(urb->transfer_buffer_length) |
3523 xhci_td_remainder(urb->transfer_buffer_length) |
3524 TRB_INTR_TARGET(0);
3525 if (urb->transfer_buffer_length > 0) {
3526 if (setup->bRequestType & USB_DIR_IN)
3527 field |= TRB_DIR_IN;
3528 queue_trb(xhci, ep_ring, true,
3529 lower_32_bits(urb->transfer_dma),
3530 upper_32_bits(urb->transfer_dma),
3531 length_field,
3532 field | ep_ring->cycle_state);
3533 }
3534
3535 /* Save the DMA address of the last TRB in the TD */
3536 td->last_trb = ep_ring->enqueue;
3537
3538 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3539 /* If the device sent data, the status stage is an OUT transfer */
3540 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3541 field = 0;
3542 else
3543 field = TRB_DIR_IN;
3544 queue_trb(xhci, ep_ring, false,
3545 0,
3546 0,
3547 TRB_INTR_TARGET(0),
3548 /* Event on completion */
3549 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3550
3551 giveback_first_trb(xhci, slot_id, ep_index, 0,
3552 start_cycle, start_trb);
3553 return 0;
3554 }
3555
count_isoc_trbs_needed(struct xhci_hcd * xhci,struct urb * urb,int i)3556 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3557 struct urb *urb, int i)
3558 {
3559 int num_trbs = 0;
3560 u64 addr, td_len;
3561
3562 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3563 td_len = urb->iso_frame_desc[i].length;
3564
3565 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3566 TRB_MAX_BUFF_SIZE);
3567 if (num_trbs == 0)
3568 num_trbs++;
3569
3570 return num_trbs;
3571 }
3572
3573 /*
3574 * The transfer burst count field of the isochronous TRB defines the number of
3575 * bursts that are required to move all packets in this TD. Only SuperSpeed
3576 * devices can burst up to bMaxBurst number of packets per service interval.
3577 * This field is zero based, meaning a value of zero in the field means one
3578 * burst. Basically, for everything but SuperSpeed devices, this field will be
3579 * zero. Only xHCI 1.0 host controllers support this field.
3580 */
xhci_get_burst_count(struct xhci_hcd * xhci,struct usb_device * udev,struct urb * urb,unsigned int total_packet_count)3581 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3582 struct usb_device *udev,
3583 struct urb *urb, unsigned int total_packet_count)
3584 {
3585 unsigned int max_burst;
3586
3587 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3588 return 0;
3589
3590 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3591 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3592 }
3593
3594 /*
3595 * Returns the number of packets in the last "burst" of packets. This field is
3596 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3597 * the last burst packet count is equal to the total number of packets in the
3598 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3599 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3600 * contain 1 to (bMaxBurst + 1) packets.
3601 */
xhci_get_last_burst_packet_count(struct xhci_hcd * xhci,struct usb_device * udev,struct urb * urb,unsigned int total_packet_count)3602 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3603 struct usb_device *udev,
3604 struct urb *urb, unsigned int total_packet_count)
3605 {
3606 unsigned int max_burst;
3607 unsigned int residue;
3608
3609 if (xhci->hci_version < 0x100)
3610 return 0;
3611
3612 switch (udev->speed) {
3613 case USB_SPEED_SUPER:
3614 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3615 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3616 residue = total_packet_count % (max_burst + 1);
3617 /* If residue is zero, the last burst contains (max_burst + 1)
3618 * number of packets, but the TLBPC field is zero-based.
3619 */
3620 if (residue == 0)
3621 return max_burst;
3622 return residue - 1;
3623 default:
3624 if (total_packet_count == 0)
3625 return 0;
3626 return total_packet_count - 1;
3627 }
3628 }
3629
3630 /* This is for isoc transfer */
xhci_queue_isoc_tx(struct xhci_hcd * xhci,gfp_t mem_flags,struct urb * urb,int slot_id,unsigned int ep_index)3631 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3632 struct urb *urb, int slot_id, unsigned int ep_index)
3633 {
3634 struct xhci_ring *ep_ring;
3635 struct urb_priv *urb_priv;
3636 struct xhci_td *td;
3637 int num_tds, trbs_per_td;
3638 struct xhci_generic_trb *start_trb;
3639 bool first_trb;
3640 int start_cycle;
3641 u32 field, length_field;
3642 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3643 u64 start_addr, addr;
3644 int i, j;
3645 bool more_trbs_coming;
3646
3647 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3648
3649 num_tds = urb->number_of_packets;
3650 if (num_tds < 1) {
3651 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3652 return -EINVAL;
3653 }
3654
3655 start_addr = (u64) urb->transfer_dma;
3656 start_trb = &ep_ring->enqueue->generic;
3657 start_cycle = ep_ring->cycle_state;
3658
3659 urb_priv = urb->hcpriv;
3660 /* Queue the first TRB, even if it's zero-length */
3661 for (i = 0; i < num_tds; i++) {
3662 unsigned int total_packet_count;
3663 unsigned int burst_count;
3664 unsigned int residue;
3665
3666 first_trb = true;
3667 running_total = 0;
3668 addr = start_addr + urb->iso_frame_desc[i].offset;
3669 td_len = urb->iso_frame_desc[i].length;
3670 td_remain_len = td_len;
3671 total_packet_count = DIV_ROUND_UP(td_len,
3672 GET_MAX_PACKET(
3673 usb_endpoint_maxp(&urb->ep->desc)));
3674 /* A zero-length transfer still involves at least one packet. */
3675 if (total_packet_count == 0)
3676 total_packet_count++;
3677 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3678 total_packet_count);
3679 residue = xhci_get_last_burst_packet_count(xhci,
3680 urb->dev, urb, total_packet_count);
3681
3682 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3683
3684 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3685 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3686 if (ret < 0) {
3687 if (i == 0)
3688 return ret;
3689 goto cleanup;
3690 }
3691
3692 td = urb_priv->td[i];
3693 for (j = 0; j < trbs_per_td; j++) {
3694 u32 remainder = 0;
3695 field = 0;
3696
3697 if (first_trb) {
3698 field = TRB_TBC(burst_count) |
3699 TRB_TLBPC(residue);
3700 /* Queue the isoc TRB */
3701 field |= TRB_TYPE(TRB_ISOC);
3702 /* Assume URB_ISO_ASAP is set */
3703 field |= TRB_SIA;
3704 if (i == 0) {
3705 if (start_cycle == 0)
3706 field |= 0x1;
3707 } else
3708 field |= ep_ring->cycle_state;
3709 first_trb = false;
3710 } else {
3711 /* Queue other normal TRBs */
3712 field |= TRB_TYPE(TRB_NORMAL);
3713 field |= ep_ring->cycle_state;
3714 }
3715
3716 /* Only set interrupt on short packet for IN EPs */
3717 if (usb_urb_dir_in(urb))
3718 field |= TRB_ISP;
3719
3720 /* Chain all the TRBs together; clear the chain bit in
3721 * the last TRB to indicate it's the last TRB in the
3722 * chain.
3723 */
3724 if (j < trbs_per_td - 1) {
3725 field |= TRB_CHAIN;
3726 more_trbs_coming = true;
3727 } else {
3728 td->last_trb = ep_ring->enqueue;
3729 field |= TRB_IOC;
3730 if (xhci->hci_version == 0x100 &&
3731 !(xhci->quirks &
3732 XHCI_AVOID_BEI)) {
3733 /* Set BEI bit except for the last td */
3734 if (i < num_tds - 1)
3735 field |= TRB_BEI;
3736 }
3737 more_trbs_coming = false;
3738 }
3739
3740 /* Calculate TRB length */
3741 trb_buff_len = TRB_MAX_BUFF_SIZE -
3742 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3743 if (trb_buff_len > td_remain_len)
3744 trb_buff_len = td_remain_len;
3745
3746 /* Set the TRB length, TD size, & interrupter fields. */
3747 if (xhci->hci_version < 0x100) {
3748 remainder = xhci_td_remainder(
3749 td_len - running_total);
3750 } else {
3751 remainder = xhci_v1_0_td_remainder(
3752 running_total, trb_buff_len,
3753 total_packet_count, urb,
3754 (trbs_per_td - j - 1));
3755 }
3756 length_field = TRB_LEN(trb_buff_len) |
3757 remainder |
3758 TRB_INTR_TARGET(0);
3759
3760 queue_trb(xhci, ep_ring, more_trbs_coming,
3761 lower_32_bits(addr),
3762 upper_32_bits(addr),
3763 length_field,
3764 field);
3765 running_total += trb_buff_len;
3766
3767 addr += trb_buff_len;
3768 td_remain_len -= trb_buff_len;
3769 }
3770
3771 /* Check TD length */
3772 if (running_total != td_len) {
3773 xhci_err(xhci, "ISOC TD length unmatch\n");
3774 ret = -EINVAL;
3775 goto cleanup;
3776 }
3777 }
3778
3779 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3780 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3781 usb_amd_quirk_pll_disable();
3782 }
3783 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3784
3785 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3786 start_cycle, start_trb);
3787 return 0;
3788 cleanup:
3789 /* Clean up a partially enqueued isoc transfer. */
3790
3791 for (i--; i >= 0; i--)
3792 list_del_init(&urb_priv->td[i]->td_list);
3793
3794 /* Use the first TD as a temporary variable to turn the TDs we've queued
3795 * into No-ops with a software-owned cycle bit. That way the hardware
3796 * won't accidentally start executing bogus TDs when we partially
3797 * overwrite them. td->first_trb and td->start_seg are already set.
3798 */
3799 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3800 /* Every TRB except the first & last will have its cycle bit flipped. */
3801 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3802
3803 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3804 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3805 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3806 ep_ring->cycle_state = start_cycle;
3807 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3808 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3809 return ret;
3810 }
3811
3812 /*
3813 * Check transfer ring to guarantee there is enough room for the urb.
3814 * Update ISO URB start_frame and interval.
3815 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3816 * update the urb->start_frame by now.
3817 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3818 */
xhci_queue_isoc_tx_prepare(struct xhci_hcd * xhci,gfp_t mem_flags,struct urb * urb,int slot_id,unsigned int ep_index)3819 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3820 struct urb *urb, int slot_id, unsigned int ep_index)
3821 {
3822 struct xhci_virt_device *xdev;
3823 struct xhci_ring *ep_ring;
3824 struct xhci_ep_ctx *ep_ctx;
3825 int start_frame;
3826 int xhci_interval;
3827 int ep_interval;
3828 int num_tds, num_trbs, i;
3829 int ret;
3830
3831 xdev = xhci->devs[slot_id];
3832 ep_ring = xdev->eps[ep_index].ring;
3833 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3834
3835 num_trbs = 0;
3836 num_tds = urb->number_of_packets;
3837 for (i = 0; i < num_tds; i++)
3838 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3839
3840 /* Check the ring to guarantee there is enough room for the whole urb.
3841 * Do not insert any td of the urb to the ring if the check failed.
3842 */
3843 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3844 num_trbs, mem_flags);
3845 if (ret)
3846 return ret;
3847
3848 start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3849 start_frame &= 0x3fff;
3850
3851 urb->start_frame = start_frame;
3852 if (urb->dev->speed == USB_SPEED_LOW ||
3853 urb->dev->speed == USB_SPEED_FULL)
3854 urb->start_frame >>= 3;
3855
3856 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3857 ep_interval = urb->interval;
3858 /* Convert to microframes */
3859 if (urb->dev->speed == USB_SPEED_LOW ||
3860 urb->dev->speed == USB_SPEED_FULL)
3861 ep_interval *= 8;
3862 /* FIXME change this to a warning and a suggestion to use the new API
3863 * to set the polling interval (once the API is added).
3864 */
3865 if (xhci_interval != ep_interval) {
3866 if (printk_ratelimit())
3867 dev_dbg(&urb->dev->dev, "Driver uses different interval"
3868 " (%d microframe%s) than xHCI "
3869 "(%d microframe%s)\n",
3870 ep_interval,
3871 ep_interval == 1 ? "" : "s",
3872 xhci_interval,
3873 xhci_interval == 1 ? "" : "s");
3874 urb->interval = xhci_interval;
3875 /* Convert back to frames for LS/FS devices */
3876 if (urb->dev->speed == USB_SPEED_LOW ||
3877 urb->dev->speed == USB_SPEED_FULL)
3878 urb->interval /= 8;
3879 }
3880 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3881
3882 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3883 }
3884
3885 /**** Command Ring Operations ****/
3886
3887 /* Generic function for queueing a command TRB on the command ring.
3888 * Check to make sure there's room on the command ring for one command TRB.
3889 * Also check that there's room reserved for commands that must not fail.
3890 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3891 * then only check for the number of reserved spots.
3892 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3893 * because the command event handler may want to resubmit a failed command.
3894 */
queue_command(struct xhci_hcd * xhci,u32 field1,u32 field2,u32 field3,u32 field4,bool command_must_succeed)3895 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3896 u32 field3, u32 field4, bool command_must_succeed)
3897 {
3898 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3899 int ret;
3900
3901 if (!command_must_succeed)
3902 reserved_trbs++;
3903
3904 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3905 reserved_trbs, GFP_ATOMIC);
3906 if (ret < 0) {
3907 xhci_err(xhci, "ERR: No room for command on command ring\n");
3908 if (command_must_succeed)
3909 xhci_err(xhci, "ERR: Reserved TRB counting for "
3910 "unfailable commands failed.\n");
3911 return ret;
3912 }
3913 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3914 field4 | xhci->cmd_ring->cycle_state);
3915 return 0;
3916 }
3917
3918 /* Queue a slot enable or disable request on the command ring */
xhci_queue_slot_control(struct xhci_hcd * xhci,u32 trb_type,u32 slot_id)3919 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3920 {
3921 return queue_command(xhci, 0, 0, 0,
3922 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3923 }
3924
3925 /* Queue an address device command TRB */
xhci_queue_address_device(struct xhci_hcd * xhci,dma_addr_t in_ctx_ptr,u32 slot_id)3926 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3927 u32 slot_id)
3928 {
3929 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3930 upper_32_bits(in_ctx_ptr), 0,
3931 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3932 false);
3933 }
3934
xhci_queue_vendor_command(struct xhci_hcd * xhci,u32 field1,u32 field2,u32 field3,u32 field4)3935 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3936 u32 field1, u32 field2, u32 field3, u32 field4)
3937 {
3938 return queue_command(xhci, field1, field2, field3, field4, false);
3939 }
3940
3941 /* Queue a reset device command TRB */
xhci_queue_reset_device(struct xhci_hcd * xhci,u32 slot_id)3942 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3943 {
3944 return queue_command(xhci, 0, 0, 0,
3945 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3946 false);
3947 }
3948
3949 /* Queue a configure endpoint command TRB */
xhci_queue_configure_endpoint(struct xhci_hcd * xhci,dma_addr_t in_ctx_ptr,u32 slot_id,bool command_must_succeed)3950 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3951 u32 slot_id, bool command_must_succeed)
3952 {
3953 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3954 upper_32_bits(in_ctx_ptr), 0,
3955 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3956 command_must_succeed);
3957 }
3958
3959 /* Queue an evaluate context command TRB */
xhci_queue_evaluate_context(struct xhci_hcd * xhci,dma_addr_t in_ctx_ptr,u32 slot_id)3960 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3961 u32 slot_id)
3962 {
3963 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3964 upper_32_bits(in_ctx_ptr), 0,
3965 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3966 false);
3967 }
3968
3969 /*
3970 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3971 * activity on an endpoint that is about to be suspended.
3972 */
xhci_queue_stop_endpoint(struct xhci_hcd * xhci,int slot_id,unsigned int ep_index,int suspend)3973 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3974 unsigned int ep_index, int suspend)
3975 {
3976 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3977 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3978 u32 type = TRB_TYPE(TRB_STOP_RING);
3979 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3980
3981 return queue_command(xhci, 0, 0, 0,
3982 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3983 }
3984
3985 /* Set Transfer Ring Dequeue Pointer command.
3986 * This should not be used for endpoints that have streams enabled.
3987 */
queue_set_tr_deq(struct xhci_hcd * xhci,int slot_id,unsigned int ep_index,unsigned int stream_id,struct xhci_segment * deq_seg,union xhci_trb * deq_ptr,u32 cycle_state)3988 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3989 unsigned int ep_index, unsigned int stream_id,
3990 struct xhci_segment *deq_seg,
3991 union xhci_trb *deq_ptr, u32 cycle_state)
3992 {
3993 dma_addr_t addr;
3994 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3995 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3996 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3997 u32 type = TRB_TYPE(TRB_SET_DEQ);
3998 struct xhci_virt_ep *ep;
3999
4000 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
4001 if (addr == 0) {
4002 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4003 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4004 deq_seg, deq_ptr);
4005 return 0;
4006 }
4007 ep = &xhci->devs[slot_id]->eps[ep_index];
4008 if ((ep->ep_state & SET_DEQ_PENDING)) {
4009 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4010 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4011 return 0;
4012 }
4013 ep->queued_deq_seg = deq_seg;
4014 ep->queued_deq_ptr = deq_ptr;
4015 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
4016 upper_32_bits(addr), trb_stream_id,
4017 trb_slot_id | trb_ep_index | type, false);
4018 }
4019
xhci_queue_reset_ep(struct xhci_hcd * xhci,int slot_id,unsigned int ep_index)4020 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
4021 unsigned int ep_index)
4022 {
4023 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4024 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4025 u32 type = TRB_TYPE(TRB_RESET_EP);
4026
4027 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
4028 false);
4029 }
4030