1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2009-2012 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 /* Macros to deal with bit fields. Each bit field must have 3 #defines 22 * associated with it (_SHIFT, _MASK, and _WORD). 23 * EG. For a bit field that is in the 7th bit of the "field4" field of a 24 * structure and is 2 bits in size the following #defines must exist: 25 * struct temp { 26 * uint32_t field1; 27 * uint32_t field2; 28 * uint32_t field3; 29 * uint32_t field4; 30 * #define example_bit_field_SHIFT 7 31 * #define example_bit_field_MASK 0x03 32 * #define example_bit_field_WORD field4 33 * uint32_t field5; 34 * }; 35 * Then the macros below may be used to get or set the value of that field. 36 * EG. To get the value of the bit field from the above example: 37 * struct temp t1; 38 * value = bf_get(example_bit_field, &t1); 39 * And then to set that bit field: 40 * bf_set(example_bit_field, &t1, 2); 41 * Or clear that bit field: 42 * bf_set(example_bit_field, &t1, 0); 43 */ 44 #define bf_get_be32(name, ptr) \ 45 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 46 #define bf_get_le32(name, ptr) \ 47 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 48 #define bf_get(name, ptr) \ 49 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 50 #define bf_set_le32(name, ptr, value) \ 51 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 52 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 53 ~(name##_MASK << name##_SHIFT))))) 54 #define bf_set(name, ptr, value) \ 55 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 56 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 57 58 struct dma_address { 59 uint32_t addr_lo; 60 uint32_t addr_hi; 61 }; 62 63 struct lpfc_sli_intf { 64 uint32_t word0; 65 #define lpfc_sli_intf_valid_SHIFT 29 66 #define lpfc_sli_intf_valid_MASK 0x00000007 67 #define lpfc_sli_intf_valid_WORD word0 68 #define LPFC_SLI_INTF_VALID 6 69 #define lpfc_sli_intf_sli_hint2_SHIFT 24 70 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 71 #define lpfc_sli_intf_sli_hint2_WORD word0 72 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0 73 #define lpfc_sli_intf_sli_hint1_SHIFT 16 74 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 75 #define lpfc_sli_intf_sli_hint1_WORD word0 76 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0 77 #define LPFC_SLI_INTF_SLI_HINT1_1 1 78 #define LPFC_SLI_INTF_SLI_HINT1_2 2 79 #define lpfc_sli_intf_if_type_SHIFT 12 80 #define lpfc_sli_intf_if_type_MASK 0x0000000F 81 #define lpfc_sli_intf_if_type_WORD word0 82 #define LPFC_SLI_INTF_IF_TYPE_0 0 83 #define LPFC_SLI_INTF_IF_TYPE_1 1 84 #define LPFC_SLI_INTF_IF_TYPE_2 2 85 #define lpfc_sli_intf_sli_family_SHIFT 8 86 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 87 #define lpfc_sli_intf_sli_family_WORD word0 88 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 89 #define LPFC_SLI_INTF_FAMILY_BE3 0x1 90 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 91 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 92 #define lpfc_sli_intf_slirev_SHIFT 4 93 #define lpfc_sli_intf_slirev_MASK 0x0000000F 94 #define lpfc_sli_intf_slirev_WORD word0 95 #define LPFC_SLI_INTF_REV_SLI3 3 96 #define LPFC_SLI_INTF_REV_SLI4 4 97 #define lpfc_sli_intf_func_type_SHIFT 0 98 #define lpfc_sli_intf_func_type_MASK 0x00000001 99 #define lpfc_sli_intf_func_type_WORD word0 100 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 101 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 102 }; 103 104 #define LPFC_SLI4_MBX_EMBED true 105 #define LPFC_SLI4_MBX_NEMBED false 106 107 #define LPFC_SLI4_MB_WORD_COUNT 64 108 #define LPFC_MAX_MQ_PAGE 8 109 #define LPFC_MAX_WQ_PAGE 8 110 #define LPFC_MAX_CQ_PAGE 4 111 #define LPFC_MAX_EQ_PAGE 8 112 113 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 114 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 115 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 116 117 /* Define SLI4 Alignment requirements. */ 118 #define LPFC_ALIGN_16_BYTE 16 119 #define LPFC_ALIGN_64_BYTE 64 120 121 /* Define SLI4 specific definitions. */ 122 #define LPFC_MQ_CQE_BYTE_OFFSET 256 123 #define LPFC_MBX_CMD_HDR_LENGTH 16 124 #define LPFC_MBX_ERROR_RANGE 0x4000 125 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 126 #define LPFC_BMBX_BIT1_ADDR_LO 0 127 #define LPFC_RPI_HDR_COUNT 64 128 #define LPFC_HDR_TEMPLATE_SIZE 4096 129 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 130 #define LPFC_FCF_RECORD_WD_CNT 132 131 #define LPFC_ENTIRE_FCF_DATABASE 0 132 #define LPFC_DFLT_FCF_INDEX 0 133 134 /* Virtual function numbers */ 135 #define LPFC_VF0 0 136 #define LPFC_VF1 1 137 #define LPFC_VF2 2 138 #define LPFC_VF3 3 139 #define LPFC_VF4 4 140 #define LPFC_VF5 5 141 #define LPFC_VF6 6 142 #define LPFC_VF7 7 143 #define LPFC_VF8 8 144 #define LPFC_VF9 9 145 #define LPFC_VF10 10 146 #define LPFC_VF11 11 147 #define LPFC_VF12 12 148 #define LPFC_VF13 13 149 #define LPFC_VF14 14 150 #define LPFC_VF15 15 151 #define LPFC_VF16 16 152 #define LPFC_VF17 17 153 #define LPFC_VF18 18 154 #define LPFC_VF19 19 155 #define LPFC_VF20 20 156 #define LPFC_VF21 21 157 #define LPFC_VF22 22 158 #define LPFC_VF23 23 159 #define LPFC_VF24 24 160 #define LPFC_VF25 25 161 #define LPFC_VF26 26 162 #define LPFC_VF27 27 163 #define LPFC_VF28 28 164 #define LPFC_VF29 29 165 #define LPFC_VF30 30 166 #define LPFC_VF31 31 167 168 /* PCI function numbers */ 169 #define LPFC_PCI_FUNC0 0 170 #define LPFC_PCI_FUNC1 1 171 #define LPFC_PCI_FUNC2 2 172 #define LPFC_PCI_FUNC3 3 173 #define LPFC_PCI_FUNC4 4 174 175 /* SLI4 interface type-2 PDEV_CTL register */ 176 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414 177 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001 178 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002 179 #define LPFC_CTL_PDEV_CTL_DD 0x00000004 180 #define LPFC_CTL_PDEV_CTL_LC 0x00000008 181 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 182 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 183 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 184 185 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 186 187 /* Active interrupt test count */ 188 #define LPFC_ACT_INTR_CNT 4 189 190 /* Delay Multiplier constant */ 191 #define LPFC_DMULT_CONST 651042 192 #define LPFC_MIM_IMAX 636 193 #define LPFC_FP_DEF_IMAX 10000 194 #define LPFC_SP_DEF_IMAX 10000 195 196 /* PORT_CAPABILITIES constants. */ 197 #define LPFC_MAX_SUPPORTED_PAGES 8 198 199 struct ulp_bde64 { 200 union ULP_BDE_TUS { 201 uint32_t w; 202 struct { 203 #ifdef __BIG_ENDIAN_BITFIELD 204 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 205 VALUE !! */ 206 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 207 #else /* __LITTLE_ENDIAN_BITFIELD */ 208 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 209 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 210 VALUE !! */ 211 #endif 212 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 213 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 214 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 215 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 216 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 217 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 218 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 219 } f; 220 } tus; 221 uint32_t addrLow; 222 uint32_t addrHigh; 223 }; 224 225 struct lpfc_sli4_flags { 226 uint32_t word0; 227 #define lpfc_idx_rsrc_rdy_SHIFT 0 228 #define lpfc_idx_rsrc_rdy_MASK 0x00000001 229 #define lpfc_idx_rsrc_rdy_WORD word0 230 #define LPFC_IDX_RSRC_RDY 1 231 #define lpfc_xri_rsrc_rdy_SHIFT 1 232 #define lpfc_xri_rsrc_rdy_MASK 0x00000001 233 #define lpfc_xri_rsrc_rdy_WORD word0 234 #define LPFC_XRI_RSRC_RDY 1 235 #define lpfc_rpi_rsrc_rdy_SHIFT 2 236 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001 237 #define lpfc_rpi_rsrc_rdy_WORD word0 238 #define LPFC_RPI_RSRC_RDY 1 239 #define lpfc_vpi_rsrc_rdy_SHIFT 3 240 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001 241 #define lpfc_vpi_rsrc_rdy_WORD word0 242 #define LPFC_VPI_RSRC_RDY 1 243 #define lpfc_vfi_rsrc_rdy_SHIFT 4 244 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001 245 #define lpfc_vfi_rsrc_rdy_WORD word0 246 #define LPFC_VFI_RSRC_RDY 1 247 }; 248 249 struct sli4_bls_rsp { 250 uint32_t word0_rsvd; /* Word0 must be reserved */ 251 uint32_t word1; 252 #define lpfc_abts_orig_SHIFT 0 253 #define lpfc_abts_orig_MASK 0x00000001 254 #define lpfc_abts_orig_WORD word1 255 #define LPFC_ABTS_UNSOL_RSP 1 256 #define LPFC_ABTS_UNSOL_INT 0 257 uint32_t word2; 258 #define lpfc_abts_rxid_SHIFT 0 259 #define lpfc_abts_rxid_MASK 0x0000FFFF 260 #define lpfc_abts_rxid_WORD word2 261 #define lpfc_abts_oxid_SHIFT 16 262 #define lpfc_abts_oxid_MASK 0x0000FFFF 263 #define lpfc_abts_oxid_WORD word2 264 uint32_t word3; 265 #define lpfc_vndr_code_SHIFT 0 266 #define lpfc_vndr_code_MASK 0x000000FF 267 #define lpfc_vndr_code_WORD word3 268 #define lpfc_rsn_expln_SHIFT 8 269 #define lpfc_rsn_expln_MASK 0x000000FF 270 #define lpfc_rsn_expln_WORD word3 271 #define lpfc_rsn_code_SHIFT 16 272 #define lpfc_rsn_code_MASK 0x000000FF 273 #define lpfc_rsn_code_WORD word3 274 275 uint32_t word4; 276 uint32_t word5_rsvd; /* Word5 must be reserved */ 277 }; 278 279 /* event queue entry structure */ 280 struct lpfc_eqe { 281 uint32_t word0; 282 #define lpfc_eqe_resource_id_SHIFT 16 283 #define lpfc_eqe_resource_id_MASK 0x000000FF 284 #define lpfc_eqe_resource_id_WORD word0 285 #define lpfc_eqe_minor_code_SHIFT 4 286 #define lpfc_eqe_minor_code_MASK 0x00000FFF 287 #define lpfc_eqe_minor_code_WORD word0 288 #define lpfc_eqe_major_code_SHIFT 1 289 #define lpfc_eqe_major_code_MASK 0x00000007 290 #define lpfc_eqe_major_code_WORD word0 291 #define lpfc_eqe_valid_SHIFT 0 292 #define lpfc_eqe_valid_MASK 0x00000001 293 #define lpfc_eqe_valid_WORD word0 294 }; 295 296 /* completion queue entry structure (common fields for all cqe types) */ 297 struct lpfc_cqe { 298 uint32_t reserved0; 299 uint32_t reserved1; 300 uint32_t reserved2; 301 uint32_t word3; 302 #define lpfc_cqe_valid_SHIFT 31 303 #define lpfc_cqe_valid_MASK 0x00000001 304 #define lpfc_cqe_valid_WORD word3 305 #define lpfc_cqe_code_SHIFT 16 306 #define lpfc_cqe_code_MASK 0x000000FF 307 #define lpfc_cqe_code_WORD word3 308 }; 309 310 /* Completion Queue Entry Status Codes */ 311 #define CQE_STATUS_SUCCESS 0x0 312 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 313 #define CQE_STATUS_REMOTE_STOP 0x2 314 #define CQE_STATUS_LOCAL_REJECT 0x3 315 #define CQE_STATUS_NPORT_RJT 0x4 316 #define CQE_STATUS_FABRIC_RJT 0x5 317 #define CQE_STATUS_NPORT_BSY 0x6 318 #define CQE_STATUS_FABRIC_BSY 0x7 319 #define CQE_STATUS_INTERMED_RSP 0x8 320 #define CQE_STATUS_LS_RJT 0x9 321 #define CQE_STATUS_CMD_REJECT 0xb 322 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 323 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 324 #define CQE_STATUS_DI_ERROR 0x16 325 326 /* Used when mapping CQE status to IOCB */ 327 #define LPFC_IOCB_STATUS_MASK 0xf 328 329 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 330 #define CQE_HW_STATUS_NO_ERR 0x0 331 #define CQE_HW_STATUS_UNDERRUN 0x1 332 #define CQE_HW_STATUS_OVERRUN 0x2 333 334 /* Completion Queue Entry Codes */ 335 #define CQE_CODE_COMPL_WQE 0x1 336 #define CQE_CODE_RELEASE_WQE 0x2 337 #define CQE_CODE_RECEIVE 0x4 338 #define CQE_CODE_XRI_ABORTED 0x5 339 #define CQE_CODE_RECEIVE_V1 0x9 340 341 /* 342 * Define mask value for xri_aborted and wcqe completed CQE extended status. 343 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 344 */ 345 #define WCQE_PARAM_MASK 0x1FF; 346 347 /* completion queue entry for wqe completions */ 348 struct lpfc_wcqe_complete { 349 uint32_t word0; 350 #define lpfc_wcqe_c_request_tag_SHIFT 16 351 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 352 #define lpfc_wcqe_c_request_tag_WORD word0 353 #define lpfc_wcqe_c_status_SHIFT 8 354 #define lpfc_wcqe_c_status_MASK 0x000000FF 355 #define lpfc_wcqe_c_status_WORD word0 356 #define lpfc_wcqe_c_hw_status_SHIFT 0 357 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 358 #define lpfc_wcqe_c_hw_status_WORD word0 359 uint32_t total_data_placed; 360 uint32_t parameter; 361 #define lpfc_wcqe_c_bg_edir_SHIFT 5 362 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001 363 #define lpfc_wcqe_c_bg_edir_WORD parameter 364 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3 365 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 366 #define lpfc_wcqe_c_bg_tdpv_WORD parameter 367 #define lpfc_wcqe_c_bg_re_SHIFT 2 368 #define lpfc_wcqe_c_bg_re_MASK 0x00000001 369 #define lpfc_wcqe_c_bg_re_WORD parameter 370 #define lpfc_wcqe_c_bg_ae_SHIFT 1 371 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001 372 #define lpfc_wcqe_c_bg_ae_WORD parameter 373 #define lpfc_wcqe_c_bg_ge_SHIFT 0 374 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001 375 #define lpfc_wcqe_c_bg_ge_WORD parameter 376 uint32_t word3; 377 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 378 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 379 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 380 #define lpfc_wcqe_c_xb_SHIFT 28 381 #define lpfc_wcqe_c_xb_MASK 0x00000001 382 #define lpfc_wcqe_c_xb_WORD word3 383 #define lpfc_wcqe_c_pv_SHIFT 27 384 #define lpfc_wcqe_c_pv_MASK 0x00000001 385 #define lpfc_wcqe_c_pv_WORD word3 386 #define lpfc_wcqe_c_priority_SHIFT 24 387 #define lpfc_wcqe_c_priority_MASK 0x00000007 388 #define lpfc_wcqe_c_priority_WORD word3 389 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 390 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 391 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 392 }; 393 394 /* completion queue entry for wqe release */ 395 struct lpfc_wcqe_release { 396 uint32_t reserved0; 397 uint32_t reserved1; 398 uint32_t word2; 399 #define lpfc_wcqe_r_wq_id_SHIFT 16 400 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 401 #define lpfc_wcqe_r_wq_id_WORD word2 402 #define lpfc_wcqe_r_wqe_index_SHIFT 0 403 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 404 #define lpfc_wcqe_r_wqe_index_WORD word2 405 uint32_t word3; 406 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 407 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 408 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 409 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 410 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 411 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 412 }; 413 414 struct sli4_wcqe_xri_aborted { 415 uint32_t word0; 416 #define lpfc_wcqe_xa_status_SHIFT 8 417 #define lpfc_wcqe_xa_status_MASK 0x000000FF 418 #define lpfc_wcqe_xa_status_WORD word0 419 uint32_t parameter; 420 uint32_t word2; 421 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 422 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 423 #define lpfc_wcqe_xa_remote_xid_WORD word2 424 #define lpfc_wcqe_xa_xri_SHIFT 0 425 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 426 #define lpfc_wcqe_xa_xri_WORD word2 427 uint32_t word3; 428 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 429 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 430 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 431 #define lpfc_wcqe_xa_ia_SHIFT 30 432 #define lpfc_wcqe_xa_ia_MASK 0x00000001 433 #define lpfc_wcqe_xa_ia_WORD word3 434 #define CQE_XRI_ABORTED_IA_REMOTE 0 435 #define CQE_XRI_ABORTED_IA_LOCAL 1 436 #define lpfc_wcqe_xa_br_SHIFT 29 437 #define lpfc_wcqe_xa_br_MASK 0x00000001 438 #define lpfc_wcqe_xa_br_WORD word3 439 #define CQE_XRI_ABORTED_BR_BA_ACC 0 440 #define CQE_XRI_ABORTED_BR_BA_RJT 1 441 #define lpfc_wcqe_xa_eo_SHIFT 28 442 #define lpfc_wcqe_xa_eo_MASK 0x00000001 443 #define lpfc_wcqe_xa_eo_WORD word3 444 #define CQE_XRI_ABORTED_EO_REMOTE 0 445 #define CQE_XRI_ABORTED_EO_LOCAL 1 446 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 447 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 448 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 449 }; 450 451 /* completion queue entry structure for rqe completion */ 452 struct lpfc_rcqe { 453 uint32_t word0; 454 #define lpfc_rcqe_bindex_SHIFT 16 455 #define lpfc_rcqe_bindex_MASK 0x0000FFF 456 #define lpfc_rcqe_bindex_WORD word0 457 #define lpfc_rcqe_status_SHIFT 8 458 #define lpfc_rcqe_status_MASK 0x000000FF 459 #define lpfc_rcqe_status_WORD word0 460 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 461 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 462 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 463 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 464 uint32_t word1; 465 #define lpfc_rcqe_fcf_id_v1_SHIFT 0 466 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 467 #define lpfc_rcqe_fcf_id_v1_WORD word1 468 uint32_t word2; 469 #define lpfc_rcqe_length_SHIFT 16 470 #define lpfc_rcqe_length_MASK 0x0000FFFF 471 #define lpfc_rcqe_length_WORD word2 472 #define lpfc_rcqe_rq_id_SHIFT 6 473 #define lpfc_rcqe_rq_id_MASK 0x000003FF 474 #define lpfc_rcqe_rq_id_WORD word2 475 #define lpfc_rcqe_fcf_id_SHIFT 0 476 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 477 #define lpfc_rcqe_fcf_id_WORD word2 478 #define lpfc_rcqe_rq_id_v1_SHIFT 0 479 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 480 #define lpfc_rcqe_rq_id_v1_WORD word2 481 uint32_t word3; 482 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 483 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 484 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 485 #define lpfc_rcqe_port_SHIFT 30 486 #define lpfc_rcqe_port_MASK 0x00000001 487 #define lpfc_rcqe_port_WORD word3 488 #define lpfc_rcqe_hdr_length_SHIFT 24 489 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 490 #define lpfc_rcqe_hdr_length_WORD word3 491 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 492 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 493 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 494 #define lpfc_rcqe_eof_SHIFT 8 495 #define lpfc_rcqe_eof_MASK 0x000000FF 496 #define lpfc_rcqe_eof_WORD word3 497 #define FCOE_EOFn 0x41 498 #define FCOE_EOFt 0x42 499 #define FCOE_EOFni 0x49 500 #define FCOE_EOFa 0x50 501 #define lpfc_rcqe_sof_SHIFT 0 502 #define lpfc_rcqe_sof_MASK 0x000000FF 503 #define lpfc_rcqe_sof_WORD word3 504 #define FCOE_SOFi2 0x2d 505 #define FCOE_SOFi3 0x2e 506 #define FCOE_SOFn2 0x35 507 #define FCOE_SOFn3 0x36 508 }; 509 510 struct lpfc_rqe { 511 uint32_t address_hi; 512 uint32_t address_lo; 513 }; 514 515 /* buffer descriptors */ 516 struct lpfc_bde4 { 517 uint32_t addr_hi; 518 uint32_t addr_lo; 519 uint32_t word2; 520 #define lpfc_bde4_last_SHIFT 31 521 #define lpfc_bde4_last_MASK 0x00000001 522 #define lpfc_bde4_last_WORD word2 523 #define lpfc_bde4_sge_offset_SHIFT 0 524 #define lpfc_bde4_sge_offset_MASK 0x000003FF 525 #define lpfc_bde4_sge_offset_WORD word2 526 uint32_t word3; 527 #define lpfc_bde4_length_SHIFT 0 528 #define lpfc_bde4_length_MASK 0x000000FF 529 #define lpfc_bde4_length_WORD word3 530 }; 531 532 struct lpfc_register { 533 uint32_t word0; 534 }; 535 536 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 537 #define LPFC_UERR_STATUS_HI 0x00A4 538 #define LPFC_UERR_STATUS_LO 0x00A0 539 #define LPFC_UE_MASK_HI 0x00AC 540 #define LPFC_UE_MASK_LO 0x00A8 541 542 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 543 #define LPFC_SLI_INTF 0x0058 544 545 #define LPFC_CTL_PORT_SEM_OFFSET 0x400 546 #define lpfc_port_smphr_perr_SHIFT 31 547 #define lpfc_port_smphr_perr_MASK 0x1 548 #define lpfc_port_smphr_perr_WORD word0 549 #define lpfc_port_smphr_sfi_SHIFT 30 550 #define lpfc_port_smphr_sfi_MASK 0x1 551 #define lpfc_port_smphr_sfi_WORD word0 552 #define lpfc_port_smphr_nip_SHIFT 29 553 #define lpfc_port_smphr_nip_MASK 0x1 554 #define lpfc_port_smphr_nip_WORD word0 555 #define lpfc_port_smphr_ipc_SHIFT 28 556 #define lpfc_port_smphr_ipc_MASK 0x1 557 #define lpfc_port_smphr_ipc_WORD word0 558 #define lpfc_port_smphr_scr1_SHIFT 27 559 #define lpfc_port_smphr_scr1_MASK 0x1 560 #define lpfc_port_smphr_scr1_WORD word0 561 #define lpfc_port_smphr_scr2_SHIFT 26 562 #define lpfc_port_smphr_scr2_MASK 0x1 563 #define lpfc_port_smphr_scr2_WORD word0 564 #define lpfc_port_smphr_host_scratch_SHIFT 16 565 #define lpfc_port_smphr_host_scratch_MASK 0xFF 566 #define lpfc_port_smphr_host_scratch_WORD word0 567 #define lpfc_port_smphr_port_status_SHIFT 0 568 #define lpfc_port_smphr_port_status_MASK 0xFFFF 569 #define lpfc_port_smphr_port_status_WORD word0 570 571 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 572 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 573 #define LPFC_POST_STAGE_HOST_RDY 0x0002 574 #define LPFC_POST_STAGE_BE_RESET 0x0003 575 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 576 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 577 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 578 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 579 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 580 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 581 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 582 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 583 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 584 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 585 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 586 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 587 #define LPFC_POST_STAGE_ARMFW_START 0x0800 588 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 589 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 590 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 591 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 592 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 593 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 594 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 595 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 596 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 597 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 598 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 599 #define LPFC_POST_STAGE_RC_DONE 0x0B07 600 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 601 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 602 #define LPFC_POST_STAGE_PORT_READY 0xC000 603 #define LPFC_POST_STAGE_PORT_UE 0xF000 604 605 #define LPFC_CTL_PORT_STA_OFFSET 0x404 606 #define lpfc_sliport_status_err_SHIFT 31 607 #define lpfc_sliport_status_err_MASK 0x1 608 #define lpfc_sliport_status_err_WORD word0 609 #define lpfc_sliport_status_end_SHIFT 30 610 #define lpfc_sliport_status_end_MASK 0x1 611 #define lpfc_sliport_status_end_WORD word0 612 #define lpfc_sliport_status_oti_SHIFT 29 613 #define lpfc_sliport_status_oti_MASK 0x1 614 #define lpfc_sliport_status_oti_WORD word0 615 #define lpfc_sliport_status_rn_SHIFT 24 616 #define lpfc_sliport_status_rn_MASK 0x1 617 #define lpfc_sliport_status_rn_WORD word0 618 #define lpfc_sliport_status_rdy_SHIFT 23 619 #define lpfc_sliport_status_rdy_MASK 0x1 620 #define lpfc_sliport_status_rdy_WORD word0 621 #define MAX_IF_TYPE_2_RESETS 1000 622 623 #define LPFC_CTL_PORT_CTL_OFFSET 0x408 624 #define lpfc_sliport_ctrl_end_SHIFT 30 625 #define lpfc_sliport_ctrl_end_MASK 0x1 626 #define lpfc_sliport_ctrl_end_WORD word0 627 #define LPFC_SLIPORT_LITTLE_ENDIAN 0 628 #define LPFC_SLIPORT_BIG_ENDIAN 1 629 #define lpfc_sliport_ctrl_ip_SHIFT 27 630 #define lpfc_sliport_ctrl_ip_MASK 0x1 631 #define lpfc_sliport_ctrl_ip_WORD word0 632 #define LPFC_SLIPORT_INIT_PORT 1 633 634 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C 635 #define LPFC_CTL_PORT_ER2_OFFSET 0x410 636 637 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 638 * reside in BAR 2. 639 */ 640 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC 641 642 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 643 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 644 645 #define LPFC_HST_ISR0 0x0C18 646 #define LPFC_HST_ISR1 0x0C1C 647 #define LPFC_HST_ISR2 0x0C20 648 #define LPFC_HST_ISR3 0x0C24 649 #define LPFC_HST_ISR4 0x0C28 650 651 #define LPFC_HST_IMR0 0x0C48 652 #define LPFC_HST_IMR1 0x0C4C 653 #define LPFC_HST_IMR2 0x0C50 654 #define LPFC_HST_IMR3 0x0C54 655 #define LPFC_HST_IMR4 0x0C58 656 657 #define LPFC_HST_ISCR0 0x0C78 658 #define LPFC_HST_ISCR1 0x0C7C 659 #define LPFC_HST_ISCR2 0x0C80 660 #define LPFC_HST_ISCR3 0x0C84 661 #define LPFC_HST_ISCR4 0x0C88 662 663 #define LPFC_SLI4_INTR0 BIT0 664 #define LPFC_SLI4_INTR1 BIT1 665 #define LPFC_SLI4_INTR2 BIT2 666 #define LPFC_SLI4_INTR3 BIT3 667 #define LPFC_SLI4_INTR4 BIT4 668 #define LPFC_SLI4_INTR5 BIT5 669 #define LPFC_SLI4_INTR6 BIT6 670 #define LPFC_SLI4_INTR7 BIT7 671 #define LPFC_SLI4_INTR8 BIT8 672 #define LPFC_SLI4_INTR9 BIT9 673 #define LPFC_SLI4_INTR10 BIT10 674 #define LPFC_SLI4_INTR11 BIT11 675 #define LPFC_SLI4_INTR12 BIT12 676 #define LPFC_SLI4_INTR13 BIT13 677 #define LPFC_SLI4_INTR14 BIT14 678 #define LPFC_SLI4_INTR15 BIT15 679 #define LPFC_SLI4_INTR16 BIT16 680 #define LPFC_SLI4_INTR17 BIT17 681 #define LPFC_SLI4_INTR18 BIT18 682 #define LPFC_SLI4_INTR19 BIT19 683 #define LPFC_SLI4_INTR20 BIT20 684 #define LPFC_SLI4_INTR21 BIT21 685 #define LPFC_SLI4_INTR22 BIT22 686 #define LPFC_SLI4_INTR23 BIT23 687 #define LPFC_SLI4_INTR24 BIT24 688 #define LPFC_SLI4_INTR25 BIT25 689 #define LPFC_SLI4_INTR26 BIT26 690 #define LPFC_SLI4_INTR27 BIT27 691 #define LPFC_SLI4_INTR28 BIT28 692 #define LPFC_SLI4_INTR29 BIT29 693 #define LPFC_SLI4_INTR30 BIT30 694 #define LPFC_SLI4_INTR31 BIT31 695 696 /* 697 * The Doorbell registers defined here exist in different BAR 698 * register sets depending on the UCNA Port's reported if_type 699 * value. For UCNA ports running SLI4 and if_type 0, they reside in 700 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 701 * BAR0. The offsets are the same so the driver must account for 702 * any base address difference. 703 */ 704 #define LPFC_RQ_DOORBELL 0x00A0 705 #define lpfc_rq_doorbell_num_posted_SHIFT 16 706 #define lpfc_rq_doorbell_num_posted_MASK 0x3FFF 707 #define lpfc_rq_doorbell_num_posted_WORD word0 708 #define lpfc_rq_doorbell_id_SHIFT 0 709 #define lpfc_rq_doorbell_id_MASK 0xFFFF 710 #define lpfc_rq_doorbell_id_WORD word0 711 712 #define LPFC_WQ_DOORBELL 0x0040 713 #define lpfc_wq_doorbell_num_posted_SHIFT 24 714 #define lpfc_wq_doorbell_num_posted_MASK 0x00FF 715 #define lpfc_wq_doorbell_num_posted_WORD word0 716 #define lpfc_wq_doorbell_index_SHIFT 16 717 #define lpfc_wq_doorbell_index_MASK 0x00FF 718 #define lpfc_wq_doorbell_index_WORD word0 719 #define lpfc_wq_doorbell_id_SHIFT 0 720 #define lpfc_wq_doorbell_id_MASK 0xFFFF 721 #define lpfc_wq_doorbell_id_WORD word0 722 723 #define LPFC_EQCQ_DOORBELL 0x0120 724 #define lpfc_eqcq_doorbell_se_SHIFT 31 725 #define lpfc_eqcq_doorbell_se_MASK 0x0001 726 #define lpfc_eqcq_doorbell_se_WORD word0 727 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 728 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 729 #define lpfc_eqcq_doorbell_arm_SHIFT 29 730 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 731 #define lpfc_eqcq_doorbell_arm_WORD word0 732 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 733 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 734 #define lpfc_eqcq_doorbell_num_released_WORD word0 735 #define lpfc_eqcq_doorbell_qt_SHIFT 10 736 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 737 #define lpfc_eqcq_doorbell_qt_WORD word0 738 #define LPFC_QUEUE_TYPE_COMPLETION 0 739 #define LPFC_QUEUE_TYPE_EVENT 1 740 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 741 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 742 #define lpfc_eqcq_doorbell_eqci_WORD word0 743 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 744 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 745 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0 746 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 747 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 748 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0 749 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 750 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 751 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0 752 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 753 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 754 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0 755 #define LPFC_CQID_HI_FIELD_SHIFT 10 756 #define LPFC_EQID_HI_FIELD_SHIFT 9 757 758 #define LPFC_BMBX 0x0160 759 #define lpfc_bmbx_addr_SHIFT 2 760 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 761 #define lpfc_bmbx_addr_WORD word0 762 #define lpfc_bmbx_hi_SHIFT 1 763 #define lpfc_bmbx_hi_MASK 0x0001 764 #define lpfc_bmbx_hi_WORD word0 765 #define lpfc_bmbx_rdy_SHIFT 0 766 #define lpfc_bmbx_rdy_MASK 0x0001 767 #define lpfc_bmbx_rdy_WORD word0 768 769 #define LPFC_MQ_DOORBELL 0x0140 770 #define lpfc_mq_doorbell_num_posted_SHIFT 16 771 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 772 #define lpfc_mq_doorbell_num_posted_WORD word0 773 #define lpfc_mq_doorbell_id_SHIFT 0 774 #define lpfc_mq_doorbell_id_MASK 0xFFFF 775 #define lpfc_mq_doorbell_id_WORD word0 776 777 struct lpfc_sli4_cfg_mhdr { 778 uint32_t word1; 779 #define lpfc_mbox_hdr_emb_SHIFT 0 780 #define lpfc_mbox_hdr_emb_MASK 0x00000001 781 #define lpfc_mbox_hdr_emb_WORD word1 782 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 783 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 784 #define lpfc_mbox_hdr_sge_cnt_WORD word1 785 uint32_t payload_length; 786 uint32_t tag_lo; 787 uint32_t tag_hi; 788 uint32_t reserved5; 789 }; 790 791 union lpfc_sli4_cfg_shdr { 792 struct { 793 uint32_t word6; 794 #define lpfc_mbox_hdr_opcode_SHIFT 0 795 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 796 #define lpfc_mbox_hdr_opcode_WORD word6 797 #define lpfc_mbox_hdr_subsystem_SHIFT 8 798 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 799 #define lpfc_mbox_hdr_subsystem_WORD word6 800 #define lpfc_mbox_hdr_port_number_SHIFT 16 801 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 802 #define lpfc_mbox_hdr_port_number_WORD word6 803 #define lpfc_mbox_hdr_domain_SHIFT 24 804 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 805 #define lpfc_mbox_hdr_domain_WORD word6 806 uint32_t timeout; 807 uint32_t request_length; 808 uint32_t word9; 809 #define lpfc_mbox_hdr_version_SHIFT 0 810 #define lpfc_mbox_hdr_version_MASK 0x000000FF 811 #define lpfc_mbox_hdr_version_WORD word9 812 #define lpfc_mbox_hdr_pf_num_SHIFT 16 813 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 814 #define lpfc_mbox_hdr_pf_num_WORD word9 815 #define lpfc_mbox_hdr_vh_num_SHIFT 24 816 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 817 #define lpfc_mbox_hdr_vh_num_WORD word9 818 #define LPFC_Q_CREATE_VERSION_2 2 819 #define LPFC_Q_CREATE_VERSION_1 1 820 #define LPFC_Q_CREATE_VERSION_0 0 821 #define LPFC_OPCODE_VERSION_0 0 822 #define LPFC_OPCODE_VERSION_1 1 823 } request; 824 struct { 825 uint32_t word6; 826 #define lpfc_mbox_hdr_opcode_SHIFT 0 827 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 828 #define lpfc_mbox_hdr_opcode_WORD word6 829 #define lpfc_mbox_hdr_subsystem_SHIFT 8 830 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 831 #define lpfc_mbox_hdr_subsystem_WORD word6 832 #define lpfc_mbox_hdr_domain_SHIFT 24 833 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 834 #define lpfc_mbox_hdr_domain_WORD word6 835 uint32_t word7; 836 #define lpfc_mbox_hdr_status_SHIFT 0 837 #define lpfc_mbox_hdr_status_MASK 0x000000FF 838 #define lpfc_mbox_hdr_status_WORD word7 839 #define lpfc_mbox_hdr_add_status_SHIFT 8 840 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 841 #define lpfc_mbox_hdr_add_status_WORD word7 842 uint32_t response_length; 843 uint32_t actual_response_length; 844 } response; 845 }; 846 847 /* Mailbox Header structures. 848 * struct mbox_header is defined for first generation SLI4_CFG mailbox 849 * calls deployed for BE-based ports. 850 * 851 * struct sli4_mbox_header is defined for second generation SLI4 852 * ports that don't deploy the SLI4_CFG mechanism. 853 */ 854 struct mbox_header { 855 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 856 union lpfc_sli4_cfg_shdr cfg_shdr; 857 }; 858 859 #define LPFC_EXTENT_LOCAL 0 860 #define LPFC_TIMEOUT_DEFAULT 0 861 #define LPFC_EXTENT_VERSION_DEFAULT 0 862 863 /* Subsystem Definitions */ 864 #define LPFC_MBOX_SUBSYSTEM_NA 0x0 865 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 866 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 867 868 /* Device Specific Definitions */ 869 870 /* The HOST ENDIAN defines are in Big Endian format. */ 871 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 872 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 873 874 /* Common Opcodes */ 875 #define LPFC_MBOX_OPCODE_NA 0x00 876 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 877 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 878 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 879 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 880 #define LPFC_MBOX_OPCODE_NOP 0x21 881 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 882 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 883 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 884 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 885 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 886 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 887 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 888 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 889 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 890 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 891 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 892 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 893 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 894 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 895 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 896 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 897 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 898 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 899 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 900 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 901 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 902 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 903 904 /* FCoE Opcodes */ 905 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 906 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 907 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 908 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 909 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 910 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 911 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 912 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 913 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 914 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 915 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 916 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 917 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 918 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 919 920 /* Mailbox command structures */ 921 struct eq_context { 922 uint32_t word0; 923 #define lpfc_eq_context_size_SHIFT 31 924 #define lpfc_eq_context_size_MASK 0x00000001 925 #define lpfc_eq_context_size_WORD word0 926 #define LPFC_EQE_SIZE_4 0x0 927 #define LPFC_EQE_SIZE_16 0x1 928 #define lpfc_eq_context_valid_SHIFT 29 929 #define lpfc_eq_context_valid_MASK 0x00000001 930 #define lpfc_eq_context_valid_WORD word0 931 uint32_t word1; 932 #define lpfc_eq_context_count_SHIFT 26 933 #define lpfc_eq_context_count_MASK 0x00000003 934 #define lpfc_eq_context_count_WORD word1 935 #define LPFC_EQ_CNT_256 0x0 936 #define LPFC_EQ_CNT_512 0x1 937 #define LPFC_EQ_CNT_1024 0x2 938 #define LPFC_EQ_CNT_2048 0x3 939 #define LPFC_EQ_CNT_4096 0x4 940 uint32_t word2; 941 #define lpfc_eq_context_delay_multi_SHIFT 13 942 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 943 #define lpfc_eq_context_delay_multi_WORD word2 944 uint32_t reserved3; 945 }; 946 947 struct sgl_page_pairs { 948 uint32_t sgl_pg0_addr_lo; 949 uint32_t sgl_pg0_addr_hi; 950 uint32_t sgl_pg1_addr_lo; 951 uint32_t sgl_pg1_addr_hi; 952 }; 953 954 struct lpfc_mbx_post_sgl_pages { 955 struct mbox_header header; 956 uint32_t word0; 957 #define lpfc_post_sgl_pages_xri_SHIFT 0 958 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 959 #define lpfc_post_sgl_pages_xri_WORD word0 960 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 961 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 962 #define lpfc_post_sgl_pages_xricnt_WORD word0 963 struct sgl_page_pairs sgl_pg_pairs[1]; 964 }; 965 966 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 967 struct lpfc_mbx_post_uembed_sgl_page1 { 968 union lpfc_sli4_cfg_shdr cfg_shdr; 969 uint32_t word0; 970 struct sgl_page_pairs sgl_pg_pairs; 971 }; 972 973 struct lpfc_mbx_sge { 974 uint32_t pa_lo; 975 uint32_t pa_hi; 976 uint32_t length; 977 }; 978 979 struct lpfc_mbx_nembed_cmd { 980 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 981 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 982 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 983 }; 984 985 struct lpfc_mbx_nembed_sge_virt { 986 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 987 }; 988 989 struct lpfc_mbx_eq_create { 990 struct mbox_header header; 991 union { 992 struct { 993 uint32_t word0; 994 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 995 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 996 #define lpfc_mbx_eq_create_num_pages_WORD word0 997 struct eq_context context; 998 struct dma_address page[LPFC_MAX_EQ_PAGE]; 999 } request; 1000 struct { 1001 uint32_t word0; 1002 #define lpfc_mbx_eq_create_q_id_SHIFT 0 1003 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1004 #define lpfc_mbx_eq_create_q_id_WORD word0 1005 } response; 1006 } u; 1007 }; 1008 1009 struct lpfc_mbx_eq_destroy { 1010 struct mbox_header header; 1011 union { 1012 struct { 1013 uint32_t word0; 1014 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1015 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1016 #define lpfc_mbx_eq_destroy_q_id_WORD word0 1017 } request; 1018 struct { 1019 uint32_t word0; 1020 } response; 1021 } u; 1022 }; 1023 1024 struct lpfc_mbx_nop { 1025 struct mbox_header header; 1026 uint32_t context[2]; 1027 }; 1028 1029 struct cq_context { 1030 uint32_t word0; 1031 #define lpfc_cq_context_event_SHIFT 31 1032 #define lpfc_cq_context_event_MASK 0x00000001 1033 #define lpfc_cq_context_event_WORD word0 1034 #define lpfc_cq_context_valid_SHIFT 29 1035 #define lpfc_cq_context_valid_MASK 0x00000001 1036 #define lpfc_cq_context_valid_WORD word0 1037 #define lpfc_cq_context_count_SHIFT 27 1038 #define lpfc_cq_context_count_MASK 0x00000003 1039 #define lpfc_cq_context_count_WORD word0 1040 #define LPFC_CQ_CNT_256 0x0 1041 #define LPFC_CQ_CNT_512 0x1 1042 #define LPFC_CQ_CNT_1024 0x2 1043 uint32_t word1; 1044 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1045 #define lpfc_cq_eq_id_MASK 0x000000FF 1046 #define lpfc_cq_eq_id_WORD word1 1047 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1048 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1049 #define lpfc_cq_eq_id_2_WORD word1 1050 uint32_t reserved0; 1051 uint32_t reserved1; 1052 }; 1053 1054 struct lpfc_mbx_cq_create { 1055 struct mbox_header header; 1056 union { 1057 struct { 1058 uint32_t word0; 1059 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1060 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1061 #define lpfc_mbx_cq_create_page_size_WORD word0 1062 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 1063 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1064 #define lpfc_mbx_cq_create_num_pages_WORD word0 1065 struct cq_context context; 1066 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1067 } request; 1068 struct { 1069 uint32_t word0; 1070 #define lpfc_mbx_cq_create_q_id_SHIFT 0 1071 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1072 #define lpfc_mbx_cq_create_q_id_WORD word0 1073 } response; 1074 } u; 1075 }; 1076 1077 struct lpfc_mbx_cq_destroy { 1078 struct mbox_header header; 1079 union { 1080 struct { 1081 uint32_t word0; 1082 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1083 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1084 #define lpfc_mbx_cq_destroy_q_id_WORD word0 1085 } request; 1086 struct { 1087 uint32_t word0; 1088 } response; 1089 } u; 1090 }; 1091 1092 struct wq_context { 1093 uint32_t reserved0; 1094 uint32_t reserved1; 1095 uint32_t reserved2; 1096 uint32_t reserved3; 1097 }; 1098 1099 struct lpfc_mbx_wq_create { 1100 struct mbox_header header; 1101 union { 1102 struct { /* Version 0 Request */ 1103 uint32_t word0; 1104 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 1105 #define lpfc_mbx_wq_create_num_pages_MASK 0x0000FFFF 1106 #define lpfc_mbx_wq_create_num_pages_WORD word0 1107 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 1108 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1109 #define lpfc_mbx_wq_create_cq_id_WORD word0 1110 struct dma_address page[LPFC_MAX_WQ_PAGE]; 1111 } request; 1112 struct { /* Version 1 Request */ 1113 uint32_t word0; /* Word 0 is the same as in v0 */ 1114 uint32_t word1; 1115 #define lpfc_mbx_wq_create_page_size_SHIFT 0 1116 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1117 #define lpfc_mbx_wq_create_page_size_WORD word1 1118 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1119 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1120 #define lpfc_mbx_wq_create_wqe_size_WORD word1 1121 #define LPFC_WQ_WQE_SIZE_64 0x5 1122 #define LPFC_WQ_WQE_SIZE_128 0x6 1123 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1124 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1125 #define lpfc_mbx_wq_create_wqe_count_WORD word1 1126 uint32_t word2; 1127 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1128 } request_1; 1129 struct { 1130 uint32_t word0; 1131 #define lpfc_mbx_wq_create_q_id_SHIFT 0 1132 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1133 #define lpfc_mbx_wq_create_q_id_WORD word0 1134 } response; 1135 } u; 1136 }; 1137 1138 struct lpfc_mbx_wq_destroy { 1139 struct mbox_header header; 1140 union { 1141 struct { 1142 uint32_t word0; 1143 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1144 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1145 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1146 } request; 1147 struct { 1148 uint32_t word0; 1149 } response; 1150 } u; 1151 }; 1152 1153 #define LPFC_HDR_BUF_SIZE 128 1154 #define LPFC_DATA_BUF_SIZE 2048 1155 struct rq_context { 1156 uint32_t word0; 1157 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1158 #define lpfc_rq_context_rqe_count_MASK 0x0000000F 1159 #define lpfc_rq_context_rqe_count_WORD word0 1160 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1161 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1162 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1163 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1164 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1 Only */ 1165 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1166 #define lpfc_rq_context_rqe_count_1_WORD word0 1167 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1 Only */ 1168 #define lpfc_rq_context_rqe_size_MASK 0x0000000F 1169 #define lpfc_rq_context_rqe_size_WORD word0 1170 #define LPFC_RQE_SIZE_8 2 1171 #define LPFC_RQE_SIZE_16 3 1172 #define LPFC_RQE_SIZE_32 4 1173 #define LPFC_RQE_SIZE_64 5 1174 #define LPFC_RQE_SIZE_128 6 1175 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1176 #define lpfc_rq_context_page_size_MASK 0x000000FF 1177 #define lpfc_rq_context_page_size_WORD word0 1178 uint32_t reserved1; 1179 uint32_t word2; 1180 #define lpfc_rq_context_cq_id_SHIFT 16 1181 #define lpfc_rq_context_cq_id_MASK 0x000003FF 1182 #define lpfc_rq_context_cq_id_WORD word2 1183 #define lpfc_rq_context_buf_size_SHIFT 0 1184 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1185 #define lpfc_rq_context_buf_size_WORD word2 1186 uint32_t buffer_size; /* Version 1 Only */ 1187 }; 1188 1189 struct lpfc_mbx_rq_create { 1190 struct mbox_header header; 1191 union { 1192 struct { 1193 uint32_t word0; 1194 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1195 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1196 #define lpfc_mbx_rq_create_num_pages_WORD word0 1197 struct rq_context context; 1198 struct dma_address page[LPFC_MAX_WQ_PAGE]; 1199 } request; 1200 struct { 1201 uint32_t word0; 1202 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1203 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1204 #define lpfc_mbx_rq_create_q_id_WORD word0 1205 } response; 1206 } u; 1207 }; 1208 1209 struct lpfc_mbx_rq_destroy { 1210 struct mbox_header header; 1211 union { 1212 struct { 1213 uint32_t word0; 1214 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1215 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1216 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1217 } request; 1218 struct { 1219 uint32_t word0; 1220 } response; 1221 } u; 1222 }; 1223 1224 struct mq_context { 1225 uint32_t word0; 1226 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1227 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1228 #define lpfc_mq_context_cq_id_WORD word0 1229 #define lpfc_mq_context_ring_size_SHIFT 16 1230 #define lpfc_mq_context_ring_size_MASK 0x0000000F 1231 #define lpfc_mq_context_ring_size_WORD word0 1232 #define LPFC_MQ_RING_SIZE_16 0x5 1233 #define LPFC_MQ_RING_SIZE_32 0x6 1234 #define LPFC_MQ_RING_SIZE_64 0x7 1235 #define LPFC_MQ_RING_SIZE_128 0x8 1236 uint32_t word1; 1237 #define lpfc_mq_context_valid_SHIFT 31 1238 #define lpfc_mq_context_valid_MASK 0x00000001 1239 #define lpfc_mq_context_valid_WORD word1 1240 uint32_t reserved2; 1241 uint32_t reserved3; 1242 }; 1243 1244 struct lpfc_mbx_mq_create { 1245 struct mbox_header header; 1246 union { 1247 struct { 1248 uint32_t word0; 1249 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1250 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1251 #define lpfc_mbx_mq_create_num_pages_WORD word0 1252 struct mq_context context; 1253 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1254 } request; 1255 struct { 1256 uint32_t word0; 1257 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1258 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1259 #define lpfc_mbx_mq_create_q_id_WORD word0 1260 } response; 1261 } u; 1262 }; 1263 1264 struct lpfc_mbx_mq_create_ext { 1265 struct mbox_header header; 1266 union { 1267 struct { 1268 uint32_t word0; 1269 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1270 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1271 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1272 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1273 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1274 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1275 uint32_t async_evt_bmap; 1276 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1277 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1278 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1279 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1280 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1281 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1282 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1283 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1284 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1285 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1286 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1287 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1288 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1289 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1290 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1291 struct mq_context context; 1292 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1293 } request; 1294 struct { 1295 uint32_t word0; 1296 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1297 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1298 #define lpfc_mbx_mq_create_q_id_WORD word0 1299 } response; 1300 } u; 1301 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1302 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1303 #define LPFC_ASYNC_EVENT_GROUP5 0x20 1304 }; 1305 1306 struct lpfc_mbx_mq_destroy { 1307 struct mbox_header header; 1308 union { 1309 struct { 1310 uint32_t word0; 1311 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1312 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1313 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1314 } request; 1315 struct { 1316 uint32_t word0; 1317 } response; 1318 } u; 1319 }; 1320 1321 /* Start Gen 2 SLI4 Mailbox definitions: */ 1322 1323 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1324 #define LPFC_RSC_TYPE_FCOE_VFI 0x20 1325 #define LPFC_RSC_TYPE_FCOE_VPI 0x21 1326 #define LPFC_RSC_TYPE_FCOE_RPI 0x22 1327 #define LPFC_RSC_TYPE_FCOE_XRI 0x23 1328 1329 struct lpfc_mbx_get_rsrc_extent_info { 1330 struct mbox_header header; 1331 union { 1332 struct { 1333 uint32_t word4; 1334 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1335 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1336 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1337 } req; 1338 struct { 1339 uint32_t word4; 1340 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1341 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1342 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1343 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1344 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1345 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1346 } rsp; 1347 } u; 1348 }; 1349 1350 struct lpfc_id_range { 1351 uint32_t word5; 1352 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1353 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1354 #define lpfc_mbx_rsrc_id_word4_0_WORD word5 1355 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1356 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1357 #define lpfc_mbx_rsrc_id_word4_1_WORD word5 1358 }; 1359 1360 struct lpfc_mbx_set_link_diag_state { 1361 struct mbox_header header; 1362 union { 1363 struct { 1364 uint32_t word0; 1365 #define lpfc_mbx_set_diag_state_diag_SHIFT 0 1366 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1367 #define lpfc_mbx_set_diag_state_diag_WORD word0 1368 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1369 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1370 #define lpfc_mbx_set_diag_state_link_num_WORD word0 1371 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1372 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1373 #define lpfc_mbx_set_diag_state_link_type_WORD word0 1374 } req; 1375 struct { 1376 uint32_t word0; 1377 } rsp; 1378 } u; 1379 }; 1380 1381 struct lpfc_mbx_set_link_diag_loopback { 1382 struct mbox_header header; 1383 union { 1384 struct { 1385 uint32_t word0; 1386 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1387 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1388 #define lpfc_mbx_set_diag_lpbk_type_WORD word0 1389 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1390 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 1391 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 1392 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 1393 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 1394 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 1395 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 1396 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 1397 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 1398 } req; 1399 struct { 1400 uint32_t word0; 1401 } rsp; 1402 } u; 1403 }; 1404 1405 struct lpfc_mbx_run_link_diag_test { 1406 struct mbox_header header; 1407 union { 1408 struct { 1409 uint32_t word0; 1410 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16 1411 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 1412 #define lpfc_mbx_run_diag_test_link_num_WORD word0 1413 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22 1414 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 1415 #define lpfc_mbx_run_diag_test_link_type_WORD word0 1416 uint32_t word1; 1417 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0 1418 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 1419 #define lpfc_mbx_run_diag_test_test_id_WORD word1 1420 #define lpfc_mbx_run_diag_test_loops_SHIFT 16 1421 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 1422 #define lpfc_mbx_run_diag_test_loops_WORD word1 1423 uint32_t word2; 1424 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 1425 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 1426 #define lpfc_mbx_run_diag_test_test_ver_WORD word2 1427 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16 1428 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 1429 #define lpfc_mbx_run_diag_test_err_act_WORD word2 1430 } req; 1431 struct { 1432 uint32_t word0; 1433 } rsp; 1434 } u; 1435 }; 1436 1437 /* 1438 * struct lpfc_mbx_alloc_rsrc_extents: 1439 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 1440 * 6 words of header + 4 words of shared subcommand header + 1441 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 1442 * 1443 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 1444 * for extents payload. 1445 * 1446 * 212/2 (bytes per extent) = 106 extents. 1447 * 106/2 (extents per word) = 53 words. 1448 * lpfc_id_range id is statically size to 53. 1449 * 1450 * This mailbox definition is used for ALLOC or GET_ALLOCATED 1451 * extent ranges. For ALLOC, the type and cnt are required. 1452 * For GET_ALLOCATED, only the type is required. 1453 */ 1454 struct lpfc_mbx_alloc_rsrc_extents { 1455 struct mbox_header header; 1456 union { 1457 struct { 1458 uint32_t word4; 1459 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 1460 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 1461 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 1462 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 1463 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 1464 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 1465 } req; 1466 struct { 1467 uint32_t word4; 1468 #define lpfc_mbx_rsrc_cnt_SHIFT 0 1469 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 1470 #define lpfc_mbx_rsrc_cnt_WORD word4 1471 struct lpfc_id_range id[53]; 1472 } rsp; 1473 } u; 1474 }; 1475 1476 /* 1477 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 1478 * structure shares the same SHIFT/MASK/WORD defines provided in the 1479 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 1480 * the structures defined above. This non-embedded structure provides for the 1481 * maximum number of extents supported by the port. 1482 */ 1483 struct lpfc_mbx_nembed_rsrc_extent { 1484 union lpfc_sli4_cfg_shdr cfg_shdr; 1485 uint32_t word4; 1486 struct lpfc_id_range id; 1487 }; 1488 1489 struct lpfc_mbx_dealloc_rsrc_extents { 1490 struct mbox_header header; 1491 struct { 1492 uint32_t word4; 1493 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 1494 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 1495 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 1496 } req; 1497 1498 }; 1499 1500 /* Start SLI4 FCoE specific mbox structures. */ 1501 1502 struct lpfc_mbx_post_hdr_tmpl { 1503 struct mbox_header header; 1504 uint32_t word10; 1505 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 1506 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 1507 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 1508 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 1509 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 1510 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 1511 uint32_t rpi_paddr_lo; 1512 uint32_t rpi_paddr_hi; 1513 }; 1514 1515 struct sli4_sge { /* SLI-4 */ 1516 uint32_t addr_hi; 1517 uint32_t addr_lo; 1518 1519 uint32_t word2; 1520 #define lpfc_sli4_sge_offset_SHIFT 0 1521 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 1522 #define lpfc_sli4_sge_offset_WORD word2 1523 #define lpfc_sli4_sge_type_SHIFT 27 1524 #define lpfc_sli4_sge_type_MASK 0x0000000F 1525 #define lpfc_sli4_sge_type_WORD word2 1526 #define LPFC_SGE_TYPE_DATA 0x0 1527 #define LPFC_SGE_TYPE_DIF 0x4 1528 #define LPFC_SGE_TYPE_LSP 0x5 1529 #define LPFC_SGE_TYPE_PEDIF 0x6 1530 #define LPFC_SGE_TYPE_PESEED 0x7 1531 #define LPFC_SGE_TYPE_DISEED 0x8 1532 #define LPFC_SGE_TYPE_ENC 0x9 1533 #define LPFC_SGE_TYPE_ATM 0xA 1534 #define LPFC_SGE_TYPE_SKIP 0xC 1535 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1536 #define lpfc_sli4_sge_last_MASK 0x00000001 1537 #define lpfc_sli4_sge_last_WORD word2 1538 uint32_t sge_len; 1539 }; 1540 1541 struct sli4_sge_diseed { /* SLI-4 */ 1542 uint32_t ref_tag; 1543 uint32_t ref_tag_tran; 1544 1545 uint32_t word2; 1546 #define lpfc_sli4_sge_dif_apptran_SHIFT 0 1547 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 1548 #define lpfc_sli4_sge_dif_apptran_WORD word2 1549 #define lpfc_sli4_sge_dif_af_SHIFT 24 1550 #define lpfc_sli4_sge_dif_af_MASK 0x00000001 1551 #define lpfc_sli4_sge_dif_af_WORD word2 1552 #define lpfc_sli4_sge_dif_na_SHIFT 25 1553 #define lpfc_sli4_sge_dif_na_MASK 0x00000001 1554 #define lpfc_sli4_sge_dif_na_WORD word2 1555 #define lpfc_sli4_sge_dif_hi_SHIFT 26 1556 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001 1557 #define lpfc_sli4_sge_dif_hi_WORD word2 1558 #define lpfc_sli4_sge_dif_type_SHIFT 27 1559 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F 1560 #define lpfc_sli4_sge_dif_type_WORD word2 1561 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1562 #define lpfc_sli4_sge_dif_last_MASK 0x00000001 1563 #define lpfc_sli4_sge_dif_last_WORD word2 1564 uint32_t word3; 1565 #define lpfc_sli4_sge_dif_apptag_SHIFT 0 1566 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 1567 #define lpfc_sli4_sge_dif_apptag_WORD word3 1568 #define lpfc_sli4_sge_dif_bs_SHIFT 16 1569 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007 1570 #define lpfc_sli4_sge_dif_bs_WORD word3 1571 #define lpfc_sli4_sge_dif_ai_SHIFT 19 1572 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001 1573 #define lpfc_sli4_sge_dif_ai_WORD word3 1574 #define lpfc_sli4_sge_dif_me_SHIFT 20 1575 #define lpfc_sli4_sge_dif_me_MASK 0x00000001 1576 #define lpfc_sli4_sge_dif_me_WORD word3 1577 #define lpfc_sli4_sge_dif_re_SHIFT 21 1578 #define lpfc_sli4_sge_dif_re_MASK 0x00000001 1579 #define lpfc_sli4_sge_dif_re_WORD word3 1580 #define lpfc_sli4_sge_dif_ce_SHIFT 22 1581 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001 1582 #define lpfc_sli4_sge_dif_ce_WORD word3 1583 #define lpfc_sli4_sge_dif_nr_SHIFT 23 1584 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001 1585 #define lpfc_sli4_sge_dif_nr_WORD word3 1586 #define lpfc_sli4_sge_dif_oprx_SHIFT 24 1587 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 1588 #define lpfc_sli4_sge_dif_oprx_WORD word3 1589 #define lpfc_sli4_sge_dif_optx_SHIFT 28 1590 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 1591 #define lpfc_sli4_sge_dif_optx_WORD word3 1592 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 1593 }; 1594 1595 struct fcf_record { 1596 uint32_t max_rcv_size; 1597 uint32_t fka_adv_period; 1598 uint32_t fip_priority; 1599 uint32_t word3; 1600 #define lpfc_fcf_record_mac_0_SHIFT 0 1601 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 1602 #define lpfc_fcf_record_mac_0_WORD word3 1603 #define lpfc_fcf_record_mac_1_SHIFT 8 1604 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 1605 #define lpfc_fcf_record_mac_1_WORD word3 1606 #define lpfc_fcf_record_mac_2_SHIFT 16 1607 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 1608 #define lpfc_fcf_record_mac_2_WORD word3 1609 #define lpfc_fcf_record_mac_3_SHIFT 24 1610 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 1611 #define lpfc_fcf_record_mac_3_WORD word3 1612 uint32_t word4; 1613 #define lpfc_fcf_record_mac_4_SHIFT 0 1614 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 1615 #define lpfc_fcf_record_mac_4_WORD word4 1616 #define lpfc_fcf_record_mac_5_SHIFT 8 1617 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 1618 #define lpfc_fcf_record_mac_5_WORD word4 1619 #define lpfc_fcf_record_fcf_avail_SHIFT 16 1620 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 1621 #define lpfc_fcf_record_fcf_avail_WORD word4 1622 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 1623 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 1624 #define lpfc_fcf_record_mac_addr_prov_WORD word4 1625 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 1626 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 1627 uint32_t word5; 1628 #define lpfc_fcf_record_fab_name_0_SHIFT 0 1629 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 1630 #define lpfc_fcf_record_fab_name_0_WORD word5 1631 #define lpfc_fcf_record_fab_name_1_SHIFT 8 1632 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 1633 #define lpfc_fcf_record_fab_name_1_WORD word5 1634 #define lpfc_fcf_record_fab_name_2_SHIFT 16 1635 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 1636 #define lpfc_fcf_record_fab_name_2_WORD word5 1637 #define lpfc_fcf_record_fab_name_3_SHIFT 24 1638 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 1639 #define lpfc_fcf_record_fab_name_3_WORD word5 1640 uint32_t word6; 1641 #define lpfc_fcf_record_fab_name_4_SHIFT 0 1642 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 1643 #define lpfc_fcf_record_fab_name_4_WORD word6 1644 #define lpfc_fcf_record_fab_name_5_SHIFT 8 1645 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 1646 #define lpfc_fcf_record_fab_name_5_WORD word6 1647 #define lpfc_fcf_record_fab_name_6_SHIFT 16 1648 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 1649 #define lpfc_fcf_record_fab_name_6_WORD word6 1650 #define lpfc_fcf_record_fab_name_7_SHIFT 24 1651 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 1652 #define lpfc_fcf_record_fab_name_7_WORD word6 1653 uint32_t word7; 1654 #define lpfc_fcf_record_fc_map_0_SHIFT 0 1655 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 1656 #define lpfc_fcf_record_fc_map_0_WORD word7 1657 #define lpfc_fcf_record_fc_map_1_SHIFT 8 1658 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 1659 #define lpfc_fcf_record_fc_map_1_WORD word7 1660 #define lpfc_fcf_record_fc_map_2_SHIFT 16 1661 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 1662 #define lpfc_fcf_record_fc_map_2_WORD word7 1663 #define lpfc_fcf_record_fcf_valid_SHIFT 24 1664 #define lpfc_fcf_record_fcf_valid_MASK 0x000000FF 1665 #define lpfc_fcf_record_fcf_valid_WORD word7 1666 uint32_t word8; 1667 #define lpfc_fcf_record_fcf_index_SHIFT 0 1668 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 1669 #define lpfc_fcf_record_fcf_index_WORD word8 1670 #define lpfc_fcf_record_fcf_state_SHIFT 16 1671 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 1672 #define lpfc_fcf_record_fcf_state_WORD word8 1673 uint8_t vlan_bitmap[512]; 1674 uint32_t word137; 1675 #define lpfc_fcf_record_switch_name_0_SHIFT 0 1676 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 1677 #define lpfc_fcf_record_switch_name_0_WORD word137 1678 #define lpfc_fcf_record_switch_name_1_SHIFT 8 1679 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 1680 #define lpfc_fcf_record_switch_name_1_WORD word137 1681 #define lpfc_fcf_record_switch_name_2_SHIFT 16 1682 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 1683 #define lpfc_fcf_record_switch_name_2_WORD word137 1684 #define lpfc_fcf_record_switch_name_3_SHIFT 24 1685 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 1686 #define lpfc_fcf_record_switch_name_3_WORD word137 1687 uint32_t word138; 1688 #define lpfc_fcf_record_switch_name_4_SHIFT 0 1689 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 1690 #define lpfc_fcf_record_switch_name_4_WORD word138 1691 #define lpfc_fcf_record_switch_name_5_SHIFT 8 1692 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 1693 #define lpfc_fcf_record_switch_name_5_WORD word138 1694 #define lpfc_fcf_record_switch_name_6_SHIFT 16 1695 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 1696 #define lpfc_fcf_record_switch_name_6_WORD word138 1697 #define lpfc_fcf_record_switch_name_7_SHIFT 24 1698 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 1699 #define lpfc_fcf_record_switch_name_7_WORD word138 1700 }; 1701 1702 struct lpfc_mbx_read_fcf_tbl { 1703 union lpfc_sli4_cfg_shdr cfg_shdr; 1704 union { 1705 struct { 1706 uint32_t word10; 1707 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 1708 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 1709 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 1710 } request; 1711 struct { 1712 uint32_t eventag; 1713 } response; 1714 } u; 1715 uint32_t word11; 1716 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 1717 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 1718 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 1719 }; 1720 1721 struct lpfc_mbx_add_fcf_tbl_entry { 1722 union lpfc_sli4_cfg_shdr cfg_shdr; 1723 uint32_t word10; 1724 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 1725 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 1726 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 1727 struct lpfc_mbx_sge fcf_sge; 1728 }; 1729 1730 struct lpfc_mbx_del_fcf_tbl_entry { 1731 struct mbox_header header; 1732 uint32_t word10; 1733 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 1734 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 1735 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 1736 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 1737 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 1738 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 1739 }; 1740 1741 struct lpfc_mbx_redisc_fcf_tbl { 1742 struct mbox_header header; 1743 uint32_t word10; 1744 #define lpfc_mbx_redisc_fcf_count_SHIFT 0 1745 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 1746 #define lpfc_mbx_redisc_fcf_count_WORD word10 1747 uint32_t resvd; 1748 uint32_t word12; 1749 #define lpfc_mbx_redisc_fcf_index_SHIFT 0 1750 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 1751 #define lpfc_mbx_redisc_fcf_index_WORD word12 1752 }; 1753 1754 struct lpfc_mbx_query_fw_cfg { 1755 struct mbox_header header; 1756 uint32_t config_number; 1757 uint32_t asic_rev; 1758 uint32_t phys_port; 1759 uint32_t function_mode; 1760 /* firmware Function Mode */ 1761 #define lpfc_function_mode_toe_SHIFT 0 1762 #define lpfc_function_mode_toe_MASK 0x00000001 1763 #define lpfc_function_mode_toe_WORD function_mode 1764 #define lpfc_function_mode_nic_SHIFT 1 1765 #define lpfc_function_mode_nic_MASK 0x00000001 1766 #define lpfc_function_mode_nic_WORD function_mode 1767 #define lpfc_function_mode_rdma_SHIFT 2 1768 #define lpfc_function_mode_rdma_MASK 0x00000001 1769 #define lpfc_function_mode_rdma_WORD function_mode 1770 #define lpfc_function_mode_vm_SHIFT 3 1771 #define lpfc_function_mode_vm_MASK 0x00000001 1772 #define lpfc_function_mode_vm_WORD function_mode 1773 #define lpfc_function_mode_iscsi_i_SHIFT 4 1774 #define lpfc_function_mode_iscsi_i_MASK 0x00000001 1775 #define lpfc_function_mode_iscsi_i_WORD function_mode 1776 #define lpfc_function_mode_iscsi_t_SHIFT 5 1777 #define lpfc_function_mode_iscsi_t_MASK 0x00000001 1778 #define lpfc_function_mode_iscsi_t_WORD function_mode 1779 #define lpfc_function_mode_fcoe_i_SHIFT 6 1780 #define lpfc_function_mode_fcoe_i_MASK 0x00000001 1781 #define lpfc_function_mode_fcoe_i_WORD function_mode 1782 #define lpfc_function_mode_fcoe_t_SHIFT 7 1783 #define lpfc_function_mode_fcoe_t_MASK 0x00000001 1784 #define lpfc_function_mode_fcoe_t_WORD function_mode 1785 #define lpfc_function_mode_dal_SHIFT 8 1786 #define lpfc_function_mode_dal_MASK 0x00000001 1787 #define lpfc_function_mode_dal_WORD function_mode 1788 #define lpfc_function_mode_lro_SHIFT 9 1789 #define lpfc_function_mode_lro_MASK 0x00000001 1790 #define lpfc_function_mode_lro_WORD function_mode 1791 #define lpfc_function_mode_flex10_SHIFT 10 1792 #define lpfc_function_mode_flex10_MASK 0x00000001 1793 #define lpfc_function_mode_flex10_WORD function_mode 1794 #define lpfc_function_mode_ncsi_SHIFT 11 1795 #define lpfc_function_mode_ncsi_MASK 0x00000001 1796 #define lpfc_function_mode_ncsi_WORD function_mode 1797 }; 1798 1799 /* Status field for embedded SLI_CONFIG mailbox command */ 1800 #define STATUS_SUCCESS 0x0 1801 #define STATUS_FAILED 0x1 1802 #define STATUS_ILLEGAL_REQUEST 0x2 1803 #define STATUS_ILLEGAL_FIELD 0x3 1804 #define STATUS_INSUFFICIENT_BUFFER 0x4 1805 #define STATUS_UNAUTHORIZED_REQUEST 0x5 1806 #define STATUS_FLASHROM_SAVE_FAILED 0x17 1807 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 1808 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 1809 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 1810 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 1811 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 1812 #define STATUS_ASSERT_FAILED 0x1e 1813 #define STATUS_INVALID_SESSION 0x1f 1814 #define STATUS_INVALID_CONNECTION 0x20 1815 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 1816 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 1817 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 1818 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 1819 #define STATUS_FLASHROM_READ_FAILED 0x27 1820 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 1821 #define STATUS_ERROR_ACITMAIN 0x2a 1822 #define STATUS_REBOOT_REQUIRED 0x2c 1823 #define STATUS_FCF_IN_USE 0x3a 1824 #define STATUS_FCF_TABLE_EMPTY 0x43 1825 1826 struct lpfc_mbx_sli4_config { 1827 struct mbox_header header; 1828 }; 1829 1830 struct lpfc_mbx_init_vfi { 1831 uint32_t word1; 1832 #define lpfc_init_vfi_vr_SHIFT 31 1833 #define lpfc_init_vfi_vr_MASK 0x00000001 1834 #define lpfc_init_vfi_vr_WORD word1 1835 #define lpfc_init_vfi_vt_SHIFT 30 1836 #define lpfc_init_vfi_vt_MASK 0x00000001 1837 #define lpfc_init_vfi_vt_WORD word1 1838 #define lpfc_init_vfi_vf_SHIFT 29 1839 #define lpfc_init_vfi_vf_MASK 0x00000001 1840 #define lpfc_init_vfi_vf_WORD word1 1841 #define lpfc_init_vfi_vp_SHIFT 28 1842 #define lpfc_init_vfi_vp_MASK 0x00000001 1843 #define lpfc_init_vfi_vp_WORD word1 1844 #define lpfc_init_vfi_vfi_SHIFT 0 1845 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 1846 #define lpfc_init_vfi_vfi_WORD word1 1847 uint32_t word2; 1848 #define lpfc_init_vfi_vpi_SHIFT 16 1849 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF 1850 #define lpfc_init_vfi_vpi_WORD word2 1851 #define lpfc_init_vfi_fcfi_SHIFT 0 1852 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 1853 #define lpfc_init_vfi_fcfi_WORD word2 1854 uint32_t word3; 1855 #define lpfc_init_vfi_pri_SHIFT 13 1856 #define lpfc_init_vfi_pri_MASK 0x00000007 1857 #define lpfc_init_vfi_pri_WORD word3 1858 #define lpfc_init_vfi_vf_id_SHIFT 1 1859 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 1860 #define lpfc_init_vfi_vf_id_WORD word3 1861 uint32_t word4; 1862 #define lpfc_init_vfi_hop_count_SHIFT 24 1863 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 1864 #define lpfc_init_vfi_hop_count_WORD word4 1865 }; 1866 #define MBX_VFI_IN_USE 0x9F02 1867 1868 1869 struct lpfc_mbx_reg_vfi { 1870 uint32_t word1; 1871 #define lpfc_reg_vfi_vp_SHIFT 28 1872 #define lpfc_reg_vfi_vp_MASK 0x00000001 1873 #define lpfc_reg_vfi_vp_WORD word1 1874 #define lpfc_reg_vfi_vfi_SHIFT 0 1875 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 1876 #define lpfc_reg_vfi_vfi_WORD word1 1877 uint32_t word2; 1878 #define lpfc_reg_vfi_vpi_SHIFT 16 1879 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 1880 #define lpfc_reg_vfi_vpi_WORD word2 1881 #define lpfc_reg_vfi_fcfi_SHIFT 0 1882 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 1883 #define lpfc_reg_vfi_fcfi_WORD word2 1884 uint32_t wwn[2]; 1885 struct ulp_bde64 bde; 1886 uint32_t e_d_tov; 1887 uint32_t r_a_tov; 1888 uint32_t word10; 1889 #define lpfc_reg_vfi_nport_id_SHIFT 0 1890 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 1891 #define lpfc_reg_vfi_nport_id_WORD word10 1892 }; 1893 1894 struct lpfc_mbx_init_vpi { 1895 uint32_t word1; 1896 #define lpfc_init_vpi_vfi_SHIFT 16 1897 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 1898 #define lpfc_init_vpi_vfi_WORD word1 1899 #define lpfc_init_vpi_vpi_SHIFT 0 1900 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 1901 #define lpfc_init_vpi_vpi_WORD word1 1902 }; 1903 1904 struct lpfc_mbx_read_vpi { 1905 uint32_t word1_rsvd; 1906 uint32_t word2; 1907 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 1908 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 1909 #define lpfc_mbx_read_vpi_vnportid_WORD word2 1910 uint32_t word3_rsvd; 1911 uint32_t word4; 1912 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 1913 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 1914 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 1915 #define lpfc_mbx_read_vpi_pb_SHIFT 15 1916 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 1917 #define lpfc_mbx_read_vpi_pb_WORD word4 1918 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 1919 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 1920 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 1921 #define lpfc_mbx_read_vpi_ns_SHIFT 30 1922 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 1923 #define lpfc_mbx_read_vpi_ns_WORD word4 1924 #define lpfc_mbx_read_vpi_hl_SHIFT 31 1925 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 1926 #define lpfc_mbx_read_vpi_hl_WORD word4 1927 uint32_t word5_rsvd; 1928 uint32_t word6; 1929 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 1930 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 1931 #define lpfc_mbx_read_vpi_vpi_WORD word6 1932 uint32_t word7; 1933 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 1934 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 1935 #define lpfc_mbx_read_vpi_mac_0_WORD word7 1936 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 1937 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 1938 #define lpfc_mbx_read_vpi_mac_1_WORD word7 1939 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 1940 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 1941 #define lpfc_mbx_read_vpi_mac_2_WORD word7 1942 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 1943 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 1944 #define lpfc_mbx_read_vpi_mac_3_WORD word7 1945 uint32_t word8; 1946 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 1947 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 1948 #define lpfc_mbx_read_vpi_mac_4_WORD word8 1949 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 1950 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 1951 #define lpfc_mbx_read_vpi_mac_5_WORD word8 1952 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 1953 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 1954 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 1955 #define lpfc_mbx_read_vpi_vv_SHIFT 28 1956 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 1957 #define lpfc_mbx_read_vpi_vv_WORD word8 1958 }; 1959 1960 struct lpfc_mbx_unreg_vfi { 1961 uint32_t word1_rsvd; 1962 uint32_t word2; 1963 #define lpfc_unreg_vfi_vfi_SHIFT 0 1964 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 1965 #define lpfc_unreg_vfi_vfi_WORD word2 1966 }; 1967 1968 struct lpfc_mbx_resume_rpi { 1969 uint32_t word1; 1970 #define lpfc_resume_rpi_index_SHIFT 0 1971 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 1972 #define lpfc_resume_rpi_index_WORD word1 1973 #define lpfc_resume_rpi_ii_SHIFT 30 1974 #define lpfc_resume_rpi_ii_MASK 0x00000003 1975 #define lpfc_resume_rpi_ii_WORD word1 1976 #define RESUME_INDEX_RPI 0 1977 #define RESUME_INDEX_VPI 1 1978 #define RESUME_INDEX_VFI 2 1979 #define RESUME_INDEX_FCFI 3 1980 uint32_t event_tag; 1981 }; 1982 1983 #define REG_FCF_INVALID_QID 0xFFFF 1984 struct lpfc_mbx_reg_fcfi { 1985 uint32_t word1; 1986 #define lpfc_reg_fcfi_info_index_SHIFT 0 1987 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 1988 #define lpfc_reg_fcfi_info_index_WORD word1 1989 #define lpfc_reg_fcfi_fcfi_SHIFT 16 1990 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 1991 #define lpfc_reg_fcfi_fcfi_WORD word1 1992 uint32_t word2; 1993 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 1994 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 1995 #define lpfc_reg_fcfi_rq_id1_WORD word2 1996 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 1997 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 1998 #define lpfc_reg_fcfi_rq_id0_WORD word2 1999 uint32_t word3; 2000 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 2001 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2002 #define lpfc_reg_fcfi_rq_id3_WORD word3 2003 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 2004 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2005 #define lpfc_reg_fcfi_rq_id2_WORD word3 2006 uint32_t word4; 2007 #define lpfc_reg_fcfi_type_match0_SHIFT 24 2008 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2009 #define lpfc_reg_fcfi_type_match0_WORD word4 2010 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 2011 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2012 #define lpfc_reg_fcfi_type_mask0_WORD word4 2013 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2014 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2015 #define lpfc_reg_fcfi_rctl_match0_WORD word4 2016 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2017 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2018 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 2019 uint32_t word5; 2020 #define lpfc_reg_fcfi_type_match1_SHIFT 24 2021 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2022 #define lpfc_reg_fcfi_type_match1_WORD word5 2023 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 2024 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2025 #define lpfc_reg_fcfi_type_mask1_WORD word5 2026 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2027 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2028 #define lpfc_reg_fcfi_rctl_match1_WORD word5 2029 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2030 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2031 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 2032 uint32_t word6; 2033 #define lpfc_reg_fcfi_type_match2_SHIFT 24 2034 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2035 #define lpfc_reg_fcfi_type_match2_WORD word6 2036 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 2037 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2038 #define lpfc_reg_fcfi_type_mask2_WORD word6 2039 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2040 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2041 #define lpfc_reg_fcfi_rctl_match2_WORD word6 2042 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2043 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2044 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 2045 uint32_t word7; 2046 #define lpfc_reg_fcfi_type_match3_SHIFT 24 2047 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2048 #define lpfc_reg_fcfi_type_match3_WORD word7 2049 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 2050 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2051 #define lpfc_reg_fcfi_type_mask3_WORD word7 2052 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2053 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2054 #define lpfc_reg_fcfi_rctl_match3_WORD word7 2055 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2056 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2057 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 2058 uint32_t word8; 2059 #define lpfc_reg_fcfi_mam_SHIFT 13 2060 #define lpfc_reg_fcfi_mam_MASK 0x00000003 2061 #define lpfc_reg_fcfi_mam_WORD word8 2062 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2063 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2064 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2065 #define lpfc_reg_fcfi_vv_SHIFT 12 2066 #define lpfc_reg_fcfi_vv_MASK 0x00000001 2067 #define lpfc_reg_fcfi_vv_WORD word8 2068 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2069 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2070 #define lpfc_reg_fcfi_vlan_tag_WORD word8 2071 }; 2072 2073 struct lpfc_mbx_unreg_fcfi { 2074 uint32_t word1_rsv; 2075 uint32_t word2; 2076 #define lpfc_unreg_fcfi_SHIFT 0 2077 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 2078 #define lpfc_unreg_fcfi_WORD word2 2079 }; 2080 2081 struct lpfc_mbx_read_rev { 2082 uint32_t word1; 2083 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2084 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2085 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2086 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2087 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2088 #define lpfc_mbx_rd_rev_fcoe_WORD word1 2089 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2090 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2091 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 2092 #define LPFC_PREDCBX_CEE_MODE 0 2093 #define LPFC_DCBX_CEE_MODE 1 2094 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 2095 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2096 #define lpfc_mbx_rd_rev_vpd_WORD word1 2097 uint32_t first_hw_rev; 2098 uint32_t second_hw_rev; 2099 uint32_t word4_rsvd; 2100 uint32_t third_hw_rev; 2101 uint32_t word6; 2102 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2103 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2104 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 2105 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2106 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2107 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 2108 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2109 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2110 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2111 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2112 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2113 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2114 uint32_t word7_rsvd; 2115 uint32_t fw_id_rev; 2116 uint8_t fw_name[16]; 2117 uint32_t ulp_fw_id_rev; 2118 uint8_t ulp_fw_name[16]; 2119 uint32_t word18_47_rsvd[30]; 2120 uint32_t word48; 2121 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2122 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2123 #define lpfc_mbx_rd_rev_avail_len_WORD word48 2124 uint32_t vpd_paddr_low; 2125 uint32_t vpd_paddr_high; 2126 uint32_t avail_vpd_len; 2127 uint32_t rsvd_52_63[12]; 2128 }; 2129 2130 struct lpfc_mbx_read_config { 2131 uint32_t word1; 2132 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2133 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2134 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2135 uint32_t word2; 2136 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2137 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2138 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2139 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2140 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2141 #define lpfc_mbx_rd_conf_lnk_type_WORD word2 2142 #define LPFC_LNK_TYPE_GE 0 2143 #define LPFC_LNK_TYPE_FC 1 2144 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2145 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2146 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2147 #define lpfc_mbx_rd_conf_topology_SHIFT 24 2148 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2149 #define lpfc_mbx_rd_conf_topology_WORD word2 2150 uint32_t rsvd_3; 2151 uint32_t word4; 2152 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2153 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2154 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2155 uint32_t rsvd_5; 2156 uint32_t word6; 2157 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2158 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2159 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2160 uint32_t rsvd_7; 2161 uint32_t rsvd_8; 2162 uint32_t word9; 2163 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 2164 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2165 #define lpfc_mbx_rd_conf_lmt_WORD word9 2166 uint32_t rsvd_10; 2167 uint32_t rsvd_11; 2168 uint32_t word12; 2169 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2170 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2171 #define lpfc_mbx_rd_conf_xri_base_WORD word12 2172 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2173 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2174 #define lpfc_mbx_rd_conf_xri_count_WORD word12 2175 uint32_t word13; 2176 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2177 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2178 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 2179 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2180 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2181 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 2182 uint32_t word14; 2183 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2184 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2185 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 2186 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2187 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2188 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 2189 uint32_t word15; 2190 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2191 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2192 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 2193 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2194 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2195 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 2196 uint32_t word16; 2197 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2198 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2199 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2200 uint32_t word17; 2201 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2202 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2203 #define lpfc_mbx_rd_conf_rq_count_WORD word17 2204 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 2205 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 2206 #define lpfc_mbx_rd_conf_eq_count_WORD word17 2207 uint32_t word18; 2208 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 2209 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 2210 #define lpfc_mbx_rd_conf_wq_count_WORD word18 2211 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 2212 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 2213 #define lpfc_mbx_rd_conf_cq_count_WORD word18 2214 }; 2215 2216 struct lpfc_mbx_request_features { 2217 uint32_t word1; 2218 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 2219 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 2220 #define lpfc_mbx_rq_ftr_qry_WORD word1 2221 uint32_t word2; 2222 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 2223 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 2224 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 2225 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 2226 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 2227 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 2228 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 2229 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 2230 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 2231 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 2232 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 2233 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 2234 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 2235 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 2236 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 2237 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 2238 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 2239 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 2240 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 2241 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 2242 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 2243 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 2244 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 2245 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 2246 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 2247 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 2248 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 2249 uint32_t word3; 2250 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 2251 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 2252 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 2253 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 2254 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 2255 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 2256 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 2257 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 2258 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 2259 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 2260 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 2261 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 2262 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 2263 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 2264 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 2265 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 2266 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 2267 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 2268 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 2269 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 2270 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 2271 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 2272 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 2273 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 2274 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 2275 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 2276 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 2277 }; 2278 2279 struct lpfc_mbx_supp_pages { 2280 uint32_t word1; 2281 #define qs_SHIFT 0 2282 #define qs_MASK 0x00000001 2283 #define qs_WORD word1 2284 #define wr_SHIFT 1 2285 #define wr_MASK 0x00000001 2286 #define wr_WORD word1 2287 #define pf_SHIFT 8 2288 #define pf_MASK 0x000000ff 2289 #define pf_WORD word1 2290 #define cpn_SHIFT 16 2291 #define cpn_MASK 0x000000ff 2292 #define cpn_WORD word1 2293 uint32_t word2; 2294 #define list_offset_SHIFT 0 2295 #define list_offset_MASK 0x000000ff 2296 #define list_offset_WORD word2 2297 #define next_offset_SHIFT 8 2298 #define next_offset_MASK 0x000000ff 2299 #define next_offset_WORD word2 2300 #define elem_cnt_SHIFT 16 2301 #define elem_cnt_MASK 0x000000ff 2302 #define elem_cnt_WORD word2 2303 uint32_t word3; 2304 #define pn_0_SHIFT 24 2305 #define pn_0_MASK 0x000000ff 2306 #define pn_0_WORD word3 2307 #define pn_1_SHIFT 16 2308 #define pn_1_MASK 0x000000ff 2309 #define pn_1_WORD word3 2310 #define pn_2_SHIFT 8 2311 #define pn_2_MASK 0x000000ff 2312 #define pn_2_WORD word3 2313 #define pn_3_SHIFT 0 2314 #define pn_3_MASK 0x000000ff 2315 #define pn_3_WORD word3 2316 uint32_t word4; 2317 #define pn_4_SHIFT 24 2318 #define pn_4_MASK 0x000000ff 2319 #define pn_4_WORD word4 2320 #define pn_5_SHIFT 16 2321 #define pn_5_MASK 0x000000ff 2322 #define pn_5_WORD word4 2323 #define pn_6_SHIFT 8 2324 #define pn_6_MASK 0x000000ff 2325 #define pn_6_WORD word4 2326 #define pn_7_SHIFT 0 2327 #define pn_7_MASK 0x000000ff 2328 #define pn_7_WORD word4 2329 uint32_t rsvd[27]; 2330 #define LPFC_SUPP_PAGES 0 2331 #define LPFC_BLOCK_GUARD_PROFILES 1 2332 #define LPFC_SLI4_PARAMETERS 2 2333 }; 2334 2335 struct lpfc_mbx_pc_sli4_params { 2336 uint32_t word1; 2337 #define qs_SHIFT 0 2338 #define qs_MASK 0x00000001 2339 #define qs_WORD word1 2340 #define wr_SHIFT 1 2341 #define wr_MASK 0x00000001 2342 #define wr_WORD word1 2343 #define pf_SHIFT 8 2344 #define pf_MASK 0x000000ff 2345 #define pf_WORD word1 2346 #define cpn_SHIFT 16 2347 #define cpn_MASK 0x000000ff 2348 #define cpn_WORD word1 2349 uint32_t word2; 2350 #define if_type_SHIFT 0 2351 #define if_type_MASK 0x00000007 2352 #define if_type_WORD word2 2353 #define sli_rev_SHIFT 4 2354 #define sli_rev_MASK 0x0000000f 2355 #define sli_rev_WORD word2 2356 #define sli_family_SHIFT 8 2357 #define sli_family_MASK 0x000000ff 2358 #define sli_family_WORD word2 2359 #define featurelevel_1_SHIFT 16 2360 #define featurelevel_1_MASK 0x000000ff 2361 #define featurelevel_1_WORD word2 2362 #define featurelevel_2_SHIFT 24 2363 #define featurelevel_2_MASK 0x0000001f 2364 #define featurelevel_2_WORD word2 2365 uint32_t word3; 2366 #define fcoe_SHIFT 0 2367 #define fcoe_MASK 0x00000001 2368 #define fcoe_WORD word3 2369 #define fc_SHIFT 1 2370 #define fc_MASK 0x00000001 2371 #define fc_WORD word3 2372 #define nic_SHIFT 2 2373 #define nic_MASK 0x00000001 2374 #define nic_WORD word3 2375 #define iscsi_SHIFT 3 2376 #define iscsi_MASK 0x00000001 2377 #define iscsi_WORD word3 2378 #define rdma_SHIFT 4 2379 #define rdma_MASK 0x00000001 2380 #define rdma_WORD word3 2381 uint32_t sge_supp_len; 2382 #define SLI4_PAGE_SIZE 4096 2383 uint32_t word5; 2384 #define if_page_sz_SHIFT 0 2385 #define if_page_sz_MASK 0x0000ffff 2386 #define if_page_sz_WORD word5 2387 #define loopbk_scope_SHIFT 24 2388 #define loopbk_scope_MASK 0x0000000f 2389 #define loopbk_scope_WORD word5 2390 #define rq_db_window_SHIFT 28 2391 #define rq_db_window_MASK 0x0000000f 2392 #define rq_db_window_WORD word5 2393 uint32_t word6; 2394 #define eq_pages_SHIFT 0 2395 #define eq_pages_MASK 0x0000000f 2396 #define eq_pages_WORD word6 2397 #define eqe_size_SHIFT 8 2398 #define eqe_size_MASK 0x000000ff 2399 #define eqe_size_WORD word6 2400 uint32_t word7; 2401 #define cq_pages_SHIFT 0 2402 #define cq_pages_MASK 0x0000000f 2403 #define cq_pages_WORD word7 2404 #define cqe_size_SHIFT 8 2405 #define cqe_size_MASK 0x000000ff 2406 #define cqe_size_WORD word7 2407 uint32_t word8; 2408 #define mq_pages_SHIFT 0 2409 #define mq_pages_MASK 0x0000000f 2410 #define mq_pages_WORD word8 2411 #define mqe_size_SHIFT 8 2412 #define mqe_size_MASK 0x000000ff 2413 #define mqe_size_WORD word8 2414 #define mq_elem_cnt_SHIFT 16 2415 #define mq_elem_cnt_MASK 0x000000ff 2416 #define mq_elem_cnt_WORD word8 2417 uint32_t word9; 2418 #define wq_pages_SHIFT 0 2419 #define wq_pages_MASK 0x0000ffff 2420 #define wq_pages_WORD word9 2421 #define wqe_size_SHIFT 8 2422 #define wqe_size_MASK 0x000000ff 2423 #define wqe_size_WORD word9 2424 uint32_t word10; 2425 #define rq_pages_SHIFT 0 2426 #define rq_pages_MASK 0x0000ffff 2427 #define rq_pages_WORD word10 2428 #define rqe_size_SHIFT 8 2429 #define rqe_size_MASK 0x000000ff 2430 #define rqe_size_WORD word10 2431 uint32_t word11; 2432 #define hdr_pages_SHIFT 0 2433 #define hdr_pages_MASK 0x0000000f 2434 #define hdr_pages_WORD word11 2435 #define hdr_size_SHIFT 8 2436 #define hdr_size_MASK 0x0000000f 2437 #define hdr_size_WORD word11 2438 #define hdr_pp_align_SHIFT 16 2439 #define hdr_pp_align_MASK 0x0000ffff 2440 #define hdr_pp_align_WORD word11 2441 uint32_t word12; 2442 #define sgl_pages_SHIFT 0 2443 #define sgl_pages_MASK 0x0000000f 2444 #define sgl_pages_WORD word12 2445 #define sgl_pp_align_SHIFT 16 2446 #define sgl_pp_align_MASK 0x0000ffff 2447 #define sgl_pp_align_WORD word12 2448 uint32_t rsvd_13_63[51]; 2449 }; 2450 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 2451 &(~((SLI4_PAGE_SIZE)-1))) 2452 2453 struct lpfc_sli4_parameters { 2454 uint32_t word0; 2455 #define cfg_prot_type_SHIFT 0 2456 #define cfg_prot_type_MASK 0x000000FF 2457 #define cfg_prot_type_WORD word0 2458 uint32_t word1; 2459 #define cfg_ft_SHIFT 0 2460 #define cfg_ft_MASK 0x00000001 2461 #define cfg_ft_WORD word1 2462 #define cfg_sli_rev_SHIFT 4 2463 #define cfg_sli_rev_MASK 0x0000000f 2464 #define cfg_sli_rev_WORD word1 2465 #define cfg_sli_family_SHIFT 8 2466 #define cfg_sli_family_MASK 0x0000000f 2467 #define cfg_sli_family_WORD word1 2468 #define cfg_if_type_SHIFT 12 2469 #define cfg_if_type_MASK 0x0000000f 2470 #define cfg_if_type_WORD word1 2471 #define cfg_sli_hint_1_SHIFT 16 2472 #define cfg_sli_hint_1_MASK 0x000000ff 2473 #define cfg_sli_hint_1_WORD word1 2474 #define cfg_sli_hint_2_SHIFT 24 2475 #define cfg_sli_hint_2_MASK 0x0000001f 2476 #define cfg_sli_hint_2_WORD word1 2477 uint32_t word2; 2478 uint32_t word3; 2479 uint32_t word4; 2480 #define cfg_cqv_SHIFT 14 2481 #define cfg_cqv_MASK 0x00000003 2482 #define cfg_cqv_WORD word4 2483 uint32_t word5; 2484 uint32_t word6; 2485 #define cfg_mqv_SHIFT 14 2486 #define cfg_mqv_MASK 0x00000003 2487 #define cfg_mqv_WORD word6 2488 uint32_t word7; 2489 uint32_t word8; 2490 #define cfg_wqv_SHIFT 14 2491 #define cfg_wqv_MASK 0x00000003 2492 #define cfg_wqv_WORD word8 2493 uint32_t word9; 2494 uint32_t word10; 2495 #define cfg_rqv_SHIFT 14 2496 #define cfg_rqv_MASK 0x00000003 2497 #define cfg_rqv_WORD word10 2498 uint32_t word11; 2499 #define cfg_rq_db_window_SHIFT 28 2500 #define cfg_rq_db_window_MASK 0x0000000f 2501 #define cfg_rq_db_window_WORD word11 2502 uint32_t word12; 2503 #define cfg_fcoe_SHIFT 0 2504 #define cfg_fcoe_MASK 0x00000001 2505 #define cfg_fcoe_WORD word12 2506 #define cfg_ext_SHIFT 1 2507 #define cfg_ext_MASK 0x00000001 2508 #define cfg_ext_WORD word12 2509 #define cfg_hdrr_SHIFT 2 2510 #define cfg_hdrr_MASK 0x00000001 2511 #define cfg_hdrr_WORD word12 2512 #define cfg_phwq_SHIFT 15 2513 #define cfg_phwq_MASK 0x00000001 2514 #define cfg_phwq_WORD word12 2515 #define cfg_loopbk_scope_SHIFT 28 2516 #define cfg_loopbk_scope_MASK 0x0000000f 2517 #define cfg_loopbk_scope_WORD word12 2518 uint32_t sge_supp_len; 2519 uint32_t word14; 2520 #define cfg_sgl_page_cnt_SHIFT 0 2521 #define cfg_sgl_page_cnt_MASK 0x0000000f 2522 #define cfg_sgl_page_cnt_WORD word14 2523 #define cfg_sgl_page_size_SHIFT 8 2524 #define cfg_sgl_page_size_MASK 0x000000ff 2525 #define cfg_sgl_page_size_WORD word14 2526 #define cfg_sgl_pp_align_SHIFT 16 2527 #define cfg_sgl_pp_align_MASK 0x000000ff 2528 #define cfg_sgl_pp_align_WORD word14 2529 uint32_t word15; 2530 uint32_t word16; 2531 uint32_t word17; 2532 uint32_t word18; 2533 uint32_t word19; 2534 }; 2535 2536 struct lpfc_mbx_get_sli4_parameters { 2537 struct mbox_header header; 2538 struct lpfc_sli4_parameters sli4_parameters; 2539 }; 2540 2541 struct lpfc_rscr_desc_generic { 2542 #define LPFC_RSRC_DESC_WSIZE 18 2543 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 2544 }; 2545 2546 struct lpfc_rsrc_desc_pcie { 2547 uint32_t word0; 2548 #define lpfc_rsrc_desc_pcie_type_SHIFT 0 2549 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 2550 #define lpfc_rsrc_desc_pcie_type_WORD word0 2551 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40 2552 uint32_t word1; 2553 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 2554 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 2555 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1 2556 uint32_t reserved; 2557 uint32_t word3; 2558 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 2559 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 2560 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 2561 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 2562 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 2563 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 2564 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 2565 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 2566 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3 2567 uint32_t word4; 2568 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 2569 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 2570 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 2571 }; 2572 2573 struct lpfc_rsrc_desc_fcfcoe { 2574 uint32_t word0; 2575 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 2576 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 2577 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0 2578 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 2579 uint32_t word1; 2580 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 2581 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 2582 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 2583 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 2584 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 2585 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 2586 uint32_t word2; 2587 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 2588 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 2589 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 2590 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 2591 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 2592 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 2593 uint32_t word3; 2594 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 2595 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 2596 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 2597 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 2598 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 2599 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 2600 uint32_t word4; 2601 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 2602 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 2603 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 2604 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 2605 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 2606 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 2607 uint32_t word5; 2608 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 2609 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 2610 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 2611 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 2612 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 2613 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 2614 uint32_t word6; 2615 uint32_t word7; 2616 uint32_t word8; 2617 uint32_t word9; 2618 uint32_t word10; 2619 uint32_t word11; 2620 uint32_t word12; 2621 uint32_t word13; 2622 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 2623 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 2624 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 2625 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 2626 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 2627 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 2628 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 2629 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 2630 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 2631 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 2632 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 2633 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 2634 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 2635 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 2636 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 2637 }; 2638 2639 struct lpfc_func_cfg { 2640 #define LPFC_RSRC_DESC_MAX_NUM 2 2641 uint32_t rsrc_desc_count; 2642 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 2643 }; 2644 2645 struct lpfc_mbx_get_func_cfg { 2646 struct mbox_header header; 2647 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 2648 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 2649 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 2650 struct lpfc_func_cfg func_cfg; 2651 }; 2652 2653 struct lpfc_prof_cfg { 2654 #define LPFC_RSRC_DESC_MAX_NUM 2 2655 uint32_t rsrc_desc_count; 2656 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 2657 }; 2658 2659 struct lpfc_mbx_get_prof_cfg { 2660 struct mbox_header header; 2661 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 2662 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 2663 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 2664 union { 2665 struct { 2666 uint32_t word10; 2667 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 2668 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 2669 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 2670 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 2671 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 2672 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 2673 } request; 2674 struct { 2675 struct lpfc_prof_cfg prof_cfg; 2676 } response; 2677 } u; 2678 }; 2679 2680 struct lpfc_controller_attribute { 2681 uint32_t version_string[8]; 2682 uint32_t manufacturer_name[8]; 2683 uint32_t supported_modes; 2684 uint32_t word17; 2685 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 2686 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 2687 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17 2688 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 2689 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 2690 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17 2691 uint32_t mbx_da_struct_ver; 2692 uint32_t ep_fw_da_struct_ver; 2693 uint32_t ncsi_ver_str[3]; 2694 uint32_t dflt_ext_timeout; 2695 uint32_t model_number[8]; 2696 uint32_t description[16]; 2697 uint32_t serial_number[8]; 2698 uint32_t ip_ver_str[8]; 2699 uint32_t fw_ver_str[8]; 2700 uint32_t bios_ver_str[8]; 2701 uint32_t redboot_ver_str[8]; 2702 uint32_t driver_ver_str[8]; 2703 uint32_t flash_fw_ver_str[8]; 2704 uint32_t functionality; 2705 uint32_t word105; 2706 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0 2707 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 2708 #define lpfc_cntl_attr_max_cbd_len_WORD word105 2709 #define lpfc_cntl_attr_asic_rev_SHIFT 16 2710 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 2711 #define lpfc_cntl_attr_asic_rev_WORD word105 2712 #define lpfc_cntl_attr_gen_guid0_SHIFT 24 2713 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 2714 #define lpfc_cntl_attr_gen_guid0_WORD word105 2715 uint32_t gen_guid1_12[3]; 2716 uint32_t word109; 2717 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 2718 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 2719 #define lpfc_cntl_attr_gen_guid13_14_WORD word109 2720 #define lpfc_cntl_attr_gen_guid15_SHIFT 16 2721 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 2722 #define lpfc_cntl_attr_gen_guid15_WORD word109 2723 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 2724 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 2725 #define lpfc_cntl_attr_hba_port_cnt_WORD word109 2726 uint32_t word110; 2727 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 2728 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 2729 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 2730 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24 2731 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 2732 #define lpfc_cntl_attr_multi_func_dev_WORD word110 2733 uint32_t word111; 2734 #define lpfc_cntl_attr_cache_valid_SHIFT 0 2735 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 2736 #define lpfc_cntl_attr_cache_valid_WORD word111 2737 #define lpfc_cntl_attr_hba_status_SHIFT 8 2738 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff 2739 #define lpfc_cntl_attr_hba_status_WORD word111 2740 #define lpfc_cntl_attr_max_domain_SHIFT 16 2741 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff 2742 #define lpfc_cntl_attr_max_domain_WORD word111 2743 #define lpfc_cntl_attr_lnk_numb_SHIFT 24 2744 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 2745 #define lpfc_cntl_attr_lnk_numb_WORD word111 2746 #define lpfc_cntl_attr_lnk_type_SHIFT 30 2747 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003 2748 #define lpfc_cntl_attr_lnk_type_WORD word111 2749 uint32_t fw_post_status; 2750 uint32_t hba_mtu[8]; 2751 uint32_t word121; 2752 uint32_t reserved1[3]; 2753 uint32_t word125; 2754 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 2755 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 2756 #define lpfc_cntl_attr_pci_vendor_id_WORD word125 2757 #define lpfc_cntl_attr_pci_device_id_SHIFT 16 2758 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 2759 #define lpfc_cntl_attr_pci_device_id_WORD word125 2760 uint32_t word126; 2761 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 2762 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 2763 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126 2764 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 2765 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 2766 #define lpfc_cntl_attr_pci_subsys_id_WORD word126 2767 uint32_t word127; 2768 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0 2769 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 2770 #define lpfc_cntl_attr_pci_bus_num_WORD word127 2771 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8 2772 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 2773 #define lpfc_cntl_attr_pci_dev_num_WORD word127 2774 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 2775 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 2776 #define lpfc_cntl_attr_pci_fnc_num_WORD word127 2777 #define lpfc_cntl_attr_inf_type_SHIFT 24 2778 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff 2779 #define lpfc_cntl_attr_inf_type_WORD word127 2780 uint32_t unique_id[2]; 2781 uint32_t word130; 2782 #define lpfc_cntl_attr_num_netfil_SHIFT 0 2783 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 2784 #define lpfc_cntl_attr_num_netfil_WORD word130 2785 uint32_t reserved2[4]; 2786 }; 2787 2788 struct lpfc_mbx_get_cntl_attributes { 2789 union lpfc_sli4_cfg_shdr cfg_shdr; 2790 struct lpfc_controller_attribute cntl_attr; 2791 }; 2792 2793 struct lpfc_mbx_get_port_name { 2794 struct mbox_header header; 2795 union { 2796 struct { 2797 uint32_t word4; 2798 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 2799 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 2800 #define lpfc_mbx_get_port_name_lnk_type_WORD word4 2801 } request; 2802 struct { 2803 uint32_t word4; 2804 #define lpfc_mbx_get_port_name_name0_SHIFT 0 2805 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 2806 #define lpfc_mbx_get_port_name_name0_WORD word4 2807 #define lpfc_mbx_get_port_name_name1_SHIFT 8 2808 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 2809 #define lpfc_mbx_get_port_name_name1_WORD word4 2810 #define lpfc_mbx_get_port_name_name2_SHIFT 16 2811 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 2812 #define lpfc_mbx_get_port_name_name2_WORD word4 2813 #define lpfc_mbx_get_port_name_name3_SHIFT 24 2814 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 2815 #define lpfc_mbx_get_port_name_name3_WORD word4 2816 #define LPFC_LINK_NUMBER_0 0 2817 #define LPFC_LINK_NUMBER_1 1 2818 #define LPFC_LINK_NUMBER_2 2 2819 #define LPFC_LINK_NUMBER_3 3 2820 } response; 2821 } u; 2822 }; 2823 2824 /* Mailbox Completion Queue Error Messages */ 2825 #define MB_CQE_STATUS_SUCCESS 0x0 2826 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 2827 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 2828 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 2829 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 2830 #define MB_CQE_STATUS_DMA_FAILED 0x5 2831 2832 #define LPFC_MBX_WR_CONFIG_MAX_BDE 8 2833 struct lpfc_mbx_wr_object { 2834 struct mbox_header header; 2835 union { 2836 struct { 2837 uint32_t word4; 2838 #define lpfc_wr_object_eof_SHIFT 31 2839 #define lpfc_wr_object_eof_MASK 0x00000001 2840 #define lpfc_wr_object_eof_WORD word4 2841 #define lpfc_wr_object_write_length_SHIFT 0 2842 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF 2843 #define lpfc_wr_object_write_length_WORD word4 2844 uint32_t write_offset; 2845 uint32_t object_name[26]; 2846 uint32_t bde_count; 2847 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 2848 } request; 2849 struct { 2850 uint32_t actual_write_length; 2851 } response; 2852 } u; 2853 }; 2854 2855 /* mailbox queue entry structure */ 2856 struct lpfc_mqe { 2857 uint32_t word0; 2858 #define lpfc_mqe_status_SHIFT 16 2859 #define lpfc_mqe_status_MASK 0x0000FFFF 2860 #define lpfc_mqe_status_WORD word0 2861 #define lpfc_mqe_command_SHIFT 8 2862 #define lpfc_mqe_command_MASK 0x000000FF 2863 #define lpfc_mqe_command_WORD word0 2864 union { 2865 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 2866 /* sli4 mailbox commands */ 2867 struct lpfc_mbx_sli4_config sli4_config; 2868 struct lpfc_mbx_init_vfi init_vfi; 2869 struct lpfc_mbx_reg_vfi reg_vfi; 2870 struct lpfc_mbx_reg_vfi unreg_vfi; 2871 struct lpfc_mbx_init_vpi init_vpi; 2872 struct lpfc_mbx_resume_rpi resume_rpi; 2873 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 2874 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 2875 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 2876 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 2877 struct lpfc_mbx_reg_fcfi reg_fcfi; 2878 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 2879 struct lpfc_mbx_mq_create mq_create; 2880 struct lpfc_mbx_mq_create_ext mq_create_ext; 2881 struct lpfc_mbx_eq_create eq_create; 2882 struct lpfc_mbx_cq_create cq_create; 2883 struct lpfc_mbx_wq_create wq_create; 2884 struct lpfc_mbx_rq_create rq_create; 2885 struct lpfc_mbx_mq_destroy mq_destroy; 2886 struct lpfc_mbx_eq_destroy eq_destroy; 2887 struct lpfc_mbx_cq_destroy cq_destroy; 2888 struct lpfc_mbx_wq_destroy wq_destroy; 2889 struct lpfc_mbx_rq_destroy rq_destroy; 2890 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 2891 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 2892 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 2893 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 2894 struct lpfc_mbx_nembed_cmd nembed_cmd; 2895 struct lpfc_mbx_read_rev read_rev; 2896 struct lpfc_mbx_read_vpi read_vpi; 2897 struct lpfc_mbx_read_config rd_config; 2898 struct lpfc_mbx_request_features req_ftrs; 2899 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 2900 struct lpfc_mbx_query_fw_cfg query_fw_cfg; 2901 struct lpfc_mbx_supp_pages supp_pages; 2902 struct lpfc_mbx_pc_sli4_params sli4_params; 2903 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 2904 struct lpfc_mbx_set_link_diag_state link_diag_state; 2905 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 2906 struct lpfc_mbx_run_link_diag_test link_diag_test; 2907 struct lpfc_mbx_get_func_cfg get_func_cfg; 2908 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 2909 struct lpfc_mbx_wr_object wr_object; 2910 struct lpfc_mbx_get_port_name get_port_name; 2911 struct lpfc_mbx_nop nop; 2912 } un; 2913 }; 2914 2915 struct lpfc_mcqe { 2916 uint32_t word0; 2917 #define lpfc_mcqe_status_SHIFT 0 2918 #define lpfc_mcqe_status_MASK 0x0000FFFF 2919 #define lpfc_mcqe_status_WORD word0 2920 #define lpfc_mcqe_ext_status_SHIFT 16 2921 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 2922 #define lpfc_mcqe_ext_status_WORD word0 2923 uint32_t mcqe_tag0; 2924 uint32_t mcqe_tag1; 2925 uint32_t trailer; 2926 #define lpfc_trailer_valid_SHIFT 31 2927 #define lpfc_trailer_valid_MASK 0x00000001 2928 #define lpfc_trailer_valid_WORD trailer 2929 #define lpfc_trailer_async_SHIFT 30 2930 #define lpfc_trailer_async_MASK 0x00000001 2931 #define lpfc_trailer_async_WORD trailer 2932 #define lpfc_trailer_hpi_SHIFT 29 2933 #define lpfc_trailer_hpi_MASK 0x00000001 2934 #define lpfc_trailer_hpi_WORD trailer 2935 #define lpfc_trailer_completed_SHIFT 28 2936 #define lpfc_trailer_completed_MASK 0x00000001 2937 #define lpfc_trailer_completed_WORD trailer 2938 #define lpfc_trailer_consumed_SHIFT 27 2939 #define lpfc_trailer_consumed_MASK 0x00000001 2940 #define lpfc_trailer_consumed_WORD trailer 2941 #define lpfc_trailer_type_SHIFT 16 2942 #define lpfc_trailer_type_MASK 0x000000FF 2943 #define lpfc_trailer_type_WORD trailer 2944 #define lpfc_trailer_code_SHIFT 8 2945 #define lpfc_trailer_code_MASK 0x000000FF 2946 #define lpfc_trailer_code_WORD trailer 2947 #define LPFC_TRAILER_CODE_LINK 0x1 2948 #define LPFC_TRAILER_CODE_FCOE 0x2 2949 #define LPFC_TRAILER_CODE_DCBX 0x3 2950 #define LPFC_TRAILER_CODE_GRP5 0x5 2951 #define LPFC_TRAILER_CODE_FC 0x10 2952 #define LPFC_TRAILER_CODE_SLI 0x11 2953 }; 2954 2955 struct lpfc_acqe_link { 2956 uint32_t word0; 2957 #define lpfc_acqe_link_speed_SHIFT 24 2958 #define lpfc_acqe_link_speed_MASK 0x000000FF 2959 #define lpfc_acqe_link_speed_WORD word0 2960 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 2961 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 2962 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 2963 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 2964 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 2965 #define lpfc_acqe_link_duplex_SHIFT 16 2966 #define lpfc_acqe_link_duplex_MASK 0x000000FF 2967 #define lpfc_acqe_link_duplex_WORD word0 2968 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 2969 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 2970 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 2971 #define lpfc_acqe_link_status_SHIFT 8 2972 #define lpfc_acqe_link_status_MASK 0x000000FF 2973 #define lpfc_acqe_link_status_WORD word0 2974 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 2975 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 2976 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 2977 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 2978 #define lpfc_acqe_link_type_SHIFT 6 2979 #define lpfc_acqe_link_type_MASK 0x00000003 2980 #define lpfc_acqe_link_type_WORD word0 2981 #define lpfc_acqe_link_number_SHIFT 0 2982 #define lpfc_acqe_link_number_MASK 0x0000003F 2983 #define lpfc_acqe_link_number_WORD word0 2984 uint32_t word1; 2985 #define lpfc_acqe_link_fault_SHIFT 0 2986 #define lpfc_acqe_link_fault_MASK 0x000000FF 2987 #define lpfc_acqe_link_fault_WORD word1 2988 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 2989 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 2990 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 2991 #define lpfc_acqe_logical_link_speed_SHIFT 16 2992 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 2993 #define lpfc_acqe_logical_link_speed_WORD word1 2994 uint32_t event_tag; 2995 uint32_t trailer; 2996 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 2997 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 2998 }; 2999 3000 struct lpfc_acqe_fip { 3001 uint32_t index; 3002 uint32_t word1; 3003 #define lpfc_acqe_fip_fcf_count_SHIFT 0 3004 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 3005 #define lpfc_acqe_fip_fcf_count_WORD word1 3006 #define lpfc_acqe_fip_event_type_SHIFT 16 3007 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 3008 #define lpfc_acqe_fip_event_type_WORD word1 3009 uint32_t event_tag; 3010 uint32_t trailer; 3011 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 3012 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 3013 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 3014 #define LPFC_FIP_EVENT_TYPE_CVL 0x4 3015 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 3016 }; 3017 3018 struct lpfc_acqe_dcbx { 3019 uint32_t tlv_ttl; 3020 uint32_t reserved; 3021 uint32_t event_tag; 3022 uint32_t trailer; 3023 }; 3024 3025 struct lpfc_acqe_grp5 { 3026 uint32_t word0; 3027 #define lpfc_acqe_grp5_type_SHIFT 6 3028 #define lpfc_acqe_grp5_type_MASK 0x00000003 3029 #define lpfc_acqe_grp5_type_WORD word0 3030 #define lpfc_acqe_grp5_number_SHIFT 0 3031 #define lpfc_acqe_grp5_number_MASK 0x0000003F 3032 #define lpfc_acqe_grp5_number_WORD word0 3033 uint32_t word1; 3034 #define lpfc_acqe_grp5_llink_spd_SHIFT 16 3035 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 3036 #define lpfc_acqe_grp5_llink_spd_WORD word1 3037 uint32_t event_tag; 3038 uint32_t trailer; 3039 }; 3040 3041 struct lpfc_acqe_fc_la { 3042 uint32_t word0; 3043 #define lpfc_acqe_fc_la_speed_SHIFT 24 3044 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF 3045 #define lpfc_acqe_fc_la_speed_WORD word0 3046 #define LPFC_FC_LA_SPEED_UNKOWN 0x0 3047 #define LPFC_FC_LA_SPEED_1G 0x1 3048 #define LPFC_FC_LA_SPEED_2G 0x2 3049 #define LPFC_FC_LA_SPEED_4G 0x4 3050 #define LPFC_FC_LA_SPEED_8G 0x8 3051 #define LPFC_FC_LA_SPEED_10G 0xA 3052 #define LPFC_FC_LA_SPEED_16G 0x10 3053 #define lpfc_acqe_fc_la_topology_SHIFT 16 3054 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF 3055 #define lpfc_acqe_fc_la_topology_WORD word0 3056 #define LPFC_FC_LA_TOP_UNKOWN 0x0 3057 #define LPFC_FC_LA_TOP_P2P 0x1 3058 #define LPFC_FC_LA_TOP_FCAL 0x2 3059 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 3060 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 3061 #define lpfc_acqe_fc_la_att_type_SHIFT 8 3062 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 3063 #define lpfc_acqe_fc_la_att_type_WORD word0 3064 #define LPFC_FC_LA_TYPE_LINK_UP 0x1 3065 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 3066 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 3067 #define lpfc_acqe_fc_la_port_type_SHIFT 6 3068 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003 3069 #define lpfc_acqe_fc_la_port_type_WORD word0 3070 #define LPFC_LINK_TYPE_ETHERNET 0x0 3071 #define LPFC_LINK_TYPE_FC 0x1 3072 #define lpfc_acqe_fc_la_port_number_SHIFT 0 3073 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 3074 #define lpfc_acqe_fc_la_port_number_WORD word0 3075 uint32_t word1; 3076 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16 3077 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 3078 #define lpfc_acqe_fc_la_llink_spd_WORD word1 3079 #define lpfc_acqe_fc_la_fault_SHIFT 0 3080 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF 3081 #define lpfc_acqe_fc_la_fault_WORD word1 3082 #define LPFC_FC_LA_FAULT_NONE 0x0 3083 #define LPFC_FC_LA_FAULT_LOCAL 0x1 3084 #define LPFC_FC_LA_FAULT_REMOTE 0x2 3085 uint32_t event_tag; 3086 uint32_t trailer; 3087 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 3088 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 3089 }; 3090 3091 struct lpfc_acqe_sli { 3092 uint32_t event_data1; 3093 uint32_t event_data2; 3094 uint32_t reserved; 3095 uint32_t trailer; 3096 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 3097 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 3098 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 3099 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 3100 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 3101 }; 3102 3103 /* 3104 * Define the bootstrap mailbox (bmbx) region used to communicate 3105 * mailbox command between the host and port. The mailbox consists 3106 * of a payload area of 256 bytes and a completion queue of length 3107 * 16 bytes. 3108 */ 3109 struct lpfc_bmbx_create { 3110 struct lpfc_mqe mqe; 3111 struct lpfc_mcqe mcqe; 3112 }; 3113 3114 #define SGL_ALIGN_SZ 64 3115 #define SGL_PAGE_SIZE 4096 3116 /* align SGL addr on a size boundary - adjust address up */ 3117 #define NO_XRI 0xffff 3118 3119 struct wqe_common { 3120 uint32_t word6; 3121 #define wqe_xri_tag_SHIFT 0 3122 #define wqe_xri_tag_MASK 0x0000FFFF 3123 #define wqe_xri_tag_WORD word6 3124 #define wqe_ctxt_tag_SHIFT 16 3125 #define wqe_ctxt_tag_MASK 0x0000FFFF 3126 #define wqe_ctxt_tag_WORD word6 3127 uint32_t word7; 3128 #define wqe_dif_SHIFT 0 3129 #define wqe_dif_MASK 0x00000003 3130 #define wqe_dif_WORD word7 3131 #define wqe_ct_SHIFT 2 3132 #define wqe_ct_MASK 0x00000003 3133 #define wqe_ct_WORD word7 3134 #define wqe_status_SHIFT 4 3135 #define wqe_status_MASK 0x0000000f 3136 #define wqe_status_WORD word7 3137 #define wqe_cmnd_SHIFT 8 3138 #define wqe_cmnd_MASK 0x000000ff 3139 #define wqe_cmnd_WORD word7 3140 #define wqe_class_SHIFT 16 3141 #define wqe_class_MASK 0x00000007 3142 #define wqe_class_WORD word7 3143 #define wqe_ar_SHIFT 19 3144 #define wqe_ar_MASK 0x00000001 3145 #define wqe_ar_WORD word7 3146 #define wqe_ag_SHIFT wqe_ar_SHIFT 3147 #define wqe_ag_MASK wqe_ar_MASK 3148 #define wqe_ag_WORD wqe_ar_WORD 3149 #define wqe_pu_SHIFT 20 3150 #define wqe_pu_MASK 0x00000003 3151 #define wqe_pu_WORD word7 3152 #define wqe_erp_SHIFT 22 3153 #define wqe_erp_MASK 0x00000001 3154 #define wqe_erp_WORD word7 3155 #define wqe_conf_SHIFT wqe_erp_SHIFT 3156 #define wqe_conf_MASK wqe_erp_MASK 3157 #define wqe_conf_WORD wqe_erp_WORD 3158 #define wqe_lnk_SHIFT 23 3159 #define wqe_lnk_MASK 0x00000001 3160 #define wqe_lnk_WORD word7 3161 #define wqe_tmo_SHIFT 24 3162 #define wqe_tmo_MASK 0x000000ff 3163 #define wqe_tmo_WORD word7 3164 uint32_t abort_tag; /* word 8 in WQE */ 3165 uint32_t word9; 3166 #define wqe_reqtag_SHIFT 0 3167 #define wqe_reqtag_MASK 0x0000FFFF 3168 #define wqe_reqtag_WORD word9 3169 #define wqe_temp_rpi_SHIFT 16 3170 #define wqe_temp_rpi_MASK 0x0000FFFF 3171 #define wqe_temp_rpi_WORD word9 3172 #define wqe_rcvoxid_SHIFT 16 3173 #define wqe_rcvoxid_MASK 0x0000FFFF 3174 #define wqe_rcvoxid_WORD word9 3175 uint32_t word10; 3176 #define wqe_ebde_cnt_SHIFT 0 3177 #define wqe_ebde_cnt_MASK 0x0000000f 3178 #define wqe_ebde_cnt_WORD word10 3179 #define wqe_lenloc_SHIFT 7 3180 #define wqe_lenloc_MASK 0x00000003 3181 #define wqe_lenloc_WORD word10 3182 #define LPFC_WQE_LENLOC_NONE 0 3183 #define LPFC_WQE_LENLOC_WORD3 1 3184 #define LPFC_WQE_LENLOC_WORD12 2 3185 #define LPFC_WQE_LENLOC_WORD4 3 3186 #define wqe_qosd_SHIFT 9 3187 #define wqe_qosd_MASK 0x00000001 3188 #define wqe_qosd_WORD word10 3189 #define wqe_xbl_SHIFT 11 3190 #define wqe_xbl_MASK 0x00000001 3191 #define wqe_xbl_WORD word10 3192 #define wqe_iod_SHIFT 13 3193 #define wqe_iod_MASK 0x00000001 3194 #define wqe_iod_WORD word10 3195 #define LPFC_WQE_IOD_WRITE 0 3196 #define LPFC_WQE_IOD_READ 1 3197 #define wqe_dbde_SHIFT 14 3198 #define wqe_dbde_MASK 0x00000001 3199 #define wqe_dbde_WORD word10 3200 #define wqe_wqes_SHIFT 15 3201 #define wqe_wqes_MASK 0x00000001 3202 #define wqe_wqes_WORD word10 3203 /* Note that this field overlaps above fields */ 3204 #define wqe_wqid_SHIFT 1 3205 #define wqe_wqid_MASK 0x00007fff 3206 #define wqe_wqid_WORD word10 3207 #define wqe_pri_SHIFT 16 3208 #define wqe_pri_MASK 0x00000007 3209 #define wqe_pri_WORD word10 3210 #define wqe_pv_SHIFT 19 3211 #define wqe_pv_MASK 0x00000001 3212 #define wqe_pv_WORD word10 3213 #define wqe_xc_SHIFT 21 3214 #define wqe_xc_MASK 0x00000001 3215 #define wqe_xc_WORD word10 3216 #define wqe_sr_SHIFT 22 3217 #define wqe_sr_MASK 0x00000001 3218 #define wqe_sr_WORD word10 3219 #define wqe_ccpe_SHIFT 23 3220 #define wqe_ccpe_MASK 0x00000001 3221 #define wqe_ccpe_WORD word10 3222 #define wqe_ccp_SHIFT 24 3223 #define wqe_ccp_MASK 0x000000ff 3224 #define wqe_ccp_WORD word10 3225 uint32_t word11; 3226 #define wqe_cmd_type_SHIFT 0 3227 #define wqe_cmd_type_MASK 0x0000000f 3228 #define wqe_cmd_type_WORD word11 3229 #define wqe_els_id_SHIFT 4 3230 #define wqe_els_id_MASK 0x00000003 3231 #define wqe_els_id_WORD word11 3232 #define LPFC_ELS_ID_FLOGI 3 3233 #define LPFC_ELS_ID_FDISC 2 3234 #define LPFC_ELS_ID_LOGO 1 3235 #define LPFC_ELS_ID_DEFAULT 0 3236 #define wqe_wqec_SHIFT 7 3237 #define wqe_wqec_MASK 0x00000001 3238 #define wqe_wqec_WORD word11 3239 #define wqe_cqid_SHIFT 16 3240 #define wqe_cqid_MASK 0x0000ffff 3241 #define wqe_cqid_WORD word11 3242 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 3243 }; 3244 3245 struct wqe_did { 3246 uint32_t word5; 3247 #define wqe_els_did_SHIFT 0 3248 #define wqe_els_did_MASK 0x00FFFFFF 3249 #define wqe_els_did_WORD word5 3250 #define wqe_xmit_bls_pt_SHIFT 28 3251 #define wqe_xmit_bls_pt_MASK 0x00000003 3252 #define wqe_xmit_bls_pt_WORD word5 3253 #define wqe_xmit_bls_ar_SHIFT 30 3254 #define wqe_xmit_bls_ar_MASK 0x00000001 3255 #define wqe_xmit_bls_ar_WORD word5 3256 #define wqe_xmit_bls_xo_SHIFT 31 3257 #define wqe_xmit_bls_xo_MASK 0x00000001 3258 #define wqe_xmit_bls_xo_WORD word5 3259 }; 3260 3261 struct lpfc_wqe_generic{ 3262 struct ulp_bde64 bde; 3263 uint32_t word3; 3264 uint32_t word4; 3265 uint32_t word5; 3266 struct wqe_common wqe_com; 3267 uint32_t payload[4]; 3268 }; 3269 3270 struct els_request64_wqe { 3271 struct ulp_bde64 bde; 3272 uint32_t payload_len; 3273 uint32_t word4; 3274 #define els_req64_sid_SHIFT 0 3275 #define els_req64_sid_MASK 0x00FFFFFF 3276 #define els_req64_sid_WORD word4 3277 #define els_req64_sp_SHIFT 24 3278 #define els_req64_sp_MASK 0x00000001 3279 #define els_req64_sp_WORD word4 3280 #define els_req64_vf_SHIFT 25 3281 #define els_req64_vf_MASK 0x00000001 3282 #define els_req64_vf_WORD word4 3283 struct wqe_did wqe_dest; 3284 struct wqe_common wqe_com; /* words 6-11 */ 3285 uint32_t word12; 3286 #define els_req64_vfid_SHIFT 1 3287 #define els_req64_vfid_MASK 0x00000FFF 3288 #define els_req64_vfid_WORD word12 3289 #define els_req64_pri_SHIFT 13 3290 #define els_req64_pri_MASK 0x00000007 3291 #define els_req64_pri_WORD word12 3292 uint32_t word13; 3293 #define els_req64_hopcnt_SHIFT 24 3294 #define els_req64_hopcnt_MASK 0x000000ff 3295 #define els_req64_hopcnt_WORD word13 3296 uint32_t reserved[2]; 3297 }; 3298 3299 struct xmit_els_rsp64_wqe { 3300 struct ulp_bde64 bde; 3301 uint32_t response_payload_len; 3302 uint32_t rsvd4; 3303 struct wqe_did wqe_dest; 3304 struct wqe_common wqe_com; /* words 6-11 */ 3305 uint32_t word12; 3306 #define wqe_rsp_temp_rpi_SHIFT 0 3307 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF 3308 #define wqe_rsp_temp_rpi_WORD word12 3309 uint32_t rsvd_13_15[3]; 3310 }; 3311 3312 struct xmit_bls_rsp64_wqe { 3313 uint32_t payload0; 3314 /* Payload0 for BA_ACC */ 3315 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 3316 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 3317 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 3318 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 3319 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 3320 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 3321 /* Payload0 for BA_RJT */ 3322 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 3323 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 3324 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 3325 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 3326 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 3327 #define xmit_bls_rsp64_rjt_expc_WORD payload0 3328 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 3329 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 3330 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 3331 uint32_t word1; 3332 #define xmit_bls_rsp64_rxid_SHIFT 0 3333 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 3334 #define xmit_bls_rsp64_rxid_WORD word1 3335 #define xmit_bls_rsp64_oxid_SHIFT 16 3336 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 3337 #define xmit_bls_rsp64_oxid_WORD word1 3338 uint32_t word2; 3339 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 3340 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 3341 #define xmit_bls_rsp64_seqcnthi_WORD word2 3342 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 3343 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 3344 #define xmit_bls_rsp64_seqcntlo_WORD word2 3345 uint32_t rsrvd3; 3346 uint32_t rsrvd4; 3347 struct wqe_did wqe_dest; 3348 struct wqe_common wqe_com; /* words 6-11 */ 3349 uint32_t word12; 3350 #define xmit_bls_rsp64_temprpi_SHIFT 0 3351 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 3352 #define xmit_bls_rsp64_temprpi_WORD word12 3353 uint32_t rsvd_13_15[3]; 3354 }; 3355 3356 struct wqe_rctl_dfctl { 3357 uint32_t word5; 3358 #define wqe_si_SHIFT 2 3359 #define wqe_si_MASK 0x000000001 3360 #define wqe_si_WORD word5 3361 #define wqe_la_SHIFT 3 3362 #define wqe_la_MASK 0x000000001 3363 #define wqe_la_WORD word5 3364 #define wqe_xo_SHIFT 6 3365 #define wqe_xo_MASK 0x000000001 3366 #define wqe_xo_WORD word5 3367 #define wqe_ls_SHIFT 7 3368 #define wqe_ls_MASK 0x000000001 3369 #define wqe_ls_WORD word5 3370 #define wqe_dfctl_SHIFT 8 3371 #define wqe_dfctl_MASK 0x0000000ff 3372 #define wqe_dfctl_WORD word5 3373 #define wqe_type_SHIFT 16 3374 #define wqe_type_MASK 0x0000000ff 3375 #define wqe_type_WORD word5 3376 #define wqe_rctl_SHIFT 24 3377 #define wqe_rctl_MASK 0x0000000ff 3378 #define wqe_rctl_WORD word5 3379 }; 3380 3381 struct xmit_seq64_wqe { 3382 struct ulp_bde64 bde; 3383 uint32_t rsvd3; 3384 uint32_t relative_offset; 3385 struct wqe_rctl_dfctl wge_ctl; 3386 struct wqe_common wqe_com; /* words 6-11 */ 3387 uint32_t xmit_len; 3388 uint32_t rsvd_12_15[3]; 3389 }; 3390 struct xmit_bcast64_wqe { 3391 struct ulp_bde64 bde; 3392 uint32_t seq_payload_len; 3393 uint32_t rsvd4; 3394 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 3395 struct wqe_common wqe_com; /* words 6-11 */ 3396 uint32_t rsvd_12_15[4]; 3397 }; 3398 3399 struct gen_req64_wqe { 3400 struct ulp_bde64 bde; 3401 uint32_t request_payload_len; 3402 uint32_t relative_offset; 3403 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 3404 struct wqe_common wqe_com; /* words 6-11 */ 3405 uint32_t rsvd_12_15[4]; 3406 }; 3407 3408 struct create_xri_wqe { 3409 uint32_t rsrvd[5]; /* words 0-4 */ 3410 struct wqe_did wqe_dest; /* word 5 */ 3411 struct wqe_common wqe_com; /* words 6-11 */ 3412 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3413 }; 3414 3415 #define T_REQUEST_TAG 3 3416 #define T_XRI_TAG 1 3417 3418 struct abort_cmd_wqe { 3419 uint32_t rsrvd[3]; 3420 uint32_t word3; 3421 #define abort_cmd_ia_SHIFT 0 3422 #define abort_cmd_ia_MASK 0x000000001 3423 #define abort_cmd_ia_WORD word3 3424 #define abort_cmd_criteria_SHIFT 8 3425 #define abort_cmd_criteria_MASK 0x0000000ff 3426 #define abort_cmd_criteria_WORD word3 3427 uint32_t rsrvd4; 3428 uint32_t rsrvd5; 3429 struct wqe_common wqe_com; /* words 6-11 */ 3430 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3431 }; 3432 3433 struct fcp_iwrite64_wqe { 3434 struct ulp_bde64 bde; 3435 uint32_t payload_offset_len; 3436 uint32_t total_xfer_len; 3437 uint32_t initial_xfer_len; 3438 struct wqe_common wqe_com; /* words 6-11 */ 3439 uint32_t rsrvd12; 3440 struct ulp_bde64 ph_bde; /* words 13-15 */ 3441 }; 3442 3443 struct fcp_iread64_wqe { 3444 struct ulp_bde64 bde; 3445 uint32_t payload_offset_len; /* word 3 */ 3446 uint32_t total_xfer_len; /* word 4 */ 3447 uint32_t rsrvd5; /* word 5 */ 3448 struct wqe_common wqe_com; /* words 6-11 */ 3449 uint32_t rsrvd12; 3450 struct ulp_bde64 ph_bde; /* words 13-15 */ 3451 }; 3452 3453 struct fcp_icmnd64_wqe { 3454 struct ulp_bde64 bde; /* words 0-2 */ 3455 uint32_t rsrvd3; /* word 3 */ 3456 uint32_t rsrvd4; /* word 4 */ 3457 uint32_t rsrvd5; /* word 5 */ 3458 struct wqe_common wqe_com; /* words 6-11 */ 3459 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3460 }; 3461 3462 3463 union lpfc_wqe { 3464 uint32_t words[16]; 3465 struct lpfc_wqe_generic generic; 3466 struct fcp_icmnd64_wqe fcp_icmd; 3467 struct fcp_iread64_wqe fcp_iread; 3468 struct fcp_iwrite64_wqe fcp_iwrite; 3469 struct abort_cmd_wqe abort_cmd; 3470 struct create_xri_wqe create_xri; 3471 struct xmit_bcast64_wqe xmit_bcast64; 3472 struct xmit_seq64_wqe xmit_sequence; 3473 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 3474 struct xmit_els_rsp64_wqe xmit_els_rsp; 3475 struct els_request64_wqe els_req; 3476 struct gen_req64_wqe gen_req; 3477 }; 3478 3479 #define LPFC_GROUP_OJECT_MAGIC_NUM 0xfeaa0001 3480 #define LPFC_FILE_TYPE_GROUP 0xf7 3481 #define LPFC_FILE_ID_GROUP 0xa2 3482 struct lpfc_grp_hdr { 3483 uint32_t size; 3484 uint32_t magic_number; 3485 uint32_t word2; 3486 #define lpfc_grp_hdr_file_type_SHIFT 24 3487 #define lpfc_grp_hdr_file_type_MASK 0x000000FF 3488 #define lpfc_grp_hdr_file_type_WORD word2 3489 #define lpfc_grp_hdr_id_SHIFT 16 3490 #define lpfc_grp_hdr_id_MASK 0x000000FF 3491 #define lpfc_grp_hdr_id_WORD word2 3492 uint8_t rev_name[128]; 3493 uint8_t date[12]; 3494 uint8_t revision[32]; 3495 }; 3496 3497 #define FCP_COMMAND 0x0 3498 #define FCP_COMMAND_DATA_OUT 0x1 3499 #define ELS_COMMAND_NON_FIP 0xC 3500 #define ELS_COMMAND_FIP 0xD 3501 #define OTHER_COMMAND 0x8 3502 3503 #define LPFC_FW_DUMP 1 3504 #define LPFC_FW_RESET 2 3505 #define LPFC_DV_RESET 3 3506