1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *****************************************************************************/
62
63
64 #include <linux/kernel.h>
65 #include <linux/module.h>
66 #include <linux/slab.h>
67 #include <linux/init.h>
68
69 #include <net/mac80211.h>
70
71 #include "iwl-commands.h"
72 #include "iwl-dev.h"
73 #include "iwl-core.h"
74 #include "iwl-debug.h"
75 #include "iwl-agn.h"
76 #include "iwl-eeprom.h"
77 #include "iwl-io.h"
78 #include "iwl-prph.h"
79
80 /************************** EEPROM BANDS ****************************
81 *
82 * The iwl_eeprom_band definitions below provide the mapping from the
83 * EEPROM contents to the specific channel number supported for each
84 * band.
85 *
86 * For example, iwl_priv->eeprom.band_3_channels[4] from the band_3
87 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
88 * The specific geography and calibration information for that channel
89 * is contained in the eeprom map itself.
90 *
91 * During init, we copy the eeprom information and channel map
92 * information into priv->channel_info_24/52 and priv->channel_map_24/52
93 *
94 * channel_map_24/52 provides the index in the channel_info array for a
95 * given channel. We have to have two separate maps as there is channel
96 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
97 * band_2
98 *
99 * A value of 0xff stored in the channel_map indicates that the channel
100 * is not supported by the hardware at all.
101 *
102 * A value of 0xfe in the channel_map indicates that the channel is not
103 * valid for Tx with the current hardware. This means that
104 * while the system can tune and receive on a given channel, it may not
105 * be able to associate or transmit any frames on that
106 * channel. There is no corresponding channel information for that
107 * entry.
108 *
109 *********************************************************************/
110
111 /* 2.4 GHz */
112 const u8 iwl_eeprom_band_1[14] = {
113 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
114 };
115
116 /* 5.2 GHz bands */
117 static const u8 iwl_eeprom_band_2[] = { /* 4915-5080MHz */
118 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
119 };
120
121 static const u8 iwl_eeprom_band_3[] = { /* 5170-5320MHz */
122 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
123 };
124
125 static const u8 iwl_eeprom_band_4[] = { /* 5500-5700MHz */
126 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
127 };
128
129 static const u8 iwl_eeprom_band_5[] = { /* 5725-5825MHz */
130 145, 149, 153, 157, 161, 165
131 };
132
133 static const u8 iwl_eeprom_band_6[] = { /* 2.4 ht40 channel */
134 1, 2, 3, 4, 5, 6, 7
135 };
136
137 static const u8 iwl_eeprom_band_7[] = { /* 5.2 ht40 channel */
138 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
139 };
140
141 /******************************************************************************
142 *
143 * generic NVM functions
144 *
145 ******************************************************************************/
146
147 /*
148 * The device's EEPROM semaphore prevents conflicts between driver and uCode
149 * when accessing the EEPROM; each access is a series of pulses to/from the
150 * EEPROM chip, not a single event, so even reads could conflict if they
151 * weren't arbitrated by the semaphore.
152 */
153
154 #define EEPROM_SEM_TIMEOUT 10 /* milliseconds */
155 #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
156
iwl_eeprom_acquire_semaphore(struct iwl_trans * trans)157 static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans)
158 {
159 u16 count;
160 int ret;
161
162 for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
163 /* Request semaphore */
164 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
165 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
166
167 /* See if we got it */
168 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
169 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
170 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
171 EEPROM_SEM_TIMEOUT);
172 if (ret >= 0) {
173 IWL_DEBUG_EEPROM(trans,
174 "Acquired semaphore after %d tries.\n",
175 count+1);
176 return ret;
177 }
178 }
179
180 return ret;
181 }
182
iwl_eeprom_release_semaphore(struct iwl_trans * trans)183 static void iwl_eeprom_release_semaphore(struct iwl_trans *trans)
184 {
185 iwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG,
186 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
187
188 }
189
iwl_eeprom_verify_signature(struct iwl_trans * trans)190 static int iwl_eeprom_verify_signature(struct iwl_trans *trans)
191 {
192 u32 gp = iwl_read32(trans, CSR_EEPROM_GP) &
193 CSR_EEPROM_GP_VALID_MSK;
194 int ret = 0;
195
196 IWL_DEBUG_EEPROM(trans, "EEPROM signature=0x%08x\n", gp);
197 switch (gp) {
198 case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP:
199 if (trans->nvm_device_type != NVM_DEVICE_TYPE_OTP) {
200 IWL_ERR(trans, "EEPROM with bad signature: 0x%08x\n",
201 gp);
202 ret = -ENOENT;
203 }
204 break;
205 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
206 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
207 if (trans->nvm_device_type != NVM_DEVICE_TYPE_EEPROM) {
208 IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp);
209 ret = -ENOENT;
210 }
211 break;
212 case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP:
213 default:
214 IWL_ERR(trans, "bad EEPROM/OTP signature, type=%s, "
215 "EEPROM_GP=0x%08x\n",
216 (trans->nvm_device_type == NVM_DEVICE_TYPE_OTP)
217 ? "OTP" : "EEPROM", gp);
218 ret = -ENOENT;
219 break;
220 }
221 return ret;
222 }
223
iwl_eeprom_query16(const struct iwl_shared * shrd,size_t offset)224 u16 iwl_eeprom_query16(const struct iwl_shared *shrd, size_t offset)
225 {
226 if (!shrd->eeprom)
227 return 0;
228 return (u16)shrd->eeprom[offset] | ((u16)shrd->eeprom[offset + 1] << 8);
229 }
230
iwl_eeprom_check_version(struct iwl_priv * priv)231 int iwl_eeprom_check_version(struct iwl_priv *priv)
232 {
233 u16 eeprom_ver;
234 u16 calib_ver;
235
236 eeprom_ver = iwl_eeprom_query16(priv->shrd, EEPROM_VERSION);
237 calib_ver = iwl_eeprom_calib_version(priv->shrd);
238
239 if (eeprom_ver < cfg(priv)->eeprom_ver ||
240 calib_ver < cfg(priv)->eeprom_calib_ver)
241 goto err;
242
243 IWL_INFO(priv, "device EEPROM VER=0x%x, CALIB=0x%x\n",
244 eeprom_ver, calib_ver);
245
246 return 0;
247 err:
248 IWL_ERR(priv, "Unsupported (too old) EEPROM VER=0x%x < 0x%x "
249 "CALIB=0x%x < 0x%x\n",
250 eeprom_ver, cfg(priv)->eeprom_ver,
251 calib_ver, cfg(priv)->eeprom_calib_ver);
252 return -EINVAL;
253
254 }
255
iwl_eeprom_init_hw_params(struct iwl_priv * priv)256 int iwl_eeprom_init_hw_params(struct iwl_priv *priv)
257 {
258 struct iwl_shared *shrd = priv->shrd;
259 u16 radio_cfg;
260
261 hw_params(priv).sku = iwl_eeprom_query16(shrd, EEPROM_SKU_CAP);
262 if (hw_params(priv).sku & EEPROM_SKU_CAP_11N_ENABLE &&
263 !cfg(priv)->ht_params) {
264 IWL_ERR(priv, "Invalid 11n configuration\n");
265 return -EINVAL;
266 }
267
268 if (!hw_params(priv).sku) {
269 IWL_ERR(priv, "Invalid device sku\n");
270 return -EINVAL;
271 }
272
273 IWL_INFO(priv, "Device SKU: 0x%X\n", hw_params(priv).sku);
274
275 radio_cfg = iwl_eeprom_query16(shrd, EEPROM_RADIO_CONFIG);
276
277 hw_params(priv).valid_tx_ant = EEPROM_RF_CFG_TX_ANT_MSK(radio_cfg);
278 hw_params(priv).valid_rx_ant = EEPROM_RF_CFG_RX_ANT_MSK(radio_cfg);
279
280 /* check overrides (some devices have wrong EEPROM) */
281 if (cfg(priv)->valid_tx_ant)
282 hw_params(priv).valid_tx_ant = cfg(priv)->valid_tx_ant;
283 if (cfg(priv)->valid_rx_ant)
284 hw_params(priv).valid_rx_ant = cfg(priv)->valid_rx_ant;
285
286 if (!hw_params(priv).valid_tx_ant || !hw_params(priv).valid_rx_ant) {
287 IWL_ERR(priv, "Invalid chain (0x%X, 0x%X)\n",
288 hw_params(priv).valid_tx_ant,
289 hw_params(priv).valid_rx_ant);
290 return -EINVAL;
291 }
292
293 IWL_INFO(priv, "Valid Tx ant: 0x%X, Valid Rx ant: 0x%X\n",
294 hw_params(priv).valid_tx_ant, hw_params(priv).valid_rx_ant);
295
296 return 0;
297 }
298
iwl_eeprom_get_mac(const struct iwl_shared * shrd,u8 * mac)299 void iwl_eeprom_get_mac(const struct iwl_shared *shrd, u8 *mac)
300 {
301 const u8 *addr = iwl_eeprom_query_addr(shrd,
302 EEPROM_MAC_ADDRESS);
303 memcpy(mac, addr, ETH_ALEN);
304 }
305
306 /******************************************************************************
307 *
308 * OTP related functions
309 *
310 ******************************************************************************/
311
iwl_set_otp_access(struct iwl_trans * trans,enum iwl_access_mode mode)312 static void iwl_set_otp_access(struct iwl_trans *trans,
313 enum iwl_access_mode mode)
314 {
315 iwl_read32(trans, CSR_OTP_GP_REG);
316
317 if (mode == IWL_OTP_ACCESS_ABSOLUTE)
318 iwl_clear_bit(trans, CSR_OTP_GP_REG,
319 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
320 else
321 iwl_set_bit(trans, CSR_OTP_GP_REG,
322 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
323 }
324
iwl_get_nvm_type(struct iwl_trans * trans,u32 hw_rev)325 static int iwl_get_nvm_type(struct iwl_trans *trans, u32 hw_rev)
326 {
327 u32 otpgp;
328 int nvm_type;
329
330 /* OTP only valid for CP/PP and after */
331 switch (hw_rev & CSR_HW_REV_TYPE_MSK) {
332 case CSR_HW_REV_TYPE_NONE:
333 IWL_ERR(trans, "Unknown hardware type\n");
334 return -ENOENT;
335 case CSR_HW_REV_TYPE_5300:
336 case CSR_HW_REV_TYPE_5350:
337 case CSR_HW_REV_TYPE_5100:
338 case CSR_HW_REV_TYPE_5150:
339 nvm_type = NVM_DEVICE_TYPE_EEPROM;
340 break;
341 default:
342 otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
343 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
344 nvm_type = NVM_DEVICE_TYPE_OTP;
345 else
346 nvm_type = NVM_DEVICE_TYPE_EEPROM;
347 break;
348 }
349 return nvm_type;
350 }
351
iwl_init_otp_access(struct iwl_trans * trans)352 static int iwl_init_otp_access(struct iwl_trans *trans)
353 {
354 int ret;
355
356 /* Enable 40MHz radio clock */
357 iwl_write32(trans, CSR_GP_CNTRL,
358 iwl_read32(trans, CSR_GP_CNTRL) |
359 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
360
361 /* wait for clock to be ready */
362 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
363 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
364 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
365 25000);
366 if (ret < 0)
367 IWL_ERR(trans, "Time out access OTP\n");
368 else {
369 iwl_set_bits_prph(trans, APMG_PS_CTRL_REG,
370 APMG_PS_CTRL_VAL_RESET_REQ);
371 udelay(5);
372 iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG,
373 APMG_PS_CTRL_VAL_RESET_REQ);
374
375 /*
376 * CSR auto clock gate disable bit -
377 * this is only applicable for HW with OTP shadow RAM
378 */
379 if (cfg(trans)->base_params->shadow_ram_support)
380 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
381 CSR_RESET_LINK_PWR_MGMT_DISABLED);
382 }
383 return ret;
384 }
385
iwl_read_otp_word(struct iwl_trans * trans,u16 addr,__le16 * eeprom_data)386 static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr,
387 __le16 *eeprom_data)
388 {
389 int ret = 0;
390 u32 r;
391 u32 otpgp;
392
393 iwl_write32(trans, CSR_EEPROM_REG,
394 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
395 ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
396 CSR_EEPROM_REG_READ_VALID_MSK,
397 CSR_EEPROM_REG_READ_VALID_MSK,
398 IWL_EEPROM_ACCESS_TIMEOUT);
399 if (ret < 0) {
400 IWL_ERR(trans, "Time out reading OTP[%d]\n", addr);
401 return ret;
402 }
403 r = iwl_read32(trans, CSR_EEPROM_REG);
404 /* check for ECC errors: */
405 otpgp = iwl_read32(trans, CSR_OTP_GP_REG);
406 if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
407 /* stop in this case */
408 /* set the uncorrectable OTP ECC bit for acknowledgement */
409 iwl_set_bit(trans, CSR_OTP_GP_REG,
410 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
411 IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n");
412 return -EINVAL;
413 }
414 if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
415 /* continue in this case */
416 /* set the correctable OTP ECC bit for acknowledgement */
417 iwl_set_bit(trans, CSR_OTP_GP_REG,
418 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
419 IWL_ERR(trans, "Correctable OTP ECC error, continue read\n");
420 }
421 *eeprom_data = cpu_to_le16(r >> 16);
422 return 0;
423 }
424
425 /*
426 * iwl_is_otp_empty: check for empty OTP
427 */
iwl_is_otp_empty(struct iwl_trans * trans)428 static bool iwl_is_otp_empty(struct iwl_trans *trans)
429 {
430 u16 next_link_addr = 0;
431 __le16 link_value;
432 bool is_empty = false;
433
434 /* locate the beginning of OTP link list */
435 if (!iwl_read_otp_word(trans, next_link_addr, &link_value)) {
436 if (!link_value) {
437 IWL_ERR(trans, "OTP is empty\n");
438 is_empty = true;
439 }
440 } else {
441 IWL_ERR(trans, "Unable to read first block of OTP list.\n");
442 is_empty = true;
443 }
444
445 return is_empty;
446 }
447
448
449 /*
450 * iwl_find_otp_image: find EEPROM image in OTP
451 * finding the OTP block that contains the EEPROM image.
452 * the last valid block on the link list (the block _before_ the last block)
453 * is the block we should read and used to configure the device.
454 * If all the available OTP blocks are full, the last block will be the block
455 * we should read and used to configure the device.
456 * only perform this operation if shadow RAM is disabled
457 */
iwl_find_otp_image(struct iwl_trans * trans,u16 * validblockaddr)458 static int iwl_find_otp_image(struct iwl_trans *trans,
459 u16 *validblockaddr)
460 {
461 u16 next_link_addr = 0, valid_addr;
462 __le16 link_value = 0;
463 int usedblocks = 0;
464
465 /* set addressing mode to absolute to traverse the link list */
466 iwl_set_otp_access(trans, IWL_OTP_ACCESS_ABSOLUTE);
467
468 /* checking for empty OTP or error */
469 if (iwl_is_otp_empty(trans))
470 return -EINVAL;
471
472 /*
473 * start traverse link list
474 * until reach the max number of OTP blocks
475 * different devices have different number of OTP blocks
476 */
477 do {
478 /* save current valid block address
479 * check for more block on the link list
480 */
481 valid_addr = next_link_addr;
482 next_link_addr = le16_to_cpu(link_value) * sizeof(u16);
483 IWL_DEBUG_EEPROM(trans, "OTP blocks %d addr 0x%x\n",
484 usedblocks, next_link_addr);
485 if (iwl_read_otp_word(trans, next_link_addr, &link_value))
486 return -EINVAL;
487 if (!link_value) {
488 /*
489 * reach the end of link list, return success and
490 * set address point to the starting address
491 * of the image
492 */
493 *validblockaddr = valid_addr;
494 /* skip first 2 bytes (link list pointer) */
495 *validblockaddr += 2;
496 return 0;
497 }
498 /* more in the link list, continue */
499 usedblocks++;
500 } while (usedblocks <= cfg(trans)->base_params->max_ll_items);
501
502 /* OTP has no valid blocks */
503 IWL_DEBUG_EEPROM(trans, "OTP has no valid blocks\n");
504 return -EINVAL;
505 }
506
507 /******************************************************************************
508 *
509 * Tx Power related functions
510 *
511 ******************************************************************************/
512 /**
513 * iwl_get_max_txpower_avg - get the highest tx power from all chains.
514 * find the highest tx power from all chains for the channel
515 */
iwl_get_max_txpower_avg(struct iwl_priv * priv,struct iwl_eeprom_enhanced_txpwr * enhanced_txpower,int element,s8 * max_txpower_in_half_dbm)516 static s8 iwl_get_max_txpower_avg(struct iwl_priv *priv,
517 struct iwl_eeprom_enhanced_txpwr *enhanced_txpower,
518 int element, s8 *max_txpower_in_half_dbm)
519 {
520 s8 max_txpower_avg = 0; /* (dBm) */
521
522 /* Take the highest tx power from any valid chains */
523 if ((hw_params(priv).valid_tx_ant & ANT_A) &&
524 (enhanced_txpower[element].chain_a_max > max_txpower_avg))
525 max_txpower_avg = enhanced_txpower[element].chain_a_max;
526 if ((hw_params(priv).valid_tx_ant & ANT_B) &&
527 (enhanced_txpower[element].chain_b_max > max_txpower_avg))
528 max_txpower_avg = enhanced_txpower[element].chain_b_max;
529 if ((hw_params(priv).valid_tx_ant & ANT_C) &&
530 (enhanced_txpower[element].chain_c_max > max_txpower_avg))
531 max_txpower_avg = enhanced_txpower[element].chain_c_max;
532 if (((hw_params(priv).valid_tx_ant == ANT_AB) |
533 (hw_params(priv).valid_tx_ant == ANT_BC) |
534 (hw_params(priv).valid_tx_ant == ANT_AC)) &&
535 (enhanced_txpower[element].mimo2_max > max_txpower_avg))
536 max_txpower_avg = enhanced_txpower[element].mimo2_max;
537 if ((hw_params(priv).valid_tx_ant == ANT_ABC) &&
538 (enhanced_txpower[element].mimo3_max > max_txpower_avg))
539 max_txpower_avg = enhanced_txpower[element].mimo3_max;
540
541 /*
542 * max. tx power in EEPROM is in 1/2 dBm format
543 * convert from 1/2 dBm to dBm (round-up convert)
544 * but we also do not want to loss 1/2 dBm resolution which
545 * will impact performance
546 */
547 *max_txpower_in_half_dbm = max_txpower_avg;
548 return (max_txpower_avg & 0x01) + (max_txpower_avg >> 1);
549 }
550
551 static void
iwl_eeprom_enh_txp_read_element(struct iwl_priv * priv,struct iwl_eeprom_enhanced_txpwr * txp,s8 max_txpower_avg)552 iwl_eeprom_enh_txp_read_element(struct iwl_priv *priv,
553 struct iwl_eeprom_enhanced_txpwr *txp,
554 s8 max_txpower_avg)
555 {
556 int ch_idx;
557 bool is_ht40 = txp->flags & IWL_EEPROM_ENH_TXP_FL_40MHZ;
558 enum ieee80211_band band;
559
560 band = txp->flags & IWL_EEPROM_ENH_TXP_FL_BAND_52G ?
561 IEEE80211_BAND_5GHZ : IEEE80211_BAND_2GHZ;
562
563 for (ch_idx = 0; ch_idx < priv->channel_count; ch_idx++) {
564 struct iwl_channel_info *ch_info = &priv->channel_info[ch_idx];
565
566 /* update matching channel or from common data only */
567 if (txp->channel != 0 && ch_info->channel != txp->channel)
568 continue;
569
570 /* update matching band only */
571 if (band != ch_info->band)
572 continue;
573
574 if (ch_info->max_power_avg < max_txpower_avg && !is_ht40) {
575 ch_info->max_power_avg = max_txpower_avg;
576 ch_info->curr_txpow = max_txpower_avg;
577 ch_info->scan_power = max_txpower_avg;
578 }
579
580 if (is_ht40 && ch_info->ht40_max_power_avg < max_txpower_avg)
581 ch_info->ht40_max_power_avg = max_txpower_avg;
582 }
583 }
584
585 #define EEPROM_TXP_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT)
586 #define EEPROM_TXP_ENTRY_LEN sizeof(struct iwl_eeprom_enhanced_txpwr)
587 #define EEPROM_TXP_SZ_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT_SIZE)
588
589 #define TXP_CHECK_AND_PRINT(x) ((txp->flags & IWL_EEPROM_ENH_TXP_FL_##x) \
590 ? # x " " : "")
591
iwl_eeprom_enhanced_txpower(struct iwl_priv * priv)592 static void iwl_eeprom_enhanced_txpower(struct iwl_priv *priv)
593 {
594 struct iwl_shared *shrd = priv->shrd;
595 struct iwl_eeprom_enhanced_txpwr *txp_array, *txp;
596 int idx, entries;
597 __le16 *txp_len;
598 s8 max_txp_avg, max_txp_avg_halfdbm;
599
600 BUILD_BUG_ON(sizeof(struct iwl_eeprom_enhanced_txpwr) != 8);
601
602 /* the length is in 16-bit words, but we want entries */
603 txp_len = (__le16 *) iwl_eeprom_query_addr(shrd, EEPROM_TXP_SZ_OFFS);
604 entries = le16_to_cpup(txp_len) * 2 / EEPROM_TXP_ENTRY_LEN;
605
606 txp_array = (void *) iwl_eeprom_query_addr(shrd, EEPROM_TXP_OFFS);
607
608 for (idx = 0; idx < entries; idx++) {
609 txp = &txp_array[idx];
610 /* skip invalid entries */
611 if (!(txp->flags & IWL_EEPROM_ENH_TXP_FL_VALID))
612 continue;
613
614 IWL_DEBUG_EEPROM(priv, "%s %d:\t %s%s%s%s%s%s%s%s (0x%02x)\n",
615 (txp->channel && (txp->flags &
616 IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE)) ?
617 "Common " : (txp->channel) ?
618 "Channel" : "Common",
619 (txp->channel),
620 TXP_CHECK_AND_PRINT(VALID),
621 TXP_CHECK_AND_PRINT(BAND_52G),
622 TXP_CHECK_AND_PRINT(OFDM),
623 TXP_CHECK_AND_PRINT(40MHZ),
624 TXP_CHECK_AND_PRINT(HT_AP),
625 TXP_CHECK_AND_PRINT(RES1),
626 TXP_CHECK_AND_PRINT(RES2),
627 TXP_CHECK_AND_PRINT(COMMON_TYPE),
628 txp->flags);
629 IWL_DEBUG_EEPROM(priv, "\t\t chain_A: 0x%02x "
630 "chain_B: 0X%02x chain_C: 0X%02x\n",
631 txp->chain_a_max, txp->chain_b_max,
632 txp->chain_c_max);
633 IWL_DEBUG_EEPROM(priv, "\t\t MIMO2: 0x%02x "
634 "MIMO3: 0x%02x High 20_on_40: 0x%02x "
635 "Low 20_on_40: 0x%02x\n",
636 txp->mimo2_max, txp->mimo3_max,
637 ((txp->delta_20_in_40 & 0xf0) >> 4),
638 (txp->delta_20_in_40 & 0x0f));
639
640 max_txp_avg = iwl_get_max_txpower_avg(priv, txp_array, idx,
641 &max_txp_avg_halfdbm);
642
643 /*
644 * Update the user limit values values to the highest
645 * power supported by any channel
646 */
647 if (max_txp_avg > priv->tx_power_user_lmt)
648 priv->tx_power_user_lmt = max_txp_avg;
649 if (max_txp_avg_halfdbm > priv->tx_power_lmt_in_half_dbm)
650 priv->tx_power_lmt_in_half_dbm = max_txp_avg_halfdbm;
651
652 iwl_eeprom_enh_txp_read_element(priv, txp, max_txp_avg);
653 }
654 }
655
656 /**
657 * iwl_eeprom_init - read EEPROM contents
658 *
659 * Load the EEPROM contents from adapter into shrd->eeprom
660 *
661 * NOTE: This routine uses the non-debug IO access functions.
662 */
iwl_eeprom_init(struct iwl_trans * trans,u32 hw_rev)663 int iwl_eeprom_init(struct iwl_trans *trans, u32 hw_rev)
664 {
665 __le16 *e;
666 u32 gp = iwl_read32(trans, CSR_EEPROM_GP);
667 int sz;
668 int ret;
669 u16 addr;
670 u16 validblockaddr = 0;
671 u16 cache_addr = 0;
672
673 trans->nvm_device_type = iwl_get_nvm_type(trans, hw_rev);
674 if (trans->nvm_device_type == -ENOENT)
675 return -ENOENT;
676 /* allocate eeprom */
677 sz = cfg(trans)->base_params->eeprom_size;
678 IWL_DEBUG_EEPROM(trans, "NVM size = %d\n", sz);
679 trans->shrd->eeprom = kzalloc(sz, GFP_KERNEL);
680 if (!trans->shrd->eeprom) {
681 ret = -ENOMEM;
682 goto alloc_err;
683 }
684 e = (__le16 *)trans->shrd->eeprom;
685
686 ret = iwl_eeprom_verify_signature(trans);
687 if (ret < 0) {
688 IWL_ERR(trans, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
689 ret = -ENOENT;
690 goto err;
691 }
692
693 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
694 ret = iwl_eeprom_acquire_semaphore(trans);
695 if (ret < 0) {
696 IWL_ERR(trans, "Failed to acquire EEPROM semaphore.\n");
697 ret = -ENOENT;
698 goto err;
699 }
700
701 if (trans->nvm_device_type == NVM_DEVICE_TYPE_OTP) {
702
703 ret = iwl_init_otp_access(trans);
704 if (ret) {
705 IWL_ERR(trans, "Failed to initialize OTP access.\n");
706 ret = -ENOENT;
707 goto done;
708 }
709 iwl_write32(trans, CSR_EEPROM_GP,
710 iwl_read32(trans, CSR_EEPROM_GP) &
711 ~CSR_EEPROM_GP_IF_OWNER_MSK);
712
713 iwl_set_bit(trans, CSR_OTP_GP_REG,
714 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
715 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
716 /* traversing the linked list if no shadow ram supported */
717 if (!cfg(trans)->base_params->shadow_ram_support) {
718 if (iwl_find_otp_image(trans, &validblockaddr)) {
719 ret = -ENOENT;
720 goto done;
721 }
722 }
723 for (addr = validblockaddr; addr < validblockaddr + sz;
724 addr += sizeof(u16)) {
725 __le16 eeprom_data;
726
727 ret = iwl_read_otp_word(trans, addr, &eeprom_data);
728 if (ret)
729 goto done;
730 e[cache_addr / 2] = eeprom_data;
731 cache_addr += sizeof(u16);
732 }
733 } else {
734 /* eeprom is an array of 16bit values */
735 for (addr = 0; addr < sz; addr += sizeof(u16)) {
736 u32 r;
737
738 iwl_write32(trans, CSR_EEPROM_REG,
739 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
740
741 ret = iwl_poll_bit(trans, CSR_EEPROM_REG,
742 CSR_EEPROM_REG_READ_VALID_MSK,
743 CSR_EEPROM_REG_READ_VALID_MSK,
744 IWL_EEPROM_ACCESS_TIMEOUT);
745 if (ret < 0) {
746 IWL_ERR(trans,
747 "Time out reading EEPROM[%d]\n", addr);
748 goto done;
749 }
750 r = iwl_read32(trans, CSR_EEPROM_REG);
751 e[addr / 2] = cpu_to_le16(r >> 16);
752 }
753 }
754
755 IWL_DEBUG_EEPROM(trans, "NVM Type: %s, version: 0x%x\n",
756 (trans->nvm_device_type == NVM_DEVICE_TYPE_OTP)
757 ? "OTP" : "EEPROM",
758 iwl_eeprom_query16(trans->shrd, EEPROM_VERSION));
759
760 ret = 0;
761 done:
762 iwl_eeprom_release_semaphore(trans);
763
764 err:
765 if (ret)
766 iwl_eeprom_free(trans->shrd);
767 alloc_err:
768 return ret;
769 }
770
iwl_eeprom_free(struct iwl_shared * shrd)771 void iwl_eeprom_free(struct iwl_shared *shrd)
772 {
773 kfree(shrd->eeprom);
774 shrd->eeprom = NULL;
775 }
776
iwl_init_band_reference(const struct iwl_priv * priv,int eep_band,int * eeprom_ch_count,const struct iwl_eeprom_channel ** eeprom_ch_info,const u8 ** eeprom_ch_index)777 static void iwl_init_band_reference(const struct iwl_priv *priv,
778 int eep_band, int *eeprom_ch_count,
779 const struct iwl_eeprom_channel **eeprom_ch_info,
780 const u8 **eeprom_ch_index)
781 {
782 struct iwl_shared *shrd = priv->shrd;
783 u32 offset = cfg(priv)->lib->
784 eeprom_ops.regulatory_bands[eep_band - 1];
785 switch (eep_band) {
786 case 1: /* 2.4GHz band */
787 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_1);
788 *eeprom_ch_info = (struct iwl_eeprom_channel *)
789 iwl_eeprom_query_addr(shrd, offset);
790 *eeprom_ch_index = iwl_eeprom_band_1;
791 break;
792 case 2: /* 4.9GHz band */
793 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_2);
794 *eeprom_ch_info = (struct iwl_eeprom_channel *)
795 iwl_eeprom_query_addr(shrd, offset);
796 *eeprom_ch_index = iwl_eeprom_band_2;
797 break;
798 case 3: /* 5.2GHz band */
799 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_3);
800 *eeprom_ch_info = (struct iwl_eeprom_channel *)
801 iwl_eeprom_query_addr(shrd, offset);
802 *eeprom_ch_index = iwl_eeprom_band_3;
803 break;
804 case 4: /* 5.5GHz band */
805 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_4);
806 *eeprom_ch_info = (struct iwl_eeprom_channel *)
807 iwl_eeprom_query_addr(shrd, offset);
808 *eeprom_ch_index = iwl_eeprom_band_4;
809 break;
810 case 5: /* 5.7GHz band */
811 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_5);
812 *eeprom_ch_info = (struct iwl_eeprom_channel *)
813 iwl_eeprom_query_addr(shrd, offset);
814 *eeprom_ch_index = iwl_eeprom_band_5;
815 break;
816 case 6: /* 2.4GHz ht40 channels */
817 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_6);
818 *eeprom_ch_info = (struct iwl_eeprom_channel *)
819 iwl_eeprom_query_addr(shrd, offset);
820 *eeprom_ch_index = iwl_eeprom_band_6;
821 break;
822 case 7: /* 5 GHz ht40 channels */
823 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_7);
824 *eeprom_ch_info = (struct iwl_eeprom_channel *)
825 iwl_eeprom_query_addr(shrd, offset);
826 *eeprom_ch_index = iwl_eeprom_band_7;
827 break;
828 default:
829 BUG();
830 return;
831 }
832 }
833
834 #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
835 ? # x " " : "")
836 /**
837 * iwl_mod_ht40_chan_info - Copy ht40 channel info into driver's priv.
838 *
839 * Does not set up a command, or touch hardware.
840 */
iwl_mod_ht40_chan_info(struct iwl_priv * priv,enum ieee80211_band band,u16 channel,const struct iwl_eeprom_channel * eeprom_ch,u8 clear_ht40_extension_channel)841 static int iwl_mod_ht40_chan_info(struct iwl_priv *priv,
842 enum ieee80211_band band, u16 channel,
843 const struct iwl_eeprom_channel *eeprom_ch,
844 u8 clear_ht40_extension_channel)
845 {
846 struct iwl_channel_info *ch_info;
847
848 ch_info = (struct iwl_channel_info *)
849 iwl_get_channel_info(priv, band, channel);
850
851 if (!is_channel_valid(ch_info))
852 return -1;
853
854 IWL_DEBUG_EEPROM(priv, "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
855 " Ad-Hoc %ssupported\n",
856 ch_info->channel,
857 is_channel_a_band(ch_info) ?
858 "5.2" : "2.4",
859 CHECK_AND_PRINT(IBSS),
860 CHECK_AND_PRINT(ACTIVE),
861 CHECK_AND_PRINT(RADAR),
862 CHECK_AND_PRINT(WIDE),
863 CHECK_AND_PRINT(DFS),
864 eeprom_ch->flags,
865 eeprom_ch->max_power_avg,
866 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS)
867 && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ?
868 "" : "not ");
869
870 ch_info->ht40_eeprom = *eeprom_ch;
871 ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
872 ch_info->ht40_flags = eeprom_ch->flags;
873 if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
874 ch_info->ht40_extension_channel &= ~clear_ht40_extension_channel;
875
876 return 0;
877 }
878
879 #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
880 ? # x " " : "")
881
882 /**
883 * iwl_init_channel_map - Set up driver's info for all possible channels
884 */
iwl_init_channel_map(struct iwl_priv * priv)885 int iwl_init_channel_map(struct iwl_priv *priv)
886 {
887 int eeprom_ch_count = 0;
888 const u8 *eeprom_ch_index = NULL;
889 const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
890 int band, ch;
891 struct iwl_channel_info *ch_info;
892
893 if (priv->channel_count) {
894 IWL_DEBUG_EEPROM(priv, "Channel map already initialized.\n");
895 return 0;
896 }
897
898 IWL_DEBUG_EEPROM(priv, "Initializing regulatory info from EEPROM\n");
899
900 priv->channel_count =
901 ARRAY_SIZE(iwl_eeprom_band_1) +
902 ARRAY_SIZE(iwl_eeprom_band_2) +
903 ARRAY_SIZE(iwl_eeprom_band_3) +
904 ARRAY_SIZE(iwl_eeprom_band_4) +
905 ARRAY_SIZE(iwl_eeprom_band_5);
906
907 IWL_DEBUG_EEPROM(priv, "Parsing data for %d channels.\n",
908 priv->channel_count);
909
910 priv->channel_info = kcalloc(priv->channel_count,
911 sizeof(struct iwl_channel_info),
912 GFP_KERNEL);
913 if (!priv->channel_info) {
914 IWL_ERR(priv, "Could not allocate channel_info\n");
915 priv->channel_count = 0;
916 return -ENOMEM;
917 }
918
919 ch_info = priv->channel_info;
920
921 /* Loop through the 5 EEPROM bands adding them in order to the
922 * channel map we maintain (that contains additional information than
923 * what just in the EEPROM) */
924 for (band = 1; band <= 5; band++) {
925
926 iwl_init_band_reference(priv, band, &eeprom_ch_count,
927 &eeprom_ch_info, &eeprom_ch_index);
928
929 /* Loop through each band adding each of the channels */
930 for (ch = 0; ch < eeprom_ch_count; ch++) {
931 ch_info->channel = eeprom_ch_index[ch];
932 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
933 IEEE80211_BAND_5GHZ;
934
935 /* permanently store EEPROM's channel regulatory flags
936 * and max power in channel info database. */
937 ch_info->eeprom = eeprom_ch_info[ch];
938
939 /* Copy the run-time flags so they are there even on
940 * invalid channels */
941 ch_info->flags = eeprom_ch_info[ch].flags;
942 /* First write that ht40 is not enabled, and then enable
943 * one by one */
944 ch_info->ht40_extension_channel =
945 IEEE80211_CHAN_NO_HT40;
946
947 if (!(is_channel_valid(ch_info))) {
948 IWL_DEBUG_EEPROM(priv,
949 "Ch. %d Flags %x [%sGHz] - "
950 "No traffic\n",
951 ch_info->channel,
952 ch_info->flags,
953 is_channel_a_band(ch_info) ?
954 "5.2" : "2.4");
955 ch_info++;
956 continue;
957 }
958
959 /* Initialize regulatory-based run-time data */
960 ch_info->max_power_avg = ch_info->curr_txpow =
961 eeprom_ch_info[ch].max_power_avg;
962 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
963 ch_info->min_power = 0;
964
965 IWL_DEBUG_EEPROM(priv, "Ch. %d [%sGHz] "
966 "%s%s%s%s%s%s(0x%02x %ddBm):"
967 " Ad-Hoc %ssupported\n",
968 ch_info->channel,
969 is_channel_a_band(ch_info) ?
970 "5.2" : "2.4",
971 CHECK_AND_PRINT_I(VALID),
972 CHECK_AND_PRINT_I(IBSS),
973 CHECK_AND_PRINT_I(ACTIVE),
974 CHECK_AND_PRINT_I(RADAR),
975 CHECK_AND_PRINT_I(WIDE),
976 CHECK_AND_PRINT_I(DFS),
977 eeprom_ch_info[ch].flags,
978 eeprom_ch_info[ch].max_power_avg,
979 ((eeprom_ch_info[ch].
980 flags & EEPROM_CHANNEL_IBSS)
981 && !(eeprom_ch_info[ch].
982 flags & EEPROM_CHANNEL_RADAR))
983 ? "" : "not ");
984
985 ch_info++;
986 }
987 }
988
989 /* Check if we do have HT40 channels */
990 if (cfg(priv)->lib->eeprom_ops.regulatory_bands[5] ==
991 EEPROM_REGULATORY_BAND_NO_HT40 &&
992 cfg(priv)->lib->eeprom_ops.regulatory_bands[6] ==
993 EEPROM_REGULATORY_BAND_NO_HT40)
994 return 0;
995
996 /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
997 for (band = 6; band <= 7; band++) {
998 enum ieee80211_band ieeeband;
999
1000 iwl_init_band_reference(priv, band, &eeprom_ch_count,
1001 &eeprom_ch_info, &eeprom_ch_index);
1002
1003 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
1004 ieeeband =
1005 (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
1006
1007 /* Loop through each band adding each of the channels */
1008 for (ch = 0; ch < eeprom_ch_count; ch++) {
1009 /* Set up driver's info for lower half */
1010 iwl_mod_ht40_chan_info(priv, ieeeband,
1011 eeprom_ch_index[ch],
1012 &eeprom_ch_info[ch],
1013 IEEE80211_CHAN_NO_HT40PLUS);
1014
1015 /* Set up driver's info for upper half */
1016 iwl_mod_ht40_chan_info(priv, ieeeband,
1017 eeprom_ch_index[ch] + 4,
1018 &eeprom_ch_info[ch],
1019 IEEE80211_CHAN_NO_HT40MINUS);
1020 }
1021 }
1022
1023 /* for newer device (6000 series and up)
1024 * EEPROM contain enhanced tx power information
1025 * driver need to process addition information
1026 * to determine the max channel tx power limits
1027 */
1028 if (cfg(priv)->lib->eeprom_ops.enhanced_txpower)
1029 iwl_eeprom_enhanced_txpower(priv);
1030
1031 return 0;
1032 }
1033
1034 /*
1035 * iwl_free_channel_map - undo allocations in iwl_init_channel_map
1036 */
iwl_free_channel_map(struct iwl_priv * priv)1037 void iwl_free_channel_map(struct iwl_priv *priv)
1038 {
1039 kfree(priv->channel_info);
1040 priv->channel_count = 0;
1041 }
1042
1043 /**
1044 * iwl_get_channel_info - Find driver's private channel info
1045 *
1046 * Based on band and channel number.
1047 */
iwl_get_channel_info(const struct iwl_priv * priv,enum ieee80211_band band,u16 channel)1048 const struct iwl_channel_info *iwl_get_channel_info(const struct iwl_priv *priv,
1049 enum ieee80211_band band, u16 channel)
1050 {
1051 int i;
1052
1053 switch (band) {
1054 case IEEE80211_BAND_5GHZ:
1055 for (i = 14; i < priv->channel_count; i++) {
1056 if (priv->channel_info[i].channel == channel)
1057 return &priv->channel_info[i];
1058 }
1059 break;
1060 case IEEE80211_BAND_2GHZ:
1061 if (channel >= 1 && channel <= 14)
1062 return &priv->channel_info[channel - 1];
1063 break;
1064 default:
1065 BUG();
1066 }
1067
1068 return NULL;
1069 }
1070
iwl_rf_config(struct iwl_priv * priv)1071 void iwl_rf_config(struct iwl_priv *priv)
1072 {
1073 u16 radio_cfg;
1074
1075 radio_cfg = iwl_eeprom_query16(priv->shrd, EEPROM_RADIO_CONFIG);
1076
1077 /* write radio config values to register */
1078 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) <= EEPROM_RF_CONFIG_TYPE_MAX) {
1079 iwl_set_bit(trans(priv), CSR_HW_IF_CONFIG_REG,
1080 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
1081 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
1082 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
1083 IWL_INFO(priv, "Radio type=0x%x-0x%x-0x%x\n",
1084 EEPROM_RF_CFG_TYPE_MSK(radio_cfg),
1085 EEPROM_RF_CFG_STEP_MSK(radio_cfg),
1086 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
1087 } else
1088 WARN_ON(1);
1089
1090 /* set CSR_HW_CONFIG_REG for uCode use */
1091 iwl_set_bit(trans(priv), CSR_HW_IF_CONFIG_REG,
1092 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
1093 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
1094 }
1095