1 /* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef SI_H 25 #define SI_H 26 27 #define CG_MULT_THERMAL_STATUS 0x714 28 #define ASIC_MAX_TEMP(x) ((x) << 0) 29 #define ASIC_MAX_TEMP_MASK 0x000001ff 30 #define ASIC_MAX_TEMP_SHIFT 0 31 #define CTF_TEMP(x) ((x) << 9) 32 #define CTF_TEMP_MASK 0x0003fe00 33 #define CTF_TEMP_SHIFT 9 34 35 #define SI_MAX_SH_GPRS 256 36 #define SI_MAX_TEMP_GPRS 16 37 #define SI_MAX_SH_THREADS 256 38 #define SI_MAX_SH_STACK_ENTRIES 4096 39 #define SI_MAX_FRC_EOV_CNT 16384 40 #define SI_MAX_BACKENDS 8 41 #define SI_MAX_BACKENDS_MASK 0xFF 42 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F 43 #define SI_MAX_SIMDS 12 44 #define SI_MAX_SIMDS_MASK 0x0FFF 45 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF 46 #define SI_MAX_PIPES 8 47 #define SI_MAX_PIPES_MASK 0xFF 48 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F 49 #define SI_MAX_LDS_NUM 0xFFFF 50 #define SI_MAX_TCC 16 51 #define SI_MAX_TCC_MASK 0xFFFF 52 53 #define VGA_HDP_CONTROL 0x328 54 #define VGA_MEMORY_DISABLE (1 << 4) 55 56 #define DMIF_ADDR_CONFIG 0xBD4 57 58 #define DMIF_ADDR_CALC 0xC00 59 60 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 61 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) 62 # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) 63 64 #define SRBM_STATUS 0xE50 65 66 #define CC_SYS_RB_BACKEND_DISABLE 0xe80 67 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 68 69 #define VM_L2_CNTL 0x1400 70 #define ENABLE_L2_CACHE (1 << 0) 71 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 72 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 73 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 74 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 75 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 76 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 77 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 78 #define VM_L2_CNTL2 0x1404 79 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 80 #define INVALIDATE_L2_CACHE (1 << 1) 81 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 82 #define INVALIDATE_PTE_AND_PDE_CACHES 0 83 #define INVALIDATE_ONLY_PTE_CACHES 1 84 #define INVALIDATE_ONLY_PDE_CACHES 2 85 #define VM_L2_CNTL3 0x1408 86 #define BANK_SELECT(x) ((x) << 0) 87 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 88 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 89 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 90 #define VM_L2_STATUS 0x140C 91 #define L2_BUSY (1 << 0) 92 #define VM_CONTEXT0_CNTL 0x1410 93 #define ENABLE_CONTEXT (1 << 0) 94 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 95 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 96 #define VM_CONTEXT1_CNTL 0x1414 97 #define VM_CONTEXT0_CNTL2 0x1430 98 #define VM_CONTEXT1_CNTL2 0x1434 99 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 100 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 101 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 102 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 103 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 104 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 105 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 106 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 107 108 #define VM_INVALIDATE_REQUEST 0x1478 109 #define VM_INVALIDATE_RESPONSE 0x147c 110 111 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 112 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 113 114 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 115 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 116 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 117 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 118 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 119 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 120 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 121 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 122 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 123 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 124 125 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 126 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 127 128 #define MC_SHARED_CHMAP 0x2004 129 #define NOOFCHAN_SHIFT 12 130 #define NOOFCHAN_MASK 0x0000f000 131 #define MC_SHARED_CHREMAP 0x2008 132 133 #define MC_VM_FB_LOCATION 0x2024 134 #define MC_VM_AGP_TOP 0x2028 135 #define MC_VM_AGP_BOT 0x202C 136 #define MC_VM_AGP_BASE 0x2030 137 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 138 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 139 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 140 141 #define MC_VM_MX_L1_TLB_CNTL 0x2064 142 #define ENABLE_L1_TLB (1 << 0) 143 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 144 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 145 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 146 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 147 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 148 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 149 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 150 151 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 152 153 #define MC_ARB_RAMCFG 0x2760 154 #define NOOFBANK_SHIFT 0 155 #define NOOFBANK_MASK 0x00000003 156 #define NOOFRANK_SHIFT 2 157 #define NOOFRANK_MASK 0x00000004 158 #define NOOFROWS_SHIFT 3 159 #define NOOFROWS_MASK 0x00000038 160 #define NOOFCOLS_SHIFT 6 161 #define NOOFCOLS_MASK 0x000000C0 162 #define CHANSIZE_SHIFT 8 163 #define CHANSIZE_MASK 0x00000100 164 #define CHANSIZE_OVERRIDE (1 << 11) 165 #define NOOFGROUPS_SHIFT 12 166 #define NOOFGROUPS_MASK 0x00001000 167 168 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 169 #define TRAIN_DONE_D0 (1 << 30) 170 #define TRAIN_DONE_D1 (1 << 31) 171 172 #define MC_SEQ_SUP_CNTL 0x28c8 173 #define RUN_MASK (1 << 0) 174 #define MC_SEQ_SUP_PGM 0x28cc 175 176 #define MC_IO_PAD_CNTL_D0 0x29d0 177 #define MEM_FALL_OUT_CMD (1 << 8) 178 179 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 180 #define MC_SEQ_IO_DEBUG_DATA 0x2a48 181 182 #define HDP_HOST_PATH_CNTL 0x2C00 183 #define HDP_NONSURFACE_BASE 0x2C04 184 #define HDP_NONSURFACE_INFO 0x2C08 185 #define HDP_NONSURFACE_SIZE 0x2C0C 186 187 #define HDP_ADDR_CONFIG 0x2F48 188 #define HDP_MISC_CNTL 0x2F4C 189 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 190 191 #define IH_RB_CNTL 0x3e00 192 # define IH_RB_ENABLE (1 << 0) 193 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 194 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 195 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 196 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 197 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 198 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 199 #define IH_RB_BASE 0x3e04 200 #define IH_RB_RPTR 0x3e08 201 #define IH_RB_WPTR 0x3e0c 202 # define RB_OVERFLOW (1 << 0) 203 # define WPTR_OFFSET_MASK 0x3fffc 204 #define IH_RB_WPTR_ADDR_HI 0x3e10 205 #define IH_RB_WPTR_ADDR_LO 0x3e14 206 #define IH_CNTL 0x3e18 207 # define ENABLE_INTR (1 << 0) 208 # define IH_MC_SWAP(x) ((x) << 1) 209 # define IH_MC_SWAP_NONE 0 210 # define IH_MC_SWAP_16BIT 1 211 # define IH_MC_SWAP_32BIT 2 212 # define IH_MC_SWAP_64BIT 3 213 # define RPTR_REARM (1 << 4) 214 # define MC_WRREQ_CREDIT(x) ((x) << 15) 215 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 216 # define MC_VMID(x) ((x) << 25) 217 218 #define CONFIG_MEMSIZE 0x5428 219 220 #define INTERRUPT_CNTL 0x5468 221 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 222 # define IH_DUMMY_RD_EN (1 << 1) 223 # define IH_REQ_NONSNOOP_EN (1 << 3) 224 # define GEN_IH_INT_EN (1 << 8) 225 #define INTERRUPT_CNTL2 0x546c 226 227 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 228 229 #define BIF_FB_EN 0x5490 230 #define FB_READ_EN (1 << 0) 231 #define FB_WRITE_EN (1 << 1) 232 233 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 234 235 #define DC_LB_MEMORY_SPLIT 0x6b0c 236 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) 237 238 #define PRIORITY_A_CNT 0x6b18 239 #define PRIORITY_MARK_MASK 0x7fff 240 #define PRIORITY_OFF (1 << 16) 241 #define PRIORITY_ALWAYS_ON (1 << 20) 242 #define PRIORITY_B_CNT 0x6b1c 243 244 #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8 245 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) 246 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 247 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 248 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 249 250 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 251 #define VLINE_STATUS 0x6bb8 252 # define VLINE_OCCURRED (1 << 0) 253 # define VLINE_ACK (1 << 4) 254 # define VLINE_STAT (1 << 12) 255 # define VLINE_INTERRUPT (1 << 16) 256 # define VLINE_INTERRUPT_TYPE (1 << 17) 257 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 258 #define VBLANK_STATUS 0x6bbc 259 # define VBLANK_OCCURRED (1 << 0) 260 # define VBLANK_ACK (1 << 4) 261 # define VBLANK_STAT (1 << 12) 262 # define VBLANK_INTERRUPT (1 << 16) 263 # define VBLANK_INTERRUPT_TYPE (1 << 17) 264 265 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 266 #define INT_MASK 0x6b40 267 # define VBLANK_INT_MASK (1 << 0) 268 # define VLINE_INT_MASK (1 << 4) 269 270 #define DISP_INTERRUPT_STATUS 0x60f4 271 # define LB_D1_VLINE_INTERRUPT (1 << 2) 272 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 273 # define DC_HPD1_INTERRUPT (1 << 17) 274 # define DC_HPD1_RX_INTERRUPT (1 << 18) 275 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 276 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 277 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 278 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 279 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 280 # define LB_D2_VLINE_INTERRUPT (1 << 2) 281 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 282 # define DC_HPD2_INTERRUPT (1 << 17) 283 # define DC_HPD2_RX_INTERRUPT (1 << 18) 284 # define DISP_TIMER_INTERRUPT (1 << 24) 285 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 286 # define LB_D3_VLINE_INTERRUPT (1 << 2) 287 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 288 # define DC_HPD3_INTERRUPT (1 << 17) 289 # define DC_HPD3_RX_INTERRUPT (1 << 18) 290 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 291 # define LB_D4_VLINE_INTERRUPT (1 << 2) 292 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 293 # define DC_HPD4_INTERRUPT (1 << 17) 294 # define DC_HPD4_RX_INTERRUPT (1 << 18) 295 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 296 # define LB_D5_VLINE_INTERRUPT (1 << 2) 297 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 298 # define DC_HPD5_INTERRUPT (1 << 17) 299 # define DC_HPD5_RX_INTERRUPT (1 << 18) 300 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 301 # define LB_D6_VLINE_INTERRUPT (1 << 2) 302 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 303 # define DC_HPD6_INTERRUPT (1 << 17) 304 # define DC_HPD6_RX_INTERRUPT (1 << 18) 305 306 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 307 #define GRPH_INT_STATUS 0x6858 308 # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 309 # define GRPH_PFLIP_INT_CLEAR (1 << 8) 310 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 311 #define GRPH_INT_CONTROL 0x685c 312 # define GRPH_PFLIP_INT_MASK (1 << 0) 313 # define GRPH_PFLIP_INT_TYPE (1 << 8) 314 315 #define DACA_AUTODETECT_INT_CONTROL 0x66c8 316 317 #define DC_HPD1_INT_STATUS 0x601c 318 #define DC_HPD2_INT_STATUS 0x6028 319 #define DC_HPD3_INT_STATUS 0x6034 320 #define DC_HPD4_INT_STATUS 0x6040 321 #define DC_HPD5_INT_STATUS 0x604c 322 #define DC_HPD6_INT_STATUS 0x6058 323 # define DC_HPDx_INT_STATUS (1 << 0) 324 # define DC_HPDx_SENSE (1 << 1) 325 # define DC_HPDx_RX_INT_STATUS (1 << 8) 326 327 #define DC_HPD1_INT_CONTROL 0x6020 328 #define DC_HPD2_INT_CONTROL 0x602c 329 #define DC_HPD3_INT_CONTROL 0x6038 330 #define DC_HPD4_INT_CONTROL 0x6044 331 #define DC_HPD5_INT_CONTROL 0x6050 332 #define DC_HPD6_INT_CONTROL 0x605c 333 # define DC_HPDx_INT_ACK (1 << 0) 334 # define DC_HPDx_INT_POLARITY (1 << 8) 335 # define DC_HPDx_INT_EN (1 << 16) 336 # define DC_HPDx_RX_INT_ACK (1 << 20) 337 # define DC_HPDx_RX_INT_EN (1 << 24) 338 339 #define DC_HPD1_CONTROL 0x6024 340 #define DC_HPD2_CONTROL 0x6030 341 #define DC_HPD3_CONTROL 0x603c 342 #define DC_HPD4_CONTROL 0x6048 343 #define DC_HPD5_CONTROL 0x6054 344 #define DC_HPD6_CONTROL 0x6060 345 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 346 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 347 # define DC_HPDx_EN (1 << 28) 348 349 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 350 #define CRTC_STATUS_FRAME_COUNT 0x6e98 351 352 #define GRBM_CNTL 0x8000 353 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 354 355 #define GRBM_STATUS2 0x8008 356 #define RLC_RQ_PENDING (1 << 0) 357 #define RLC_BUSY (1 << 8) 358 #define TC_BUSY (1 << 9) 359 360 #define GRBM_STATUS 0x8010 361 #define CMDFIFO_AVAIL_MASK 0x0000000F 362 #define RING2_RQ_PENDING (1 << 4) 363 #define SRBM_RQ_PENDING (1 << 5) 364 #define RING1_RQ_PENDING (1 << 6) 365 #define CF_RQ_PENDING (1 << 7) 366 #define PF_RQ_PENDING (1 << 8) 367 #define GDS_DMA_RQ_PENDING (1 << 9) 368 #define GRBM_EE_BUSY (1 << 10) 369 #define DB_CLEAN (1 << 12) 370 #define CB_CLEAN (1 << 13) 371 #define TA_BUSY (1 << 14) 372 #define GDS_BUSY (1 << 15) 373 #define VGT_BUSY (1 << 17) 374 #define IA_BUSY_NO_DMA (1 << 18) 375 #define IA_BUSY (1 << 19) 376 #define SX_BUSY (1 << 20) 377 #define SPI_BUSY (1 << 22) 378 #define BCI_BUSY (1 << 23) 379 #define SC_BUSY (1 << 24) 380 #define PA_BUSY (1 << 25) 381 #define DB_BUSY (1 << 26) 382 #define CP_COHERENCY_BUSY (1 << 28) 383 #define CP_BUSY (1 << 29) 384 #define CB_BUSY (1 << 30) 385 #define GUI_ACTIVE (1 << 31) 386 #define GRBM_STATUS_SE0 0x8014 387 #define GRBM_STATUS_SE1 0x8018 388 #define SE_DB_CLEAN (1 << 1) 389 #define SE_CB_CLEAN (1 << 2) 390 #define SE_BCI_BUSY (1 << 22) 391 #define SE_VGT_BUSY (1 << 23) 392 #define SE_PA_BUSY (1 << 24) 393 #define SE_TA_BUSY (1 << 25) 394 #define SE_SX_BUSY (1 << 26) 395 #define SE_SPI_BUSY (1 << 27) 396 #define SE_SC_BUSY (1 << 29) 397 #define SE_DB_BUSY (1 << 30) 398 #define SE_CB_BUSY (1 << 31) 399 400 #define GRBM_SOFT_RESET 0x8020 401 #define SOFT_RESET_CP (1 << 0) 402 #define SOFT_RESET_CB (1 << 1) 403 #define SOFT_RESET_RLC (1 << 2) 404 #define SOFT_RESET_DB (1 << 3) 405 #define SOFT_RESET_GDS (1 << 4) 406 #define SOFT_RESET_PA (1 << 5) 407 #define SOFT_RESET_SC (1 << 6) 408 #define SOFT_RESET_BCI (1 << 7) 409 #define SOFT_RESET_SPI (1 << 8) 410 #define SOFT_RESET_SX (1 << 10) 411 #define SOFT_RESET_TC (1 << 11) 412 #define SOFT_RESET_TA (1 << 12) 413 #define SOFT_RESET_VGT (1 << 14) 414 #define SOFT_RESET_IA (1 << 15) 415 416 #define GRBM_GFX_INDEX 0x802C 417 418 #define GRBM_INT_CNTL 0x8060 419 # define RDERR_INT_ENABLE (1 << 0) 420 # define GUI_IDLE_INT_ENABLE (1 << 19) 421 422 #define CP_STRMOUT_CNTL 0x84FC 423 #define SCRATCH_REG0 0x8500 424 #define SCRATCH_REG1 0x8504 425 #define SCRATCH_REG2 0x8508 426 #define SCRATCH_REG3 0x850C 427 #define SCRATCH_REG4 0x8510 428 #define SCRATCH_REG5 0x8514 429 #define SCRATCH_REG6 0x8518 430 #define SCRATCH_REG7 0x851C 431 432 #define SCRATCH_UMSK 0x8540 433 #define SCRATCH_ADDR 0x8544 434 435 #define CP_SEM_WAIT_TIMER 0x85BC 436 437 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 438 439 #define CP_ME_CNTL 0x86D8 440 #define CP_CE_HALT (1 << 24) 441 #define CP_PFP_HALT (1 << 26) 442 #define CP_ME_HALT (1 << 28) 443 444 #define CP_COHER_CNTL2 0x85E8 445 446 #define CP_RB2_RPTR 0x86f8 447 #define CP_RB1_RPTR 0x86fc 448 #define CP_RB0_RPTR 0x8700 449 #define CP_RB_WPTR_DELAY 0x8704 450 451 #define CP_QUEUE_THRESHOLDS 0x8760 452 #define ROQ_IB1_START(x) ((x) << 0) 453 #define ROQ_IB2_START(x) ((x) << 8) 454 #define CP_MEQ_THRESHOLDS 0x8764 455 #define MEQ1_START(x) ((x) << 0) 456 #define MEQ2_START(x) ((x) << 8) 457 458 #define CP_PERFMON_CNTL 0x87FC 459 460 #define VGT_VTX_VECT_EJECT_REG 0x88B0 461 462 #define VGT_CACHE_INVALIDATION 0x88C4 463 #define CACHE_INVALIDATION(x) ((x) << 0) 464 #define VC_ONLY 0 465 #define TC_ONLY 1 466 #define VC_AND_TC 2 467 #define AUTO_INVLD_EN(x) ((x) << 6) 468 #define NO_AUTO 0 469 #define ES_AUTO 1 470 #define GS_AUTO 2 471 #define ES_AND_GS_AUTO 3 472 #define VGT_ESGS_RING_SIZE 0x88C8 473 #define VGT_GSVS_RING_SIZE 0x88CC 474 475 #define VGT_GS_VERTEX_REUSE 0x88D4 476 477 #define VGT_PRIMITIVE_TYPE 0x8958 478 #define VGT_INDEX_TYPE 0x895C 479 480 #define VGT_NUM_INDICES 0x8970 481 #define VGT_NUM_INSTANCES 0x8974 482 483 #define VGT_TF_RING_SIZE 0x8988 484 485 #define VGT_HS_OFFCHIP_PARAM 0x89B0 486 487 #define VGT_TF_MEMORY_BASE 0x89B8 488 489 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 490 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 491 492 #define PA_CL_ENHANCE 0x8A14 493 #define CLIP_VTX_REORDER_ENA (1 << 0) 494 #define NUM_CLIP_SEQ(x) ((x) << 1) 495 496 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 497 498 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 499 500 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 501 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 502 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 503 504 #define PA_SC_FIFO_SIZE 0x8BCC 505 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 506 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 507 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 508 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 509 510 #define PA_SC_ENHANCE 0x8BF0 511 512 #define SQ_CONFIG 0x8C00 513 514 #define SQC_CACHES 0x8C08 515 516 #define SX_DEBUG_1 0x9060 517 518 #define SPI_STATIC_THREAD_MGMT_1 0x90E0 519 #define SPI_STATIC_THREAD_MGMT_2 0x90E4 520 #define SPI_STATIC_THREAD_MGMT_3 0x90E8 521 #define SPI_PS_MAX_WAVE_ID 0x90EC 522 523 #define SPI_CONFIG_CNTL 0x9100 524 525 #define SPI_CONFIG_CNTL_1 0x913C 526 #define VTX_DONE_DELAY(x) ((x) << 0) 527 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 528 529 #define CGTS_TCC_DISABLE 0x9148 530 #define CGTS_USER_TCC_DISABLE 0x914C 531 #define TCC_DISABLE_MASK 0xFFFF0000 532 #define TCC_DISABLE_SHIFT 16 533 534 #define TA_CNTL_AUX 0x9508 535 536 #define CC_RB_BACKEND_DISABLE 0x98F4 537 #define BACKEND_DISABLE(x) ((x) << 16) 538 #define GB_ADDR_CONFIG 0x98F8 539 #define NUM_PIPES(x) ((x) << 0) 540 #define NUM_PIPES_MASK 0x00000007 541 #define NUM_PIPES_SHIFT 0 542 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 543 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 544 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 545 #define NUM_SHADER_ENGINES(x) ((x) << 12) 546 #define NUM_SHADER_ENGINES_MASK 0x00003000 547 #define NUM_SHADER_ENGINES_SHIFT 12 548 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 549 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 550 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 551 #define NUM_GPUS(x) ((x) << 20) 552 #define NUM_GPUS_MASK 0x00700000 553 #define NUM_GPUS_SHIFT 20 554 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 555 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 556 #define MULTI_GPU_TILE_SIZE_SHIFT 24 557 #define ROW_SIZE(x) ((x) << 28) 558 #define ROW_SIZE_MASK 0x30000000 559 #define ROW_SIZE_SHIFT 28 560 561 #define GB_TILE_MODE0 0x9910 562 # define MICRO_TILE_MODE(x) ((x) << 0) 563 # define ADDR_SURF_DISPLAY_MICRO_TILING 0 564 # define ADDR_SURF_THIN_MICRO_TILING 1 565 # define ADDR_SURF_DEPTH_MICRO_TILING 2 566 # define ARRAY_MODE(x) ((x) << 2) 567 # define ARRAY_LINEAR_GENERAL 0 568 # define ARRAY_LINEAR_ALIGNED 1 569 # define ARRAY_1D_TILED_THIN1 2 570 # define ARRAY_2D_TILED_THIN1 4 571 # define PIPE_CONFIG(x) ((x) << 6) 572 # define ADDR_SURF_P2 0 573 # define ADDR_SURF_P4_8x16 4 574 # define ADDR_SURF_P4_16x16 5 575 # define ADDR_SURF_P4_16x32 6 576 # define ADDR_SURF_P4_32x32 7 577 # define ADDR_SURF_P8_16x16_8x16 8 578 # define ADDR_SURF_P8_16x32_8x16 9 579 # define ADDR_SURF_P8_32x32_8x16 10 580 # define ADDR_SURF_P8_16x32_16x16 11 581 # define ADDR_SURF_P8_32x32_16x16 12 582 # define ADDR_SURF_P8_32x32_16x32 13 583 # define ADDR_SURF_P8_32x64_32x32 14 584 # define TILE_SPLIT(x) ((x) << 11) 585 # define ADDR_SURF_TILE_SPLIT_64B 0 586 # define ADDR_SURF_TILE_SPLIT_128B 1 587 # define ADDR_SURF_TILE_SPLIT_256B 2 588 # define ADDR_SURF_TILE_SPLIT_512B 3 589 # define ADDR_SURF_TILE_SPLIT_1KB 4 590 # define ADDR_SURF_TILE_SPLIT_2KB 5 591 # define ADDR_SURF_TILE_SPLIT_4KB 6 592 # define BANK_WIDTH(x) ((x) << 14) 593 # define ADDR_SURF_BANK_WIDTH_1 0 594 # define ADDR_SURF_BANK_WIDTH_2 1 595 # define ADDR_SURF_BANK_WIDTH_4 2 596 # define ADDR_SURF_BANK_WIDTH_8 3 597 # define BANK_HEIGHT(x) ((x) << 16) 598 # define ADDR_SURF_BANK_HEIGHT_1 0 599 # define ADDR_SURF_BANK_HEIGHT_2 1 600 # define ADDR_SURF_BANK_HEIGHT_4 2 601 # define ADDR_SURF_BANK_HEIGHT_8 3 602 # define MACRO_TILE_ASPECT(x) ((x) << 18) 603 # define ADDR_SURF_MACRO_ASPECT_1 0 604 # define ADDR_SURF_MACRO_ASPECT_2 1 605 # define ADDR_SURF_MACRO_ASPECT_4 2 606 # define ADDR_SURF_MACRO_ASPECT_8 3 607 # define NUM_BANKS(x) ((x) << 20) 608 # define ADDR_SURF_2_BANK 0 609 # define ADDR_SURF_4_BANK 1 610 # define ADDR_SURF_8_BANK 2 611 # define ADDR_SURF_16_BANK 3 612 613 #define CB_PERFCOUNTER0_SELECT0 0x9a20 614 #define CB_PERFCOUNTER0_SELECT1 0x9a24 615 #define CB_PERFCOUNTER1_SELECT0 0x9a28 616 #define CB_PERFCOUNTER1_SELECT1 0x9a2c 617 #define CB_PERFCOUNTER2_SELECT0 0x9a30 618 #define CB_PERFCOUNTER2_SELECT1 0x9a34 619 #define CB_PERFCOUNTER3_SELECT0 0x9a38 620 #define CB_PERFCOUNTER3_SELECT1 0x9a3c 621 622 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 623 #define BACKEND_DISABLE_MASK 0x00FF0000 624 #define BACKEND_DISABLE_SHIFT 16 625 626 #define TCP_CHAN_STEER_LO 0xac0c 627 #define TCP_CHAN_STEER_HI 0xac10 628 629 #define CP_RB0_BASE 0xC100 630 #define CP_RB0_CNTL 0xC104 631 #define RB_BUFSZ(x) ((x) << 0) 632 #define RB_BLKSZ(x) ((x) << 8) 633 #define BUF_SWAP_32BIT (2 << 16) 634 #define RB_NO_UPDATE (1 << 27) 635 #define RB_RPTR_WR_ENA (1 << 31) 636 637 #define CP_RB0_RPTR_ADDR 0xC10C 638 #define CP_RB0_RPTR_ADDR_HI 0xC110 639 #define CP_RB0_WPTR 0xC114 640 641 #define CP_PFP_UCODE_ADDR 0xC150 642 #define CP_PFP_UCODE_DATA 0xC154 643 #define CP_ME_RAM_RADDR 0xC158 644 #define CP_ME_RAM_WADDR 0xC15C 645 #define CP_ME_RAM_DATA 0xC160 646 647 #define CP_CE_UCODE_ADDR 0xC168 648 #define CP_CE_UCODE_DATA 0xC16C 649 650 #define CP_RB1_BASE 0xC180 651 #define CP_RB1_CNTL 0xC184 652 #define CP_RB1_RPTR_ADDR 0xC188 653 #define CP_RB1_RPTR_ADDR_HI 0xC18C 654 #define CP_RB1_WPTR 0xC190 655 #define CP_RB2_BASE 0xC194 656 #define CP_RB2_CNTL 0xC198 657 #define CP_RB2_RPTR_ADDR 0xC19C 658 #define CP_RB2_RPTR_ADDR_HI 0xC1A0 659 #define CP_RB2_WPTR 0xC1A4 660 #define CP_INT_CNTL_RING0 0xC1A8 661 #define CP_INT_CNTL_RING1 0xC1AC 662 #define CP_INT_CNTL_RING2 0xC1B0 663 # define CNTX_BUSY_INT_ENABLE (1 << 19) 664 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 665 # define WAIT_MEM_SEM_INT_ENABLE (1 << 21) 666 # define TIME_STAMP_INT_ENABLE (1 << 26) 667 # define CP_RINGID2_INT_ENABLE (1 << 29) 668 # define CP_RINGID1_INT_ENABLE (1 << 30) 669 # define CP_RINGID0_INT_ENABLE (1 << 31) 670 #define CP_INT_STATUS_RING0 0xC1B4 671 #define CP_INT_STATUS_RING1 0xC1B8 672 #define CP_INT_STATUS_RING2 0xC1BC 673 # define WAIT_MEM_SEM_INT_STAT (1 << 21) 674 # define TIME_STAMP_INT_STAT (1 << 26) 675 # define CP_RINGID2_INT_STAT (1 << 29) 676 # define CP_RINGID1_INT_STAT (1 << 30) 677 # define CP_RINGID0_INT_STAT (1 << 31) 678 679 #define CP_DEBUG 0xC1FC 680 681 #define RLC_CNTL 0xC300 682 # define RLC_ENABLE (1 << 0) 683 #define RLC_RL_BASE 0xC304 684 #define RLC_RL_SIZE 0xC308 685 #define RLC_LB_CNTL 0xC30C 686 #define RLC_SAVE_AND_RESTORE_BASE 0xC310 687 #define RLC_LB_CNTR_MAX 0xC314 688 #define RLC_LB_CNTR_INIT 0xC318 689 690 #define RLC_CLEAR_STATE_RESTORE_BASE 0xC320 691 692 #define RLC_UCODE_ADDR 0xC32C 693 #define RLC_UCODE_DATA 0xC330 694 695 #define RLC_MC_CNTL 0xC344 696 #define RLC_UCODE_CNTL 0xC348 697 698 #define VGT_EVENT_INITIATOR 0x28a90 699 # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 700 # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 701 # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 702 # define CACHE_FLUSH_TS (4 << 0) 703 # define CACHE_FLUSH (6 << 0) 704 # define CS_PARTIAL_FLUSH (7 << 0) 705 # define VGT_STREAMOUT_RESET (10 << 0) 706 # define END_OF_PIPE_INCR_DE (11 << 0) 707 # define END_OF_PIPE_IB_END (12 << 0) 708 # define RST_PIX_CNT (13 << 0) 709 # define VS_PARTIAL_FLUSH (15 << 0) 710 # define PS_PARTIAL_FLUSH (16 << 0) 711 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 712 # define ZPASS_DONE (21 << 0) 713 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 714 # define PERFCOUNTER_START (23 << 0) 715 # define PERFCOUNTER_STOP (24 << 0) 716 # define PIPELINESTAT_START (25 << 0) 717 # define PIPELINESTAT_STOP (26 << 0) 718 # define PERFCOUNTER_SAMPLE (27 << 0) 719 # define SAMPLE_PIPELINESTAT (30 << 0) 720 # define SAMPLE_STREAMOUTSTATS (32 << 0) 721 # define RESET_VTX_CNT (33 << 0) 722 # define VGT_FLUSH (36 << 0) 723 # define BOTTOM_OF_PIPE_TS (40 << 0) 724 # define DB_CACHE_FLUSH_AND_INV (42 << 0) 725 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 726 # define FLUSH_AND_INV_DB_META (44 << 0) 727 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 728 # define FLUSH_AND_INV_CB_META (46 << 0) 729 # define CS_DONE (47 << 0) 730 # define PS_DONE (48 << 0) 731 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 732 # define THREAD_TRACE_START (51 << 0) 733 # define THREAD_TRACE_STOP (52 << 0) 734 # define THREAD_TRACE_FLUSH (54 << 0) 735 # define THREAD_TRACE_FINISH (55 << 0) 736 737 /* 738 * PM4 739 */ 740 #define PACKET_TYPE0 0 741 #define PACKET_TYPE1 1 742 #define PACKET_TYPE2 2 743 #define PACKET_TYPE3 3 744 745 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 746 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 747 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 748 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 749 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 750 (((reg) >> 2) & 0xFFFF) | \ 751 ((n) & 0x3FFF) << 16) 752 #define CP_PACKET2 0x80000000 753 #define PACKET2_PAD_SHIFT 0 754 #define PACKET2_PAD_MASK (0x3fffffff << 0) 755 756 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 757 758 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 759 (((op) & 0xFF) << 8) | \ 760 ((n) & 0x3FFF) << 16) 761 762 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 763 764 /* Packet 3 types */ 765 #define PACKET3_NOP 0x10 766 #define PACKET3_SET_BASE 0x11 767 #define PACKET3_BASE_INDEX(x) ((x) << 0) 768 #define GDS_PARTITION_BASE 2 769 #define CE_PARTITION_BASE 3 770 #define PACKET3_CLEAR_STATE 0x12 771 #define PACKET3_INDEX_BUFFER_SIZE 0x13 772 #define PACKET3_DISPATCH_DIRECT 0x15 773 #define PACKET3_DISPATCH_INDIRECT 0x16 774 #define PACKET3_ALLOC_GDS 0x1B 775 #define PACKET3_WRITE_GDS_RAM 0x1C 776 #define PACKET3_ATOMIC_GDS 0x1D 777 #define PACKET3_ATOMIC 0x1E 778 #define PACKET3_OCCLUSION_QUERY 0x1F 779 #define PACKET3_SET_PREDICATION 0x20 780 #define PACKET3_REG_RMW 0x21 781 #define PACKET3_COND_EXEC 0x22 782 #define PACKET3_PRED_EXEC 0x23 783 #define PACKET3_DRAW_INDIRECT 0x24 784 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 785 #define PACKET3_INDEX_BASE 0x26 786 #define PACKET3_DRAW_INDEX_2 0x27 787 #define PACKET3_CONTEXT_CONTROL 0x28 788 #define PACKET3_INDEX_TYPE 0x2A 789 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 790 #define PACKET3_DRAW_INDEX_AUTO 0x2D 791 #define PACKET3_DRAW_INDEX_IMMD 0x2E 792 #define PACKET3_NUM_INSTANCES 0x2F 793 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 794 #define PACKET3_INDIRECT_BUFFER_CONST 0x31 795 #define PACKET3_INDIRECT_BUFFER 0x32 796 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 797 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 798 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 799 #define PACKET3_WRITE_DATA 0x37 800 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 801 #define PACKET3_MEM_SEMAPHORE 0x39 802 #define PACKET3_MPEG_INDEX 0x3A 803 #define PACKET3_COPY_DW 0x3B 804 #define PACKET3_WAIT_REG_MEM 0x3C 805 #define PACKET3_MEM_WRITE 0x3D 806 #define PACKET3_COPY_DATA 0x40 807 #define PACKET3_PFP_SYNC_ME 0x42 808 #define PACKET3_SURFACE_SYNC 0x43 809 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 810 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 811 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 812 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 813 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 814 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 815 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 816 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 817 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 818 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 819 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 820 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 821 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 822 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 823 # define PACKET3_TC_ACTION_ENA (1 << 23) 824 # define PACKET3_CB_ACTION_ENA (1 << 25) 825 # define PACKET3_DB_ACTION_ENA (1 << 26) 826 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 827 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 828 #define PACKET3_ME_INITIALIZE 0x44 829 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 830 #define PACKET3_COND_WRITE 0x45 831 #define PACKET3_EVENT_WRITE 0x46 832 #define EVENT_TYPE(x) ((x) << 0) 833 #define EVENT_INDEX(x) ((x) << 8) 834 /* 0 - any non-TS event 835 * 1 - ZPASS_DONE 836 * 2 - SAMPLE_PIPELINESTAT 837 * 3 - SAMPLE_STREAMOUTSTAT* 838 * 4 - *S_PARTIAL_FLUSH 839 * 5 - EOP events 840 * 6 - EOS events 841 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT 842 */ 843 #define INV_L2 (1 << 20) 844 /* INV TC L2 cache when EVENT_INDEX = 7 */ 845 #define PACKET3_EVENT_WRITE_EOP 0x47 846 #define DATA_SEL(x) ((x) << 29) 847 /* 0 - discard 848 * 1 - send low 32bit data 849 * 2 - send 64bit data 850 * 3 - send 64bit counter value 851 */ 852 #define INT_SEL(x) ((x) << 24) 853 /* 0 - none 854 * 1 - interrupt only (DATA_SEL = 0) 855 * 2 - interrupt when data write is confirmed 856 */ 857 #define PACKET3_EVENT_WRITE_EOS 0x48 858 #define PACKET3_PREAMBLE_CNTL 0x4A 859 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 860 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 861 #define PACKET3_ONE_REG_WRITE 0x57 862 #define PACKET3_LOAD_CONFIG_REG 0x5F 863 #define PACKET3_LOAD_CONTEXT_REG 0x60 864 #define PACKET3_LOAD_SH_REG 0x61 865 #define PACKET3_SET_CONFIG_REG 0x68 866 #define PACKET3_SET_CONFIG_REG_START 0x00008000 867 #define PACKET3_SET_CONFIG_REG_END 0x0000b000 868 #define PACKET3_SET_CONTEXT_REG 0x69 869 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 870 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 871 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 872 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 873 #define PACKET3_SET_SH_REG 0x76 874 #define PACKET3_SET_SH_REG_START 0x0000b000 875 #define PACKET3_SET_SH_REG_END 0x0000c000 876 #define PACKET3_SET_SH_REG_OFFSET 0x77 877 #define PACKET3_ME_WRITE 0x7A 878 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 879 #define PACKET3_SCRATCH_RAM_READ 0x7E 880 #define PACKET3_CE_WRITE 0x7F 881 #define PACKET3_LOAD_CONST_RAM 0x80 882 #define PACKET3_WRITE_CONST_RAM 0x81 883 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 884 #define PACKET3_DUMP_CONST_RAM 0x83 885 #define PACKET3_INCREMENT_CE_COUNTER 0x84 886 #define PACKET3_INCREMENT_DE_COUNTER 0x85 887 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 888 #define PACKET3_WAIT_ON_DE_COUNTER 0x87 889 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 890 #define PACKET3_SET_CE_DE_COUNTERS 0x89 891 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A 892 893 #endif 894