1 #ifndef _ASM_POWERPC_MMU_HASH32_H_ 2 #define _ASM_POWERPC_MMU_HASH32_H_ 3 /* 4 * 32-bit hash table MMU support 5 */ 6 7 /* 8 * BATs 9 */ 10 11 /* Block size masks */ 12 #define BL_128K 0x000 13 #define BL_256K 0x001 14 #define BL_512K 0x003 15 #define BL_1M 0x007 16 #define BL_2M 0x00F 17 #define BL_4M 0x01F 18 #define BL_8M 0x03F 19 #define BL_16M 0x07F 20 #define BL_32M 0x0FF 21 #define BL_64M 0x1FF 22 #define BL_128M 0x3FF 23 #define BL_256M 0x7FF 24 25 /* BAT Access Protection */ 26 #define BPP_XX 0x00 /* No access */ 27 #define BPP_RX 0x01 /* Read only */ 28 #define BPP_RW 0x02 /* Read/write */ 29 30 #ifndef __ASSEMBLY__ 31 /* Contort a phys_addr_t into the right format/bits for a BAT */ 32 #ifdef CONFIG_PHYS_64BIT 33 #define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \ 34 ((x & 0x0000000e00000000ULL) >> 24) | \ 35 ((x & 0x0000000100000000ULL) >> 30))) 36 #else 37 #define BAT_PHYS_ADDR(x) (x) 38 #endif 39 40 struct ppc_bat { 41 u32 batu; 42 u32 batl; 43 }; 44 #endif /* !__ASSEMBLY__ */ 45 46 /* 47 * Hash table 48 */ 49 50 /* Values for PP (assumes Ks=0, Kp=1) */ 51 #define PP_RWXX 0 /* Supervisor read/write, User none */ 52 #define PP_RWRX 1 /* Supervisor read/write, User read */ 53 #define PP_RWRW 2 /* Supervisor read/write, User read/write */ 54 #define PP_RXRX 3 /* Supervisor read, User read */ 55 56 #ifndef __ASSEMBLY__ 57 58 /* 59 * Hardware Page Table Entry 60 * Note that the xpn and x bitfields are used only by processors that 61 * support extended addressing; otherwise, those bits are reserved. 62 */ 63 struct hash_pte { 64 unsigned long v:1; /* Entry is valid */ 65 unsigned long vsid:24; /* Virtual segment identifier */ 66 unsigned long h:1; /* Hash algorithm indicator */ 67 unsigned long api:6; /* Abbreviated page index */ 68 unsigned long rpn:20; /* Real (physical) page number */ 69 unsigned long xpn:3; /* Real page number bits 0-2, optional */ 70 unsigned long r:1; /* Referenced */ 71 unsigned long c:1; /* Changed */ 72 unsigned long w:1; /* Write-thru cache mode */ 73 unsigned long i:1; /* Cache inhibited */ 74 unsigned long m:1; /* Memory coherence */ 75 unsigned long g:1; /* Guarded */ 76 unsigned long x:1; /* Real page number bit 3, optional */ 77 unsigned long pp:2; /* Page protection */ 78 }; 79 80 typedef struct { 81 unsigned long id; 82 unsigned long vdso_base; 83 } mm_context_t; 84 85 #endif /* !__ASSEMBLY__ */ 86 87 /* We happily ignore the smaller BATs on 601, we don't actually use 88 * those definitions on hash32 at the moment anyway 89 */ 90 #define mmu_virtual_psize MMU_PAGE_4K 91 #define mmu_linear_psize MMU_PAGE_256M 92 93 #endif /* _ASM_POWERPC_MMU_HASH32_H_ */ 94