1 /* MN10300 SMP support
2 *
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * Modified by Matsushita Electric Industrial Co., Ltd.
7 * Modifications:
8 * 13-Nov-2006 MEI Define IPI-IRQ number and add inline/macro function
9 * for SMP support.
10 * 22-Jan-2007 MEI Add the define related to SMP_BOOT_IRQ.
11 * 23-Feb-2007 MEI Add the define related to SMP icahce invalidate.
12 * 23-Jun-2008 MEI Delete INTC_IPI.
13 * 22-Jul-2008 MEI Add smp_nmi_call_function and related defines.
14 * 04-Aug-2008 MEI Delete USE_DOIRQ_CACHE_IPI.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public Licence
18 * as published by the Free Software Foundation; either version
19 * 2 of the Licence, or (at your option) any later version.
20 */
21 #ifndef _ASM_SMP_H
22 #define _ASM_SMP_H
23
24 #ifndef __ASSEMBLY__
25 #include <linux/threads.h>
26 #include <linux/cpumask.h>
27 #endif
28
29 #ifdef CONFIG_SMP
30 #include <proc/smp-regs.h>
31
32 #define RESCHEDULE_IPI 63
33 #define CALL_FUNC_SINGLE_IPI 192
34 #define LOCAL_TIMER_IPI 193
35 #define FLUSH_CACHE_IPI 194
36 #define CALL_FUNCTION_NMI_IPI 195
37 #define DEBUGGER_NMI_IPI 196
38
39 #define SMP_BOOT_IRQ 195
40
41 #define RESCHEDULE_GxICR_LV GxICR_LEVEL_6
42 #define CALL_FUNCTION_GxICR_LV GxICR_LEVEL_4
43 #define LOCAL_TIMER_GxICR_LV GxICR_LEVEL_4
44 #define FLUSH_CACHE_GxICR_LV GxICR_LEVEL_0
45 #define SMP_BOOT_GxICR_LV GxICR_LEVEL_0
46 #define DEBUGGER_GxICR_LV CONFIG_DEBUGGER_IRQ_LEVEL
47
48 #define TIME_OUT_COUNT_BOOT_IPI 100
49 #define DELAY_TIME_BOOT_IPI 75000
50
51
52 #ifndef __ASSEMBLY__
53
54 /**
55 * raw_smp_processor_id - Determine the raw CPU ID of the CPU running it
56 *
57 * What we really want to do is to use the CPUID hardware CPU register to get
58 * this information, but accesses to that aren't cached, and run at system bus
59 * speed, not CPU speed. A copy of this value is, however, stored in the
60 * thread_info struct, and that can be cached.
61 *
62 * An alternate way of dealing with this could be to use the EPSW.S bits to
63 * cache this information for systems with up to four CPUs.
64 */
65 #define arch_smp_processor_id() (CPUID)
66 #if 0
67 #define raw_smp_processor_id() (arch_smp_processor_id())
68 #else
69 #define raw_smp_processor_id() (current_thread_info()->cpu)
70 #endif
71
cpu_logical_map(int cpu)72 static inline int cpu_logical_map(int cpu)
73 {
74 return cpu;
75 }
76
cpu_number_map(int cpu)77 static inline int cpu_number_map(int cpu)
78 {
79 return cpu;
80 }
81
82
83 extern cpumask_t cpu_boot_map;
84
85 extern void smp_init_cpus(void);
86 extern void smp_cache_interrupt(void);
87 extern void send_IPI_allbutself(int irq);
88 extern int smp_nmi_call_function(smp_call_func_t func, void *info, int wait);
89
90 extern void arch_send_call_function_single_ipi(int cpu);
91 extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
92
93 #ifdef CONFIG_HOTPLUG_CPU
94 extern int __cpu_disable(void);
95 extern void __cpu_die(unsigned int cpu);
96 #endif /* CONFIG_HOTPLUG_CPU */
97
98 #endif /* __ASSEMBLY__ */
99 #else /* CONFIG_SMP */
100 #ifndef __ASSEMBLY__
101
smp_init_cpus(void)102 static inline void smp_init_cpus(void) {}
103
104 #endif /* __ASSEMBLY__ */
105 #endif /* CONFIG_SMP */
106
107 #endif /* _ASM_SMP_H */
108