1 /*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19 #ifndef __MACH_MXS_H__
20 #define __MACH_MXS_H__
21
22 #ifndef __ASSEMBLER__
23 #include <linux/io.h>
24 #endif
25 #include <asm/mach-types.h>
26 #include <mach/digctl.h>
27 #include <mach/hardware.h>
28
29 /*
30 * IO addresses common to MXS-based
31 */
32 #define MXS_IO_BASE_ADDR 0x80000000
33 #define MXS_IO_SIZE SZ_1M
34
35 #define MXS_ICOLL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x000000)
36 #define MXS_APBH_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x004000)
37 #define MXS_BCH_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00a000)
38 #define MXS_GPMI_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00c000)
39 #define MXS_PINCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x018000)
40 #define MXS_DIGCTL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x01c000)
41 #define MXS_APBX_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x024000)
42 #define MXS_DCP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x028000)
43 #define MXS_PXP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02a000)
44 #define MXS_OCOTP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02c000)
45 #define MXS_AXI_AHB0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02e000)
46 #define MXS_LCDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x030000)
47 #define MXS_CLKCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x040000)
48 #define MXS_SAIF0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x042000)
49 #define MXS_POWER_BASE_ADDR (MXS_IO_BASE_ADDR + 0x044000)
50 #define MXS_SAIF1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x046000)
51 #define MXS_LRADC_BASE_ADDR (MXS_IO_BASE_ADDR + 0x050000)
52 #define MXS_SPDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x054000)
53 #define MXS_I2C0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x058000)
54 #define MXS_PWM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x064000)
55 #define MXS_TIMROT_BASE_ADDR (MXS_IO_BASE_ADDR + 0x068000)
56 #define MXS_AUART1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06c000)
57 #define MXS_AUART2_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06e000)
58 #define MXS_DRAM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x0e0000)
59
60 /*
61 * It maps the whole address space to [0xf4000000, 0xf50fffff].
62 *
63 * OCRAM 0x00000000+0x020000 -> 0xf4000000+0x020000
64 * IO 0x80000000+0x100000 -> 0xf5000000+0x100000
65 */
66 #define MXS_IO_P2V(x) (0xf4000000 + \
67 (((x) & 0x80000000) >> 7) + \
68 (((x) & 0x000fffff)))
69
70 #define MXS_IO_ADDRESS(x) IOMEM(MXS_IO_P2V(x))
71
72 #define mxs_map_entry(soc, name, _type) { \
73 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
74 .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \
75 .length = soc ## _ ## name ## _SIZE, \
76 .type = _type, \
77 }
78
79 #define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr))
80
81 #define MXS_SET_ADDR 0x4
82 #define MXS_CLR_ADDR 0x8
83 #define MXS_TOG_ADDR 0xc
84
85 #ifndef __ASSEMBLER__
__mxs_setl(u32 mask,void __iomem * reg)86 static inline void __mxs_setl(u32 mask, void __iomem *reg)
87 {
88 __raw_writel(mask, reg + MXS_SET_ADDR);
89 }
90
__mxs_clrl(u32 mask,void __iomem * reg)91 static inline void __mxs_clrl(u32 mask, void __iomem *reg)
92 {
93 __raw_writel(mask, reg + MXS_CLR_ADDR);
94 }
95
__mxs_togl(u32 mask,void __iomem * reg)96 static inline void __mxs_togl(u32 mask, void __iomem *reg)
97 {
98 __raw_writel(mask, reg + MXS_TOG_ADDR);
99 }
100
101 /*
102 * MXS CPU types
103 */
104 #define MXS_CHIPID (MXS_IO_ADDRESS(MXS_DIGCTL_BASE_ADDR) + HW_DIGCTL_CHIPID)
105
cpu_is_mx23(void)106 static inline int cpu_is_mx23(void)
107 {
108 return ((__raw_readl(MXS_CHIPID) >> 16) == 0x3780);
109 }
110
cpu_is_mx28(void)111 static inline int cpu_is_mx28(void)
112 {
113 return ((__raw_readl(MXS_CHIPID) >> 16) == 0x2800);
114 }
115 #endif
116
117 #endif /* __MACH_MXS_H__ */
118