1 /* 2 * include/linux/mmc/sdio.h 3 * 4 * Copyright 2006-2007 Pierre Ossman 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or (at 9 * your option) any later version. 10 */ 11 12 #ifndef MMC_SDIO_H 13 #define MMC_SDIO_H 14 15 /* SDIO commands type argument response */ 16 #define SD_IO_SEND_OP_COND 5 /* bcr [23:0] OCR R4 */ 17 #define SD_IO_RW_DIRECT 52 /* ac [31:0] See below R5 */ 18 #define SD_IO_RW_EXTENDED 53 /* adtc [31:0] See below R5 */ 19 20 /* 21 * SD_IO_RW_DIRECT argument format: 22 * 23 * [31] R/W flag 24 * [30:28] Function number 25 * [27] RAW flag 26 * [25:9] Register address 27 * [7:0] Data 28 */ 29 30 /* 31 * SD_IO_RW_EXTENDED argument format: 32 * 33 * [31] R/W flag 34 * [30:28] Function number 35 * [27] Block mode 36 * [26] Increment address 37 * [25:9] Register address 38 * [8:0] Byte/block count 39 */ 40 41 #define R4_MEMORY_PRESENT (1 << 27) 42 43 /* 44 SDIO status in R5 45 Type 46 e : error bit 47 s : status bit 48 r : detected and set for the actual command response 49 x : detected and set during command execution. the host must poll 50 the card by sending status command in order to read these bits. 51 Clear condition 52 a : according to the card state 53 b : always related to the previous command. Reception of 54 a valid command will clear it (with a delay of one command) 55 c : clear by read 56 */ 57 58 #define R5_COM_CRC_ERROR (1 << 15) /* er, b */ 59 #define R5_ILLEGAL_COMMAND (1 << 14) /* er, b */ 60 #define R5_ERROR (1 << 11) /* erx, c */ 61 #define R5_FUNCTION_NUMBER (1 << 9) /* er, c */ 62 #define R5_OUT_OF_RANGE (1 << 8) /* er, c */ 63 #define R5_STATUS(x) (x & 0xCB00) 64 #define R5_IO_CURRENT_STATE(x) ((x & 0x3000) >> 12) /* s, b */ 65 66 /* 67 * Card Common Control Registers (CCCR) 68 */ 69 70 #define SDIO_CCCR_CCCR 0x00 71 72 #define SDIO_CCCR_REV_1_00 0 /* CCCR/FBR Version 1.00 */ 73 #define SDIO_CCCR_REV_1_10 1 /* CCCR/FBR Version 1.10 */ 74 #define SDIO_CCCR_REV_1_20 2 /* CCCR/FBR Version 1.20 */ 75 76 #define SDIO_SDIO_REV_1_00 0 /* SDIO Spec Version 1.00 */ 77 #define SDIO_SDIO_REV_1_10 1 /* SDIO Spec Version 1.10 */ 78 #define SDIO_SDIO_REV_1_20 2 /* SDIO Spec Version 1.20 */ 79 #define SDIO_SDIO_REV_2_00 3 /* SDIO Spec Version 2.00 */ 80 81 #define SDIO_CCCR_SD 0x01 82 83 #define SDIO_SD_REV_1_01 0 /* SD Physical Spec Version 1.01 */ 84 #define SDIO_SD_REV_1_10 1 /* SD Physical Spec Version 1.10 */ 85 #define SDIO_SD_REV_2_00 2 /* SD Physical Spec Version 2.00 */ 86 87 #define SDIO_CCCR_IOEx 0x02 88 #define SDIO_CCCR_IORx 0x03 89 90 #define SDIO_CCCR_IENx 0x04 /* Function/Master Interrupt Enable */ 91 #define SDIO_CCCR_INTx 0x05 /* Function Interrupt Pending */ 92 93 #define SDIO_CCCR_ABORT 0x06 /* function abort/card reset */ 94 95 #define SDIO_CCCR_IF 0x07 /* bus interface controls */ 96 97 #define SDIO_BUS_WIDTH_1BIT 0x00 98 #define SDIO_BUS_WIDTH_4BIT 0x02 99 #define SDIO_BUS_ECSI 0x20 /* Enable continuous SPI interrupt */ 100 #define SDIO_BUS_SCSI 0x40 /* Support continuous SPI interrupt */ 101 102 #define SDIO_BUS_ASYNC_INT 0x20 103 104 #define SDIO_BUS_CD_DISABLE 0x80 /* disable pull-up on DAT3 (pin 1) */ 105 106 #define SDIO_CCCR_CAPS 0x08 107 108 #define SDIO_CCCR_CAP_SDC 0x01 /* can do CMD52 while data transfer */ 109 #define SDIO_CCCR_CAP_SMB 0x02 /* can do multi-block xfers (CMD53) */ 110 #define SDIO_CCCR_CAP_SRW 0x04 /* supports read-wait protocol */ 111 #define SDIO_CCCR_CAP_SBS 0x08 /* supports suspend/resume */ 112 #define SDIO_CCCR_CAP_S4MI 0x10 /* interrupt during 4-bit CMD53 */ 113 #define SDIO_CCCR_CAP_E4MI 0x20 /* enable ints during 4-bit CMD53 */ 114 #define SDIO_CCCR_CAP_LSC 0x40 /* low speed card */ 115 #define SDIO_CCCR_CAP_4BLS 0x80 /* 4 bit low speed card */ 116 117 #define SDIO_CCCR_CIS 0x09 /* common CIS pointer (3 bytes) */ 118 119 /* Following 4 regs are valid only if SBS is set */ 120 #define SDIO_CCCR_SUSPEND 0x0c 121 #define SDIO_CCCR_SELx 0x0d 122 #define SDIO_CCCR_EXECx 0x0e 123 #define SDIO_CCCR_READYx 0x0f 124 125 #define SDIO_CCCR_BLKSIZE 0x10 126 127 #define SDIO_CCCR_POWER 0x12 128 129 #define SDIO_POWER_SMPC 0x01 /* Supports Master Power Control */ 130 #define SDIO_POWER_EMPC 0x02 /* Enable Master Power Control */ 131 132 #define SDIO_CCCR_SPEED 0x13 133 134 #define SDIO_SPEED_SHS 0x01 /* Supports High-Speed mode */ 135 #define SDIO_SPEED_EHS 0x02 /* Enable High-Speed mode */ 136 137 /* 138 * Function Basic Registers (FBR) 139 */ 140 141 #define SDIO_FBR_BASE(f) ((f) * 0x100) /* base of function f's FBRs */ 142 143 #define SDIO_FBR_STD_IF 0x00 144 145 #define SDIO_FBR_SUPPORTS_CSA 0x40 /* supports Code Storage Area */ 146 #define SDIO_FBR_ENABLE_CSA 0x80 /* enable Code Storage Area */ 147 148 #define SDIO_FBR_STD_IF_EXT 0x01 149 150 #define SDIO_FBR_POWER 0x02 151 152 #define SDIO_FBR_POWER_SPS 0x01 /* Supports Power Selection */ 153 #define SDIO_FBR_POWER_EPS 0x02 /* Enable (low) Power Selection */ 154 155 #define SDIO_FBR_CIS 0x09 /* CIS pointer (3 bytes) */ 156 157 158 #define SDIO_FBR_CSA 0x0C /* CSA pointer (3 bytes) */ 159 160 #define SDIO_FBR_CSA_DATA 0x0F 161 162 #define SDIO_FBR_BLKSIZE 0x10 /* block size (2 bytes) */ 163 164 #endif 165 166