1 /* 2 * include/linux/mfd/wm8994/registers.h -- Register definitions for WM8994 3 * 4 * Copyright 2009 Wolfson Microelectronics PLC. 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 15 #ifndef __MFD_WM8994_REGISTERS_H__ 16 #define __MFD_WM8994_REGISTERS_H__ 17 18 /* 19 * Register values. 20 */ 21 #define WM8994_SOFTWARE_RESET 0x00 22 #define WM8994_POWER_MANAGEMENT_1 0x01 23 #define WM8994_POWER_MANAGEMENT_2 0x02 24 #define WM8994_POWER_MANAGEMENT_3 0x03 25 #define WM8994_POWER_MANAGEMENT_4 0x04 26 #define WM8994_POWER_MANAGEMENT_5 0x05 27 #define WM8994_POWER_MANAGEMENT_6 0x06 28 #define WM8994_INPUT_MIXER_1 0x15 29 #define WM8994_LEFT_LINE_INPUT_1_2_VOLUME 0x18 30 #define WM8994_LEFT_LINE_INPUT_3_4_VOLUME 0x19 31 #define WM8994_RIGHT_LINE_INPUT_1_2_VOLUME 0x1A 32 #define WM8994_RIGHT_LINE_INPUT_3_4_VOLUME 0x1B 33 #define WM8994_LEFT_OUTPUT_VOLUME 0x1C 34 #define WM8994_RIGHT_OUTPUT_VOLUME 0x1D 35 #define WM8994_LINE_OUTPUTS_VOLUME 0x1E 36 #define WM8994_HPOUT2_VOLUME 0x1F 37 #define WM8994_LEFT_OPGA_VOLUME 0x20 38 #define WM8994_RIGHT_OPGA_VOLUME 0x21 39 #define WM8994_SPKMIXL_ATTENUATION 0x22 40 #define WM8994_SPKMIXR_ATTENUATION 0x23 41 #define WM8994_SPKOUT_MIXERS 0x24 42 #define WM8994_CLASSD 0x25 43 #define WM8994_SPEAKER_VOLUME_LEFT 0x26 44 #define WM8994_SPEAKER_VOLUME_RIGHT 0x27 45 #define WM8994_INPUT_MIXER_2 0x28 46 #define WM8994_INPUT_MIXER_3 0x29 47 #define WM8994_INPUT_MIXER_4 0x2A 48 #define WM8994_INPUT_MIXER_5 0x2B 49 #define WM8994_INPUT_MIXER_6 0x2C 50 #define WM8994_OUTPUT_MIXER_1 0x2D 51 #define WM8994_OUTPUT_MIXER_2 0x2E 52 #define WM8994_OUTPUT_MIXER_3 0x2F 53 #define WM8994_OUTPUT_MIXER_4 0x30 54 #define WM8994_OUTPUT_MIXER_5 0x31 55 #define WM8994_OUTPUT_MIXER_6 0x32 56 #define WM8994_HPOUT2_MIXER 0x33 57 #define WM8994_LINE_MIXER_1 0x34 58 #define WM8994_LINE_MIXER_2 0x35 59 #define WM8994_SPEAKER_MIXER 0x36 60 #define WM8994_ADDITIONAL_CONTROL 0x37 61 #define WM8994_ANTIPOP_1 0x38 62 #define WM8994_ANTIPOP_2 0x39 63 #define WM8994_MICBIAS 0x3A 64 #define WM8994_LDO_1 0x3B 65 #define WM8994_LDO_2 0x3C 66 #define WM8958_MICBIAS1 0x3D 67 #define WM8958_MICBIAS2 0x3E 68 #define WM8994_CHARGE_PUMP_1 0x4C 69 #define WM8958_CHARGE_PUMP_2 0x4D 70 #define WM8994_CLASS_W_1 0x51 71 #define WM8994_DC_SERVO_1 0x54 72 #define WM8994_DC_SERVO_2 0x55 73 #define WM8994_DC_SERVO_4 0x57 74 #define WM8994_DC_SERVO_READBACK 0x58 75 #define WM8994_ANALOGUE_HP_1 0x60 76 #define WM8958_MIC_DETECT_1 0xD0 77 #define WM8958_MIC_DETECT_2 0xD1 78 #define WM8958_MIC_DETECT_3 0xD2 79 #define WM8994_CHIP_REVISION 0x100 80 #define WM8994_CONTROL_INTERFACE 0x101 81 #define WM8994_WRITE_SEQUENCER_CTRL_1 0x110 82 #define WM8994_WRITE_SEQUENCER_CTRL_2 0x111 83 #define WM8994_AIF1_CLOCKING_1 0x200 84 #define WM8994_AIF1_CLOCKING_2 0x201 85 #define WM8994_AIF2_CLOCKING_1 0x204 86 #define WM8994_AIF2_CLOCKING_2 0x205 87 #define WM8994_CLOCKING_1 0x208 88 #define WM8994_CLOCKING_2 0x209 89 #define WM8994_AIF1_RATE 0x210 90 #define WM8994_AIF2_RATE 0x211 91 #define WM8994_RATE_STATUS 0x212 92 #define WM8994_FLL1_CONTROL_1 0x220 93 #define WM8994_FLL1_CONTROL_2 0x221 94 #define WM8994_FLL1_CONTROL_3 0x222 95 #define WM8994_FLL1_CONTROL_4 0x223 96 #define WM8994_FLL1_CONTROL_5 0x224 97 #define WM8994_FLL2_CONTROL_1 0x240 98 #define WM8994_FLL2_CONTROL_2 0x241 99 #define WM8994_FLL2_CONTROL_3 0x242 100 #define WM8994_FLL2_CONTROL_4 0x243 101 #define WM8994_FLL2_CONTROL_5 0x244 102 #define WM8994_AIF1_CONTROL_1 0x300 103 #define WM8994_AIF1_CONTROL_2 0x301 104 #define WM8994_AIF1_MASTER_SLAVE 0x302 105 #define WM8994_AIF1_BCLK 0x303 106 #define WM8994_AIF1ADC_LRCLK 0x304 107 #define WM8994_AIF1DAC_LRCLK 0x305 108 #define WM8994_AIF1DAC_DATA 0x306 109 #define WM8994_AIF1ADC_DATA 0x307 110 #define WM8994_AIF2_CONTROL_1 0x310 111 #define WM8994_AIF2_CONTROL_2 0x311 112 #define WM8994_AIF2_MASTER_SLAVE 0x312 113 #define WM8994_AIF2_BCLK 0x313 114 #define WM8994_AIF2ADC_LRCLK 0x314 115 #define WM8994_AIF2DAC_LRCLK 0x315 116 #define WM8994_AIF2DAC_DATA 0x316 117 #define WM8994_AIF2ADC_DATA 0x317 118 #define WM8958_AIF3_CONTROL_1 0x320 119 #define WM8958_AIF3_CONTROL_2 0x321 120 #define WM8958_AIF3DAC_DATA 0x322 121 #define WM8958_AIF3ADC_DATA 0x323 122 #define WM8994_AIF1_ADC1_LEFT_VOLUME 0x400 123 #define WM8994_AIF1_ADC1_RIGHT_VOLUME 0x401 124 #define WM8994_AIF1_DAC1_LEFT_VOLUME 0x402 125 #define WM8994_AIF1_DAC1_RIGHT_VOLUME 0x403 126 #define WM8994_AIF1_ADC2_LEFT_VOLUME 0x404 127 #define WM8994_AIF1_ADC2_RIGHT_VOLUME 0x405 128 #define WM8994_AIF1_DAC2_LEFT_VOLUME 0x406 129 #define WM8994_AIF1_DAC2_RIGHT_VOLUME 0x407 130 #define WM8994_AIF1_ADC1_FILTERS 0x410 131 #define WM8994_AIF1_ADC2_FILTERS 0x411 132 #define WM8994_AIF1_DAC1_FILTERS_1 0x420 133 #define WM8994_AIF1_DAC1_FILTERS_2 0x421 134 #define WM8994_AIF1_DAC2_FILTERS_1 0x422 135 #define WM8994_AIF1_DAC2_FILTERS_2 0x423 136 #define WM8994_AIF1_DRC1_1 0x440 137 #define WM8994_AIF1_DRC1_2 0x441 138 #define WM8994_AIF1_DRC1_3 0x442 139 #define WM8994_AIF1_DRC1_4 0x443 140 #define WM8994_AIF1_DRC1_5 0x444 141 #define WM8994_AIF1_DRC2_1 0x450 142 #define WM8994_AIF1_DRC2_2 0x451 143 #define WM8994_AIF1_DRC2_3 0x452 144 #define WM8994_AIF1_DRC2_4 0x453 145 #define WM8994_AIF1_DRC2_5 0x454 146 #define WM8994_AIF1_DAC1_EQ_GAINS_1 0x480 147 #define WM8994_AIF1_DAC1_EQ_GAINS_2 0x481 148 #define WM8994_AIF1_DAC1_EQ_BAND_1_A 0x482 149 #define WM8994_AIF1_DAC1_EQ_BAND_1_B 0x483 150 #define WM8994_AIF1_DAC1_EQ_BAND_1_PG 0x484 151 #define WM8994_AIF1_DAC1_EQ_BAND_2_A 0x485 152 #define WM8994_AIF1_DAC1_EQ_BAND_2_B 0x486 153 #define WM8994_AIF1_DAC1_EQ_BAND_2_C 0x487 154 #define WM8994_AIF1_DAC1_EQ_BAND_2_PG 0x488 155 #define WM8994_AIF1_DAC1_EQ_BAND_3_A 0x489 156 #define WM8994_AIF1_DAC1_EQ_BAND_3_B 0x48A 157 #define WM8994_AIF1_DAC1_EQ_BAND_3_C 0x48B 158 #define WM8994_AIF1_DAC1_EQ_BAND_3_PG 0x48C 159 #define WM8994_AIF1_DAC1_EQ_BAND_4_A 0x48D 160 #define WM8994_AIF1_DAC1_EQ_BAND_4_B 0x48E 161 #define WM8994_AIF1_DAC1_EQ_BAND_4_C 0x48F 162 #define WM8994_AIF1_DAC1_EQ_BAND_4_PG 0x490 163 #define WM8994_AIF1_DAC1_EQ_BAND_5_A 0x491 164 #define WM8994_AIF1_DAC1_EQ_BAND_5_B 0x492 165 #define WM8994_AIF1_DAC1_EQ_BAND_5_PG 0x493 166 #define WM8994_AIF1_DAC2_EQ_GAINS_1 0x4A0 167 #define WM8994_AIF1_DAC2_EQ_GAINS_2 0x4A1 168 #define WM8994_AIF1_DAC2_EQ_BAND_1_A 0x4A2 169 #define WM8994_AIF1_DAC2_EQ_BAND_1_B 0x4A3 170 #define WM8994_AIF1_DAC2_EQ_BAND_1_PG 0x4A4 171 #define WM8994_AIF1_DAC2_EQ_BAND_2_A 0x4A5 172 #define WM8994_AIF1_DAC2_EQ_BAND_2_B 0x4A6 173 #define WM8994_AIF1_DAC2_EQ_BAND_2_C 0x4A7 174 #define WM8994_AIF1_DAC2_EQ_BAND_2_PG 0x4A8 175 #define WM8994_AIF1_DAC2_EQ_BAND_3_A 0x4A9 176 #define WM8994_AIF1_DAC2_EQ_BAND_3_B 0x4AA 177 #define WM8994_AIF1_DAC2_EQ_BAND_3_C 0x4AB 178 #define WM8994_AIF1_DAC2_EQ_BAND_3_PG 0x4AC 179 #define WM8994_AIF1_DAC2_EQ_BAND_4_A 0x4AD 180 #define WM8994_AIF1_DAC2_EQ_BAND_4_B 0x4AE 181 #define WM8994_AIF1_DAC2_EQ_BAND_4_C 0x4AF 182 #define WM8994_AIF1_DAC2_EQ_BAND_4_PG 0x4B0 183 #define WM8994_AIF1_DAC2_EQ_BAND_5_A 0x4B1 184 #define WM8994_AIF1_DAC2_EQ_BAND_5_B 0x4B2 185 #define WM8994_AIF1_DAC2_EQ_BAND_5_PG 0x4B3 186 #define WM8994_AIF2_ADC_LEFT_VOLUME 0x500 187 #define WM8994_AIF2_ADC_RIGHT_VOLUME 0x501 188 #define WM8994_AIF2_DAC_LEFT_VOLUME 0x502 189 #define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503 190 #define WM8994_AIF2_ADC_FILTERS 0x510 191 #define WM8994_AIF2_DAC_FILTERS_1 0x520 192 #define WM8994_AIF2_DAC_FILTERS_2 0x521 193 #define WM8994_AIF2_DRC_1 0x540 194 #define WM8994_AIF2_DRC_2 0x541 195 #define WM8994_AIF2_DRC_3 0x542 196 #define WM8994_AIF2_DRC_4 0x543 197 #define WM8994_AIF2_DRC_5 0x544 198 #define WM8994_AIF2_EQ_GAINS_1 0x580 199 #define WM8994_AIF2_EQ_GAINS_2 0x581 200 #define WM8994_AIF2_EQ_BAND_1_A 0x582 201 #define WM8994_AIF2_EQ_BAND_1_B 0x583 202 #define WM8994_AIF2_EQ_BAND_1_PG 0x584 203 #define WM8994_AIF2_EQ_BAND_2_A 0x585 204 #define WM8994_AIF2_EQ_BAND_2_B 0x586 205 #define WM8994_AIF2_EQ_BAND_2_C 0x587 206 #define WM8994_AIF2_EQ_BAND_2_PG 0x588 207 #define WM8994_AIF2_EQ_BAND_3_A 0x589 208 #define WM8994_AIF2_EQ_BAND_3_B 0x58A 209 #define WM8994_AIF2_EQ_BAND_3_C 0x58B 210 #define WM8994_AIF2_EQ_BAND_3_PG 0x58C 211 #define WM8994_AIF2_EQ_BAND_4_A 0x58D 212 #define WM8994_AIF2_EQ_BAND_4_B 0x58E 213 #define WM8994_AIF2_EQ_BAND_4_C 0x58F 214 #define WM8994_AIF2_EQ_BAND_4_PG 0x590 215 #define WM8994_AIF2_EQ_BAND_5_A 0x591 216 #define WM8994_AIF2_EQ_BAND_5_B 0x592 217 #define WM8994_AIF2_EQ_BAND_5_PG 0x593 218 #define WM8994_DAC1_MIXER_VOLUMES 0x600 219 #define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601 220 #define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602 221 #define WM8994_DAC2_MIXER_VOLUMES 0x603 222 #define WM8994_DAC2_LEFT_MIXER_ROUTING 0x604 223 #define WM8994_DAC2_RIGHT_MIXER_ROUTING 0x605 224 #define WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING 0x606 225 #define WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING 0x607 226 #define WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING 0x608 227 #define WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING 0x609 228 #define WM8994_DAC1_LEFT_VOLUME 0x610 229 #define WM8994_DAC1_RIGHT_VOLUME 0x611 230 #define WM8994_DAC2_LEFT_VOLUME 0x612 231 #define WM8994_DAC2_RIGHT_VOLUME 0x613 232 #define WM8994_DAC_SOFTMUTE 0x614 233 #define WM8994_OVERSAMPLING 0x620 234 #define WM8994_SIDETONE 0x621 235 #define WM8994_GPIO_1 0x700 236 #define WM8994_GPIO_2 0x701 237 #define WM8994_GPIO_3 0x702 238 #define WM8994_GPIO_4 0x703 239 #define WM8994_GPIO_5 0x704 240 #define WM8994_GPIO_6 0x705 241 #define WM8994_GPIO_7 0x706 242 #define WM8994_GPIO_8 0x707 243 #define WM8994_GPIO_9 0x708 244 #define WM8994_GPIO_10 0x709 245 #define WM8994_GPIO_11 0x70A 246 #define WM8994_PULL_CONTROL_1 0x720 247 #define WM8994_PULL_CONTROL_2 0x721 248 #define WM8994_INTERRUPT_STATUS_1 0x730 249 #define WM8994_INTERRUPT_STATUS_2 0x731 250 #define WM8994_INTERRUPT_RAW_STATUS_2 0x732 251 #define WM8994_INTERRUPT_STATUS_1_MASK 0x738 252 #define WM8994_INTERRUPT_STATUS_2_MASK 0x739 253 #define WM8994_INTERRUPT_CONTROL 0x740 254 #define WM8994_IRQ_DEBOUNCE 0x748 255 #define WM8958_DSP2_PROGRAM 0x900 256 #define WM8958_DSP2_CONFIG 0x901 257 #define WM8958_DSP2_MAGICNUM 0xA00 258 #define WM8958_DSP2_RELEASEYEAR 0xA01 259 #define WM8958_DSP2_RELEASEMONTHDAY 0xA02 260 #define WM8958_DSP2_RELEASETIME 0xA03 261 #define WM8958_DSP2_VERMAJMIN 0xA04 262 #define WM8958_DSP2_VERBUILD 0xA05 263 #define WM8958_DSP2_EXECCONTROL 0xA0D 264 #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1 0x2200 265 #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_2 0x2201 266 #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_1 0x2202 267 #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_2 0x2203 268 #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C3_1 0x2204 269 #define WM8958_MBC_BAND_2_LOWER_CUTOFF_C3_2 0x2205 270 #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C2_1 0x2206 271 #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C2_2 0x2207 272 #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C3_1 0x2208 273 #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C3_2 0x2209 274 #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C1_1 0x220A 275 #define WM8958_MBC_BAND_2_UPPER_CUTOFF_C1_2 0x220B 276 #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C1_1 0x220C 277 #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C1_2 0x220D 278 #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C2_1 0x220E 279 #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C2_2 0x220F 280 #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C3_1 0x2210 281 #define WM8958_MBC_BAND_1_UPPER_CUTOFF_C3_2 0x2211 282 #define WM8958_MBC_BAND_1_LOWER_CUTOFF_1 0x2212 283 #define WM8958_MBC_BAND_1_LOWER_CUTOFF_2 0x2213 284 #define WM8958_MBC_BAND_1_K_1 0x2400 285 #define WM8958_MBC_BAND_1_K_2 0x2401 286 #define WM8958_MBC_BAND_1_N1_1 0x2402 287 #define WM8958_MBC_BAND_1_N1_2 0x2403 288 #define WM8958_MBC_BAND_1_N2_1 0x2404 289 #define WM8958_MBC_BAND_1_N2_2 0x2405 290 #define WM8958_MBC_BAND_1_N3_1 0x2406 291 #define WM8958_MBC_BAND_1_N3_2 0x2407 292 #define WM8958_MBC_BAND_1_N4_1 0x2408 293 #define WM8958_MBC_BAND_1_N4_2 0x2409 294 #define WM8958_MBC_BAND_1_N5_1 0x240A 295 #define WM8958_MBC_BAND_1_N5_2 0x240B 296 #define WM8958_MBC_BAND_1_X1_1 0x240C 297 #define WM8958_MBC_BAND_1_X1_2 0x240D 298 #define WM8958_MBC_BAND_1_X2_1 0x240E 299 #define WM8958_MBC_BAND_1_X2_2 0x240F 300 #define WM8958_MBC_BAND_1_X3_1 0x2410 301 #define WM8958_MBC_BAND_1_X3_2 0x2411 302 #define WM8958_MBC_BAND_1_ATTACK_1 0x2412 303 #define WM8958_MBC_BAND_1_ATTACK_2 0x2413 304 #define WM8958_MBC_BAND_1_DECAY_1 0x2414 305 #define WM8958_MBC_BAND_1_DECAY_2 0x2415 306 #define WM8958_MBC_BAND_2_K_1 0x2416 307 #define WM8958_MBC_BAND_2_K_2 0x2417 308 #define WM8958_MBC_BAND_2_N1_1 0x2418 309 #define WM8958_MBC_BAND_2_N1_2 0x2419 310 #define WM8958_MBC_BAND_2_N2_1 0x241A 311 #define WM8958_MBC_BAND_2_N2_2 0x241B 312 #define WM8958_MBC_BAND_2_N3_1 0x241C 313 #define WM8958_MBC_BAND_2_N3_2 0x241D 314 #define WM8958_MBC_BAND_2_N4_1 0x241E 315 #define WM8958_MBC_BAND_2_N4_2 0x241F 316 #define WM8958_MBC_BAND_2_N5_1 0x2420 317 #define WM8958_MBC_BAND_2_N5_2 0x2421 318 #define WM8958_MBC_BAND_2_X1_1 0x2422 319 #define WM8958_MBC_BAND_2_X1_2 0x2423 320 #define WM8958_MBC_BAND_2_X2_1 0x2424 321 #define WM8958_MBC_BAND_2_X2_2 0x2425 322 #define WM8958_MBC_BAND_2_X3_1 0x2426 323 #define WM8958_MBC_BAND_2_X3_2 0x2427 324 #define WM8958_MBC_BAND_2_ATTACK_1 0x2428 325 #define WM8958_MBC_BAND_2_ATTACK_2 0x2429 326 #define WM8958_MBC_BAND_2_DECAY_1 0x242A 327 #define WM8958_MBC_BAND_2_DECAY_2 0x242B 328 #define WM8958_MBC_B2_PG2_1 0x242C 329 #define WM8958_MBC_B2_PG2_2 0x242D 330 #define WM8958_MBC_B1_PG2_1 0x242E 331 #define WM8958_MBC_B1_PG2_2 0x242F 332 #define WM8994_WRITE_SEQUENCER_0 0x3000 333 #define WM8994_WRITE_SEQUENCER_1 0x3001 334 #define WM8994_WRITE_SEQUENCER_2 0x3002 335 #define WM8994_WRITE_SEQUENCER_3 0x3003 336 #define WM8994_WRITE_SEQUENCER_4 0x3004 337 #define WM8994_WRITE_SEQUENCER_5 0x3005 338 #define WM8994_WRITE_SEQUENCER_6 0x3006 339 #define WM8994_WRITE_SEQUENCER_7 0x3007 340 #define WM8994_WRITE_SEQUENCER_8 0x3008 341 #define WM8994_WRITE_SEQUENCER_9 0x3009 342 #define WM8994_WRITE_SEQUENCER_10 0x300A 343 #define WM8994_WRITE_SEQUENCER_11 0x300B 344 #define WM8994_WRITE_SEQUENCER_12 0x300C 345 #define WM8994_WRITE_SEQUENCER_13 0x300D 346 #define WM8994_WRITE_SEQUENCER_14 0x300E 347 #define WM8994_WRITE_SEQUENCER_15 0x300F 348 #define WM8994_WRITE_SEQUENCER_16 0x3010 349 #define WM8994_WRITE_SEQUENCER_17 0x3011 350 #define WM8994_WRITE_SEQUENCER_18 0x3012 351 #define WM8994_WRITE_SEQUENCER_19 0x3013 352 #define WM8994_WRITE_SEQUENCER_20 0x3014 353 #define WM8994_WRITE_SEQUENCER_21 0x3015 354 #define WM8994_WRITE_SEQUENCER_22 0x3016 355 #define WM8994_WRITE_SEQUENCER_23 0x3017 356 #define WM8994_WRITE_SEQUENCER_24 0x3018 357 #define WM8994_WRITE_SEQUENCER_25 0x3019 358 #define WM8994_WRITE_SEQUENCER_26 0x301A 359 #define WM8994_WRITE_SEQUENCER_27 0x301B 360 #define WM8994_WRITE_SEQUENCER_28 0x301C 361 #define WM8994_WRITE_SEQUENCER_29 0x301D 362 #define WM8994_WRITE_SEQUENCER_30 0x301E 363 #define WM8994_WRITE_SEQUENCER_31 0x301F 364 #define WM8994_WRITE_SEQUENCER_32 0x3020 365 #define WM8994_WRITE_SEQUENCER_33 0x3021 366 #define WM8994_WRITE_SEQUENCER_34 0x3022 367 #define WM8994_WRITE_SEQUENCER_35 0x3023 368 #define WM8994_WRITE_SEQUENCER_36 0x3024 369 #define WM8994_WRITE_SEQUENCER_37 0x3025 370 #define WM8994_WRITE_SEQUENCER_38 0x3026 371 #define WM8994_WRITE_SEQUENCER_39 0x3027 372 #define WM8994_WRITE_SEQUENCER_40 0x3028 373 #define WM8994_WRITE_SEQUENCER_41 0x3029 374 #define WM8994_WRITE_SEQUENCER_42 0x302A 375 #define WM8994_WRITE_SEQUENCER_43 0x302B 376 #define WM8994_WRITE_SEQUENCER_44 0x302C 377 #define WM8994_WRITE_SEQUENCER_45 0x302D 378 #define WM8994_WRITE_SEQUENCER_46 0x302E 379 #define WM8994_WRITE_SEQUENCER_47 0x302F 380 #define WM8994_WRITE_SEQUENCER_48 0x3030 381 #define WM8994_WRITE_SEQUENCER_49 0x3031 382 #define WM8994_WRITE_SEQUENCER_50 0x3032 383 #define WM8994_WRITE_SEQUENCER_51 0x3033 384 #define WM8994_WRITE_SEQUENCER_52 0x3034 385 #define WM8994_WRITE_SEQUENCER_53 0x3035 386 #define WM8994_WRITE_SEQUENCER_54 0x3036 387 #define WM8994_WRITE_SEQUENCER_55 0x3037 388 #define WM8994_WRITE_SEQUENCER_56 0x3038 389 #define WM8994_WRITE_SEQUENCER_57 0x3039 390 #define WM8994_WRITE_SEQUENCER_58 0x303A 391 #define WM8994_WRITE_SEQUENCER_59 0x303B 392 #define WM8994_WRITE_SEQUENCER_60 0x303C 393 #define WM8994_WRITE_SEQUENCER_61 0x303D 394 #define WM8994_WRITE_SEQUENCER_62 0x303E 395 #define WM8994_WRITE_SEQUENCER_63 0x303F 396 #define WM8994_WRITE_SEQUENCER_64 0x3040 397 #define WM8994_WRITE_SEQUENCER_65 0x3041 398 #define WM8994_WRITE_SEQUENCER_66 0x3042 399 #define WM8994_WRITE_SEQUENCER_67 0x3043 400 #define WM8994_WRITE_SEQUENCER_68 0x3044 401 #define WM8994_WRITE_SEQUENCER_69 0x3045 402 #define WM8994_WRITE_SEQUENCER_70 0x3046 403 #define WM8994_WRITE_SEQUENCER_71 0x3047 404 #define WM8994_WRITE_SEQUENCER_72 0x3048 405 #define WM8994_WRITE_SEQUENCER_73 0x3049 406 #define WM8994_WRITE_SEQUENCER_74 0x304A 407 #define WM8994_WRITE_SEQUENCER_75 0x304B 408 #define WM8994_WRITE_SEQUENCER_76 0x304C 409 #define WM8994_WRITE_SEQUENCER_77 0x304D 410 #define WM8994_WRITE_SEQUENCER_78 0x304E 411 #define WM8994_WRITE_SEQUENCER_79 0x304F 412 #define WM8994_WRITE_SEQUENCER_80 0x3050 413 #define WM8994_WRITE_SEQUENCER_81 0x3051 414 #define WM8994_WRITE_SEQUENCER_82 0x3052 415 #define WM8994_WRITE_SEQUENCER_83 0x3053 416 #define WM8994_WRITE_SEQUENCER_84 0x3054 417 #define WM8994_WRITE_SEQUENCER_85 0x3055 418 #define WM8994_WRITE_SEQUENCER_86 0x3056 419 #define WM8994_WRITE_SEQUENCER_87 0x3057 420 #define WM8994_WRITE_SEQUENCER_88 0x3058 421 #define WM8994_WRITE_SEQUENCER_89 0x3059 422 #define WM8994_WRITE_SEQUENCER_90 0x305A 423 #define WM8994_WRITE_SEQUENCER_91 0x305B 424 #define WM8994_WRITE_SEQUENCER_92 0x305C 425 #define WM8994_WRITE_SEQUENCER_93 0x305D 426 #define WM8994_WRITE_SEQUENCER_94 0x305E 427 #define WM8994_WRITE_SEQUENCER_95 0x305F 428 #define WM8994_WRITE_SEQUENCER_96 0x3060 429 #define WM8994_WRITE_SEQUENCER_97 0x3061 430 #define WM8994_WRITE_SEQUENCER_98 0x3062 431 #define WM8994_WRITE_SEQUENCER_99 0x3063 432 #define WM8994_WRITE_SEQUENCER_100 0x3064 433 #define WM8994_WRITE_SEQUENCER_101 0x3065 434 #define WM8994_WRITE_SEQUENCER_102 0x3066 435 #define WM8994_WRITE_SEQUENCER_103 0x3067 436 #define WM8994_WRITE_SEQUENCER_104 0x3068 437 #define WM8994_WRITE_SEQUENCER_105 0x3069 438 #define WM8994_WRITE_SEQUENCER_106 0x306A 439 #define WM8994_WRITE_SEQUENCER_107 0x306B 440 #define WM8994_WRITE_SEQUENCER_108 0x306C 441 #define WM8994_WRITE_SEQUENCER_109 0x306D 442 #define WM8994_WRITE_SEQUENCER_110 0x306E 443 #define WM8994_WRITE_SEQUENCER_111 0x306F 444 #define WM8994_WRITE_SEQUENCER_112 0x3070 445 #define WM8994_WRITE_SEQUENCER_113 0x3071 446 #define WM8994_WRITE_SEQUENCER_114 0x3072 447 #define WM8994_WRITE_SEQUENCER_115 0x3073 448 #define WM8994_WRITE_SEQUENCER_116 0x3074 449 #define WM8994_WRITE_SEQUENCER_117 0x3075 450 #define WM8994_WRITE_SEQUENCER_118 0x3076 451 #define WM8994_WRITE_SEQUENCER_119 0x3077 452 #define WM8994_WRITE_SEQUENCER_120 0x3078 453 #define WM8994_WRITE_SEQUENCER_121 0x3079 454 #define WM8994_WRITE_SEQUENCER_122 0x307A 455 #define WM8994_WRITE_SEQUENCER_123 0x307B 456 #define WM8994_WRITE_SEQUENCER_124 0x307C 457 #define WM8994_WRITE_SEQUENCER_125 0x307D 458 #define WM8994_WRITE_SEQUENCER_126 0x307E 459 #define WM8994_WRITE_SEQUENCER_127 0x307F 460 #define WM8994_WRITE_SEQUENCER_128 0x3080 461 #define WM8994_WRITE_SEQUENCER_129 0x3081 462 #define WM8994_WRITE_SEQUENCER_130 0x3082 463 #define WM8994_WRITE_SEQUENCER_131 0x3083 464 #define WM8994_WRITE_SEQUENCER_132 0x3084 465 #define WM8994_WRITE_SEQUENCER_133 0x3085 466 #define WM8994_WRITE_SEQUENCER_134 0x3086 467 #define WM8994_WRITE_SEQUENCER_135 0x3087 468 #define WM8994_WRITE_SEQUENCER_136 0x3088 469 #define WM8994_WRITE_SEQUENCER_137 0x3089 470 #define WM8994_WRITE_SEQUENCER_138 0x308A 471 #define WM8994_WRITE_SEQUENCER_139 0x308B 472 #define WM8994_WRITE_SEQUENCER_140 0x308C 473 #define WM8994_WRITE_SEQUENCER_141 0x308D 474 #define WM8994_WRITE_SEQUENCER_142 0x308E 475 #define WM8994_WRITE_SEQUENCER_143 0x308F 476 #define WM8994_WRITE_SEQUENCER_144 0x3090 477 #define WM8994_WRITE_SEQUENCER_145 0x3091 478 #define WM8994_WRITE_SEQUENCER_146 0x3092 479 #define WM8994_WRITE_SEQUENCER_147 0x3093 480 #define WM8994_WRITE_SEQUENCER_148 0x3094 481 #define WM8994_WRITE_SEQUENCER_149 0x3095 482 #define WM8994_WRITE_SEQUENCER_150 0x3096 483 #define WM8994_WRITE_SEQUENCER_151 0x3097 484 #define WM8994_WRITE_SEQUENCER_152 0x3098 485 #define WM8994_WRITE_SEQUENCER_153 0x3099 486 #define WM8994_WRITE_SEQUENCER_154 0x309A 487 #define WM8994_WRITE_SEQUENCER_155 0x309B 488 #define WM8994_WRITE_SEQUENCER_156 0x309C 489 #define WM8994_WRITE_SEQUENCER_157 0x309D 490 #define WM8994_WRITE_SEQUENCER_158 0x309E 491 #define WM8994_WRITE_SEQUENCER_159 0x309F 492 #define WM8994_WRITE_SEQUENCER_160 0x30A0 493 #define WM8994_WRITE_SEQUENCER_161 0x30A1 494 #define WM8994_WRITE_SEQUENCER_162 0x30A2 495 #define WM8994_WRITE_SEQUENCER_163 0x30A3 496 #define WM8994_WRITE_SEQUENCER_164 0x30A4 497 #define WM8994_WRITE_SEQUENCER_165 0x30A5 498 #define WM8994_WRITE_SEQUENCER_166 0x30A6 499 #define WM8994_WRITE_SEQUENCER_167 0x30A7 500 #define WM8994_WRITE_SEQUENCER_168 0x30A8 501 #define WM8994_WRITE_SEQUENCER_169 0x30A9 502 #define WM8994_WRITE_SEQUENCER_170 0x30AA 503 #define WM8994_WRITE_SEQUENCER_171 0x30AB 504 #define WM8994_WRITE_SEQUENCER_172 0x30AC 505 #define WM8994_WRITE_SEQUENCER_173 0x30AD 506 #define WM8994_WRITE_SEQUENCER_174 0x30AE 507 #define WM8994_WRITE_SEQUENCER_175 0x30AF 508 #define WM8994_WRITE_SEQUENCER_176 0x30B0 509 #define WM8994_WRITE_SEQUENCER_177 0x30B1 510 #define WM8994_WRITE_SEQUENCER_178 0x30B2 511 #define WM8994_WRITE_SEQUENCER_179 0x30B3 512 #define WM8994_WRITE_SEQUENCER_180 0x30B4 513 #define WM8994_WRITE_SEQUENCER_181 0x30B5 514 #define WM8994_WRITE_SEQUENCER_182 0x30B6 515 #define WM8994_WRITE_SEQUENCER_183 0x30B7 516 #define WM8994_WRITE_SEQUENCER_184 0x30B8 517 #define WM8994_WRITE_SEQUENCER_185 0x30B9 518 #define WM8994_WRITE_SEQUENCER_186 0x30BA 519 #define WM8994_WRITE_SEQUENCER_187 0x30BB 520 #define WM8994_WRITE_SEQUENCER_188 0x30BC 521 #define WM8994_WRITE_SEQUENCER_189 0x30BD 522 #define WM8994_WRITE_SEQUENCER_190 0x30BE 523 #define WM8994_WRITE_SEQUENCER_191 0x30BF 524 #define WM8994_WRITE_SEQUENCER_192 0x30C0 525 #define WM8994_WRITE_SEQUENCER_193 0x30C1 526 #define WM8994_WRITE_SEQUENCER_194 0x30C2 527 #define WM8994_WRITE_SEQUENCER_195 0x30C3 528 #define WM8994_WRITE_SEQUENCER_196 0x30C4 529 #define WM8994_WRITE_SEQUENCER_197 0x30C5 530 #define WM8994_WRITE_SEQUENCER_198 0x30C6 531 #define WM8994_WRITE_SEQUENCER_199 0x30C7 532 #define WM8994_WRITE_SEQUENCER_200 0x30C8 533 #define WM8994_WRITE_SEQUENCER_201 0x30C9 534 #define WM8994_WRITE_SEQUENCER_202 0x30CA 535 #define WM8994_WRITE_SEQUENCER_203 0x30CB 536 #define WM8994_WRITE_SEQUENCER_204 0x30CC 537 #define WM8994_WRITE_SEQUENCER_205 0x30CD 538 #define WM8994_WRITE_SEQUENCER_206 0x30CE 539 #define WM8994_WRITE_SEQUENCER_207 0x30CF 540 #define WM8994_WRITE_SEQUENCER_208 0x30D0 541 #define WM8994_WRITE_SEQUENCER_209 0x30D1 542 #define WM8994_WRITE_SEQUENCER_210 0x30D2 543 #define WM8994_WRITE_SEQUENCER_211 0x30D3 544 #define WM8994_WRITE_SEQUENCER_212 0x30D4 545 #define WM8994_WRITE_SEQUENCER_213 0x30D5 546 #define WM8994_WRITE_SEQUENCER_214 0x30D6 547 #define WM8994_WRITE_SEQUENCER_215 0x30D7 548 #define WM8994_WRITE_SEQUENCER_216 0x30D8 549 #define WM8994_WRITE_SEQUENCER_217 0x30D9 550 #define WM8994_WRITE_SEQUENCER_218 0x30DA 551 #define WM8994_WRITE_SEQUENCER_219 0x30DB 552 #define WM8994_WRITE_SEQUENCER_220 0x30DC 553 #define WM8994_WRITE_SEQUENCER_221 0x30DD 554 #define WM8994_WRITE_SEQUENCER_222 0x30DE 555 #define WM8994_WRITE_SEQUENCER_223 0x30DF 556 #define WM8994_WRITE_SEQUENCER_224 0x30E0 557 #define WM8994_WRITE_SEQUENCER_225 0x30E1 558 #define WM8994_WRITE_SEQUENCER_226 0x30E2 559 #define WM8994_WRITE_SEQUENCER_227 0x30E3 560 #define WM8994_WRITE_SEQUENCER_228 0x30E4 561 #define WM8994_WRITE_SEQUENCER_229 0x30E5 562 #define WM8994_WRITE_SEQUENCER_230 0x30E6 563 #define WM8994_WRITE_SEQUENCER_231 0x30E7 564 #define WM8994_WRITE_SEQUENCER_232 0x30E8 565 #define WM8994_WRITE_SEQUENCER_233 0x30E9 566 #define WM8994_WRITE_SEQUENCER_234 0x30EA 567 #define WM8994_WRITE_SEQUENCER_235 0x30EB 568 #define WM8994_WRITE_SEQUENCER_236 0x30EC 569 #define WM8994_WRITE_SEQUENCER_237 0x30ED 570 #define WM8994_WRITE_SEQUENCER_238 0x30EE 571 #define WM8994_WRITE_SEQUENCER_239 0x30EF 572 #define WM8994_WRITE_SEQUENCER_240 0x30F0 573 #define WM8994_WRITE_SEQUENCER_241 0x30F1 574 #define WM8994_WRITE_SEQUENCER_242 0x30F2 575 #define WM8994_WRITE_SEQUENCER_243 0x30F3 576 #define WM8994_WRITE_SEQUENCER_244 0x30F4 577 #define WM8994_WRITE_SEQUENCER_245 0x30F5 578 #define WM8994_WRITE_SEQUENCER_246 0x30F6 579 #define WM8994_WRITE_SEQUENCER_247 0x30F7 580 #define WM8994_WRITE_SEQUENCER_248 0x30F8 581 #define WM8994_WRITE_SEQUENCER_249 0x30F9 582 #define WM8994_WRITE_SEQUENCER_250 0x30FA 583 #define WM8994_WRITE_SEQUENCER_251 0x30FB 584 #define WM8994_WRITE_SEQUENCER_252 0x30FC 585 #define WM8994_WRITE_SEQUENCER_253 0x30FD 586 #define WM8994_WRITE_SEQUENCER_254 0x30FE 587 #define WM8994_WRITE_SEQUENCER_255 0x30FF 588 #define WM8994_WRITE_SEQUENCER_256 0x3100 589 #define WM8994_WRITE_SEQUENCER_257 0x3101 590 #define WM8994_WRITE_SEQUENCER_258 0x3102 591 #define WM8994_WRITE_SEQUENCER_259 0x3103 592 #define WM8994_WRITE_SEQUENCER_260 0x3104 593 #define WM8994_WRITE_SEQUENCER_261 0x3105 594 #define WM8994_WRITE_SEQUENCER_262 0x3106 595 #define WM8994_WRITE_SEQUENCER_263 0x3107 596 #define WM8994_WRITE_SEQUENCER_264 0x3108 597 #define WM8994_WRITE_SEQUENCER_265 0x3109 598 #define WM8994_WRITE_SEQUENCER_266 0x310A 599 #define WM8994_WRITE_SEQUENCER_267 0x310B 600 #define WM8994_WRITE_SEQUENCER_268 0x310C 601 #define WM8994_WRITE_SEQUENCER_269 0x310D 602 #define WM8994_WRITE_SEQUENCER_270 0x310E 603 #define WM8994_WRITE_SEQUENCER_271 0x310F 604 #define WM8994_WRITE_SEQUENCER_272 0x3110 605 #define WM8994_WRITE_SEQUENCER_273 0x3111 606 #define WM8994_WRITE_SEQUENCER_274 0x3112 607 #define WM8994_WRITE_SEQUENCER_275 0x3113 608 #define WM8994_WRITE_SEQUENCER_276 0x3114 609 #define WM8994_WRITE_SEQUENCER_277 0x3115 610 #define WM8994_WRITE_SEQUENCER_278 0x3116 611 #define WM8994_WRITE_SEQUENCER_279 0x3117 612 #define WM8994_WRITE_SEQUENCER_280 0x3118 613 #define WM8994_WRITE_SEQUENCER_281 0x3119 614 #define WM8994_WRITE_SEQUENCER_282 0x311A 615 #define WM8994_WRITE_SEQUENCER_283 0x311B 616 #define WM8994_WRITE_SEQUENCER_284 0x311C 617 #define WM8994_WRITE_SEQUENCER_285 0x311D 618 #define WM8994_WRITE_SEQUENCER_286 0x311E 619 #define WM8994_WRITE_SEQUENCER_287 0x311F 620 #define WM8994_WRITE_SEQUENCER_288 0x3120 621 #define WM8994_WRITE_SEQUENCER_289 0x3121 622 #define WM8994_WRITE_SEQUENCER_290 0x3122 623 #define WM8994_WRITE_SEQUENCER_291 0x3123 624 #define WM8994_WRITE_SEQUENCER_292 0x3124 625 #define WM8994_WRITE_SEQUENCER_293 0x3125 626 #define WM8994_WRITE_SEQUENCER_294 0x3126 627 #define WM8994_WRITE_SEQUENCER_295 0x3127 628 #define WM8994_WRITE_SEQUENCER_296 0x3128 629 #define WM8994_WRITE_SEQUENCER_297 0x3129 630 #define WM8994_WRITE_SEQUENCER_298 0x312A 631 #define WM8994_WRITE_SEQUENCER_299 0x312B 632 #define WM8994_WRITE_SEQUENCER_300 0x312C 633 #define WM8994_WRITE_SEQUENCER_301 0x312D 634 #define WM8994_WRITE_SEQUENCER_302 0x312E 635 #define WM8994_WRITE_SEQUENCER_303 0x312F 636 #define WM8994_WRITE_SEQUENCER_304 0x3130 637 #define WM8994_WRITE_SEQUENCER_305 0x3131 638 #define WM8994_WRITE_SEQUENCER_306 0x3132 639 #define WM8994_WRITE_SEQUENCER_307 0x3133 640 #define WM8994_WRITE_SEQUENCER_308 0x3134 641 #define WM8994_WRITE_SEQUENCER_309 0x3135 642 #define WM8994_WRITE_SEQUENCER_310 0x3136 643 #define WM8994_WRITE_SEQUENCER_311 0x3137 644 #define WM8994_WRITE_SEQUENCER_312 0x3138 645 #define WM8994_WRITE_SEQUENCER_313 0x3139 646 #define WM8994_WRITE_SEQUENCER_314 0x313A 647 #define WM8994_WRITE_SEQUENCER_315 0x313B 648 #define WM8994_WRITE_SEQUENCER_316 0x313C 649 #define WM8994_WRITE_SEQUENCER_317 0x313D 650 #define WM8994_WRITE_SEQUENCER_318 0x313E 651 #define WM8994_WRITE_SEQUENCER_319 0x313F 652 #define WM8994_WRITE_SEQUENCER_320 0x3140 653 #define WM8994_WRITE_SEQUENCER_321 0x3141 654 #define WM8994_WRITE_SEQUENCER_322 0x3142 655 #define WM8994_WRITE_SEQUENCER_323 0x3143 656 #define WM8994_WRITE_SEQUENCER_324 0x3144 657 #define WM8994_WRITE_SEQUENCER_325 0x3145 658 #define WM8994_WRITE_SEQUENCER_326 0x3146 659 #define WM8994_WRITE_SEQUENCER_327 0x3147 660 #define WM8994_WRITE_SEQUENCER_328 0x3148 661 #define WM8994_WRITE_SEQUENCER_329 0x3149 662 #define WM8994_WRITE_SEQUENCER_330 0x314A 663 #define WM8994_WRITE_SEQUENCER_331 0x314B 664 #define WM8994_WRITE_SEQUENCER_332 0x314C 665 #define WM8994_WRITE_SEQUENCER_333 0x314D 666 #define WM8994_WRITE_SEQUENCER_334 0x314E 667 #define WM8994_WRITE_SEQUENCER_335 0x314F 668 #define WM8994_WRITE_SEQUENCER_336 0x3150 669 #define WM8994_WRITE_SEQUENCER_337 0x3151 670 #define WM8994_WRITE_SEQUENCER_338 0x3152 671 #define WM8994_WRITE_SEQUENCER_339 0x3153 672 #define WM8994_WRITE_SEQUENCER_340 0x3154 673 #define WM8994_WRITE_SEQUENCER_341 0x3155 674 #define WM8994_WRITE_SEQUENCER_342 0x3156 675 #define WM8994_WRITE_SEQUENCER_343 0x3157 676 #define WM8994_WRITE_SEQUENCER_344 0x3158 677 #define WM8994_WRITE_SEQUENCER_345 0x3159 678 #define WM8994_WRITE_SEQUENCER_346 0x315A 679 #define WM8994_WRITE_SEQUENCER_347 0x315B 680 #define WM8994_WRITE_SEQUENCER_348 0x315C 681 #define WM8994_WRITE_SEQUENCER_349 0x315D 682 #define WM8994_WRITE_SEQUENCER_350 0x315E 683 #define WM8994_WRITE_SEQUENCER_351 0x315F 684 #define WM8994_WRITE_SEQUENCER_352 0x3160 685 #define WM8994_WRITE_SEQUENCER_353 0x3161 686 #define WM8994_WRITE_SEQUENCER_354 0x3162 687 #define WM8994_WRITE_SEQUENCER_355 0x3163 688 #define WM8994_WRITE_SEQUENCER_356 0x3164 689 #define WM8994_WRITE_SEQUENCER_357 0x3165 690 #define WM8994_WRITE_SEQUENCER_358 0x3166 691 #define WM8994_WRITE_SEQUENCER_359 0x3167 692 #define WM8994_WRITE_SEQUENCER_360 0x3168 693 #define WM8994_WRITE_SEQUENCER_361 0x3169 694 #define WM8994_WRITE_SEQUENCER_362 0x316A 695 #define WM8994_WRITE_SEQUENCER_363 0x316B 696 #define WM8994_WRITE_SEQUENCER_364 0x316C 697 #define WM8994_WRITE_SEQUENCER_365 0x316D 698 #define WM8994_WRITE_SEQUENCER_366 0x316E 699 #define WM8994_WRITE_SEQUENCER_367 0x316F 700 #define WM8994_WRITE_SEQUENCER_368 0x3170 701 #define WM8994_WRITE_SEQUENCER_369 0x3171 702 #define WM8994_WRITE_SEQUENCER_370 0x3172 703 #define WM8994_WRITE_SEQUENCER_371 0x3173 704 #define WM8994_WRITE_SEQUENCER_372 0x3174 705 #define WM8994_WRITE_SEQUENCER_373 0x3175 706 #define WM8994_WRITE_SEQUENCER_374 0x3176 707 #define WM8994_WRITE_SEQUENCER_375 0x3177 708 #define WM8994_WRITE_SEQUENCER_376 0x3178 709 #define WM8994_WRITE_SEQUENCER_377 0x3179 710 #define WM8994_WRITE_SEQUENCER_378 0x317A 711 #define WM8994_WRITE_SEQUENCER_379 0x317B 712 #define WM8994_WRITE_SEQUENCER_380 0x317C 713 #define WM8994_WRITE_SEQUENCER_381 0x317D 714 #define WM8994_WRITE_SEQUENCER_382 0x317E 715 #define WM8994_WRITE_SEQUENCER_383 0x317F 716 #define WM8994_WRITE_SEQUENCER_384 0x3180 717 #define WM8994_WRITE_SEQUENCER_385 0x3181 718 #define WM8994_WRITE_SEQUENCER_386 0x3182 719 #define WM8994_WRITE_SEQUENCER_387 0x3183 720 #define WM8994_WRITE_SEQUENCER_388 0x3184 721 #define WM8994_WRITE_SEQUENCER_389 0x3185 722 #define WM8994_WRITE_SEQUENCER_390 0x3186 723 #define WM8994_WRITE_SEQUENCER_391 0x3187 724 #define WM8994_WRITE_SEQUENCER_392 0x3188 725 #define WM8994_WRITE_SEQUENCER_393 0x3189 726 #define WM8994_WRITE_SEQUENCER_394 0x318A 727 #define WM8994_WRITE_SEQUENCER_395 0x318B 728 #define WM8994_WRITE_SEQUENCER_396 0x318C 729 #define WM8994_WRITE_SEQUENCER_397 0x318D 730 #define WM8994_WRITE_SEQUENCER_398 0x318E 731 #define WM8994_WRITE_SEQUENCER_399 0x318F 732 #define WM8994_WRITE_SEQUENCER_400 0x3190 733 #define WM8994_WRITE_SEQUENCER_401 0x3191 734 #define WM8994_WRITE_SEQUENCER_402 0x3192 735 #define WM8994_WRITE_SEQUENCER_403 0x3193 736 #define WM8994_WRITE_SEQUENCER_404 0x3194 737 #define WM8994_WRITE_SEQUENCER_405 0x3195 738 #define WM8994_WRITE_SEQUENCER_406 0x3196 739 #define WM8994_WRITE_SEQUENCER_407 0x3197 740 #define WM8994_WRITE_SEQUENCER_408 0x3198 741 #define WM8994_WRITE_SEQUENCER_409 0x3199 742 #define WM8994_WRITE_SEQUENCER_410 0x319A 743 #define WM8994_WRITE_SEQUENCER_411 0x319B 744 #define WM8994_WRITE_SEQUENCER_412 0x319C 745 #define WM8994_WRITE_SEQUENCER_413 0x319D 746 #define WM8994_WRITE_SEQUENCER_414 0x319E 747 #define WM8994_WRITE_SEQUENCER_415 0x319F 748 #define WM8994_WRITE_SEQUENCER_416 0x31A0 749 #define WM8994_WRITE_SEQUENCER_417 0x31A1 750 #define WM8994_WRITE_SEQUENCER_418 0x31A2 751 #define WM8994_WRITE_SEQUENCER_419 0x31A3 752 #define WM8994_WRITE_SEQUENCER_420 0x31A4 753 #define WM8994_WRITE_SEQUENCER_421 0x31A5 754 #define WM8994_WRITE_SEQUENCER_422 0x31A6 755 #define WM8994_WRITE_SEQUENCER_423 0x31A7 756 #define WM8994_WRITE_SEQUENCER_424 0x31A8 757 #define WM8994_WRITE_SEQUENCER_425 0x31A9 758 #define WM8994_WRITE_SEQUENCER_426 0x31AA 759 #define WM8994_WRITE_SEQUENCER_427 0x31AB 760 #define WM8994_WRITE_SEQUENCER_428 0x31AC 761 #define WM8994_WRITE_SEQUENCER_429 0x31AD 762 #define WM8994_WRITE_SEQUENCER_430 0x31AE 763 #define WM8994_WRITE_SEQUENCER_431 0x31AF 764 #define WM8994_WRITE_SEQUENCER_432 0x31B0 765 #define WM8994_WRITE_SEQUENCER_433 0x31B1 766 #define WM8994_WRITE_SEQUENCER_434 0x31B2 767 #define WM8994_WRITE_SEQUENCER_435 0x31B3 768 #define WM8994_WRITE_SEQUENCER_436 0x31B4 769 #define WM8994_WRITE_SEQUENCER_437 0x31B5 770 #define WM8994_WRITE_SEQUENCER_438 0x31B6 771 #define WM8994_WRITE_SEQUENCER_439 0x31B7 772 #define WM8994_WRITE_SEQUENCER_440 0x31B8 773 #define WM8994_WRITE_SEQUENCER_441 0x31B9 774 #define WM8994_WRITE_SEQUENCER_442 0x31BA 775 #define WM8994_WRITE_SEQUENCER_443 0x31BB 776 #define WM8994_WRITE_SEQUENCER_444 0x31BC 777 #define WM8994_WRITE_SEQUENCER_445 0x31BD 778 #define WM8994_WRITE_SEQUENCER_446 0x31BE 779 #define WM8994_WRITE_SEQUENCER_447 0x31BF 780 #define WM8994_WRITE_SEQUENCER_448 0x31C0 781 #define WM8994_WRITE_SEQUENCER_449 0x31C1 782 #define WM8994_WRITE_SEQUENCER_450 0x31C2 783 #define WM8994_WRITE_SEQUENCER_451 0x31C3 784 #define WM8994_WRITE_SEQUENCER_452 0x31C4 785 #define WM8994_WRITE_SEQUENCER_453 0x31C5 786 #define WM8994_WRITE_SEQUENCER_454 0x31C6 787 #define WM8994_WRITE_SEQUENCER_455 0x31C7 788 #define WM8994_WRITE_SEQUENCER_456 0x31C8 789 #define WM8994_WRITE_SEQUENCER_457 0x31C9 790 #define WM8994_WRITE_SEQUENCER_458 0x31CA 791 #define WM8994_WRITE_SEQUENCER_459 0x31CB 792 #define WM8994_WRITE_SEQUENCER_460 0x31CC 793 #define WM8994_WRITE_SEQUENCER_461 0x31CD 794 #define WM8994_WRITE_SEQUENCER_462 0x31CE 795 #define WM8994_WRITE_SEQUENCER_463 0x31CF 796 #define WM8994_WRITE_SEQUENCER_464 0x31D0 797 #define WM8994_WRITE_SEQUENCER_465 0x31D1 798 #define WM8994_WRITE_SEQUENCER_466 0x31D2 799 #define WM8994_WRITE_SEQUENCER_467 0x31D3 800 #define WM8994_WRITE_SEQUENCER_468 0x31D4 801 #define WM8994_WRITE_SEQUENCER_469 0x31D5 802 #define WM8994_WRITE_SEQUENCER_470 0x31D6 803 #define WM8994_WRITE_SEQUENCER_471 0x31D7 804 #define WM8994_WRITE_SEQUENCER_472 0x31D8 805 #define WM8994_WRITE_SEQUENCER_473 0x31D9 806 #define WM8994_WRITE_SEQUENCER_474 0x31DA 807 #define WM8994_WRITE_SEQUENCER_475 0x31DB 808 #define WM8994_WRITE_SEQUENCER_476 0x31DC 809 #define WM8994_WRITE_SEQUENCER_477 0x31DD 810 #define WM8994_WRITE_SEQUENCER_478 0x31DE 811 #define WM8994_WRITE_SEQUENCER_479 0x31DF 812 #define WM8994_WRITE_SEQUENCER_480 0x31E0 813 #define WM8994_WRITE_SEQUENCER_481 0x31E1 814 #define WM8994_WRITE_SEQUENCER_482 0x31E2 815 #define WM8994_WRITE_SEQUENCER_483 0x31E3 816 #define WM8994_WRITE_SEQUENCER_484 0x31E4 817 #define WM8994_WRITE_SEQUENCER_485 0x31E5 818 #define WM8994_WRITE_SEQUENCER_486 0x31E6 819 #define WM8994_WRITE_SEQUENCER_487 0x31E7 820 #define WM8994_WRITE_SEQUENCER_488 0x31E8 821 #define WM8994_WRITE_SEQUENCER_489 0x31E9 822 #define WM8994_WRITE_SEQUENCER_490 0x31EA 823 #define WM8994_WRITE_SEQUENCER_491 0x31EB 824 #define WM8994_WRITE_SEQUENCER_492 0x31EC 825 #define WM8994_WRITE_SEQUENCER_493 0x31ED 826 #define WM8994_WRITE_SEQUENCER_494 0x31EE 827 #define WM8994_WRITE_SEQUENCER_495 0x31EF 828 #define WM8994_WRITE_SEQUENCER_496 0x31F0 829 #define WM8994_WRITE_SEQUENCER_497 0x31F1 830 #define WM8994_WRITE_SEQUENCER_498 0x31F2 831 #define WM8994_WRITE_SEQUENCER_499 0x31F3 832 #define WM8994_WRITE_SEQUENCER_500 0x31F4 833 #define WM8994_WRITE_SEQUENCER_501 0x31F5 834 #define WM8994_WRITE_SEQUENCER_502 0x31F6 835 #define WM8994_WRITE_SEQUENCER_503 0x31F7 836 #define WM8994_WRITE_SEQUENCER_504 0x31F8 837 #define WM8994_WRITE_SEQUENCER_505 0x31F9 838 #define WM8994_WRITE_SEQUENCER_506 0x31FA 839 #define WM8994_WRITE_SEQUENCER_507 0x31FB 840 #define WM8994_WRITE_SEQUENCER_508 0x31FC 841 #define WM8994_WRITE_SEQUENCER_509 0x31FD 842 #define WM8994_WRITE_SEQUENCER_510 0x31FE 843 #define WM8994_WRITE_SEQUENCER_511 0x31FF 844 845 #define WM8994_REGISTER_COUNT 736 846 #define WM8994_MAX_REGISTER 0x31FF 847 #define WM8994_MAX_CACHED_REGISTER 0x749 848 849 /* 850 * Field Definitions. 851 */ 852 853 /* 854 * R0 (0x00) - Software Reset 855 */ 856 #define WM8994_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */ 857 #define WM8994_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */ 858 #define WM8994_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */ 859 860 /* 861 * R1 (0x01) - Power Management (1) 862 */ 863 #define WM8994_SPKOUTR_ENA 0x2000 /* SPKOUTR_ENA */ 864 #define WM8994_SPKOUTR_ENA_MASK 0x2000 /* SPKOUTR_ENA */ 865 #define WM8994_SPKOUTR_ENA_SHIFT 13 /* SPKOUTR_ENA */ 866 #define WM8994_SPKOUTR_ENA_WIDTH 1 /* SPKOUTR_ENA */ 867 #define WM8994_SPKOUTL_ENA 0x1000 /* SPKOUTL_ENA */ 868 #define WM8994_SPKOUTL_ENA_MASK 0x1000 /* SPKOUTL_ENA */ 869 #define WM8994_SPKOUTL_ENA_SHIFT 12 /* SPKOUTL_ENA */ 870 #define WM8994_SPKOUTL_ENA_WIDTH 1 /* SPKOUTL_ENA */ 871 #define WM8994_HPOUT2_ENA 0x0800 /* HPOUT2_ENA */ 872 #define WM8994_HPOUT2_ENA_MASK 0x0800 /* HPOUT2_ENA */ 873 #define WM8994_HPOUT2_ENA_SHIFT 11 /* HPOUT2_ENA */ 874 #define WM8994_HPOUT2_ENA_WIDTH 1 /* HPOUT2_ENA */ 875 #define WM8994_HPOUT1L_ENA 0x0200 /* HPOUT1L_ENA */ 876 #define WM8994_HPOUT1L_ENA_MASK 0x0200 /* HPOUT1L_ENA */ 877 #define WM8994_HPOUT1L_ENA_SHIFT 9 /* HPOUT1L_ENA */ 878 #define WM8994_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */ 879 #define WM8994_HPOUT1R_ENA 0x0100 /* HPOUT1R_ENA */ 880 #define WM8994_HPOUT1R_ENA_MASK 0x0100 /* HPOUT1R_ENA */ 881 #define WM8994_HPOUT1R_ENA_SHIFT 8 /* HPOUT1R_ENA */ 882 #define WM8994_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */ 883 #define WM8994_MICB2_ENA 0x0020 /* MICB2_ENA */ 884 #define WM8994_MICB2_ENA_MASK 0x0020 /* MICB2_ENA */ 885 #define WM8994_MICB2_ENA_SHIFT 5 /* MICB2_ENA */ 886 #define WM8994_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ 887 #define WM8994_MICB1_ENA 0x0010 /* MICB1_ENA */ 888 #define WM8994_MICB1_ENA_MASK 0x0010 /* MICB1_ENA */ 889 #define WM8994_MICB1_ENA_SHIFT 4 /* MICB1_ENA */ 890 #define WM8994_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ 891 #define WM8994_VMID_SEL_MASK 0x0006 /* VMID_SEL - [2:1] */ 892 #define WM8994_VMID_SEL_SHIFT 1 /* VMID_SEL - [2:1] */ 893 #define WM8994_VMID_SEL_WIDTH 2 /* VMID_SEL - [2:1] */ 894 #define WM8994_BIAS_ENA 0x0001 /* BIAS_ENA */ 895 #define WM8994_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */ 896 #define WM8994_BIAS_ENA_SHIFT 0 /* BIAS_ENA */ 897 #define WM8994_BIAS_ENA_WIDTH 1 /* BIAS_ENA */ 898 899 /* 900 * R2 (0x02) - Power Management (2) 901 */ 902 #define WM8994_TSHUT_ENA 0x4000 /* TSHUT_ENA */ 903 #define WM8994_TSHUT_ENA_MASK 0x4000 /* TSHUT_ENA */ 904 #define WM8994_TSHUT_ENA_SHIFT 14 /* TSHUT_ENA */ 905 #define WM8994_TSHUT_ENA_WIDTH 1 /* TSHUT_ENA */ 906 #define WM8994_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */ 907 #define WM8994_TSHUT_OPDIS_MASK 0x2000 /* TSHUT_OPDIS */ 908 #define WM8994_TSHUT_OPDIS_SHIFT 13 /* TSHUT_OPDIS */ 909 #define WM8994_TSHUT_OPDIS_WIDTH 1 /* TSHUT_OPDIS */ 910 #define WM8994_OPCLK_ENA 0x0800 /* OPCLK_ENA */ 911 #define WM8994_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */ 912 #define WM8994_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */ 913 #define WM8994_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */ 914 #define WM8994_MIXINL_ENA 0x0200 /* MIXINL_ENA */ 915 #define WM8994_MIXINL_ENA_MASK 0x0200 /* MIXINL_ENA */ 916 #define WM8994_MIXINL_ENA_SHIFT 9 /* MIXINL_ENA */ 917 #define WM8994_MIXINL_ENA_WIDTH 1 /* MIXINL_ENA */ 918 #define WM8994_MIXINR_ENA 0x0100 /* MIXINR_ENA */ 919 #define WM8994_MIXINR_ENA_MASK 0x0100 /* MIXINR_ENA */ 920 #define WM8994_MIXINR_ENA_SHIFT 8 /* MIXINR_ENA */ 921 #define WM8994_MIXINR_ENA_WIDTH 1 /* MIXINR_ENA */ 922 #define WM8994_IN2L_ENA 0x0080 /* IN2L_ENA */ 923 #define WM8994_IN2L_ENA_MASK 0x0080 /* IN2L_ENA */ 924 #define WM8994_IN2L_ENA_SHIFT 7 /* IN2L_ENA */ 925 #define WM8994_IN2L_ENA_WIDTH 1 /* IN2L_ENA */ 926 #define WM8994_IN1L_ENA 0x0040 /* IN1L_ENA */ 927 #define WM8994_IN1L_ENA_MASK 0x0040 /* IN1L_ENA */ 928 #define WM8994_IN1L_ENA_SHIFT 6 /* IN1L_ENA */ 929 #define WM8994_IN1L_ENA_WIDTH 1 /* IN1L_ENA */ 930 #define WM8994_IN2R_ENA 0x0020 /* IN2R_ENA */ 931 #define WM8994_IN2R_ENA_MASK 0x0020 /* IN2R_ENA */ 932 #define WM8994_IN2R_ENA_SHIFT 5 /* IN2R_ENA */ 933 #define WM8994_IN2R_ENA_WIDTH 1 /* IN2R_ENA */ 934 #define WM8994_IN1R_ENA 0x0010 /* IN1R_ENA */ 935 #define WM8994_IN1R_ENA_MASK 0x0010 /* IN1R_ENA */ 936 #define WM8994_IN1R_ENA_SHIFT 4 /* IN1R_ENA */ 937 #define WM8994_IN1R_ENA_WIDTH 1 /* IN1R_ENA */ 938 939 /* 940 * R3 (0x03) - Power Management (3) 941 */ 942 #define WM8994_LINEOUT1N_ENA 0x2000 /* LINEOUT1N_ENA */ 943 #define WM8994_LINEOUT1N_ENA_MASK 0x2000 /* LINEOUT1N_ENA */ 944 #define WM8994_LINEOUT1N_ENA_SHIFT 13 /* LINEOUT1N_ENA */ 945 #define WM8994_LINEOUT1N_ENA_WIDTH 1 /* LINEOUT1N_ENA */ 946 #define WM8994_LINEOUT1P_ENA 0x1000 /* LINEOUT1P_ENA */ 947 #define WM8994_LINEOUT1P_ENA_MASK 0x1000 /* LINEOUT1P_ENA */ 948 #define WM8994_LINEOUT1P_ENA_SHIFT 12 /* LINEOUT1P_ENA */ 949 #define WM8994_LINEOUT1P_ENA_WIDTH 1 /* LINEOUT1P_ENA */ 950 #define WM8994_LINEOUT2N_ENA 0x0800 /* LINEOUT2N_ENA */ 951 #define WM8994_LINEOUT2N_ENA_MASK 0x0800 /* LINEOUT2N_ENA */ 952 #define WM8994_LINEOUT2N_ENA_SHIFT 11 /* LINEOUT2N_ENA */ 953 #define WM8994_LINEOUT2N_ENA_WIDTH 1 /* LINEOUT2N_ENA */ 954 #define WM8994_LINEOUT2P_ENA 0x0400 /* LINEOUT2P_ENA */ 955 #define WM8994_LINEOUT2P_ENA_MASK 0x0400 /* LINEOUT2P_ENA */ 956 #define WM8994_LINEOUT2P_ENA_SHIFT 10 /* LINEOUT2P_ENA */ 957 #define WM8994_LINEOUT2P_ENA_WIDTH 1 /* LINEOUT2P_ENA */ 958 #define WM8994_SPKRVOL_ENA 0x0200 /* SPKRVOL_ENA */ 959 #define WM8994_SPKRVOL_ENA_MASK 0x0200 /* SPKRVOL_ENA */ 960 #define WM8994_SPKRVOL_ENA_SHIFT 9 /* SPKRVOL_ENA */ 961 #define WM8994_SPKRVOL_ENA_WIDTH 1 /* SPKRVOL_ENA */ 962 #define WM8994_SPKLVOL_ENA 0x0100 /* SPKLVOL_ENA */ 963 #define WM8994_SPKLVOL_ENA_MASK 0x0100 /* SPKLVOL_ENA */ 964 #define WM8994_SPKLVOL_ENA_SHIFT 8 /* SPKLVOL_ENA */ 965 #define WM8994_SPKLVOL_ENA_WIDTH 1 /* SPKLVOL_ENA */ 966 #define WM8994_MIXOUTLVOL_ENA 0x0080 /* MIXOUTLVOL_ENA */ 967 #define WM8994_MIXOUTLVOL_ENA_MASK 0x0080 /* MIXOUTLVOL_ENA */ 968 #define WM8994_MIXOUTLVOL_ENA_SHIFT 7 /* MIXOUTLVOL_ENA */ 969 #define WM8994_MIXOUTLVOL_ENA_WIDTH 1 /* MIXOUTLVOL_ENA */ 970 #define WM8994_MIXOUTRVOL_ENA 0x0040 /* MIXOUTRVOL_ENA */ 971 #define WM8994_MIXOUTRVOL_ENA_MASK 0x0040 /* MIXOUTRVOL_ENA */ 972 #define WM8994_MIXOUTRVOL_ENA_SHIFT 6 /* MIXOUTRVOL_ENA */ 973 #define WM8994_MIXOUTRVOL_ENA_WIDTH 1 /* MIXOUTRVOL_ENA */ 974 #define WM8994_MIXOUTL_ENA 0x0020 /* MIXOUTL_ENA */ 975 #define WM8994_MIXOUTL_ENA_MASK 0x0020 /* MIXOUTL_ENA */ 976 #define WM8994_MIXOUTL_ENA_SHIFT 5 /* MIXOUTL_ENA */ 977 #define WM8994_MIXOUTL_ENA_WIDTH 1 /* MIXOUTL_ENA */ 978 #define WM8994_MIXOUTR_ENA 0x0010 /* MIXOUTR_ENA */ 979 #define WM8994_MIXOUTR_ENA_MASK 0x0010 /* MIXOUTR_ENA */ 980 #define WM8994_MIXOUTR_ENA_SHIFT 4 /* MIXOUTR_ENA */ 981 #define WM8994_MIXOUTR_ENA_WIDTH 1 /* MIXOUTR_ENA */ 982 983 /* 984 * R4 (0x04) - Power Management (4) 985 */ 986 #define WM8994_AIF2ADCL_ENA 0x2000 /* AIF2ADCL_ENA */ 987 #define WM8994_AIF2ADCL_ENA_MASK 0x2000 /* AIF2ADCL_ENA */ 988 #define WM8994_AIF2ADCL_ENA_SHIFT 13 /* AIF2ADCL_ENA */ 989 #define WM8994_AIF2ADCL_ENA_WIDTH 1 /* AIF2ADCL_ENA */ 990 #define WM8994_AIF2ADCR_ENA 0x1000 /* AIF2ADCR_ENA */ 991 #define WM8994_AIF2ADCR_ENA_MASK 0x1000 /* AIF2ADCR_ENA */ 992 #define WM8994_AIF2ADCR_ENA_SHIFT 12 /* AIF2ADCR_ENA */ 993 #define WM8994_AIF2ADCR_ENA_WIDTH 1 /* AIF2ADCR_ENA */ 994 #define WM8994_AIF1ADC2L_ENA 0x0800 /* AIF1ADC2L_ENA */ 995 #define WM8994_AIF1ADC2L_ENA_MASK 0x0800 /* AIF1ADC2L_ENA */ 996 #define WM8994_AIF1ADC2L_ENA_SHIFT 11 /* AIF1ADC2L_ENA */ 997 #define WM8994_AIF1ADC2L_ENA_WIDTH 1 /* AIF1ADC2L_ENA */ 998 #define WM8994_AIF1ADC2R_ENA 0x0400 /* AIF1ADC2R_ENA */ 999 #define WM8994_AIF1ADC2R_ENA_MASK 0x0400 /* AIF1ADC2R_ENA */ 1000 #define WM8994_AIF1ADC2R_ENA_SHIFT 10 /* AIF1ADC2R_ENA */ 1001 #define WM8994_AIF1ADC2R_ENA_WIDTH 1 /* AIF1ADC2R_ENA */ 1002 #define WM8994_AIF1ADC1L_ENA 0x0200 /* AIF1ADC1L_ENA */ 1003 #define WM8994_AIF1ADC1L_ENA_MASK 0x0200 /* AIF1ADC1L_ENA */ 1004 #define WM8994_AIF1ADC1L_ENA_SHIFT 9 /* AIF1ADC1L_ENA */ 1005 #define WM8994_AIF1ADC1L_ENA_WIDTH 1 /* AIF1ADC1L_ENA */ 1006 #define WM8994_AIF1ADC1R_ENA 0x0100 /* AIF1ADC1R_ENA */ 1007 #define WM8994_AIF1ADC1R_ENA_MASK 0x0100 /* AIF1ADC1R_ENA */ 1008 #define WM8994_AIF1ADC1R_ENA_SHIFT 8 /* AIF1ADC1R_ENA */ 1009 #define WM8994_AIF1ADC1R_ENA_WIDTH 1 /* AIF1ADC1R_ENA */ 1010 #define WM8994_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */ 1011 #define WM8994_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */ 1012 #define WM8994_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */ 1013 #define WM8994_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */ 1014 #define WM8994_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */ 1015 #define WM8994_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */ 1016 #define WM8994_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */ 1017 #define WM8994_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */ 1018 #define WM8994_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */ 1019 #define WM8994_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */ 1020 #define WM8994_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */ 1021 #define WM8994_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */ 1022 #define WM8994_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */ 1023 #define WM8994_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */ 1024 #define WM8994_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */ 1025 #define WM8994_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */ 1026 #define WM8994_ADCL_ENA 0x0002 /* ADCL_ENA */ 1027 #define WM8994_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */ 1028 #define WM8994_ADCL_ENA_SHIFT 1 /* ADCL_ENA */ 1029 #define WM8994_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ 1030 #define WM8994_ADCR_ENA 0x0001 /* ADCR_ENA */ 1031 #define WM8994_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */ 1032 #define WM8994_ADCR_ENA_SHIFT 0 /* ADCR_ENA */ 1033 #define WM8994_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ 1034 1035 /* 1036 * R5 (0x05) - Power Management (5) 1037 */ 1038 #define WM8994_AIF2DACL_ENA 0x2000 /* AIF2DACL_ENA */ 1039 #define WM8994_AIF2DACL_ENA_MASK 0x2000 /* AIF2DACL_ENA */ 1040 #define WM8994_AIF2DACL_ENA_SHIFT 13 /* AIF2DACL_ENA */ 1041 #define WM8994_AIF2DACL_ENA_WIDTH 1 /* AIF2DACL_ENA */ 1042 #define WM8994_AIF2DACR_ENA 0x1000 /* AIF2DACR_ENA */ 1043 #define WM8994_AIF2DACR_ENA_MASK 0x1000 /* AIF2DACR_ENA */ 1044 #define WM8994_AIF2DACR_ENA_SHIFT 12 /* AIF2DACR_ENA */ 1045 #define WM8994_AIF2DACR_ENA_WIDTH 1 /* AIF2DACR_ENA */ 1046 #define WM8994_AIF1DAC2L_ENA 0x0800 /* AIF1DAC2L_ENA */ 1047 #define WM8994_AIF1DAC2L_ENA_MASK 0x0800 /* AIF1DAC2L_ENA */ 1048 #define WM8994_AIF1DAC2L_ENA_SHIFT 11 /* AIF1DAC2L_ENA */ 1049 #define WM8994_AIF1DAC2L_ENA_WIDTH 1 /* AIF1DAC2L_ENA */ 1050 #define WM8994_AIF1DAC2R_ENA 0x0400 /* AIF1DAC2R_ENA */ 1051 #define WM8994_AIF1DAC2R_ENA_MASK 0x0400 /* AIF1DAC2R_ENA */ 1052 #define WM8994_AIF1DAC2R_ENA_SHIFT 10 /* AIF1DAC2R_ENA */ 1053 #define WM8994_AIF1DAC2R_ENA_WIDTH 1 /* AIF1DAC2R_ENA */ 1054 #define WM8994_AIF1DAC1L_ENA 0x0200 /* AIF1DAC1L_ENA */ 1055 #define WM8994_AIF1DAC1L_ENA_MASK 0x0200 /* AIF1DAC1L_ENA */ 1056 #define WM8994_AIF1DAC1L_ENA_SHIFT 9 /* AIF1DAC1L_ENA */ 1057 #define WM8994_AIF1DAC1L_ENA_WIDTH 1 /* AIF1DAC1L_ENA */ 1058 #define WM8994_AIF1DAC1R_ENA 0x0100 /* AIF1DAC1R_ENA */ 1059 #define WM8994_AIF1DAC1R_ENA_MASK 0x0100 /* AIF1DAC1R_ENA */ 1060 #define WM8994_AIF1DAC1R_ENA_SHIFT 8 /* AIF1DAC1R_ENA */ 1061 #define WM8994_AIF1DAC1R_ENA_WIDTH 1 /* AIF1DAC1R_ENA */ 1062 #define WM8994_DAC2L_ENA 0x0008 /* DAC2L_ENA */ 1063 #define WM8994_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */ 1064 #define WM8994_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */ 1065 #define WM8994_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */ 1066 #define WM8994_DAC2R_ENA 0x0004 /* DAC2R_ENA */ 1067 #define WM8994_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */ 1068 #define WM8994_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */ 1069 #define WM8994_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */ 1070 #define WM8994_DAC1L_ENA 0x0002 /* DAC1L_ENA */ 1071 #define WM8994_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */ 1072 #define WM8994_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */ 1073 #define WM8994_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */ 1074 #define WM8994_DAC1R_ENA 0x0001 /* DAC1R_ENA */ 1075 #define WM8994_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */ 1076 #define WM8994_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */ 1077 #define WM8994_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */ 1078 1079 /* 1080 * R6 (0x06) - Power Management (6) 1081 */ 1082 #define WM8958_AIF3ADC_SRC_MASK 0x0600 /* AIF3ADC_SRC - [10:9] */ 1083 #define WM8958_AIF3ADC_SRC_SHIFT 9 /* AIF3ADC_SRC - [10:9] */ 1084 #define WM8958_AIF3ADC_SRC_WIDTH 2 /* AIF3ADC_SRC - [10:9] */ 1085 #define WM8958_AIF2DAC_SRC_MASK 0x0180 /* AIF2DAC_SRC - [8:7] */ 1086 #define WM8958_AIF2DAC_SRC_SHIFT 7 /* AIF2DAC_SRC - [8:7] */ 1087 #define WM8958_AIF2DAC_SRC_WIDTH 2 /* AIF2DAC_SRC - [8:7] */ 1088 #define WM8994_AIF3_TRI 0x0020 /* AIF3_TRI */ 1089 #define WM8994_AIF3_TRI_MASK 0x0020 /* AIF3_TRI */ 1090 #define WM8994_AIF3_TRI_SHIFT 5 /* AIF3_TRI */ 1091 #define WM8994_AIF3_TRI_WIDTH 1 /* AIF3_TRI */ 1092 #define WM8994_AIF3_ADCDAT_SRC_MASK 0x0018 /* AIF3_ADCDAT_SRC - [4:3] */ 1093 #define WM8994_AIF3_ADCDAT_SRC_SHIFT 3 /* AIF3_ADCDAT_SRC - [4:3] */ 1094 #define WM8994_AIF3_ADCDAT_SRC_WIDTH 2 /* AIF3_ADCDAT_SRC - [4:3] */ 1095 #define WM8994_AIF2_ADCDAT_SRC 0x0004 /* AIF2_ADCDAT_SRC */ 1096 #define WM8994_AIF2_ADCDAT_SRC_MASK 0x0004 /* AIF2_ADCDAT_SRC */ 1097 #define WM8994_AIF2_ADCDAT_SRC_SHIFT 2 /* AIF2_ADCDAT_SRC */ 1098 #define WM8994_AIF2_ADCDAT_SRC_WIDTH 1 /* AIF2_ADCDAT_SRC */ 1099 #define WM8994_AIF2_DACDAT_SRC 0x0002 /* AIF2_DACDAT_SRC */ 1100 #define WM8994_AIF2_DACDAT_SRC_MASK 0x0002 /* AIF2_DACDAT_SRC */ 1101 #define WM8994_AIF2_DACDAT_SRC_SHIFT 1 /* AIF2_DACDAT_SRC */ 1102 #define WM8994_AIF2_DACDAT_SRC_WIDTH 1 /* AIF2_DACDAT_SRC */ 1103 #define WM8994_AIF1_DACDAT_SRC 0x0001 /* AIF1_DACDAT_SRC */ 1104 #define WM8994_AIF1_DACDAT_SRC_MASK 0x0001 /* AIF1_DACDAT_SRC */ 1105 #define WM8994_AIF1_DACDAT_SRC_SHIFT 0 /* AIF1_DACDAT_SRC */ 1106 #define WM8994_AIF1_DACDAT_SRC_WIDTH 1 /* AIF1_DACDAT_SRC */ 1107 1108 /* 1109 * R21 (0x15) - Input Mixer (1) 1110 */ 1111 #define WM8994_IN1RP_MIXINR_BOOST 0x0100 /* IN1RP_MIXINR_BOOST */ 1112 #define WM8994_IN1RP_MIXINR_BOOST_MASK 0x0100 /* IN1RP_MIXINR_BOOST */ 1113 #define WM8994_IN1RP_MIXINR_BOOST_SHIFT 8 /* IN1RP_MIXINR_BOOST */ 1114 #define WM8994_IN1RP_MIXINR_BOOST_WIDTH 1 /* IN1RP_MIXINR_BOOST */ 1115 #define WM8994_IN1LP_MIXINL_BOOST 0x0080 /* IN1LP_MIXINL_BOOST */ 1116 #define WM8994_IN1LP_MIXINL_BOOST_MASK 0x0080 /* IN1LP_MIXINL_BOOST */ 1117 #define WM8994_IN1LP_MIXINL_BOOST_SHIFT 7 /* IN1LP_MIXINL_BOOST */ 1118 #define WM8994_IN1LP_MIXINL_BOOST_WIDTH 1 /* IN1LP_MIXINL_BOOST */ 1119 #define WM8994_INPUTS_CLAMP 0x0040 /* INPUTS_CLAMP */ 1120 #define WM8994_INPUTS_CLAMP_MASK 0x0040 /* INPUTS_CLAMP */ 1121 #define WM8994_INPUTS_CLAMP_SHIFT 6 /* INPUTS_CLAMP */ 1122 #define WM8994_INPUTS_CLAMP_WIDTH 1 /* INPUTS_CLAMP */ 1123 1124 /* 1125 * R24 (0x18) - Left Line Input 1&2 Volume 1126 */ 1127 #define WM8994_IN1_VU 0x0100 /* IN1_VU */ 1128 #define WM8994_IN1_VU_MASK 0x0100 /* IN1_VU */ 1129 #define WM8994_IN1_VU_SHIFT 8 /* IN1_VU */ 1130 #define WM8994_IN1_VU_WIDTH 1 /* IN1_VU */ 1131 #define WM8994_IN1L_MUTE 0x0080 /* IN1L_MUTE */ 1132 #define WM8994_IN1L_MUTE_MASK 0x0080 /* IN1L_MUTE */ 1133 #define WM8994_IN1L_MUTE_SHIFT 7 /* IN1L_MUTE */ 1134 #define WM8994_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */ 1135 #define WM8994_IN1L_ZC 0x0040 /* IN1L_ZC */ 1136 #define WM8994_IN1L_ZC_MASK 0x0040 /* IN1L_ZC */ 1137 #define WM8994_IN1L_ZC_SHIFT 6 /* IN1L_ZC */ 1138 #define WM8994_IN1L_ZC_WIDTH 1 /* IN1L_ZC */ 1139 #define WM8994_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */ 1140 #define WM8994_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */ 1141 #define WM8994_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */ 1142 1143 /* 1144 * R25 (0x19) - Left Line Input 3&4 Volume 1145 */ 1146 #define WM8994_IN2_VU 0x0100 /* IN2_VU */ 1147 #define WM8994_IN2_VU_MASK 0x0100 /* IN2_VU */ 1148 #define WM8994_IN2_VU_SHIFT 8 /* IN2_VU */ 1149 #define WM8994_IN2_VU_WIDTH 1 /* IN2_VU */ 1150 #define WM8994_IN2L_MUTE 0x0080 /* IN2L_MUTE */ 1151 #define WM8994_IN2L_MUTE_MASK 0x0080 /* IN2L_MUTE */ 1152 #define WM8994_IN2L_MUTE_SHIFT 7 /* IN2L_MUTE */ 1153 #define WM8994_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */ 1154 #define WM8994_IN2L_ZC 0x0040 /* IN2L_ZC */ 1155 #define WM8994_IN2L_ZC_MASK 0x0040 /* IN2L_ZC */ 1156 #define WM8994_IN2L_ZC_SHIFT 6 /* IN2L_ZC */ 1157 #define WM8994_IN2L_ZC_WIDTH 1 /* IN2L_ZC */ 1158 #define WM8994_IN2L_VOL_MASK 0x001F /* IN2L_VOL - [4:0] */ 1159 #define WM8994_IN2L_VOL_SHIFT 0 /* IN2L_VOL - [4:0] */ 1160 #define WM8994_IN2L_VOL_WIDTH 5 /* IN2L_VOL - [4:0] */ 1161 1162 /* 1163 * R26 (0x1A) - Right Line Input 1&2 Volume 1164 */ 1165 #define WM8994_IN1_VU 0x0100 /* IN1_VU */ 1166 #define WM8994_IN1_VU_MASK 0x0100 /* IN1_VU */ 1167 #define WM8994_IN1_VU_SHIFT 8 /* IN1_VU */ 1168 #define WM8994_IN1_VU_WIDTH 1 /* IN1_VU */ 1169 #define WM8994_IN1R_MUTE 0x0080 /* IN1R_MUTE */ 1170 #define WM8994_IN1R_MUTE_MASK 0x0080 /* IN1R_MUTE */ 1171 #define WM8994_IN1R_MUTE_SHIFT 7 /* IN1R_MUTE */ 1172 #define WM8994_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */ 1173 #define WM8994_IN1R_ZC 0x0040 /* IN1R_ZC */ 1174 #define WM8994_IN1R_ZC_MASK 0x0040 /* IN1R_ZC */ 1175 #define WM8994_IN1R_ZC_SHIFT 6 /* IN1R_ZC */ 1176 #define WM8994_IN1R_ZC_WIDTH 1 /* IN1R_ZC */ 1177 #define WM8994_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */ 1178 #define WM8994_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */ 1179 #define WM8994_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */ 1180 1181 /* 1182 * R27 (0x1B) - Right Line Input 3&4 Volume 1183 */ 1184 #define WM8994_IN2_VU 0x0100 /* IN2_VU */ 1185 #define WM8994_IN2_VU_MASK 0x0100 /* IN2_VU */ 1186 #define WM8994_IN2_VU_SHIFT 8 /* IN2_VU */ 1187 #define WM8994_IN2_VU_WIDTH 1 /* IN2_VU */ 1188 #define WM8994_IN2R_MUTE 0x0080 /* IN2R_MUTE */ 1189 #define WM8994_IN2R_MUTE_MASK 0x0080 /* IN2R_MUTE */ 1190 #define WM8994_IN2R_MUTE_SHIFT 7 /* IN2R_MUTE */ 1191 #define WM8994_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */ 1192 #define WM8994_IN2R_ZC 0x0040 /* IN2R_ZC */ 1193 #define WM8994_IN2R_ZC_MASK 0x0040 /* IN2R_ZC */ 1194 #define WM8994_IN2R_ZC_SHIFT 6 /* IN2R_ZC */ 1195 #define WM8994_IN2R_ZC_WIDTH 1 /* IN2R_ZC */ 1196 #define WM8994_IN2R_VOL_MASK 0x001F /* IN2R_VOL - [4:0] */ 1197 #define WM8994_IN2R_VOL_SHIFT 0 /* IN2R_VOL - [4:0] */ 1198 #define WM8994_IN2R_VOL_WIDTH 5 /* IN2R_VOL - [4:0] */ 1199 1200 /* 1201 * R28 (0x1C) - Left Output Volume 1202 */ 1203 #define WM8994_HPOUT1_VU 0x0100 /* HPOUT1_VU */ 1204 #define WM8994_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */ 1205 #define WM8994_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */ 1206 #define WM8994_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */ 1207 #define WM8994_HPOUT1L_ZC 0x0080 /* HPOUT1L_ZC */ 1208 #define WM8994_HPOUT1L_ZC_MASK 0x0080 /* HPOUT1L_ZC */ 1209 #define WM8994_HPOUT1L_ZC_SHIFT 7 /* HPOUT1L_ZC */ 1210 #define WM8994_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */ 1211 #define WM8994_HPOUT1L_MUTE_N 0x0040 /* HPOUT1L_MUTE_N */ 1212 #define WM8994_HPOUT1L_MUTE_N_MASK 0x0040 /* HPOUT1L_MUTE_N */ 1213 #define WM8994_HPOUT1L_MUTE_N_SHIFT 6 /* HPOUT1L_MUTE_N */ 1214 #define WM8994_HPOUT1L_MUTE_N_WIDTH 1 /* HPOUT1L_MUTE_N */ 1215 #define WM8994_HPOUT1L_VOL_MASK 0x003F /* HPOUT1L_VOL - [5:0] */ 1216 #define WM8994_HPOUT1L_VOL_SHIFT 0 /* HPOUT1L_VOL - [5:0] */ 1217 #define WM8994_HPOUT1L_VOL_WIDTH 6 /* HPOUT1L_VOL - [5:0] */ 1218 1219 /* 1220 * R29 (0x1D) - Right Output Volume 1221 */ 1222 #define WM8994_HPOUT1_VU 0x0100 /* HPOUT1_VU */ 1223 #define WM8994_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */ 1224 #define WM8994_HPOUT1_VU_SHIFT 8 /* HPOUT1_VU */ 1225 #define WM8994_HPOUT1_VU_WIDTH 1 /* HPOUT1_VU */ 1226 #define WM8994_HPOUT1R_ZC 0x0080 /* HPOUT1R_ZC */ 1227 #define WM8994_HPOUT1R_ZC_MASK 0x0080 /* HPOUT1R_ZC */ 1228 #define WM8994_HPOUT1R_ZC_SHIFT 7 /* HPOUT1R_ZC */ 1229 #define WM8994_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */ 1230 #define WM8994_HPOUT1R_MUTE_N 0x0040 /* HPOUT1R_MUTE_N */ 1231 #define WM8994_HPOUT1R_MUTE_N_MASK 0x0040 /* HPOUT1R_MUTE_N */ 1232 #define WM8994_HPOUT1R_MUTE_N_SHIFT 6 /* HPOUT1R_MUTE_N */ 1233 #define WM8994_HPOUT1R_MUTE_N_WIDTH 1 /* HPOUT1R_MUTE_N */ 1234 #define WM8994_HPOUT1R_VOL_MASK 0x003F /* HPOUT1R_VOL - [5:0] */ 1235 #define WM8994_HPOUT1R_VOL_SHIFT 0 /* HPOUT1R_VOL - [5:0] */ 1236 #define WM8994_HPOUT1R_VOL_WIDTH 6 /* HPOUT1R_VOL - [5:0] */ 1237 1238 /* 1239 * R30 (0x1E) - Line Outputs Volume 1240 */ 1241 #define WM8994_LINEOUT1N_MUTE 0x0040 /* LINEOUT1N_MUTE */ 1242 #define WM8994_LINEOUT1N_MUTE_MASK 0x0040 /* LINEOUT1N_MUTE */ 1243 #define WM8994_LINEOUT1N_MUTE_SHIFT 6 /* LINEOUT1N_MUTE */ 1244 #define WM8994_LINEOUT1N_MUTE_WIDTH 1 /* LINEOUT1N_MUTE */ 1245 #define WM8994_LINEOUT1P_MUTE 0x0020 /* LINEOUT1P_MUTE */ 1246 #define WM8994_LINEOUT1P_MUTE_MASK 0x0020 /* LINEOUT1P_MUTE */ 1247 #define WM8994_LINEOUT1P_MUTE_SHIFT 5 /* LINEOUT1P_MUTE */ 1248 #define WM8994_LINEOUT1P_MUTE_WIDTH 1 /* LINEOUT1P_MUTE */ 1249 #define WM8994_LINEOUT1_VOL 0x0010 /* LINEOUT1_VOL */ 1250 #define WM8994_LINEOUT1_VOL_MASK 0x0010 /* LINEOUT1_VOL */ 1251 #define WM8994_LINEOUT1_VOL_SHIFT 4 /* LINEOUT1_VOL */ 1252 #define WM8994_LINEOUT1_VOL_WIDTH 1 /* LINEOUT1_VOL */ 1253 #define WM8994_LINEOUT2N_MUTE 0x0004 /* LINEOUT2N_MUTE */ 1254 #define WM8994_LINEOUT2N_MUTE_MASK 0x0004 /* LINEOUT2N_MUTE */ 1255 #define WM8994_LINEOUT2N_MUTE_SHIFT 2 /* LINEOUT2N_MUTE */ 1256 #define WM8994_LINEOUT2N_MUTE_WIDTH 1 /* LINEOUT2N_MUTE */ 1257 #define WM8994_LINEOUT2P_MUTE 0x0002 /* LINEOUT2P_MUTE */ 1258 #define WM8994_LINEOUT2P_MUTE_MASK 0x0002 /* LINEOUT2P_MUTE */ 1259 #define WM8994_LINEOUT2P_MUTE_SHIFT 1 /* LINEOUT2P_MUTE */ 1260 #define WM8994_LINEOUT2P_MUTE_WIDTH 1 /* LINEOUT2P_MUTE */ 1261 #define WM8994_LINEOUT2_VOL 0x0001 /* LINEOUT2_VOL */ 1262 #define WM8994_LINEOUT2_VOL_MASK 0x0001 /* LINEOUT2_VOL */ 1263 #define WM8994_LINEOUT2_VOL_SHIFT 0 /* LINEOUT2_VOL */ 1264 #define WM8994_LINEOUT2_VOL_WIDTH 1 /* LINEOUT2_VOL */ 1265 1266 /* 1267 * R31 (0x1F) - HPOUT2 Volume 1268 */ 1269 #define WM8994_HPOUT2_MUTE 0x0020 /* HPOUT2_MUTE */ 1270 #define WM8994_HPOUT2_MUTE_MASK 0x0020 /* HPOUT2_MUTE */ 1271 #define WM8994_HPOUT2_MUTE_SHIFT 5 /* HPOUT2_MUTE */ 1272 #define WM8994_HPOUT2_MUTE_WIDTH 1 /* HPOUT2_MUTE */ 1273 #define WM8994_HPOUT2_VOL 0x0010 /* HPOUT2_VOL */ 1274 #define WM8994_HPOUT2_VOL_MASK 0x0010 /* HPOUT2_VOL */ 1275 #define WM8994_HPOUT2_VOL_SHIFT 4 /* HPOUT2_VOL */ 1276 #define WM8994_HPOUT2_VOL_WIDTH 1 /* HPOUT2_VOL */ 1277 1278 /* 1279 * R32 (0x20) - Left OPGA Volume 1280 */ 1281 #define WM8994_MIXOUT_VU 0x0100 /* MIXOUT_VU */ 1282 #define WM8994_MIXOUT_VU_MASK 0x0100 /* MIXOUT_VU */ 1283 #define WM8994_MIXOUT_VU_SHIFT 8 /* MIXOUT_VU */ 1284 #define WM8994_MIXOUT_VU_WIDTH 1 /* MIXOUT_VU */ 1285 #define WM8994_MIXOUTL_ZC 0x0080 /* MIXOUTL_ZC */ 1286 #define WM8994_MIXOUTL_ZC_MASK 0x0080 /* MIXOUTL_ZC */ 1287 #define WM8994_MIXOUTL_ZC_SHIFT 7 /* MIXOUTL_ZC */ 1288 #define WM8994_MIXOUTL_ZC_WIDTH 1 /* MIXOUTL_ZC */ 1289 #define WM8994_MIXOUTL_MUTE_N 0x0040 /* MIXOUTL_MUTE_N */ 1290 #define WM8994_MIXOUTL_MUTE_N_MASK 0x0040 /* MIXOUTL_MUTE_N */ 1291 #define WM8994_MIXOUTL_MUTE_N_SHIFT 6 /* MIXOUTL_MUTE_N */ 1292 #define WM8994_MIXOUTL_MUTE_N_WIDTH 1 /* MIXOUTL_MUTE_N */ 1293 #define WM8994_MIXOUTL_VOL_MASK 0x003F /* MIXOUTL_VOL - [5:0] */ 1294 #define WM8994_MIXOUTL_VOL_SHIFT 0 /* MIXOUTL_VOL - [5:0] */ 1295 #define WM8994_MIXOUTL_VOL_WIDTH 6 /* MIXOUTL_VOL - [5:0] */ 1296 1297 /* 1298 * R33 (0x21) - Right OPGA Volume 1299 */ 1300 #define WM8994_MIXOUT_VU 0x0100 /* MIXOUT_VU */ 1301 #define WM8994_MIXOUT_VU_MASK 0x0100 /* MIXOUT_VU */ 1302 #define WM8994_MIXOUT_VU_SHIFT 8 /* MIXOUT_VU */ 1303 #define WM8994_MIXOUT_VU_WIDTH 1 /* MIXOUT_VU */ 1304 #define WM8994_MIXOUTR_ZC 0x0080 /* MIXOUTR_ZC */ 1305 #define WM8994_MIXOUTR_ZC_MASK 0x0080 /* MIXOUTR_ZC */ 1306 #define WM8994_MIXOUTR_ZC_SHIFT 7 /* MIXOUTR_ZC */ 1307 #define WM8994_MIXOUTR_ZC_WIDTH 1 /* MIXOUTR_ZC */ 1308 #define WM8994_MIXOUTR_MUTE_N 0x0040 /* MIXOUTR_MUTE_N */ 1309 #define WM8994_MIXOUTR_MUTE_N_MASK 0x0040 /* MIXOUTR_MUTE_N */ 1310 #define WM8994_MIXOUTR_MUTE_N_SHIFT 6 /* MIXOUTR_MUTE_N */ 1311 #define WM8994_MIXOUTR_MUTE_N_WIDTH 1 /* MIXOUTR_MUTE_N */ 1312 #define WM8994_MIXOUTR_VOL_MASK 0x003F /* MIXOUTR_VOL - [5:0] */ 1313 #define WM8994_MIXOUTR_VOL_SHIFT 0 /* MIXOUTR_VOL - [5:0] */ 1314 #define WM8994_MIXOUTR_VOL_WIDTH 6 /* MIXOUTR_VOL - [5:0] */ 1315 1316 /* 1317 * R34 (0x22) - SPKMIXL Attenuation 1318 */ 1319 #define WM8994_DAC2L_SPKMIXL_VOL 0x0040 /* DAC2L_SPKMIXL_VOL */ 1320 #define WM8994_DAC2L_SPKMIXL_VOL_MASK 0x0040 /* DAC2L_SPKMIXL_VOL */ 1321 #define WM8994_DAC2L_SPKMIXL_VOL_SHIFT 6 /* DAC2L_SPKMIXL_VOL */ 1322 #define WM8994_DAC2L_SPKMIXL_VOL_WIDTH 1 /* DAC2L_SPKMIXL_VOL */ 1323 #define WM8994_MIXINL_SPKMIXL_VOL 0x0020 /* MIXINL_SPKMIXL_VOL */ 1324 #define WM8994_MIXINL_SPKMIXL_VOL_MASK 0x0020 /* MIXINL_SPKMIXL_VOL */ 1325 #define WM8994_MIXINL_SPKMIXL_VOL_SHIFT 5 /* MIXINL_SPKMIXL_VOL */ 1326 #define WM8994_MIXINL_SPKMIXL_VOL_WIDTH 1 /* MIXINL_SPKMIXL_VOL */ 1327 #define WM8994_IN1LP_SPKMIXL_VOL 0x0010 /* IN1LP_SPKMIXL_VOL */ 1328 #define WM8994_IN1LP_SPKMIXL_VOL_MASK 0x0010 /* IN1LP_SPKMIXL_VOL */ 1329 #define WM8994_IN1LP_SPKMIXL_VOL_SHIFT 4 /* IN1LP_SPKMIXL_VOL */ 1330 #define WM8994_IN1LP_SPKMIXL_VOL_WIDTH 1 /* IN1LP_SPKMIXL_VOL */ 1331 #define WM8994_MIXOUTL_SPKMIXL_VOL 0x0008 /* MIXOUTL_SPKMIXL_VOL */ 1332 #define WM8994_MIXOUTL_SPKMIXL_VOL_MASK 0x0008 /* MIXOUTL_SPKMIXL_VOL */ 1333 #define WM8994_MIXOUTL_SPKMIXL_VOL_SHIFT 3 /* MIXOUTL_SPKMIXL_VOL */ 1334 #define WM8994_MIXOUTL_SPKMIXL_VOL_WIDTH 1 /* MIXOUTL_SPKMIXL_VOL */ 1335 #define WM8994_DAC1L_SPKMIXL_VOL 0x0004 /* DAC1L_SPKMIXL_VOL */ 1336 #define WM8994_DAC1L_SPKMIXL_VOL_MASK 0x0004 /* DAC1L_SPKMIXL_VOL */ 1337 #define WM8994_DAC1L_SPKMIXL_VOL_SHIFT 2 /* DAC1L_SPKMIXL_VOL */ 1338 #define WM8994_DAC1L_SPKMIXL_VOL_WIDTH 1 /* DAC1L_SPKMIXL_VOL */ 1339 #define WM8994_SPKMIXL_VOL_MASK 0x0003 /* SPKMIXL_VOL - [1:0] */ 1340 #define WM8994_SPKMIXL_VOL_SHIFT 0 /* SPKMIXL_VOL - [1:0] */ 1341 #define WM8994_SPKMIXL_VOL_WIDTH 2 /* SPKMIXL_VOL - [1:0] */ 1342 1343 /* 1344 * R35 (0x23) - SPKMIXR Attenuation 1345 */ 1346 #define WM8994_SPKOUT_CLASSAB 0x0100 /* SPKOUT_CLASSAB */ 1347 #define WM8994_SPKOUT_CLASSAB_MASK 0x0100 /* SPKOUT_CLASSAB */ 1348 #define WM8994_SPKOUT_CLASSAB_SHIFT 8 /* SPKOUT_CLASSAB */ 1349 #define WM8994_SPKOUT_CLASSAB_WIDTH 1 /* SPKOUT_CLASSAB */ 1350 #define WM8994_DAC2R_SPKMIXR_VOL 0x0040 /* DAC2R_SPKMIXR_VOL */ 1351 #define WM8994_DAC2R_SPKMIXR_VOL_MASK 0x0040 /* DAC2R_SPKMIXR_VOL */ 1352 #define WM8994_DAC2R_SPKMIXR_VOL_SHIFT 6 /* DAC2R_SPKMIXR_VOL */ 1353 #define WM8994_DAC2R_SPKMIXR_VOL_WIDTH 1 /* DAC2R_SPKMIXR_VOL */ 1354 #define WM8994_MIXINR_SPKMIXR_VOL 0x0020 /* MIXINR_SPKMIXR_VOL */ 1355 #define WM8994_MIXINR_SPKMIXR_VOL_MASK 0x0020 /* MIXINR_SPKMIXR_VOL */ 1356 #define WM8994_MIXINR_SPKMIXR_VOL_SHIFT 5 /* MIXINR_SPKMIXR_VOL */ 1357 #define WM8994_MIXINR_SPKMIXR_VOL_WIDTH 1 /* MIXINR_SPKMIXR_VOL */ 1358 #define WM8994_IN1RP_SPKMIXR_VOL 0x0010 /* IN1RP_SPKMIXR_VOL */ 1359 #define WM8994_IN1RP_SPKMIXR_VOL_MASK 0x0010 /* IN1RP_SPKMIXR_VOL */ 1360 #define WM8994_IN1RP_SPKMIXR_VOL_SHIFT 4 /* IN1RP_SPKMIXR_VOL */ 1361 #define WM8994_IN1RP_SPKMIXR_VOL_WIDTH 1 /* IN1RP_SPKMIXR_VOL */ 1362 #define WM8994_MIXOUTR_SPKMIXR_VOL 0x0008 /* MIXOUTR_SPKMIXR_VOL */ 1363 #define WM8994_MIXOUTR_SPKMIXR_VOL_MASK 0x0008 /* MIXOUTR_SPKMIXR_VOL */ 1364 #define WM8994_MIXOUTR_SPKMIXR_VOL_SHIFT 3 /* MIXOUTR_SPKMIXR_VOL */ 1365 #define WM8994_MIXOUTR_SPKMIXR_VOL_WIDTH 1 /* MIXOUTR_SPKMIXR_VOL */ 1366 #define WM8994_DAC1R_SPKMIXR_VOL 0x0004 /* DAC1R_SPKMIXR_VOL */ 1367 #define WM8994_DAC1R_SPKMIXR_VOL_MASK 0x0004 /* DAC1R_SPKMIXR_VOL */ 1368 #define WM8994_DAC1R_SPKMIXR_VOL_SHIFT 2 /* DAC1R_SPKMIXR_VOL */ 1369 #define WM8994_DAC1R_SPKMIXR_VOL_WIDTH 1 /* DAC1R_SPKMIXR_VOL */ 1370 #define WM8994_SPKMIXR_VOL_MASK 0x0003 /* SPKMIXR_VOL - [1:0] */ 1371 #define WM8994_SPKMIXR_VOL_SHIFT 0 /* SPKMIXR_VOL - [1:0] */ 1372 #define WM8994_SPKMIXR_VOL_WIDTH 2 /* SPKMIXR_VOL - [1:0] */ 1373 1374 /* 1375 * R36 (0x24) - SPKOUT Mixers 1376 */ 1377 #define WM8994_IN2LRP_TO_SPKOUTL 0x0020 /* IN2LRP_TO_SPKOUTL */ 1378 #define WM8994_IN2LRP_TO_SPKOUTL_MASK 0x0020 /* IN2LRP_TO_SPKOUTL */ 1379 #define WM8994_IN2LRP_TO_SPKOUTL_SHIFT 5 /* IN2LRP_TO_SPKOUTL */ 1380 #define WM8994_IN2LRP_TO_SPKOUTL_WIDTH 1 /* IN2LRP_TO_SPKOUTL */ 1381 #define WM8994_SPKMIXL_TO_SPKOUTL 0x0010 /* SPKMIXL_TO_SPKOUTL */ 1382 #define WM8994_SPKMIXL_TO_SPKOUTL_MASK 0x0010 /* SPKMIXL_TO_SPKOUTL */ 1383 #define WM8994_SPKMIXL_TO_SPKOUTL_SHIFT 4 /* SPKMIXL_TO_SPKOUTL */ 1384 #define WM8994_SPKMIXL_TO_SPKOUTL_WIDTH 1 /* SPKMIXL_TO_SPKOUTL */ 1385 #define WM8994_SPKMIXR_TO_SPKOUTL 0x0008 /* SPKMIXR_TO_SPKOUTL */ 1386 #define WM8994_SPKMIXR_TO_SPKOUTL_MASK 0x0008 /* SPKMIXR_TO_SPKOUTL */ 1387 #define WM8994_SPKMIXR_TO_SPKOUTL_SHIFT 3 /* SPKMIXR_TO_SPKOUTL */ 1388 #define WM8994_SPKMIXR_TO_SPKOUTL_WIDTH 1 /* SPKMIXR_TO_SPKOUTL */ 1389 #define WM8994_IN2LRP_TO_SPKOUTR 0x0004 /* IN2LRP_TO_SPKOUTR */ 1390 #define WM8994_IN2LRP_TO_SPKOUTR_MASK 0x0004 /* IN2LRP_TO_SPKOUTR */ 1391 #define WM8994_IN2LRP_TO_SPKOUTR_SHIFT 2 /* IN2LRP_TO_SPKOUTR */ 1392 #define WM8994_IN2LRP_TO_SPKOUTR_WIDTH 1 /* IN2LRP_TO_SPKOUTR */ 1393 #define WM8994_SPKMIXL_TO_SPKOUTR 0x0002 /* SPKMIXL_TO_SPKOUTR */ 1394 #define WM8994_SPKMIXL_TO_SPKOUTR_MASK 0x0002 /* SPKMIXL_TO_SPKOUTR */ 1395 #define WM8994_SPKMIXL_TO_SPKOUTR_SHIFT 1 /* SPKMIXL_TO_SPKOUTR */ 1396 #define WM8994_SPKMIXL_TO_SPKOUTR_WIDTH 1 /* SPKMIXL_TO_SPKOUTR */ 1397 #define WM8994_SPKMIXR_TO_SPKOUTR 0x0001 /* SPKMIXR_TO_SPKOUTR */ 1398 #define WM8994_SPKMIXR_TO_SPKOUTR_MASK 0x0001 /* SPKMIXR_TO_SPKOUTR */ 1399 #define WM8994_SPKMIXR_TO_SPKOUTR_SHIFT 0 /* SPKMIXR_TO_SPKOUTR */ 1400 #define WM8994_SPKMIXR_TO_SPKOUTR_WIDTH 1 /* SPKMIXR_TO_SPKOUTR */ 1401 1402 /* 1403 * R37 (0x25) - ClassD 1404 */ 1405 #define WM8994_SPKOUTL_BOOST_MASK 0x0038 /* SPKOUTL_BOOST - [5:3] */ 1406 #define WM8994_SPKOUTL_BOOST_SHIFT 3 /* SPKOUTL_BOOST - [5:3] */ 1407 #define WM8994_SPKOUTL_BOOST_WIDTH 3 /* SPKOUTL_BOOST - [5:3] */ 1408 #define WM8994_SPKOUTR_BOOST_MASK 0x0007 /* SPKOUTR_BOOST - [2:0] */ 1409 #define WM8994_SPKOUTR_BOOST_SHIFT 0 /* SPKOUTR_BOOST - [2:0] */ 1410 #define WM8994_SPKOUTR_BOOST_WIDTH 3 /* SPKOUTR_BOOST - [2:0] */ 1411 1412 /* 1413 * R38 (0x26) - Speaker Volume Left 1414 */ 1415 #define WM8994_SPKOUT_VU 0x0100 /* SPKOUT_VU */ 1416 #define WM8994_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */ 1417 #define WM8994_SPKOUT_VU_SHIFT 8 /* SPKOUT_VU */ 1418 #define WM8994_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */ 1419 #define WM8994_SPKOUTL_ZC 0x0080 /* SPKOUTL_ZC */ 1420 #define WM8994_SPKOUTL_ZC_MASK 0x0080 /* SPKOUTL_ZC */ 1421 #define WM8994_SPKOUTL_ZC_SHIFT 7 /* SPKOUTL_ZC */ 1422 #define WM8994_SPKOUTL_ZC_WIDTH 1 /* SPKOUTL_ZC */ 1423 #define WM8994_SPKOUTL_MUTE_N 0x0040 /* SPKOUTL_MUTE_N */ 1424 #define WM8994_SPKOUTL_MUTE_N_MASK 0x0040 /* SPKOUTL_MUTE_N */ 1425 #define WM8994_SPKOUTL_MUTE_N_SHIFT 6 /* SPKOUTL_MUTE_N */ 1426 #define WM8994_SPKOUTL_MUTE_N_WIDTH 1 /* SPKOUTL_MUTE_N */ 1427 #define WM8994_SPKOUTL_VOL_MASK 0x003F /* SPKOUTL_VOL - [5:0] */ 1428 #define WM8994_SPKOUTL_VOL_SHIFT 0 /* SPKOUTL_VOL - [5:0] */ 1429 #define WM8994_SPKOUTL_VOL_WIDTH 6 /* SPKOUTL_VOL - [5:0] */ 1430 1431 /* 1432 * R39 (0x27) - Speaker Volume Right 1433 */ 1434 #define WM8994_SPKOUT_VU 0x0100 /* SPKOUT_VU */ 1435 #define WM8994_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */ 1436 #define WM8994_SPKOUT_VU_SHIFT 8 /* SPKOUT_VU */ 1437 #define WM8994_SPKOUT_VU_WIDTH 1 /* SPKOUT_VU */ 1438 #define WM8994_SPKOUTR_ZC 0x0080 /* SPKOUTR_ZC */ 1439 #define WM8994_SPKOUTR_ZC_MASK 0x0080 /* SPKOUTR_ZC */ 1440 #define WM8994_SPKOUTR_ZC_SHIFT 7 /* SPKOUTR_ZC */ 1441 #define WM8994_SPKOUTR_ZC_WIDTH 1 /* SPKOUTR_ZC */ 1442 #define WM8994_SPKOUTR_MUTE_N 0x0040 /* SPKOUTR_MUTE_N */ 1443 #define WM8994_SPKOUTR_MUTE_N_MASK 0x0040 /* SPKOUTR_MUTE_N */ 1444 #define WM8994_SPKOUTR_MUTE_N_SHIFT 6 /* SPKOUTR_MUTE_N */ 1445 #define WM8994_SPKOUTR_MUTE_N_WIDTH 1 /* SPKOUTR_MUTE_N */ 1446 #define WM8994_SPKOUTR_VOL_MASK 0x003F /* SPKOUTR_VOL - [5:0] */ 1447 #define WM8994_SPKOUTR_VOL_SHIFT 0 /* SPKOUTR_VOL - [5:0] */ 1448 #define WM8994_SPKOUTR_VOL_WIDTH 6 /* SPKOUTR_VOL - [5:0] */ 1449 1450 /* 1451 * R40 (0x28) - Input Mixer (2) 1452 */ 1453 #define WM8994_IN2LP_TO_IN2L 0x0080 /* IN2LP_TO_IN2L */ 1454 #define WM8994_IN2LP_TO_IN2L_MASK 0x0080 /* IN2LP_TO_IN2L */ 1455 #define WM8994_IN2LP_TO_IN2L_SHIFT 7 /* IN2LP_TO_IN2L */ 1456 #define WM8994_IN2LP_TO_IN2L_WIDTH 1 /* IN2LP_TO_IN2L */ 1457 #define WM8994_IN2LN_TO_IN2L 0x0040 /* IN2LN_TO_IN2L */ 1458 #define WM8994_IN2LN_TO_IN2L_MASK 0x0040 /* IN2LN_TO_IN2L */ 1459 #define WM8994_IN2LN_TO_IN2L_SHIFT 6 /* IN2LN_TO_IN2L */ 1460 #define WM8994_IN2LN_TO_IN2L_WIDTH 1 /* IN2LN_TO_IN2L */ 1461 #define WM8994_IN1LP_TO_IN1L 0x0020 /* IN1LP_TO_IN1L */ 1462 #define WM8994_IN1LP_TO_IN1L_MASK 0x0020 /* IN1LP_TO_IN1L */ 1463 #define WM8994_IN1LP_TO_IN1L_SHIFT 5 /* IN1LP_TO_IN1L */ 1464 #define WM8994_IN1LP_TO_IN1L_WIDTH 1 /* IN1LP_TO_IN1L */ 1465 #define WM8994_IN1LN_TO_IN1L 0x0010 /* IN1LN_TO_IN1L */ 1466 #define WM8994_IN1LN_TO_IN1L_MASK 0x0010 /* IN1LN_TO_IN1L */ 1467 #define WM8994_IN1LN_TO_IN1L_SHIFT 4 /* IN1LN_TO_IN1L */ 1468 #define WM8994_IN1LN_TO_IN1L_WIDTH 1 /* IN1LN_TO_IN1L */ 1469 #define WM8994_IN2RP_TO_IN2R 0x0008 /* IN2RP_TO_IN2R */ 1470 #define WM8994_IN2RP_TO_IN2R_MASK 0x0008 /* IN2RP_TO_IN2R */ 1471 #define WM8994_IN2RP_TO_IN2R_SHIFT 3 /* IN2RP_TO_IN2R */ 1472 #define WM8994_IN2RP_TO_IN2R_WIDTH 1 /* IN2RP_TO_IN2R */ 1473 #define WM8994_IN2RN_TO_IN2R 0x0004 /* IN2RN_TO_IN2R */ 1474 #define WM8994_IN2RN_TO_IN2R_MASK 0x0004 /* IN2RN_TO_IN2R */ 1475 #define WM8994_IN2RN_TO_IN2R_SHIFT 2 /* IN2RN_TO_IN2R */ 1476 #define WM8994_IN2RN_TO_IN2R_WIDTH 1 /* IN2RN_TO_IN2R */ 1477 #define WM8994_IN1RP_TO_IN1R 0x0002 /* IN1RP_TO_IN1R */ 1478 #define WM8994_IN1RP_TO_IN1R_MASK 0x0002 /* IN1RP_TO_IN1R */ 1479 #define WM8994_IN1RP_TO_IN1R_SHIFT 1 /* IN1RP_TO_IN1R */ 1480 #define WM8994_IN1RP_TO_IN1R_WIDTH 1 /* IN1RP_TO_IN1R */ 1481 #define WM8994_IN1RN_TO_IN1R 0x0001 /* IN1RN_TO_IN1R */ 1482 #define WM8994_IN1RN_TO_IN1R_MASK 0x0001 /* IN1RN_TO_IN1R */ 1483 #define WM8994_IN1RN_TO_IN1R_SHIFT 0 /* IN1RN_TO_IN1R */ 1484 #define WM8994_IN1RN_TO_IN1R_WIDTH 1 /* IN1RN_TO_IN1R */ 1485 1486 /* 1487 * R41 (0x29) - Input Mixer (3) 1488 */ 1489 #define WM8994_IN2L_TO_MIXINL 0x0100 /* IN2L_TO_MIXINL */ 1490 #define WM8994_IN2L_TO_MIXINL_MASK 0x0100 /* IN2L_TO_MIXINL */ 1491 #define WM8994_IN2L_TO_MIXINL_SHIFT 8 /* IN2L_TO_MIXINL */ 1492 #define WM8994_IN2L_TO_MIXINL_WIDTH 1 /* IN2L_TO_MIXINL */ 1493 #define WM8994_IN2L_MIXINL_VOL 0x0080 /* IN2L_MIXINL_VOL */ 1494 #define WM8994_IN2L_MIXINL_VOL_MASK 0x0080 /* IN2L_MIXINL_VOL */ 1495 #define WM8994_IN2L_MIXINL_VOL_SHIFT 7 /* IN2L_MIXINL_VOL */ 1496 #define WM8994_IN2L_MIXINL_VOL_WIDTH 1 /* IN2L_MIXINL_VOL */ 1497 #define WM8994_IN1L_TO_MIXINL 0x0020 /* IN1L_TO_MIXINL */ 1498 #define WM8994_IN1L_TO_MIXINL_MASK 0x0020 /* IN1L_TO_MIXINL */ 1499 #define WM8994_IN1L_TO_MIXINL_SHIFT 5 /* IN1L_TO_MIXINL */ 1500 #define WM8994_IN1L_TO_MIXINL_WIDTH 1 /* IN1L_TO_MIXINL */ 1501 #define WM8994_IN1L_MIXINL_VOL 0x0010 /* IN1L_MIXINL_VOL */ 1502 #define WM8994_IN1L_MIXINL_VOL_MASK 0x0010 /* IN1L_MIXINL_VOL */ 1503 #define WM8994_IN1L_MIXINL_VOL_SHIFT 4 /* IN1L_MIXINL_VOL */ 1504 #define WM8994_IN1L_MIXINL_VOL_WIDTH 1 /* IN1L_MIXINL_VOL */ 1505 #define WM8994_MIXOUTL_MIXINL_VOL_MASK 0x0007 /* MIXOUTL_MIXINL_VOL - [2:0] */ 1506 #define WM8994_MIXOUTL_MIXINL_VOL_SHIFT 0 /* MIXOUTL_MIXINL_VOL - [2:0] */ 1507 #define WM8994_MIXOUTL_MIXINL_VOL_WIDTH 3 /* MIXOUTL_MIXINL_VOL - [2:0] */ 1508 1509 /* 1510 * R42 (0x2A) - Input Mixer (4) 1511 */ 1512 #define WM8994_IN2R_TO_MIXINR 0x0100 /* IN2R_TO_MIXINR */ 1513 #define WM8994_IN2R_TO_MIXINR_MASK 0x0100 /* IN2R_TO_MIXINR */ 1514 #define WM8994_IN2R_TO_MIXINR_SHIFT 8 /* IN2R_TO_MIXINR */ 1515 #define WM8994_IN2R_TO_MIXINR_WIDTH 1 /* IN2R_TO_MIXINR */ 1516 #define WM8994_IN2R_MIXINR_VOL 0x0080 /* IN2R_MIXINR_VOL */ 1517 #define WM8994_IN2R_MIXINR_VOL_MASK 0x0080 /* IN2R_MIXINR_VOL */ 1518 #define WM8994_IN2R_MIXINR_VOL_SHIFT 7 /* IN2R_MIXINR_VOL */ 1519 #define WM8994_IN2R_MIXINR_VOL_WIDTH 1 /* IN2R_MIXINR_VOL */ 1520 #define WM8994_IN1R_TO_MIXINR 0x0020 /* IN1R_TO_MIXINR */ 1521 #define WM8994_IN1R_TO_MIXINR_MASK 0x0020 /* IN1R_TO_MIXINR */ 1522 #define WM8994_IN1R_TO_MIXINR_SHIFT 5 /* IN1R_TO_MIXINR */ 1523 #define WM8994_IN1R_TO_MIXINR_WIDTH 1 /* IN1R_TO_MIXINR */ 1524 #define WM8994_IN1R_MIXINR_VOL 0x0010 /* IN1R_MIXINR_VOL */ 1525 #define WM8994_IN1R_MIXINR_VOL_MASK 0x0010 /* IN1R_MIXINR_VOL */ 1526 #define WM8994_IN1R_MIXINR_VOL_SHIFT 4 /* IN1R_MIXINR_VOL */ 1527 #define WM8994_IN1R_MIXINR_VOL_WIDTH 1 /* IN1R_MIXINR_VOL */ 1528 #define WM8994_MIXOUTR_MIXINR_VOL_MASK 0x0007 /* MIXOUTR_MIXINR_VOL - [2:0] */ 1529 #define WM8994_MIXOUTR_MIXINR_VOL_SHIFT 0 /* MIXOUTR_MIXINR_VOL - [2:0] */ 1530 #define WM8994_MIXOUTR_MIXINR_VOL_WIDTH 3 /* MIXOUTR_MIXINR_VOL - [2:0] */ 1531 1532 /* 1533 * R43 (0x2B) - Input Mixer (5) 1534 */ 1535 #define WM8994_IN1LP_MIXINL_VOL_MASK 0x01C0 /* IN1LP_MIXINL_VOL - [8:6] */ 1536 #define WM8994_IN1LP_MIXINL_VOL_SHIFT 6 /* IN1LP_MIXINL_VOL - [8:6] */ 1537 #define WM8994_IN1LP_MIXINL_VOL_WIDTH 3 /* IN1LP_MIXINL_VOL - [8:6] */ 1538 #define WM8994_IN2LRP_MIXINL_VOL_MASK 0x0007 /* IN2LRP_MIXINL_VOL - [2:0] */ 1539 #define WM8994_IN2LRP_MIXINL_VOL_SHIFT 0 /* IN2LRP_MIXINL_VOL - [2:0] */ 1540 #define WM8994_IN2LRP_MIXINL_VOL_WIDTH 3 /* IN2LRP_MIXINL_VOL - [2:0] */ 1541 1542 /* 1543 * R44 (0x2C) - Input Mixer (6) 1544 */ 1545 #define WM8994_IN1RP_MIXINR_VOL_MASK 0x01C0 /* IN1RP_MIXINR_VOL - [8:6] */ 1546 #define WM8994_IN1RP_MIXINR_VOL_SHIFT 6 /* IN1RP_MIXINR_VOL - [8:6] */ 1547 #define WM8994_IN1RP_MIXINR_VOL_WIDTH 3 /* IN1RP_MIXINR_VOL - [8:6] */ 1548 #define WM8994_IN2LRP_MIXINR_VOL_MASK 0x0007 /* IN2LRP_MIXINR_VOL - [2:0] */ 1549 #define WM8994_IN2LRP_MIXINR_VOL_SHIFT 0 /* IN2LRP_MIXINR_VOL - [2:0] */ 1550 #define WM8994_IN2LRP_MIXINR_VOL_WIDTH 3 /* IN2LRP_MIXINR_VOL - [2:0] */ 1551 1552 /* 1553 * R45 (0x2D) - Output Mixer (1) 1554 */ 1555 #define WM8994_DAC1L_TO_HPOUT1L 0x0100 /* DAC1L_TO_HPOUT1L */ 1556 #define WM8994_DAC1L_TO_HPOUT1L_MASK 0x0100 /* DAC1L_TO_HPOUT1L */ 1557 #define WM8994_DAC1L_TO_HPOUT1L_SHIFT 8 /* DAC1L_TO_HPOUT1L */ 1558 #define WM8994_DAC1L_TO_HPOUT1L_WIDTH 1 /* DAC1L_TO_HPOUT1L */ 1559 #define WM8994_MIXINR_TO_MIXOUTL 0x0080 /* MIXINR_TO_MIXOUTL */ 1560 #define WM8994_MIXINR_TO_MIXOUTL_MASK 0x0080 /* MIXINR_TO_MIXOUTL */ 1561 #define WM8994_MIXINR_TO_MIXOUTL_SHIFT 7 /* MIXINR_TO_MIXOUTL */ 1562 #define WM8994_MIXINR_TO_MIXOUTL_WIDTH 1 /* MIXINR_TO_MIXOUTL */ 1563 #define WM8994_MIXINL_TO_MIXOUTL 0x0040 /* MIXINL_TO_MIXOUTL */ 1564 #define WM8994_MIXINL_TO_MIXOUTL_MASK 0x0040 /* MIXINL_TO_MIXOUTL */ 1565 #define WM8994_MIXINL_TO_MIXOUTL_SHIFT 6 /* MIXINL_TO_MIXOUTL */ 1566 #define WM8994_MIXINL_TO_MIXOUTL_WIDTH 1 /* MIXINL_TO_MIXOUTL */ 1567 #define WM8994_IN2RN_TO_MIXOUTL 0x0020 /* IN2RN_TO_MIXOUTL */ 1568 #define WM8994_IN2RN_TO_MIXOUTL_MASK 0x0020 /* IN2RN_TO_MIXOUTL */ 1569 #define WM8994_IN2RN_TO_MIXOUTL_SHIFT 5 /* IN2RN_TO_MIXOUTL */ 1570 #define WM8994_IN2RN_TO_MIXOUTL_WIDTH 1 /* IN2RN_TO_MIXOUTL */ 1571 #define WM8994_IN2LN_TO_MIXOUTL 0x0010 /* IN2LN_TO_MIXOUTL */ 1572 #define WM8994_IN2LN_TO_MIXOUTL_MASK 0x0010 /* IN2LN_TO_MIXOUTL */ 1573 #define WM8994_IN2LN_TO_MIXOUTL_SHIFT 4 /* IN2LN_TO_MIXOUTL */ 1574 #define WM8994_IN2LN_TO_MIXOUTL_WIDTH 1 /* IN2LN_TO_MIXOUTL */ 1575 #define WM8994_IN1R_TO_MIXOUTL 0x0008 /* IN1R_TO_MIXOUTL */ 1576 #define WM8994_IN1R_TO_MIXOUTL_MASK 0x0008 /* IN1R_TO_MIXOUTL */ 1577 #define WM8994_IN1R_TO_MIXOUTL_SHIFT 3 /* IN1R_TO_MIXOUTL */ 1578 #define WM8994_IN1R_TO_MIXOUTL_WIDTH 1 /* IN1R_TO_MIXOUTL */ 1579 #define WM8994_IN1L_TO_MIXOUTL 0x0004 /* IN1L_TO_MIXOUTL */ 1580 #define WM8994_IN1L_TO_MIXOUTL_MASK 0x0004 /* IN1L_TO_MIXOUTL */ 1581 #define WM8994_IN1L_TO_MIXOUTL_SHIFT 2 /* IN1L_TO_MIXOUTL */ 1582 #define WM8994_IN1L_TO_MIXOUTL_WIDTH 1 /* IN1L_TO_MIXOUTL */ 1583 #define WM8994_IN2LP_TO_MIXOUTL 0x0002 /* IN2LP_TO_MIXOUTL */ 1584 #define WM8994_IN2LP_TO_MIXOUTL_MASK 0x0002 /* IN2LP_TO_MIXOUTL */ 1585 #define WM8994_IN2LP_TO_MIXOUTL_SHIFT 1 /* IN2LP_TO_MIXOUTL */ 1586 #define WM8994_IN2LP_TO_MIXOUTL_WIDTH 1 /* IN2LP_TO_MIXOUTL */ 1587 #define WM8994_DAC1L_TO_MIXOUTL 0x0001 /* DAC1L_TO_MIXOUTL */ 1588 #define WM8994_DAC1L_TO_MIXOUTL_MASK 0x0001 /* DAC1L_TO_MIXOUTL */ 1589 #define WM8994_DAC1L_TO_MIXOUTL_SHIFT 0 /* DAC1L_TO_MIXOUTL */ 1590 #define WM8994_DAC1L_TO_MIXOUTL_WIDTH 1 /* DAC1L_TO_MIXOUTL */ 1591 1592 /* 1593 * R46 (0x2E) - Output Mixer (2) 1594 */ 1595 #define WM8994_DAC1R_TO_HPOUT1R 0x0100 /* DAC1R_TO_HPOUT1R */ 1596 #define WM8994_DAC1R_TO_HPOUT1R_MASK 0x0100 /* DAC1R_TO_HPOUT1R */ 1597 #define WM8994_DAC1R_TO_HPOUT1R_SHIFT 8 /* DAC1R_TO_HPOUT1R */ 1598 #define WM8994_DAC1R_TO_HPOUT1R_WIDTH 1 /* DAC1R_TO_HPOUT1R */ 1599 #define WM8994_MIXINL_TO_MIXOUTR 0x0080 /* MIXINL_TO_MIXOUTR */ 1600 #define WM8994_MIXINL_TO_MIXOUTR_MASK 0x0080 /* MIXINL_TO_MIXOUTR */ 1601 #define WM8994_MIXINL_TO_MIXOUTR_SHIFT 7 /* MIXINL_TO_MIXOUTR */ 1602 #define WM8994_MIXINL_TO_MIXOUTR_WIDTH 1 /* MIXINL_TO_MIXOUTR */ 1603 #define WM8994_MIXINR_TO_MIXOUTR 0x0040 /* MIXINR_TO_MIXOUTR */ 1604 #define WM8994_MIXINR_TO_MIXOUTR_MASK 0x0040 /* MIXINR_TO_MIXOUTR */ 1605 #define WM8994_MIXINR_TO_MIXOUTR_SHIFT 6 /* MIXINR_TO_MIXOUTR */ 1606 #define WM8994_MIXINR_TO_MIXOUTR_WIDTH 1 /* MIXINR_TO_MIXOUTR */ 1607 #define WM8994_IN2LN_TO_MIXOUTR 0x0020 /* IN2LN_TO_MIXOUTR */ 1608 #define WM8994_IN2LN_TO_MIXOUTR_MASK 0x0020 /* IN2LN_TO_MIXOUTR */ 1609 #define WM8994_IN2LN_TO_MIXOUTR_SHIFT 5 /* IN2LN_TO_MIXOUTR */ 1610 #define WM8994_IN2LN_TO_MIXOUTR_WIDTH 1 /* IN2LN_TO_MIXOUTR */ 1611 #define WM8994_IN2RN_TO_MIXOUTR 0x0010 /* IN2RN_TO_MIXOUTR */ 1612 #define WM8994_IN2RN_TO_MIXOUTR_MASK 0x0010 /* IN2RN_TO_MIXOUTR */ 1613 #define WM8994_IN2RN_TO_MIXOUTR_SHIFT 4 /* IN2RN_TO_MIXOUTR */ 1614 #define WM8994_IN2RN_TO_MIXOUTR_WIDTH 1 /* IN2RN_TO_MIXOUTR */ 1615 #define WM8994_IN1L_TO_MIXOUTR 0x0008 /* IN1L_TO_MIXOUTR */ 1616 #define WM8994_IN1L_TO_MIXOUTR_MASK 0x0008 /* IN1L_TO_MIXOUTR */ 1617 #define WM8994_IN1L_TO_MIXOUTR_SHIFT 3 /* IN1L_TO_MIXOUTR */ 1618 #define WM8994_IN1L_TO_MIXOUTR_WIDTH 1 /* IN1L_TO_MIXOUTR */ 1619 #define WM8994_IN1R_TO_MIXOUTR 0x0004 /* IN1R_TO_MIXOUTR */ 1620 #define WM8994_IN1R_TO_MIXOUTR_MASK 0x0004 /* IN1R_TO_MIXOUTR */ 1621 #define WM8994_IN1R_TO_MIXOUTR_SHIFT 2 /* IN1R_TO_MIXOUTR */ 1622 #define WM8994_IN1R_TO_MIXOUTR_WIDTH 1 /* IN1R_TO_MIXOUTR */ 1623 #define WM8994_IN2RP_TO_MIXOUTR 0x0002 /* IN2RP_TO_MIXOUTR */ 1624 #define WM8994_IN2RP_TO_MIXOUTR_MASK 0x0002 /* IN2RP_TO_MIXOUTR */ 1625 #define WM8994_IN2RP_TO_MIXOUTR_SHIFT 1 /* IN2RP_TO_MIXOUTR */ 1626 #define WM8994_IN2RP_TO_MIXOUTR_WIDTH 1 /* IN2RP_TO_MIXOUTR */ 1627 #define WM8994_DAC1R_TO_MIXOUTR 0x0001 /* DAC1R_TO_MIXOUTR */ 1628 #define WM8994_DAC1R_TO_MIXOUTR_MASK 0x0001 /* DAC1R_TO_MIXOUTR */ 1629 #define WM8994_DAC1R_TO_MIXOUTR_SHIFT 0 /* DAC1R_TO_MIXOUTR */ 1630 #define WM8994_DAC1R_TO_MIXOUTR_WIDTH 1 /* DAC1R_TO_MIXOUTR */ 1631 1632 /* 1633 * R47 (0x2F) - Output Mixer (3) 1634 */ 1635 #define WM8994_IN2LP_MIXOUTL_VOL_MASK 0x0E00 /* IN2LP_MIXOUTL_VOL - [11:9] */ 1636 #define WM8994_IN2LP_MIXOUTL_VOL_SHIFT 9 /* IN2LP_MIXOUTL_VOL - [11:9] */ 1637 #define WM8994_IN2LP_MIXOUTL_VOL_WIDTH 3 /* IN2LP_MIXOUTL_VOL - [11:9] */ 1638 #define WM8994_IN2LN_MIXOUTL_VOL_MASK 0x01C0 /* IN2LN_MIXOUTL_VOL - [8:6] */ 1639 #define WM8994_IN2LN_MIXOUTL_VOL_SHIFT 6 /* IN2LN_MIXOUTL_VOL - [8:6] */ 1640 #define WM8994_IN2LN_MIXOUTL_VOL_WIDTH 3 /* IN2LN_MIXOUTL_VOL - [8:6] */ 1641 #define WM8994_IN1R_MIXOUTL_VOL_MASK 0x0038 /* IN1R_MIXOUTL_VOL - [5:3] */ 1642 #define WM8994_IN1R_MIXOUTL_VOL_SHIFT 3 /* IN1R_MIXOUTL_VOL - [5:3] */ 1643 #define WM8994_IN1R_MIXOUTL_VOL_WIDTH 3 /* IN1R_MIXOUTL_VOL - [5:3] */ 1644 #define WM8994_IN1L_MIXOUTL_VOL_MASK 0x0007 /* IN1L_MIXOUTL_VOL - [2:0] */ 1645 #define WM8994_IN1L_MIXOUTL_VOL_SHIFT 0 /* IN1L_MIXOUTL_VOL - [2:0] */ 1646 #define WM8994_IN1L_MIXOUTL_VOL_WIDTH 3 /* IN1L_MIXOUTL_VOL - [2:0] */ 1647 1648 /* 1649 * R48 (0x30) - Output Mixer (4) 1650 */ 1651 #define WM8994_IN2RP_MIXOUTR_VOL_MASK 0x0E00 /* IN2RP_MIXOUTR_VOL - [11:9] */ 1652 #define WM8994_IN2RP_MIXOUTR_VOL_SHIFT 9 /* IN2RP_MIXOUTR_VOL - [11:9] */ 1653 #define WM8994_IN2RP_MIXOUTR_VOL_WIDTH 3 /* IN2RP_MIXOUTR_VOL - [11:9] */ 1654 #define WM8994_IN2RN_MIXOUTR_VOL_MASK 0x01C0 /* IN2RN_MIXOUTR_VOL - [8:6] */ 1655 #define WM8994_IN2RN_MIXOUTR_VOL_SHIFT 6 /* IN2RN_MIXOUTR_VOL - [8:6] */ 1656 #define WM8994_IN2RN_MIXOUTR_VOL_WIDTH 3 /* IN2RN_MIXOUTR_VOL - [8:6] */ 1657 #define WM8994_IN1L_MIXOUTR_VOL_MASK 0x0038 /* IN1L_MIXOUTR_VOL - [5:3] */ 1658 #define WM8994_IN1L_MIXOUTR_VOL_SHIFT 3 /* IN1L_MIXOUTR_VOL - [5:3] */ 1659 #define WM8994_IN1L_MIXOUTR_VOL_WIDTH 3 /* IN1L_MIXOUTR_VOL - [5:3] */ 1660 #define WM8994_IN1R_MIXOUTR_VOL_MASK 0x0007 /* IN1R_MIXOUTR_VOL - [2:0] */ 1661 #define WM8994_IN1R_MIXOUTR_VOL_SHIFT 0 /* IN1R_MIXOUTR_VOL - [2:0] */ 1662 #define WM8994_IN1R_MIXOUTR_VOL_WIDTH 3 /* IN1R_MIXOUTR_VOL - [2:0] */ 1663 1664 /* 1665 * R49 (0x31) - Output Mixer (5) 1666 */ 1667 #define WM8994_DAC1L_MIXOUTL_VOL_MASK 0x0E00 /* DAC1L_MIXOUTL_VOL - [11:9] */ 1668 #define WM8994_DAC1L_MIXOUTL_VOL_SHIFT 9 /* DAC1L_MIXOUTL_VOL - [11:9] */ 1669 #define WM8994_DAC1L_MIXOUTL_VOL_WIDTH 3 /* DAC1L_MIXOUTL_VOL - [11:9] */ 1670 #define WM8994_IN2RN_MIXOUTL_VOL_MASK 0x01C0 /* IN2RN_MIXOUTL_VOL - [8:6] */ 1671 #define WM8994_IN2RN_MIXOUTL_VOL_SHIFT 6 /* IN2RN_MIXOUTL_VOL - [8:6] */ 1672 #define WM8994_IN2RN_MIXOUTL_VOL_WIDTH 3 /* IN2RN_MIXOUTL_VOL - [8:6] */ 1673 #define WM8994_MIXINR_MIXOUTL_VOL_MASK 0x0038 /* MIXINR_MIXOUTL_VOL - [5:3] */ 1674 #define WM8994_MIXINR_MIXOUTL_VOL_SHIFT 3 /* MIXINR_MIXOUTL_VOL - [5:3] */ 1675 #define WM8994_MIXINR_MIXOUTL_VOL_WIDTH 3 /* MIXINR_MIXOUTL_VOL - [5:3] */ 1676 #define WM8994_MIXINL_MIXOUTL_VOL_MASK 0x0007 /* MIXINL_MIXOUTL_VOL - [2:0] */ 1677 #define WM8994_MIXINL_MIXOUTL_VOL_SHIFT 0 /* MIXINL_MIXOUTL_VOL - [2:0] */ 1678 #define WM8994_MIXINL_MIXOUTL_VOL_WIDTH 3 /* MIXINL_MIXOUTL_VOL - [2:0] */ 1679 1680 /* 1681 * R50 (0x32) - Output Mixer (6) 1682 */ 1683 #define WM8994_DAC1R_MIXOUTR_VOL_MASK 0x0E00 /* DAC1R_MIXOUTR_VOL - [11:9] */ 1684 #define WM8994_DAC1R_MIXOUTR_VOL_SHIFT 9 /* DAC1R_MIXOUTR_VOL - [11:9] */ 1685 #define WM8994_DAC1R_MIXOUTR_VOL_WIDTH 3 /* DAC1R_MIXOUTR_VOL - [11:9] */ 1686 #define WM8994_IN2LN_MIXOUTR_VOL_MASK 0x01C0 /* IN2LN_MIXOUTR_VOL - [8:6] */ 1687 #define WM8994_IN2LN_MIXOUTR_VOL_SHIFT 6 /* IN2LN_MIXOUTR_VOL - [8:6] */ 1688 #define WM8994_IN2LN_MIXOUTR_VOL_WIDTH 3 /* IN2LN_MIXOUTR_VOL - [8:6] */ 1689 #define WM8994_MIXINL_MIXOUTR_VOL_MASK 0x0038 /* MIXINL_MIXOUTR_VOL - [5:3] */ 1690 #define WM8994_MIXINL_MIXOUTR_VOL_SHIFT 3 /* MIXINL_MIXOUTR_VOL - [5:3] */ 1691 #define WM8994_MIXINL_MIXOUTR_VOL_WIDTH 3 /* MIXINL_MIXOUTR_VOL - [5:3] */ 1692 #define WM8994_MIXINR_MIXOUTR_VOL_MASK 0x0007 /* MIXINR_MIXOUTR_VOL - [2:0] */ 1693 #define WM8994_MIXINR_MIXOUTR_VOL_SHIFT 0 /* MIXINR_MIXOUTR_VOL - [2:0] */ 1694 #define WM8994_MIXINR_MIXOUTR_VOL_WIDTH 3 /* MIXINR_MIXOUTR_VOL - [2:0] */ 1695 1696 /* 1697 * R51 (0x33) - HPOUT2 Mixer 1698 */ 1699 #define WM8994_IN2LRP_TO_HPOUT2 0x0020 /* IN2LRP_TO_HPOUT2 */ 1700 #define WM8994_IN2LRP_TO_HPOUT2_MASK 0x0020 /* IN2LRP_TO_HPOUT2 */ 1701 #define WM8994_IN2LRP_TO_HPOUT2_SHIFT 5 /* IN2LRP_TO_HPOUT2 */ 1702 #define WM8994_IN2LRP_TO_HPOUT2_WIDTH 1 /* IN2LRP_TO_HPOUT2 */ 1703 #define WM8994_MIXOUTLVOL_TO_HPOUT2 0x0010 /* MIXOUTLVOL_TO_HPOUT2 */ 1704 #define WM8994_MIXOUTLVOL_TO_HPOUT2_MASK 0x0010 /* MIXOUTLVOL_TO_HPOUT2 */ 1705 #define WM8994_MIXOUTLVOL_TO_HPOUT2_SHIFT 4 /* MIXOUTLVOL_TO_HPOUT2 */ 1706 #define WM8994_MIXOUTLVOL_TO_HPOUT2_WIDTH 1 /* MIXOUTLVOL_TO_HPOUT2 */ 1707 #define WM8994_MIXOUTRVOL_TO_HPOUT2 0x0008 /* MIXOUTRVOL_TO_HPOUT2 */ 1708 #define WM8994_MIXOUTRVOL_TO_HPOUT2_MASK 0x0008 /* MIXOUTRVOL_TO_HPOUT2 */ 1709 #define WM8994_MIXOUTRVOL_TO_HPOUT2_SHIFT 3 /* MIXOUTRVOL_TO_HPOUT2 */ 1710 #define WM8994_MIXOUTRVOL_TO_HPOUT2_WIDTH 1 /* MIXOUTRVOL_TO_HPOUT2 */ 1711 1712 /* 1713 * R52 (0x34) - Line Mixer (1) 1714 */ 1715 #define WM8994_MIXOUTL_TO_LINEOUT1N 0x0040 /* MIXOUTL_TO_LINEOUT1N */ 1716 #define WM8994_MIXOUTL_TO_LINEOUT1N_MASK 0x0040 /* MIXOUTL_TO_LINEOUT1N */ 1717 #define WM8994_MIXOUTL_TO_LINEOUT1N_SHIFT 6 /* MIXOUTL_TO_LINEOUT1N */ 1718 #define WM8994_MIXOUTL_TO_LINEOUT1N_WIDTH 1 /* MIXOUTL_TO_LINEOUT1N */ 1719 #define WM8994_MIXOUTR_TO_LINEOUT1N 0x0020 /* MIXOUTR_TO_LINEOUT1N */ 1720 #define WM8994_MIXOUTR_TO_LINEOUT1N_MASK 0x0020 /* MIXOUTR_TO_LINEOUT1N */ 1721 #define WM8994_MIXOUTR_TO_LINEOUT1N_SHIFT 5 /* MIXOUTR_TO_LINEOUT1N */ 1722 #define WM8994_MIXOUTR_TO_LINEOUT1N_WIDTH 1 /* MIXOUTR_TO_LINEOUT1N */ 1723 #define WM8994_LINEOUT1_MODE 0x0010 /* LINEOUT1_MODE */ 1724 #define WM8994_LINEOUT1_MODE_MASK 0x0010 /* LINEOUT1_MODE */ 1725 #define WM8994_LINEOUT1_MODE_SHIFT 4 /* LINEOUT1_MODE */ 1726 #define WM8994_LINEOUT1_MODE_WIDTH 1 /* LINEOUT1_MODE */ 1727 #define WM8994_IN1R_TO_LINEOUT1P 0x0004 /* IN1R_TO_LINEOUT1P */ 1728 #define WM8994_IN1R_TO_LINEOUT1P_MASK 0x0004 /* IN1R_TO_LINEOUT1P */ 1729 #define WM8994_IN1R_TO_LINEOUT1P_SHIFT 2 /* IN1R_TO_LINEOUT1P */ 1730 #define WM8994_IN1R_TO_LINEOUT1P_WIDTH 1 /* IN1R_TO_LINEOUT1P */ 1731 #define WM8994_IN1L_TO_LINEOUT1P 0x0002 /* IN1L_TO_LINEOUT1P */ 1732 #define WM8994_IN1L_TO_LINEOUT1P_MASK 0x0002 /* IN1L_TO_LINEOUT1P */ 1733 #define WM8994_IN1L_TO_LINEOUT1P_SHIFT 1 /* IN1L_TO_LINEOUT1P */ 1734 #define WM8994_IN1L_TO_LINEOUT1P_WIDTH 1 /* IN1L_TO_LINEOUT1P */ 1735 #define WM8994_MIXOUTL_TO_LINEOUT1P 0x0001 /* MIXOUTL_TO_LINEOUT1P */ 1736 #define WM8994_MIXOUTL_TO_LINEOUT1P_MASK 0x0001 /* MIXOUTL_TO_LINEOUT1P */ 1737 #define WM8994_MIXOUTL_TO_LINEOUT1P_SHIFT 0 /* MIXOUTL_TO_LINEOUT1P */ 1738 #define WM8994_MIXOUTL_TO_LINEOUT1P_WIDTH 1 /* MIXOUTL_TO_LINEOUT1P */ 1739 1740 /* 1741 * R53 (0x35) - Line Mixer (2) 1742 */ 1743 #define WM8994_MIXOUTR_TO_LINEOUT2N 0x0040 /* MIXOUTR_TO_LINEOUT2N */ 1744 #define WM8994_MIXOUTR_TO_LINEOUT2N_MASK 0x0040 /* MIXOUTR_TO_LINEOUT2N */ 1745 #define WM8994_MIXOUTR_TO_LINEOUT2N_SHIFT 6 /* MIXOUTR_TO_LINEOUT2N */ 1746 #define WM8994_MIXOUTR_TO_LINEOUT2N_WIDTH 1 /* MIXOUTR_TO_LINEOUT2N */ 1747 #define WM8994_MIXOUTL_TO_LINEOUT2N 0x0020 /* MIXOUTL_TO_LINEOUT2N */ 1748 #define WM8994_MIXOUTL_TO_LINEOUT2N_MASK 0x0020 /* MIXOUTL_TO_LINEOUT2N */ 1749 #define WM8994_MIXOUTL_TO_LINEOUT2N_SHIFT 5 /* MIXOUTL_TO_LINEOUT2N */ 1750 #define WM8994_MIXOUTL_TO_LINEOUT2N_WIDTH 1 /* MIXOUTL_TO_LINEOUT2N */ 1751 #define WM8994_LINEOUT2_MODE 0x0010 /* LINEOUT2_MODE */ 1752 #define WM8994_LINEOUT2_MODE_MASK 0x0010 /* LINEOUT2_MODE */ 1753 #define WM8994_LINEOUT2_MODE_SHIFT 4 /* LINEOUT2_MODE */ 1754 #define WM8994_LINEOUT2_MODE_WIDTH 1 /* LINEOUT2_MODE */ 1755 #define WM8994_IN1L_TO_LINEOUT2P 0x0004 /* IN1L_TO_LINEOUT2P */ 1756 #define WM8994_IN1L_TO_LINEOUT2P_MASK 0x0004 /* IN1L_TO_LINEOUT2P */ 1757 #define WM8994_IN1L_TO_LINEOUT2P_SHIFT 2 /* IN1L_TO_LINEOUT2P */ 1758 #define WM8994_IN1L_TO_LINEOUT2P_WIDTH 1 /* IN1L_TO_LINEOUT2P */ 1759 #define WM8994_IN1R_TO_LINEOUT2P 0x0002 /* IN1R_TO_LINEOUT2P */ 1760 #define WM8994_IN1R_TO_LINEOUT2P_MASK 0x0002 /* IN1R_TO_LINEOUT2P */ 1761 #define WM8994_IN1R_TO_LINEOUT2P_SHIFT 1 /* IN1R_TO_LINEOUT2P */ 1762 #define WM8994_IN1R_TO_LINEOUT2P_WIDTH 1 /* IN1R_TO_LINEOUT2P */ 1763 #define WM8994_MIXOUTR_TO_LINEOUT2P 0x0001 /* MIXOUTR_TO_LINEOUT2P */ 1764 #define WM8994_MIXOUTR_TO_LINEOUT2P_MASK 0x0001 /* MIXOUTR_TO_LINEOUT2P */ 1765 #define WM8994_MIXOUTR_TO_LINEOUT2P_SHIFT 0 /* MIXOUTR_TO_LINEOUT2P */ 1766 #define WM8994_MIXOUTR_TO_LINEOUT2P_WIDTH 1 /* MIXOUTR_TO_LINEOUT2P */ 1767 1768 /* 1769 * R54 (0x36) - Speaker Mixer 1770 */ 1771 #define WM8994_DAC2L_TO_SPKMIXL 0x0200 /* DAC2L_TO_SPKMIXL */ 1772 #define WM8994_DAC2L_TO_SPKMIXL_MASK 0x0200 /* DAC2L_TO_SPKMIXL */ 1773 #define WM8994_DAC2L_TO_SPKMIXL_SHIFT 9 /* DAC2L_TO_SPKMIXL */ 1774 #define WM8994_DAC2L_TO_SPKMIXL_WIDTH 1 /* DAC2L_TO_SPKMIXL */ 1775 #define WM8994_DAC2R_TO_SPKMIXR 0x0100 /* DAC2R_TO_SPKMIXR */ 1776 #define WM8994_DAC2R_TO_SPKMIXR_MASK 0x0100 /* DAC2R_TO_SPKMIXR */ 1777 #define WM8994_DAC2R_TO_SPKMIXR_SHIFT 8 /* DAC2R_TO_SPKMIXR */ 1778 #define WM8994_DAC2R_TO_SPKMIXR_WIDTH 1 /* DAC2R_TO_SPKMIXR */ 1779 #define WM8994_MIXINL_TO_SPKMIXL 0x0080 /* MIXINL_TO_SPKMIXL */ 1780 #define WM8994_MIXINL_TO_SPKMIXL_MASK 0x0080 /* MIXINL_TO_SPKMIXL */ 1781 #define WM8994_MIXINL_TO_SPKMIXL_SHIFT 7 /* MIXINL_TO_SPKMIXL */ 1782 #define WM8994_MIXINL_TO_SPKMIXL_WIDTH 1 /* MIXINL_TO_SPKMIXL */ 1783 #define WM8994_MIXINR_TO_SPKMIXR 0x0040 /* MIXINR_TO_SPKMIXR */ 1784 #define WM8994_MIXINR_TO_SPKMIXR_MASK 0x0040 /* MIXINR_TO_SPKMIXR */ 1785 #define WM8994_MIXINR_TO_SPKMIXR_SHIFT 6 /* MIXINR_TO_SPKMIXR */ 1786 #define WM8994_MIXINR_TO_SPKMIXR_WIDTH 1 /* MIXINR_TO_SPKMIXR */ 1787 #define WM8994_IN1LP_TO_SPKMIXL 0x0020 /* IN1LP_TO_SPKMIXL */ 1788 #define WM8994_IN1LP_TO_SPKMIXL_MASK 0x0020 /* IN1LP_TO_SPKMIXL */ 1789 #define WM8994_IN1LP_TO_SPKMIXL_SHIFT 5 /* IN1LP_TO_SPKMIXL */ 1790 #define WM8994_IN1LP_TO_SPKMIXL_WIDTH 1 /* IN1LP_TO_SPKMIXL */ 1791 #define WM8994_IN1RP_TO_SPKMIXR 0x0010 /* IN1RP_TO_SPKMIXR */ 1792 #define WM8994_IN1RP_TO_SPKMIXR_MASK 0x0010 /* IN1RP_TO_SPKMIXR */ 1793 #define WM8994_IN1RP_TO_SPKMIXR_SHIFT 4 /* IN1RP_TO_SPKMIXR */ 1794 #define WM8994_IN1RP_TO_SPKMIXR_WIDTH 1 /* IN1RP_TO_SPKMIXR */ 1795 #define WM8994_MIXOUTL_TO_SPKMIXL 0x0008 /* MIXOUTL_TO_SPKMIXL */ 1796 #define WM8994_MIXOUTL_TO_SPKMIXL_MASK 0x0008 /* MIXOUTL_TO_SPKMIXL */ 1797 #define WM8994_MIXOUTL_TO_SPKMIXL_SHIFT 3 /* MIXOUTL_TO_SPKMIXL */ 1798 #define WM8994_MIXOUTL_TO_SPKMIXL_WIDTH 1 /* MIXOUTL_TO_SPKMIXL */ 1799 #define WM8994_MIXOUTR_TO_SPKMIXR 0x0004 /* MIXOUTR_TO_SPKMIXR */ 1800 #define WM8994_MIXOUTR_TO_SPKMIXR_MASK 0x0004 /* MIXOUTR_TO_SPKMIXR */ 1801 #define WM8994_MIXOUTR_TO_SPKMIXR_SHIFT 2 /* MIXOUTR_TO_SPKMIXR */ 1802 #define WM8994_MIXOUTR_TO_SPKMIXR_WIDTH 1 /* MIXOUTR_TO_SPKMIXR */ 1803 #define WM8994_DAC1L_TO_SPKMIXL 0x0002 /* DAC1L_TO_SPKMIXL */ 1804 #define WM8994_DAC1L_TO_SPKMIXL_MASK 0x0002 /* DAC1L_TO_SPKMIXL */ 1805 #define WM8994_DAC1L_TO_SPKMIXL_SHIFT 1 /* DAC1L_TO_SPKMIXL */ 1806 #define WM8994_DAC1L_TO_SPKMIXL_WIDTH 1 /* DAC1L_TO_SPKMIXL */ 1807 #define WM8994_DAC1R_TO_SPKMIXR 0x0001 /* DAC1R_TO_SPKMIXR */ 1808 #define WM8994_DAC1R_TO_SPKMIXR_MASK 0x0001 /* DAC1R_TO_SPKMIXR */ 1809 #define WM8994_DAC1R_TO_SPKMIXR_SHIFT 0 /* DAC1R_TO_SPKMIXR */ 1810 #define WM8994_DAC1R_TO_SPKMIXR_WIDTH 1 /* DAC1R_TO_SPKMIXR */ 1811 1812 /* 1813 * R55 (0x37) - Additional Control 1814 */ 1815 #define WM8994_LINEOUT1_FB 0x0080 /* LINEOUT1_FB */ 1816 #define WM8994_LINEOUT1_FB_MASK 0x0080 /* LINEOUT1_FB */ 1817 #define WM8994_LINEOUT1_FB_SHIFT 7 /* LINEOUT1_FB */ 1818 #define WM8994_LINEOUT1_FB_WIDTH 1 /* LINEOUT1_FB */ 1819 #define WM8994_LINEOUT2_FB 0x0040 /* LINEOUT2_FB */ 1820 #define WM8994_LINEOUT2_FB_MASK 0x0040 /* LINEOUT2_FB */ 1821 #define WM8994_LINEOUT2_FB_SHIFT 6 /* LINEOUT2_FB */ 1822 #define WM8994_LINEOUT2_FB_WIDTH 1 /* LINEOUT2_FB */ 1823 #define WM8994_VROI 0x0001 /* VROI */ 1824 #define WM8994_VROI_MASK 0x0001 /* VROI */ 1825 #define WM8994_VROI_SHIFT 0 /* VROI */ 1826 #define WM8994_VROI_WIDTH 1 /* VROI */ 1827 1828 /* 1829 * R56 (0x38) - AntiPOP (1) 1830 */ 1831 #define WM8994_LINEOUT_VMID_BUF_ENA 0x0080 /* LINEOUT_VMID_BUF_ENA */ 1832 #define WM8994_LINEOUT_VMID_BUF_ENA_MASK 0x0080 /* LINEOUT_VMID_BUF_ENA */ 1833 #define WM8994_LINEOUT_VMID_BUF_ENA_SHIFT 7 /* LINEOUT_VMID_BUF_ENA */ 1834 #define WM8994_LINEOUT_VMID_BUF_ENA_WIDTH 1 /* LINEOUT_VMID_BUF_ENA */ 1835 #define WM8994_HPOUT2_IN_ENA 0x0040 /* HPOUT2_IN_ENA */ 1836 #define WM8994_HPOUT2_IN_ENA_MASK 0x0040 /* HPOUT2_IN_ENA */ 1837 #define WM8994_HPOUT2_IN_ENA_SHIFT 6 /* HPOUT2_IN_ENA */ 1838 #define WM8994_HPOUT2_IN_ENA_WIDTH 1 /* HPOUT2_IN_ENA */ 1839 #define WM8994_LINEOUT1_DISCH 0x0020 /* LINEOUT1_DISCH */ 1840 #define WM8994_LINEOUT1_DISCH_MASK 0x0020 /* LINEOUT1_DISCH */ 1841 #define WM8994_LINEOUT1_DISCH_SHIFT 5 /* LINEOUT1_DISCH */ 1842 #define WM8994_LINEOUT1_DISCH_WIDTH 1 /* LINEOUT1_DISCH */ 1843 #define WM8994_LINEOUT2_DISCH 0x0010 /* LINEOUT2_DISCH */ 1844 #define WM8994_LINEOUT2_DISCH_MASK 0x0010 /* LINEOUT2_DISCH */ 1845 #define WM8994_LINEOUT2_DISCH_SHIFT 4 /* LINEOUT2_DISCH */ 1846 #define WM8994_LINEOUT2_DISCH_WIDTH 1 /* LINEOUT2_DISCH */ 1847 1848 /* 1849 * R57 (0x39) - AntiPOP (2) 1850 */ 1851 #define WM8994_MICB2_DISCH 0x0100 /* MICB2_DISCH */ 1852 #define WM8994_MICB2_DISCH_MASK 0x0100 /* MICB2_DISCH */ 1853 #define WM8994_MICB2_DISCH_SHIFT 8 /* MICB2_DISCH */ 1854 #define WM8994_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ 1855 #define WM8994_MICB1_DISCH 0x0080 /* MICB1_DISCH */ 1856 #define WM8994_MICB1_DISCH_MASK 0x0080 /* MICB1_DISCH */ 1857 #define WM8994_MICB1_DISCH_SHIFT 7 /* MICB1_DISCH */ 1858 #define WM8994_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ 1859 #define WM8994_VMID_RAMP_MASK 0x0060 /* VMID_RAMP - [6:5] */ 1860 #define WM8994_VMID_RAMP_SHIFT 5 /* VMID_RAMP - [6:5] */ 1861 #define WM8994_VMID_RAMP_WIDTH 2 /* VMID_RAMP - [6:5] */ 1862 #define WM8994_VMID_BUF_ENA 0x0008 /* VMID_BUF_ENA */ 1863 #define WM8994_VMID_BUF_ENA_MASK 0x0008 /* VMID_BUF_ENA */ 1864 #define WM8994_VMID_BUF_ENA_SHIFT 3 /* VMID_BUF_ENA */ 1865 #define WM8994_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */ 1866 #define WM8994_STARTUP_BIAS_ENA 0x0004 /* STARTUP_BIAS_ENA */ 1867 #define WM8994_STARTUP_BIAS_ENA_MASK 0x0004 /* STARTUP_BIAS_ENA */ 1868 #define WM8994_STARTUP_BIAS_ENA_SHIFT 2 /* STARTUP_BIAS_ENA */ 1869 #define WM8994_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */ 1870 #define WM8994_BIAS_SRC 0x0002 /* BIAS_SRC */ 1871 #define WM8994_BIAS_SRC_MASK 0x0002 /* BIAS_SRC */ 1872 #define WM8994_BIAS_SRC_SHIFT 1 /* BIAS_SRC */ 1873 #define WM8994_BIAS_SRC_WIDTH 1 /* BIAS_SRC */ 1874 #define WM8994_VMID_DISCH 0x0001 /* VMID_DISCH */ 1875 #define WM8994_VMID_DISCH_MASK 0x0001 /* VMID_DISCH */ 1876 #define WM8994_VMID_DISCH_SHIFT 0 /* VMID_DISCH */ 1877 #define WM8994_VMID_DISCH_WIDTH 1 /* VMID_DISCH */ 1878 1879 /* 1880 * R58 (0x3A) - MICBIAS 1881 */ 1882 #define WM8994_MICD_SCTHR_MASK 0x00C0 /* MICD_SCTHR - [7:6] */ 1883 #define WM8994_MICD_SCTHR_SHIFT 6 /* MICD_SCTHR - [7:6] */ 1884 #define WM8994_MICD_SCTHR_WIDTH 2 /* MICD_SCTHR - [7:6] */ 1885 #define WM8994_MICD_THR_MASK 0x0038 /* MICD_THR - [5:3] */ 1886 #define WM8994_MICD_THR_SHIFT 3 /* MICD_THR - [5:3] */ 1887 #define WM8994_MICD_THR_WIDTH 3 /* MICD_THR - [5:3] */ 1888 #define WM8994_MICD_ENA 0x0004 /* MICD_ENA */ 1889 #define WM8994_MICD_ENA_MASK 0x0004 /* MICD_ENA */ 1890 #define WM8994_MICD_ENA_SHIFT 2 /* MICD_ENA */ 1891 #define WM8994_MICD_ENA_WIDTH 1 /* MICD_ENA */ 1892 #define WM8994_MICB2_LVL 0x0002 /* MICB2_LVL */ 1893 #define WM8994_MICB2_LVL_MASK 0x0002 /* MICB2_LVL */ 1894 #define WM8994_MICB2_LVL_SHIFT 1 /* MICB2_LVL */ 1895 #define WM8994_MICB2_LVL_WIDTH 1 /* MICB2_LVL */ 1896 #define WM8994_MICB1_LVL 0x0001 /* MICB1_LVL */ 1897 #define WM8994_MICB1_LVL_MASK 0x0001 /* MICB1_LVL */ 1898 #define WM8994_MICB1_LVL_SHIFT 0 /* MICB1_LVL */ 1899 #define WM8994_MICB1_LVL_WIDTH 1 /* MICB1_LVL */ 1900 1901 /* 1902 * R59 (0x3B) - LDO 1 1903 */ 1904 #define WM8994_LDO1_VSEL_MASK 0x000E /* LDO1_VSEL - [3:1] */ 1905 #define WM8994_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [3:1] */ 1906 #define WM8994_LDO1_VSEL_WIDTH 3 /* LDO1_VSEL - [3:1] */ 1907 #define WM8994_LDO1_DISCH 0x0001 /* LDO1_DISCH */ 1908 #define WM8994_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */ 1909 #define WM8994_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */ 1910 #define WM8994_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */ 1911 1912 /* 1913 * R60 (0x3C) - LDO 2 1914 */ 1915 #define WM8994_LDO2_VSEL_MASK 0x0006 /* LDO2_VSEL - [2:1] */ 1916 #define WM8994_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [2:1] */ 1917 #define WM8994_LDO2_VSEL_WIDTH 2 /* LDO2_VSEL - [2:1] */ 1918 #define WM8994_LDO2_DISCH 0x0001 /* LDO2_DISCH */ 1919 #define WM8994_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */ 1920 #define WM8994_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */ 1921 #define WM8994_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */ 1922 1923 /* 1924 * R76 (0x4C) - Charge Pump (1) 1925 */ 1926 #define WM8994_CP_ENA 0x8000 /* CP_ENA */ 1927 #define WM8994_CP_ENA_MASK 0x8000 /* CP_ENA */ 1928 #define WM8994_CP_ENA_SHIFT 15 /* CP_ENA */ 1929 #define WM8994_CP_ENA_WIDTH 1 /* CP_ENA */ 1930 1931 /* 1932 * R77 (0x4D) - Charge Pump (2) 1933 */ 1934 #define WM8958_CP_DISCH 0x8000 /* CP_DISCH */ 1935 #define WM8958_CP_DISCH_MASK 0x8000 /* CP_DISCH */ 1936 #define WM8958_CP_DISCH_SHIFT 15 /* CP_DISCH */ 1937 #define WM8958_CP_DISCH_WIDTH 1 /* CP_DISCH */ 1938 1939 /* 1940 * R81 (0x51) - Class W (1) 1941 */ 1942 #define WM8994_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */ 1943 #define WM8994_CP_DYN_SRC_SEL_SHIFT 8 /* CP_DYN_SRC_SEL - [9:8] */ 1944 #define WM8994_CP_DYN_SRC_SEL_WIDTH 2 /* CP_DYN_SRC_SEL - [9:8] */ 1945 #define WM8994_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */ 1946 #define WM8994_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */ 1947 #define WM8994_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */ 1948 #define WM8994_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */ 1949 1950 /* 1951 * R84 (0x54) - DC Servo (1) 1952 */ 1953 #define WM8994_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */ 1954 #define WM8994_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */ 1955 #define WM8994_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */ 1956 #define WM8994_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */ 1957 #define WM8994_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */ 1958 #define WM8994_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */ 1959 #define WM8994_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */ 1960 #define WM8994_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */ 1961 #define WM8994_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */ 1962 #define WM8994_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */ 1963 #define WM8994_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */ 1964 #define WM8994_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */ 1965 #define WM8994_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */ 1966 #define WM8994_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */ 1967 #define WM8994_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */ 1968 #define WM8994_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */ 1969 #define WM8994_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */ 1970 #define WM8994_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */ 1971 #define WM8994_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */ 1972 #define WM8994_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */ 1973 #define WM8994_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */ 1974 #define WM8994_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */ 1975 #define WM8994_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */ 1976 #define WM8994_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */ 1977 #define WM8994_DCS_TRIG_DAC_WR_1 0x0008 /* DCS_TRIG_DAC_WR_1 */ 1978 #define WM8994_DCS_TRIG_DAC_WR_1_MASK 0x0008 /* DCS_TRIG_DAC_WR_1 */ 1979 #define WM8994_DCS_TRIG_DAC_WR_1_SHIFT 3 /* DCS_TRIG_DAC_WR_1 */ 1980 #define WM8994_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */ 1981 #define WM8994_DCS_TRIG_DAC_WR_0 0x0004 /* DCS_TRIG_DAC_WR_0 */ 1982 #define WM8994_DCS_TRIG_DAC_WR_0_MASK 0x0004 /* DCS_TRIG_DAC_WR_0 */ 1983 #define WM8994_DCS_TRIG_DAC_WR_0_SHIFT 2 /* DCS_TRIG_DAC_WR_0 */ 1984 #define WM8994_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */ 1985 #define WM8994_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */ 1986 #define WM8994_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */ 1987 #define WM8994_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */ 1988 #define WM8994_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */ 1989 #define WM8994_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */ 1990 #define WM8994_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */ 1991 #define WM8994_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */ 1992 #define WM8994_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */ 1993 1994 /* 1995 * R85 (0x55) - DC Servo (2) 1996 */ 1997 #define WM8994_DCS_SERIES_NO_01_MASK 0x0FE0 /* DCS_SERIES_NO_01 - [11:5] */ 1998 #define WM8994_DCS_SERIES_NO_01_SHIFT 5 /* DCS_SERIES_NO_01 - [11:5] */ 1999 #define WM8994_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [11:5] */ 2000 #define WM8994_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */ 2001 #define WM8994_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */ 2002 #define WM8994_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */ 2003 2004 /* 2005 * R87 (0x57) - DC Servo (4) 2006 */ 2007 #define WM8994_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */ 2008 #define WM8994_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ 2009 #define WM8994_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ 2010 #define WM8994_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */ 2011 #define WM8994_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */ 2012 #define WM8994_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */ 2013 2014 /* 2015 * R88 (0x58) - DC Servo Readback 2016 */ 2017 #define WM8994_DCS_CAL_COMPLETE_MASK 0x0300 /* DCS_CAL_COMPLETE - [9:8] */ 2018 #define WM8994_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [9:8] */ 2019 #define WM8994_DCS_CAL_COMPLETE_WIDTH 2 /* DCS_CAL_COMPLETE - [9:8] */ 2020 #define WM8994_DCS_DAC_WR_COMPLETE_MASK 0x0030 /* DCS_DAC_WR_COMPLETE - [5:4] */ 2021 #define WM8994_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [5:4] */ 2022 #define WM8994_DCS_DAC_WR_COMPLETE_WIDTH 2 /* DCS_DAC_WR_COMPLETE - [5:4] */ 2023 #define WM8994_DCS_STARTUP_COMPLETE_MASK 0x0003 /* DCS_STARTUP_COMPLETE - [1:0] */ 2024 #define WM8994_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [1:0] */ 2025 #define WM8994_DCS_STARTUP_COMPLETE_WIDTH 2 /* DCS_STARTUP_COMPLETE - [1:0] */ 2026 2027 /* 2028 * R96 (0x60) - Analogue HP (1) 2029 */ 2030 #define WM8994_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */ 2031 #define WM8994_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */ 2032 #define WM8994_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */ 2033 #define WM8994_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */ 2034 #define WM8994_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */ 2035 #define WM8994_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */ 2036 #define WM8994_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */ 2037 #define WM8994_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */ 2038 #define WM8994_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */ 2039 #define WM8994_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */ 2040 #define WM8994_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */ 2041 #define WM8994_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */ 2042 #define WM8994_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */ 2043 #define WM8994_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */ 2044 #define WM8994_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */ 2045 #define WM8994_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */ 2046 #define WM8994_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */ 2047 #define WM8994_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */ 2048 #define WM8994_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */ 2049 #define WM8994_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */ 2050 #define WM8994_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */ 2051 #define WM8994_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */ 2052 #define WM8994_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */ 2053 #define WM8994_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */ 2054 2055 /* 2056 * R208 (0xD0) - Mic Detect 1 2057 */ 2058 #define WM8958_MICD_BIAS_STARTTIME_MASK 0xF000 /* MICD_BIAS_STARTTIME - [15:12] */ 2059 #define WM8958_MICD_BIAS_STARTTIME_SHIFT 12 /* MICD_BIAS_STARTTIME - [15:12] */ 2060 #define WM8958_MICD_BIAS_STARTTIME_WIDTH 4 /* MICD_BIAS_STARTTIME - [15:12] */ 2061 #define WM8958_MICD_RATE_MASK 0x0F00 /* MICD_RATE - [11:8] */ 2062 #define WM8958_MICD_RATE_SHIFT 8 /* MICD_RATE - [11:8] */ 2063 #define WM8958_MICD_RATE_WIDTH 4 /* MICD_RATE - [11:8] */ 2064 #define WM8958_MICD_DBTIME 0x0002 /* MICD_DBTIME */ 2065 #define WM8958_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */ 2066 #define WM8958_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */ 2067 #define WM8958_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */ 2068 #define WM8958_MICD_ENA 0x0001 /* MICD_ENA */ 2069 #define WM8958_MICD_ENA_MASK 0x0001 /* MICD_ENA */ 2070 #define WM8958_MICD_ENA_SHIFT 0 /* MICD_ENA */ 2071 #define WM8958_MICD_ENA_WIDTH 1 /* MICD_ENA */ 2072 2073 /* 2074 * R209 (0xD1) - Mic Detect 2 2075 */ 2076 #define WM8958_MICD_LVL_SEL_MASK 0x00FF /* MICD_LVL_SEL - [7:0] */ 2077 #define WM8958_MICD_LVL_SEL_SHIFT 0 /* MICD_LVL_SEL - [7:0] */ 2078 #define WM8958_MICD_LVL_SEL_WIDTH 8 /* MICD_LVL_SEL - [7:0] */ 2079 2080 /* 2081 * R210 (0xD2) - Mic Detect 3 2082 */ 2083 #define WM8958_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */ 2084 #define WM8958_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */ 2085 #define WM8958_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */ 2086 #define WM8958_MICD_VALID 0x0002 /* MICD_VALID */ 2087 #define WM8958_MICD_VALID_MASK 0x0002 /* MICD_VALID */ 2088 #define WM8958_MICD_VALID_SHIFT 1 /* MICD_VALID */ 2089 #define WM8958_MICD_VALID_WIDTH 1 /* MICD_VALID */ 2090 #define WM8958_MICD_STS 0x0001 /* MICD_STS */ 2091 #define WM8958_MICD_STS_MASK 0x0001 /* MICD_STS */ 2092 #define WM8958_MICD_STS_SHIFT 0 /* MICD_STS */ 2093 #define WM8958_MICD_STS_WIDTH 1 /* MICD_STS */ 2094 2095 /* 2096 * R256 (0x100) - Chip Revision 2097 */ 2098 #define WM8994_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ 2099 #define WM8994_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */ 2100 #define WM8994_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */ 2101 2102 /* 2103 * R257 (0x101) - Control Interface 2104 */ 2105 #define WM8994_SPI_CONTRD 0x0040 /* SPI_CONTRD */ 2106 #define WM8994_SPI_CONTRD_MASK 0x0040 /* SPI_CONTRD */ 2107 #define WM8994_SPI_CONTRD_SHIFT 6 /* SPI_CONTRD */ 2108 #define WM8994_SPI_CONTRD_WIDTH 1 /* SPI_CONTRD */ 2109 #define WM8994_SPI_4WIRE 0x0020 /* SPI_4WIRE */ 2110 #define WM8994_SPI_4WIRE_MASK 0x0020 /* SPI_4WIRE */ 2111 #define WM8994_SPI_4WIRE_SHIFT 5 /* SPI_4WIRE */ 2112 #define WM8994_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */ 2113 #define WM8994_SPI_CFG 0x0010 /* SPI_CFG */ 2114 #define WM8994_SPI_CFG_MASK 0x0010 /* SPI_CFG */ 2115 #define WM8994_SPI_CFG_SHIFT 4 /* SPI_CFG */ 2116 #define WM8994_SPI_CFG_WIDTH 1 /* SPI_CFG */ 2117 #define WM8994_AUTO_INC 0x0004 /* AUTO_INC */ 2118 #define WM8994_AUTO_INC_MASK 0x0004 /* AUTO_INC */ 2119 #define WM8994_AUTO_INC_SHIFT 2 /* AUTO_INC */ 2120 #define WM8994_AUTO_INC_WIDTH 1 /* AUTO_INC */ 2121 2122 /* 2123 * R272 (0x110) - Write Sequencer Ctrl (1) 2124 */ 2125 #define WM8994_WSEQ_ENA 0x8000 /* WSEQ_ENA */ 2126 #define WM8994_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */ 2127 #define WM8994_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */ 2128 #define WM8994_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 2129 #define WM8994_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ 2130 #define WM8994_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ 2131 #define WM8994_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ 2132 #define WM8994_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 2133 #define WM8994_WSEQ_START 0x0100 /* WSEQ_START */ 2134 #define WM8994_WSEQ_START_MASK 0x0100 /* WSEQ_START */ 2135 #define WM8994_WSEQ_START_SHIFT 8 /* WSEQ_START */ 2136 #define WM8994_WSEQ_START_WIDTH 1 /* WSEQ_START */ 2137 #define WM8994_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */ 2138 #define WM8994_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */ 2139 #define WM8994_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */ 2140 2141 /* 2142 * R273 (0x111) - Write Sequencer Ctrl (2) 2143 */ 2144 #define WM8994_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */ 2145 #define WM8994_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */ 2146 #define WM8994_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */ 2147 #define WM8994_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 2148 #define WM8994_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */ 2149 #define WM8994_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */ 2150 #define WM8994_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */ 2151 2152 /* 2153 * R512 (0x200) - AIF1 Clocking (1) 2154 */ 2155 #define WM8994_AIF1CLK_SRC_MASK 0x0018 /* AIF1CLK_SRC - [4:3] */ 2156 #define WM8994_AIF1CLK_SRC_SHIFT 3 /* AIF1CLK_SRC - [4:3] */ 2157 #define WM8994_AIF1CLK_SRC_WIDTH 2 /* AIF1CLK_SRC - [4:3] */ 2158 #define WM8994_AIF1CLK_INV 0x0004 /* AIF1CLK_INV */ 2159 #define WM8994_AIF1CLK_INV_MASK 0x0004 /* AIF1CLK_INV */ 2160 #define WM8994_AIF1CLK_INV_SHIFT 2 /* AIF1CLK_INV */ 2161 #define WM8994_AIF1CLK_INV_WIDTH 1 /* AIF1CLK_INV */ 2162 #define WM8994_AIF1CLK_DIV 0x0002 /* AIF1CLK_DIV */ 2163 #define WM8994_AIF1CLK_DIV_MASK 0x0002 /* AIF1CLK_DIV */ 2164 #define WM8994_AIF1CLK_DIV_SHIFT 1 /* AIF1CLK_DIV */ 2165 #define WM8994_AIF1CLK_DIV_WIDTH 1 /* AIF1CLK_DIV */ 2166 #define WM8994_AIF1CLK_ENA 0x0001 /* AIF1CLK_ENA */ 2167 #define WM8994_AIF1CLK_ENA_MASK 0x0001 /* AIF1CLK_ENA */ 2168 #define WM8994_AIF1CLK_ENA_SHIFT 0 /* AIF1CLK_ENA */ 2169 #define WM8994_AIF1CLK_ENA_WIDTH 1 /* AIF1CLK_ENA */ 2170 2171 /* 2172 * R513 (0x201) - AIF1 Clocking (2) 2173 */ 2174 #define WM8994_AIF1DAC_DIV_MASK 0x0038 /* AIF1DAC_DIV - [5:3] */ 2175 #define WM8994_AIF1DAC_DIV_SHIFT 3 /* AIF1DAC_DIV - [5:3] */ 2176 #define WM8994_AIF1DAC_DIV_WIDTH 3 /* AIF1DAC_DIV - [5:3] */ 2177 #define WM8994_AIF1ADC_DIV_MASK 0x0007 /* AIF1ADC_DIV - [2:0] */ 2178 #define WM8994_AIF1ADC_DIV_SHIFT 0 /* AIF1ADC_DIV - [2:0] */ 2179 #define WM8994_AIF1ADC_DIV_WIDTH 3 /* AIF1ADC_DIV - [2:0] */ 2180 2181 /* 2182 * R516 (0x204) - AIF2 Clocking (1) 2183 */ 2184 #define WM8994_AIF2CLK_SRC_MASK 0x0018 /* AIF2CLK_SRC - [4:3] */ 2185 #define WM8994_AIF2CLK_SRC_SHIFT 3 /* AIF2CLK_SRC - [4:3] */ 2186 #define WM8994_AIF2CLK_SRC_WIDTH 2 /* AIF2CLK_SRC - [4:3] */ 2187 #define WM8994_AIF2CLK_INV 0x0004 /* AIF2CLK_INV */ 2188 #define WM8994_AIF2CLK_INV_MASK 0x0004 /* AIF2CLK_INV */ 2189 #define WM8994_AIF2CLK_INV_SHIFT 2 /* AIF2CLK_INV */ 2190 #define WM8994_AIF2CLK_INV_WIDTH 1 /* AIF2CLK_INV */ 2191 #define WM8994_AIF2CLK_DIV 0x0002 /* AIF2CLK_DIV */ 2192 #define WM8994_AIF2CLK_DIV_MASK 0x0002 /* AIF2CLK_DIV */ 2193 #define WM8994_AIF2CLK_DIV_SHIFT 1 /* AIF2CLK_DIV */ 2194 #define WM8994_AIF2CLK_DIV_WIDTH 1 /* AIF2CLK_DIV */ 2195 #define WM8994_AIF2CLK_ENA 0x0001 /* AIF2CLK_ENA */ 2196 #define WM8994_AIF2CLK_ENA_MASK 0x0001 /* AIF2CLK_ENA */ 2197 #define WM8994_AIF2CLK_ENA_SHIFT 0 /* AIF2CLK_ENA */ 2198 #define WM8994_AIF2CLK_ENA_WIDTH 1 /* AIF2CLK_ENA */ 2199 2200 /* 2201 * R517 (0x205) - AIF2 Clocking (2) 2202 */ 2203 #define WM8994_AIF2DAC_DIV_MASK 0x0038 /* AIF2DAC_DIV - [5:3] */ 2204 #define WM8994_AIF2DAC_DIV_SHIFT 3 /* AIF2DAC_DIV - [5:3] */ 2205 #define WM8994_AIF2DAC_DIV_WIDTH 3 /* AIF2DAC_DIV - [5:3] */ 2206 #define WM8994_AIF2ADC_DIV_MASK 0x0007 /* AIF2ADC_DIV - [2:0] */ 2207 #define WM8994_AIF2ADC_DIV_SHIFT 0 /* AIF2ADC_DIV - [2:0] */ 2208 #define WM8994_AIF2ADC_DIV_WIDTH 3 /* AIF2ADC_DIV - [2:0] */ 2209 2210 /* 2211 * R520 (0x208) - Clocking (1) 2212 */ 2213 #define WM8958_DSP2CLK_ENA 0x4000 /* DSP2CLK_ENA */ 2214 #define WM8958_DSP2CLK_ENA_MASK 0x4000 /* DSP2CLK_ENA */ 2215 #define WM8958_DSP2CLK_ENA_SHIFT 14 /* DSP2CLK_ENA */ 2216 #define WM8958_DSP2CLK_ENA_WIDTH 1 /* DSP2CLK_ENA */ 2217 #define WM8958_DSP2CLK_SRC 0x1000 /* DSP2CLK_SRC */ 2218 #define WM8958_DSP2CLK_SRC_MASK 0x1000 /* DSP2CLK_SRC */ 2219 #define WM8958_DSP2CLK_SRC_SHIFT 12 /* DSP2CLK_SRC */ 2220 #define WM8958_DSP2CLK_SRC_WIDTH 1 /* DSP2CLK_SRC */ 2221 #define WM8994_TOCLK_ENA 0x0010 /* TOCLK_ENA */ 2222 #define WM8994_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */ 2223 #define WM8994_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */ 2224 #define WM8994_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */ 2225 #define WM8994_AIF1DSPCLK_ENA 0x0008 /* AIF1DSPCLK_ENA */ 2226 #define WM8994_AIF1DSPCLK_ENA_MASK 0x0008 /* AIF1DSPCLK_ENA */ 2227 #define WM8994_AIF1DSPCLK_ENA_SHIFT 3 /* AIF1DSPCLK_ENA */ 2228 #define WM8994_AIF1DSPCLK_ENA_WIDTH 1 /* AIF1DSPCLK_ENA */ 2229 #define WM8994_AIF2DSPCLK_ENA 0x0004 /* AIF2DSPCLK_ENA */ 2230 #define WM8994_AIF2DSPCLK_ENA_MASK 0x0004 /* AIF2DSPCLK_ENA */ 2231 #define WM8994_AIF2DSPCLK_ENA_SHIFT 2 /* AIF2DSPCLK_ENA */ 2232 #define WM8994_AIF2DSPCLK_ENA_WIDTH 1 /* AIF2DSPCLK_ENA */ 2233 #define WM8994_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */ 2234 #define WM8994_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */ 2235 #define WM8994_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */ 2236 #define WM8994_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */ 2237 #define WM8994_SYSCLK_SRC 0x0001 /* SYSCLK_SRC */ 2238 #define WM8994_SYSCLK_SRC_MASK 0x0001 /* SYSCLK_SRC */ 2239 #define WM8994_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC */ 2240 #define WM8994_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */ 2241 2242 /* 2243 * R521 (0x209) - Clocking (2) 2244 */ 2245 #define WM8994_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */ 2246 #define WM8994_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */ 2247 #define WM8994_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */ 2248 #define WM8994_DBCLK_DIV_MASK 0x0070 /* DBCLK_DIV - [6:4] */ 2249 #define WM8994_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [6:4] */ 2250 #define WM8994_DBCLK_DIV_WIDTH 3 /* DBCLK_DIV - [6:4] */ 2251 #define WM8994_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */ 2252 #define WM8994_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */ 2253 #define WM8994_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */ 2254 2255 /* 2256 * R528 (0x210) - AIF1 Rate 2257 */ 2258 #define WM8994_AIF1_SR_MASK 0x00F0 /* AIF1_SR - [7:4] */ 2259 #define WM8994_AIF1_SR_SHIFT 4 /* AIF1_SR - [7:4] */ 2260 #define WM8994_AIF1_SR_WIDTH 4 /* AIF1_SR - [7:4] */ 2261 #define WM8994_AIF1CLK_RATE_MASK 0x000F /* AIF1CLK_RATE - [3:0] */ 2262 #define WM8994_AIF1CLK_RATE_SHIFT 0 /* AIF1CLK_RATE - [3:0] */ 2263 #define WM8994_AIF1CLK_RATE_WIDTH 4 /* AIF1CLK_RATE - [3:0] */ 2264 2265 /* 2266 * R529 (0x211) - AIF2 Rate 2267 */ 2268 #define WM8994_AIF2_SR_MASK 0x00F0 /* AIF2_SR - [7:4] */ 2269 #define WM8994_AIF2_SR_SHIFT 4 /* AIF2_SR - [7:4] */ 2270 #define WM8994_AIF2_SR_WIDTH 4 /* AIF2_SR - [7:4] */ 2271 #define WM8994_AIF2CLK_RATE_MASK 0x000F /* AIF2CLK_RATE - [3:0] */ 2272 #define WM8994_AIF2CLK_RATE_SHIFT 0 /* AIF2CLK_RATE - [3:0] */ 2273 #define WM8994_AIF2CLK_RATE_WIDTH 4 /* AIF2CLK_RATE - [3:0] */ 2274 2275 /* 2276 * R530 (0x212) - Rate Status 2277 */ 2278 #define WM8994_SR_ERROR_MASK 0x000F /* SR_ERROR - [3:0] */ 2279 #define WM8994_SR_ERROR_SHIFT 0 /* SR_ERROR - [3:0] */ 2280 #define WM8994_SR_ERROR_WIDTH 4 /* SR_ERROR - [3:0] */ 2281 2282 /* 2283 * R544 (0x220) - FLL1 Control (1) 2284 */ 2285 #define WM8994_FLL1_FRAC 0x0004 /* FLL1_FRAC */ 2286 #define WM8994_FLL1_FRAC_MASK 0x0004 /* FLL1_FRAC */ 2287 #define WM8994_FLL1_FRAC_SHIFT 2 /* FLL1_FRAC */ 2288 #define WM8994_FLL1_FRAC_WIDTH 1 /* FLL1_FRAC */ 2289 #define WM8994_FLL1_OSC_ENA 0x0002 /* FLL1_OSC_ENA */ 2290 #define WM8994_FLL1_OSC_ENA_MASK 0x0002 /* FLL1_OSC_ENA */ 2291 #define WM8994_FLL1_OSC_ENA_SHIFT 1 /* FLL1_OSC_ENA */ 2292 #define WM8994_FLL1_OSC_ENA_WIDTH 1 /* FLL1_OSC_ENA */ 2293 #define WM8994_FLL1_ENA 0x0001 /* FLL1_ENA */ 2294 #define WM8994_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */ 2295 #define WM8994_FLL1_ENA_SHIFT 0 /* FLL1_ENA */ 2296 #define WM8994_FLL1_ENA_WIDTH 1 /* FLL1_ENA */ 2297 2298 /* 2299 * R545 (0x221) - FLL1 Control (2) 2300 */ 2301 #define WM8994_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */ 2302 #define WM8994_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */ 2303 #define WM8994_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */ 2304 #define WM8994_FLL1_CTRL_RATE_MASK 0x0070 /* FLL1_CTRL_RATE - [6:4] */ 2305 #define WM8994_FLL1_CTRL_RATE_SHIFT 4 /* FLL1_CTRL_RATE - [6:4] */ 2306 #define WM8994_FLL1_CTRL_RATE_WIDTH 3 /* FLL1_CTRL_RATE - [6:4] */ 2307 #define WM8994_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */ 2308 #define WM8994_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */ 2309 #define WM8994_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */ 2310 2311 /* 2312 * R546 (0x222) - FLL1 Control (3) 2313 */ 2314 #define WM8994_FLL1_K_MASK 0xFFFF /* FLL1_K - [15:0] */ 2315 #define WM8994_FLL1_K_SHIFT 0 /* FLL1_K - [15:0] */ 2316 #define WM8994_FLL1_K_WIDTH 16 /* FLL1_K - [15:0] */ 2317 2318 /* 2319 * R547 (0x223) - FLL1 Control (4) 2320 */ 2321 #define WM8994_FLL1_N_MASK 0x7FE0 /* FLL1_N - [14:5] */ 2322 #define WM8994_FLL1_N_SHIFT 5 /* FLL1_N - [14:5] */ 2323 #define WM8994_FLL1_N_WIDTH 10 /* FLL1_N - [14:5] */ 2324 #define WM8994_FLL1_LOOP_GAIN_MASK 0x000F /* FLL1_LOOP_GAIN - [3:0] */ 2325 #define WM8994_FLL1_LOOP_GAIN_SHIFT 0 /* FLL1_LOOP_GAIN - [3:0] */ 2326 #define WM8994_FLL1_LOOP_GAIN_WIDTH 4 /* FLL1_LOOP_GAIN - [3:0] */ 2327 2328 /* 2329 * R548 (0x224) - FLL1 Control (5) 2330 */ 2331 #define WM8994_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */ 2332 #define WM8994_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */ 2333 #define WM8994_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */ 2334 #define WM8994_FLL1_FRC_NCO 0x0040 /* FLL1_FRC_NCO */ 2335 #define WM8994_FLL1_FRC_NCO_MASK 0x0040 /* FLL1_FRC_NCO */ 2336 #define WM8994_FLL1_FRC_NCO_SHIFT 6 /* FLL1_FRC_NCO */ 2337 #define WM8994_FLL1_FRC_NCO_WIDTH 1 /* FLL1_FRC_NCO */ 2338 #define WM8994_FLL1_REFCLK_DIV_MASK 0x0018 /* FLL1_REFCLK_DIV - [4:3] */ 2339 #define WM8994_FLL1_REFCLK_DIV_SHIFT 3 /* FLL1_REFCLK_DIV - [4:3] */ 2340 #define WM8994_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [4:3] */ 2341 #define WM8994_FLL1_REFCLK_SRC_MASK 0x0003 /* FLL1_REFCLK_SRC - [1:0] */ 2342 #define WM8994_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [1:0] */ 2343 #define WM8994_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */ 2344 2345 /* 2346 * R576 (0x240) - FLL2 Control (1) 2347 */ 2348 #define WM8994_FLL2_FRAC 0x0004 /* FLL2_FRAC */ 2349 #define WM8994_FLL2_FRAC_MASK 0x0004 /* FLL2_FRAC */ 2350 #define WM8994_FLL2_FRAC_SHIFT 2 /* FLL2_FRAC */ 2351 #define WM8994_FLL2_FRAC_WIDTH 1 /* FLL2_FRAC */ 2352 #define WM8994_FLL2_OSC_ENA 0x0002 /* FLL2_OSC_ENA */ 2353 #define WM8994_FLL2_OSC_ENA_MASK 0x0002 /* FLL2_OSC_ENA */ 2354 #define WM8994_FLL2_OSC_ENA_SHIFT 1 /* FLL2_OSC_ENA */ 2355 #define WM8994_FLL2_OSC_ENA_WIDTH 1 /* FLL2_OSC_ENA */ 2356 #define WM8994_FLL2_ENA 0x0001 /* FLL2_ENA */ 2357 #define WM8994_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */ 2358 #define WM8994_FLL2_ENA_SHIFT 0 /* FLL2_ENA */ 2359 #define WM8994_FLL2_ENA_WIDTH 1 /* FLL2_ENA */ 2360 2361 /* 2362 * R577 (0x241) - FLL2 Control (2) 2363 */ 2364 #define WM8994_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */ 2365 #define WM8994_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */ 2366 #define WM8994_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */ 2367 #define WM8994_FLL2_CTRL_RATE_MASK 0x0070 /* FLL2_CTRL_RATE - [6:4] */ 2368 #define WM8994_FLL2_CTRL_RATE_SHIFT 4 /* FLL2_CTRL_RATE - [6:4] */ 2369 #define WM8994_FLL2_CTRL_RATE_WIDTH 3 /* FLL2_CTRL_RATE - [6:4] */ 2370 #define WM8994_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */ 2371 #define WM8994_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */ 2372 #define WM8994_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */ 2373 2374 /* 2375 * R578 (0x242) - FLL2 Control (3) 2376 */ 2377 #define WM8994_FLL2_K_MASK 0xFFFF /* FLL2_K - [15:0] */ 2378 #define WM8994_FLL2_K_SHIFT 0 /* FLL2_K - [15:0] */ 2379 #define WM8994_FLL2_K_WIDTH 16 /* FLL2_K - [15:0] */ 2380 2381 /* 2382 * R579 (0x243) - FLL2 Control (4) 2383 */ 2384 #define WM8994_FLL2_N_MASK 0x7FE0 /* FLL2_N - [14:5] */ 2385 #define WM8994_FLL2_N_SHIFT 5 /* FLL2_N - [14:5] */ 2386 #define WM8994_FLL2_N_WIDTH 10 /* FLL2_N - [14:5] */ 2387 #define WM8994_FLL2_LOOP_GAIN_MASK 0x000F /* FLL2_LOOP_GAIN - [3:0] */ 2388 #define WM8994_FLL2_LOOP_GAIN_SHIFT 0 /* FLL2_LOOP_GAIN - [3:0] */ 2389 #define WM8994_FLL2_LOOP_GAIN_WIDTH 4 /* FLL2_LOOP_GAIN - [3:0] */ 2390 2391 /* 2392 * R580 (0x244) - FLL2 Control (5) 2393 */ 2394 #define WM8994_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */ 2395 #define WM8994_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */ 2396 #define WM8994_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */ 2397 #define WM8994_FLL2_FRC_NCO 0x0040 /* FLL2_FRC_NCO */ 2398 #define WM8994_FLL2_FRC_NCO_MASK 0x0040 /* FLL2_FRC_NCO */ 2399 #define WM8994_FLL2_FRC_NCO_SHIFT 6 /* FLL2_FRC_NCO */ 2400 #define WM8994_FLL2_FRC_NCO_WIDTH 1 /* FLL2_FRC_NCO */ 2401 #define WM8994_FLL2_REFCLK_DIV_MASK 0x0018 /* FLL2_REFCLK_DIV - [4:3] */ 2402 #define WM8994_FLL2_REFCLK_DIV_SHIFT 3 /* FLL2_REFCLK_DIV - [4:3] */ 2403 #define WM8994_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [4:3] */ 2404 #define WM8994_FLL2_REFCLK_SRC_MASK 0x0003 /* FLL2_REFCLK_SRC - [1:0] */ 2405 #define WM8994_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [1:0] */ 2406 #define WM8994_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */ 2407 2408 /* 2409 * R768 (0x300) - AIF1 Control (1) 2410 */ 2411 #define WM8994_AIF1ADCL_SRC 0x8000 /* AIF1ADCL_SRC */ 2412 #define WM8994_AIF1ADCL_SRC_MASK 0x8000 /* AIF1ADCL_SRC */ 2413 #define WM8994_AIF1ADCL_SRC_SHIFT 15 /* AIF1ADCL_SRC */ 2414 #define WM8994_AIF1ADCL_SRC_WIDTH 1 /* AIF1ADCL_SRC */ 2415 #define WM8994_AIF1ADCR_SRC 0x4000 /* AIF1ADCR_SRC */ 2416 #define WM8994_AIF1ADCR_SRC_MASK 0x4000 /* AIF1ADCR_SRC */ 2417 #define WM8994_AIF1ADCR_SRC_SHIFT 14 /* AIF1ADCR_SRC */ 2418 #define WM8994_AIF1ADCR_SRC_WIDTH 1 /* AIF1ADCR_SRC */ 2419 #define WM8994_AIF1ADC_TDM 0x2000 /* AIF1ADC_TDM */ 2420 #define WM8994_AIF1ADC_TDM_MASK 0x2000 /* AIF1ADC_TDM */ 2421 #define WM8994_AIF1ADC_TDM_SHIFT 13 /* AIF1ADC_TDM */ 2422 #define WM8994_AIF1ADC_TDM_WIDTH 1 /* AIF1ADC_TDM */ 2423 #define WM8994_AIF1_BCLK_INV 0x0100 /* AIF1_BCLK_INV */ 2424 #define WM8994_AIF1_BCLK_INV_MASK 0x0100 /* AIF1_BCLK_INV */ 2425 #define WM8994_AIF1_BCLK_INV_SHIFT 8 /* AIF1_BCLK_INV */ 2426 #define WM8994_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ 2427 #define WM8994_AIF1_LRCLK_INV 0x0080 /* AIF1_LRCLK_INV */ 2428 #define WM8994_AIF1_LRCLK_INV_MASK 0x0080 /* AIF1_LRCLK_INV */ 2429 #define WM8994_AIF1_LRCLK_INV_SHIFT 7 /* AIF1_LRCLK_INV */ 2430 #define WM8994_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */ 2431 #define WM8994_AIF1_WL_MASK 0x0060 /* AIF1_WL - [6:5] */ 2432 #define WM8994_AIF1_WL_SHIFT 5 /* AIF1_WL - [6:5] */ 2433 #define WM8994_AIF1_WL_WIDTH 2 /* AIF1_WL - [6:5] */ 2434 #define WM8994_AIF1_FMT_MASK 0x0018 /* AIF1_FMT - [4:3] */ 2435 #define WM8994_AIF1_FMT_SHIFT 3 /* AIF1_FMT - [4:3] */ 2436 #define WM8994_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [4:3] */ 2437 2438 /* 2439 * R769 (0x301) - AIF1 Control (2) 2440 */ 2441 #define WM8994_AIF1DACL_SRC 0x8000 /* AIF1DACL_SRC */ 2442 #define WM8994_AIF1DACL_SRC_MASK 0x8000 /* AIF1DACL_SRC */ 2443 #define WM8994_AIF1DACL_SRC_SHIFT 15 /* AIF1DACL_SRC */ 2444 #define WM8994_AIF1DACL_SRC_WIDTH 1 /* AIF1DACL_SRC */ 2445 #define WM8994_AIF1DACR_SRC 0x4000 /* AIF1DACR_SRC */ 2446 #define WM8994_AIF1DACR_SRC_MASK 0x4000 /* AIF1DACR_SRC */ 2447 #define WM8994_AIF1DACR_SRC_SHIFT 14 /* AIF1DACR_SRC */ 2448 #define WM8994_AIF1DACR_SRC_WIDTH 1 /* AIF1DACR_SRC */ 2449 #define WM8994_AIF1DAC_BOOST_MASK 0x0C00 /* AIF1DAC_BOOST - [11:10] */ 2450 #define WM8994_AIF1DAC_BOOST_SHIFT 10 /* AIF1DAC_BOOST - [11:10] */ 2451 #define WM8994_AIF1DAC_BOOST_WIDTH 2 /* AIF1DAC_BOOST - [11:10] */ 2452 #define WM8994_AIF1_MONO 0x0100 /* AIF1_MONO */ 2453 #define WM8994_AIF1_MONO_MASK 0x0100 /* AIF1_MONO */ 2454 #define WM8994_AIF1_MONO_SHIFT 8 /* AIF1_MONO */ 2455 #define WM8994_AIF1_MONO_WIDTH 1 /* AIF1_MONO */ 2456 #define WM8994_AIF1DAC_COMP 0x0010 /* AIF1DAC_COMP */ 2457 #define WM8994_AIF1DAC_COMP_MASK 0x0010 /* AIF1DAC_COMP */ 2458 #define WM8994_AIF1DAC_COMP_SHIFT 4 /* AIF1DAC_COMP */ 2459 #define WM8994_AIF1DAC_COMP_WIDTH 1 /* AIF1DAC_COMP */ 2460 #define WM8994_AIF1DAC_COMPMODE 0x0008 /* AIF1DAC_COMPMODE */ 2461 #define WM8994_AIF1DAC_COMPMODE_MASK 0x0008 /* AIF1DAC_COMPMODE */ 2462 #define WM8994_AIF1DAC_COMPMODE_SHIFT 3 /* AIF1DAC_COMPMODE */ 2463 #define WM8994_AIF1DAC_COMPMODE_WIDTH 1 /* AIF1DAC_COMPMODE */ 2464 #define WM8994_AIF1ADC_COMP 0x0004 /* AIF1ADC_COMP */ 2465 #define WM8994_AIF1ADC_COMP_MASK 0x0004 /* AIF1ADC_COMP */ 2466 #define WM8994_AIF1ADC_COMP_SHIFT 2 /* AIF1ADC_COMP */ 2467 #define WM8994_AIF1ADC_COMP_WIDTH 1 /* AIF1ADC_COMP */ 2468 #define WM8994_AIF1ADC_COMPMODE 0x0002 /* AIF1ADC_COMPMODE */ 2469 #define WM8994_AIF1ADC_COMPMODE_MASK 0x0002 /* AIF1ADC_COMPMODE */ 2470 #define WM8994_AIF1ADC_COMPMODE_SHIFT 1 /* AIF1ADC_COMPMODE */ 2471 #define WM8994_AIF1ADC_COMPMODE_WIDTH 1 /* AIF1ADC_COMPMODE */ 2472 #define WM8994_AIF1_LOOPBACK 0x0001 /* AIF1_LOOPBACK */ 2473 #define WM8994_AIF1_LOOPBACK_MASK 0x0001 /* AIF1_LOOPBACK */ 2474 #define WM8994_AIF1_LOOPBACK_SHIFT 0 /* AIF1_LOOPBACK */ 2475 #define WM8994_AIF1_LOOPBACK_WIDTH 1 /* AIF1_LOOPBACK */ 2476 2477 /* 2478 * R770 (0x302) - AIF1 Master/Slave 2479 */ 2480 #define WM8994_AIF1_TRI 0x8000 /* AIF1_TRI */ 2481 #define WM8994_AIF1_TRI_MASK 0x8000 /* AIF1_TRI */ 2482 #define WM8994_AIF1_TRI_SHIFT 15 /* AIF1_TRI */ 2483 #define WM8994_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ 2484 #define WM8994_AIF1_MSTR 0x4000 /* AIF1_MSTR */ 2485 #define WM8994_AIF1_MSTR_MASK 0x4000 /* AIF1_MSTR */ 2486 #define WM8994_AIF1_MSTR_SHIFT 14 /* AIF1_MSTR */ 2487 #define WM8994_AIF1_MSTR_WIDTH 1 /* AIF1_MSTR */ 2488 #define WM8994_AIF1_CLK_FRC 0x2000 /* AIF1_CLK_FRC */ 2489 #define WM8994_AIF1_CLK_FRC_MASK 0x2000 /* AIF1_CLK_FRC */ 2490 #define WM8994_AIF1_CLK_FRC_SHIFT 13 /* AIF1_CLK_FRC */ 2491 #define WM8994_AIF1_CLK_FRC_WIDTH 1 /* AIF1_CLK_FRC */ 2492 #define WM8994_AIF1_LRCLK_FRC 0x1000 /* AIF1_LRCLK_FRC */ 2493 #define WM8994_AIF1_LRCLK_FRC_MASK 0x1000 /* AIF1_LRCLK_FRC */ 2494 #define WM8994_AIF1_LRCLK_FRC_SHIFT 12 /* AIF1_LRCLK_FRC */ 2495 #define WM8994_AIF1_LRCLK_FRC_WIDTH 1 /* AIF1_LRCLK_FRC */ 2496 2497 /* 2498 * R771 (0x303) - AIF1 BCLK 2499 */ 2500 #define WM8994_AIF1_BCLK_DIV_MASK 0x01F0 /* AIF1_BCLK_DIV - [8:4] */ 2501 #define WM8994_AIF1_BCLK_DIV_SHIFT 4 /* AIF1_BCLK_DIV - [8:4] */ 2502 #define WM8994_AIF1_BCLK_DIV_WIDTH 5 /* AIF1_BCLK_DIV - [8:4] */ 2503 2504 /* 2505 * R772 (0x304) - AIF1ADC LRCLK 2506 */ 2507 #define WM8994_AIF1ADC_LRCLK_DIR 0x0800 /* AIF1ADC_LRCLK_DIR */ 2508 #define WM8994_AIF1ADC_LRCLK_DIR_MASK 0x0800 /* AIF1ADC_LRCLK_DIR */ 2509 #define WM8994_AIF1ADC_LRCLK_DIR_SHIFT 11 /* AIF1ADC_LRCLK_DIR */ 2510 #define WM8994_AIF1ADC_LRCLK_DIR_WIDTH 1 /* AIF1ADC_LRCLK_DIR */ 2511 #define WM8994_AIF1ADC_RATE_MASK 0x07FF /* AIF1ADC_RATE - [10:0] */ 2512 #define WM8994_AIF1ADC_RATE_SHIFT 0 /* AIF1ADC_RATE - [10:0] */ 2513 #define WM8994_AIF1ADC_RATE_WIDTH 11 /* AIF1ADC_RATE - [10:0] */ 2514 2515 /* 2516 * R773 (0x305) - AIF1DAC LRCLK 2517 */ 2518 #define WM8994_AIF1DAC_LRCLK_DIR 0x0800 /* AIF1DAC_LRCLK_DIR */ 2519 #define WM8994_AIF1DAC_LRCLK_DIR_MASK 0x0800 /* AIF1DAC_LRCLK_DIR */ 2520 #define WM8994_AIF1DAC_LRCLK_DIR_SHIFT 11 /* AIF1DAC_LRCLK_DIR */ 2521 #define WM8994_AIF1DAC_LRCLK_DIR_WIDTH 1 /* AIF1DAC_LRCLK_DIR */ 2522 #define WM8994_AIF1DAC_RATE_MASK 0x07FF /* AIF1DAC_RATE - [10:0] */ 2523 #define WM8994_AIF1DAC_RATE_SHIFT 0 /* AIF1DAC_RATE - [10:0] */ 2524 #define WM8994_AIF1DAC_RATE_WIDTH 11 /* AIF1DAC_RATE - [10:0] */ 2525 2526 /* 2527 * R774 (0x306) - AIF1DAC Data 2528 */ 2529 #define WM8994_AIF1DACL_DAT_INV 0x0002 /* AIF1DACL_DAT_INV */ 2530 #define WM8994_AIF1DACL_DAT_INV_MASK 0x0002 /* AIF1DACL_DAT_INV */ 2531 #define WM8994_AIF1DACL_DAT_INV_SHIFT 1 /* AIF1DACL_DAT_INV */ 2532 #define WM8994_AIF1DACL_DAT_INV_WIDTH 1 /* AIF1DACL_DAT_INV */ 2533 #define WM8994_AIF1DACR_DAT_INV 0x0001 /* AIF1DACR_DAT_INV */ 2534 #define WM8994_AIF1DACR_DAT_INV_MASK 0x0001 /* AIF1DACR_DAT_INV */ 2535 #define WM8994_AIF1DACR_DAT_INV_SHIFT 0 /* AIF1DACR_DAT_INV */ 2536 #define WM8994_AIF1DACR_DAT_INV_WIDTH 1 /* AIF1DACR_DAT_INV */ 2537 2538 /* 2539 * R775 (0x307) - AIF1ADC Data 2540 */ 2541 #define WM8994_AIF1ADCL_DAT_INV 0x0002 /* AIF1ADCL_DAT_INV */ 2542 #define WM8994_AIF1ADCL_DAT_INV_MASK 0x0002 /* AIF1ADCL_DAT_INV */ 2543 #define WM8994_AIF1ADCL_DAT_INV_SHIFT 1 /* AIF1ADCL_DAT_INV */ 2544 #define WM8994_AIF1ADCL_DAT_INV_WIDTH 1 /* AIF1ADCL_DAT_INV */ 2545 #define WM8994_AIF1ADCR_DAT_INV 0x0001 /* AIF1ADCR_DAT_INV */ 2546 #define WM8994_AIF1ADCR_DAT_INV_MASK 0x0001 /* AIF1ADCR_DAT_INV */ 2547 #define WM8994_AIF1ADCR_DAT_INV_SHIFT 0 /* AIF1ADCR_DAT_INV */ 2548 #define WM8994_AIF1ADCR_DAT_INV_WIDTH 1 /* AIF1ADCR_DAT_INV */ 2549 2550 /* 2551 * R784 (0x310) - AIF2 Control (1) 2552 */ 2553 #define WM8994_AIF2ADCL_SRC 0x8000 /* AIF2ADCL_SRC */ 2554 #define WM8994_AIF2ADCL_SRC_MASK 0x8000 /* AIF2ADCL_SRC */ 2555 #define WM8994_AIF2ADCL_SRC_SHIFT 15 /* AIF2ADCL_SRC */ 2556 #define WM8994_AIF2ADCL_SRC_WIDTH 1 /* AIF2ADCL_SRC */ 2557 #define WM8994_AIF2ADCR_SRC 0x4000 /* AIF2ADCR_SRC */ 2558 #define WM8994_AIF2ADCR_SRC_MASK 0x4000 /* AIF2ADCR_SRC */ 2559 #define WM8994_AIF2ADCR_SRC_SHIFT 14 /* AIF2ADCR_SRC */ 2560 #define WM8994_AIF2ADCR_SRC_WIDTH 1 /* AIF2ADCR_SRC */ 2561 #define WM8994_AIF2ADC_TDM 0x2000 /* AIF2ADC_TDM */ 2562 #define WM8994_AIF2ADC_TDM_MASK 0x2000 /* AIF2ADC_TDM */ 2563 #define WM8994_AIF2ADC_TDM_SHIFT 13 /* AIF2ADC_TDM */ 2564 #define WM8994_AIF2ADC_TDM_WIDTH 1 /* AIF2ADC_TDM */ 2565 #define WM8994_AIF2ADC_TDM_CHAN 0x1000 /* AIF2ADC_TDM_CHAN */ 2566 #define WM8994_AIF2ADC_TDM_CHAN_MASK 0x1000 /* AIF2ADC_TDM_CHAN */ 2567 #define WM8994_AIF2ADC_TDM_CHAN_SHIFT 12 /* AIF2ADC_TDM_CHAN */ 2568 #define WM8994_AIF2ADC_TDM_CHAN_WIDTH 1 /* AIF2ADC_TDM_CHAN */ 2569 #define WM8994_AIF2_BCLK_INV 0x0100 /* AIF2_BCLK_INV */ 2570 #define WM8994_AIF2_BCLK_INV_MASK 0x0100 /* AIF2_BCLK_INV */ 2571 #define WM8994_AIF2_BCLK_INV_SHIFT 8 /* AIF2_BCLK_INV */ 2572 #define WM8994_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */ 2573 #define WM8994_AIF2_LRCLK_INV 0x0080 /* AIF2_LRCLK_INV */ 2574 #define WM8994_AIF2_LRCLK_INV_MASK 0x0080 /* AIF2_LRCLK_INV */ 2575 #define WM8994_AIF2_LRCLK_INV_SHIFT 7 /* AIF2_LRCLK_INV */ 2576 #define WM8994_AIF2_LRCLK_INV_WIDTH 1 /* AIF2_LRCLK_INV */ 2577 #define WM8994_AIF2_WL_MASK 0x0060 /* AIF2_WL - [6:5] */ 2578 #define WM8994_AIF2_WL_SHIFT 5 /* AIF2_WL - [6:5] */ 2579 #define WM8994_AIF2_WL_WIDTH 2 /* AIF2_WL - [6:5] */ 2580 #define WM8994_AIF2_FMT_MASK 0x0018 /* AIF2_FMT - [4:3] */ 2581 #define WM8994_AIF2_FMT_SHIFT 3 /* AIF2_FMT - [4:3] */ 2582 #define WM8994_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [4:3] */ 2583 2584 /* 2585 * R785 (0x311) - AIF2 Control (2) 2586 */ 2587 #define WM8994_AIF2DACL_SRC 0x8000 /* AIF2DACL_SRC */ 2588 #define WM8994_AIF2DACL_SRC_MASK 0x8000 /* AIF2DACL_SRC */ 2589 #define WM8994_AIF2DACL_SRC_SHIFT 15 /* AIF2DACL_SRC */ 2590 #define WM8994_AIF2DACL_SRC_WIDTH 1 /* AIF2DACL_SRC */ 2591 #define WM8994_AIF2DACR_SRC 0x4000 /* AIF2DACR_SRC */ 2592 #define WM8994_AIF2DACR_SRC_MASK 0x4000 /* AIF2DACR_SRC */ 2593 #define WM8994_AIF2DACR_SRC_SHIFT 14 /* AIF2DACR_SRC */ 2594 #define WM8994_AIF2DACR_SRC_WIDTH 1 /* AIF2DACR_SRC */ 2595 #define WM8994_AIF2DAC_TDM 0x2000 /* AIF2DAC_TDM */ 2596 #define WM8994_AIF2DAC_TDM_MASK 0x2000 /* AIF2DAC_TDM */ 2597 #define WM8994_AIF2DAC_TDM_SHIFT 13 /* AIF2DAC_TDM */ 2598 #define WM8994_AIF2DAC_TDM_WIDTH 1 /* AIF2DAC_TDM */ 2599 #define WM8994_AIF2DAC_TDM_CHAN 0x1000 /* AIF2DAC_TDM_CHAN */ 2600 #define WM8994_AIF2DAC_TDM_CHAN_MASK 0x1000 /* AIF2DAC_TDM_CHAN */ 2601 #define WM8994_AIF2DAC_TDM_CHAN_SHIFT 12 /* AIF2DAC_TDM_CHAN */ 2602 #define WM8994_AIF2DAC_TDM_CHAN_WIDTH 1 /* AIF2DAC_TDM_CHAN */ 2603 #define WM8994_AIF2DAC_BOOST_MASK 0x0C00 /* AIF2DAC_BOOST - [11:10] */ 2604 #define WM8994_AIF2DAC_BOOST_SHIFT 10 /* AIF2DAC_BOOST - [11:10] */ 2605 #define WM8994_AIF2DAC_BOOST_WIDTH 2 /* AIF2DAC_BOOST - [11:10] */ 2606 #define WM8994_AIF2_MONO 0x0100 /* AIF2_MONO */ 2607 #define WM8994_AIF2_MONO_MASK 0x0100 /* AIF2_MONO */ 2608 #define WM8994_AIF2_MONO_SHIFT 8 /* AIF2_MONO */ 2609 #define WM8994_AIF2_MONO_WIDTH 1 /* AIF2_MONO */ 2610 #define WM8994_AIF2DAC_COMP 0x0010 /* AIF2DAC_COMP */ 2611 #define WM8994_AIF2DAC_COMP_MASK 0x0010 /* AIF2DAC_COMP */ 2612 #define WM8994_AIF2DAC_COMP_SHIFT 4 /* AIF2DAC_COMP */ 2613 #define WM8994_AIF2DAC_COMP_WIDTH 1 /* AIF2DAC_COMP */ 2614 #define WM8994_AIF2DAC_COMPMODE 0x0008 /* AIF2DAC_COMPMODE */ 2615 #define WM8994_AIF2DAC_COMPMODE_MASK 0x0008 /* AIF2DAC_COMPMODE */ 2616 #define WM8994_AIF2DAC_COMPMODE_SHIFT 3 /* AIF2DAC_COMPMODE */ 2617 #define WM8994_AIF2DAC_COMPMODE_WIDTH 1 /* AIF2DAC_COMPMODE */ 2618 #define WM8994_AIF2ADC_COMP 0x0004 /* AIF2ADC_COMP */ 2619 #define WM8994_AIF2ADC_COMP_MASK 0x0004 /* AIF2ADC_COMP */ 2620 #define WM8994_AIF2ADC_COMP_SHIFT 2 /* AIF2ADC_COMP */ 2621 #define WM8994_AIF2ADC_COMP_WIDTH 1 /* AIF2ADC_COMP */ 2622 #define WM8994_AIF2ADC_COMPMODE 0x0002 /* AIF2ADC_COMPMODE */ 2623 #define WM8994_AIF2ADC_COMPMODE_MASK 0x0002 /* AIF2ADC_COMPMODE */ 2624 #define WM8994_AIF2ADC_COMPMODE_SHIFT 1 /* AIF2ADC_COMPMODE */ 2625 #define WM8994_AIF2ADC_COMPMODE_WIDTH 1 /* AIF2ADC_COMPMODE */ 2626 #define WM8994_AIF2_LOOPBACK 0x0001 /* AIF2_LOOPBACK */ 2627 #define WM8994_AIF2_LOOPBACK_MASK 0x0001 /* AIF2_LOOPBACK */ 2628 #define WM8994_AIF2_LOOPBACK_SHIFT 0 /* AIF2_LOOPBACK */ 2629 #define WM8994_AIF2_LOOPBACK_WIDTH 1 /* AIF2_LOOPBACK */ 2630 2631 /* 2632 * R786 (0x312) - AIF2 Master/Slave 2633 */ 2634 #define WM8994_AIF2_TRI 0x8000 /* AIF2_TRI */ 2635 #define WM8994_AIF2_TRI_MASK 0x8000 /* AIF2_TRI */ 2636 #define WM8994_AIF2_TRI_SHIFT 15 /* AIF2_TRI */ 2637 #define WM8994_AIF2_TRI_WIDTH 1 /* AIF2_TRI */ 2638 #define WM8994_AIF2_MSTR 0x4000 /* AIF2_MSTR */ 2639 #define WM8994_AIF2_MSTR_MASK 0x4000 /* AIF2_MSTR */ 2640 #define WM8994_AIF2_MSTR_SHIFT 14 /* AIF2_MSTR */ 2641 #define WM8994_AIF2_MSTR_WIDTH 1 /* AIF2_MSTR */ 2642 #define WM8994_AIF2_CLK_FRC 0x2000 /* AIF2_CLK_FRC */ 2643 #define WM8994_AIF2_CLK_FRC_MASK 0x2000 /* AIF2_CLK_FRC */ 2644 #define WM8994_AIF2_CLK_FRC_SHIFT 13 /* AIF2_CLK_FRC */ 2645 #define WM8994_AIF2_CLK_FRC_WIDTH 1 /* AIF2_CLK_FRC */ 2646 #define WM8994_AIF2_LRCLK_FRC 0x1000 /* AIF2_LRCLK_FRC */ 2647 #define WM8994_AIF2_LRCLK_FRC_MASK 0x1000 /* AIF2_LRCLK_FRC */ 2648 #define WM8994_AIF2_LRCLK_FRC_SHIFT 12 /* AIF2_LRCLK_FRC */ 2649 #define WM8994_AIF2_LRCLK_FRC_WIDTH 1 /* AIF2_LRCLK_FRC */ 2650 2651 /* 2652 * R787 (0x313) - AIF2 BCLK 2653 */ 2654 #define WM8994_AIF2_BCLK_DIV_MASK 0x01F0 /* AIF2_BCLK_DIV - [8:4] */ 2655 #define WM8994_AIF2_BCLK_DIV_SHIFT 4 /* AIF2_BCLK_DIV - [8:4] */ 2656 #define WM8994_AIF2_BCLK_DIV_WIDTH 5 /* AIF2_BCLK_DIV - [8:4] */ 2657 2658 /* 2659 * R788 (0x314) - AIF2ADC LRCLK 2660 */ 2661 #define WM8994_AIF2ADC_LRCLK_DIR 0x0800 /* AIF2ADC_LRCLK_DIR */ 2662 #define WM8994_AIF2ADC_LRCLK_DIR_MASK 0x0800 /* AIF2ADC_LRCLK_DIR */ 2663 #define WM8994_AIF2ADC_LRCLK_DIR_SHIFT 11 /* AIF2ADC_LRCLK_DIR */ 2664 #define WM8994_AIF2ADC_LRCLK_DIR_WIDTH 1 /* AIF2ADC_LRCLK_DIR */ 2665 #define WM8994_AIF2ADC_RATE_MASK 0x07FF /* AIF2ADC_RATE - [10:0] */ 2666 #define WM8994_AIF2ADC_RATE_SHIFT 0 /* AIF2ADC_RATE - [10:0] */ 2667 #define WM8994_AIF2ADC_RATE_WIDTH 11 /* AIF2ADC_RATE - [10:0] */ 2668 2669 /* 2670 * R789 (0x315) - AIF2DAC LRCLK 2671 */ 2672 #define WM8994_AIF2DAC_LRCLK_DIR 0x0800 /* AIF2DAC_LRCLK_DIR */ 2673 #define WM8994_AIF2DAC_LRCLK_DIR_MASK 0x0800 /* AIF2DAC_LRCLK_DIR */ 2674 #define WM8994_AIF2DAC_LRCLK_DIR_SHIFT 11 /* AIF2DAC_LRCLK_DIR */ 2675 #define WM8994_AIF2DAC_LRCLK_DIR_WIDTH 1 /* AIF2DAC_LRCLK_DIR */ 2676 #define WM8994_AIF2DAC_RATE_MASK 0x07FF /* AIF2DAC_RATE - [10:0] */ 2677 #define WM8994_AIF2DAC_RATE_SHIFT 0 /* AIF2DAC_RATE - [10:0] */ 2678 #define WM8994_AIF2DAC_RATE_WIDTH 11 /* AIF2DAC_RATE - [10:0] */ 2679 2680 /* 2681 * R790 (0x316) - AIF2DAC Data 2682 */ 2683 #define WM8994_AIF2DACL_DAT_INV 0x0002 /* AIF2DACL_DAT_INV */ 2684 #define WM8994_AIF2DACL_DAT_INV_MASK 0x0002 /* AIF2DACL_DAT_INV */ 2685 #define WM8994_AIF2DACL_DAT_INV_SHIFT 1 /* AIF2DACL_DAT_INV */ 2686 #define WM8994_AIF2DACL_DAT_INV_WIDTH 1 /* AIF2DACL_DAT_INV */ 2687 #define WM8994_AIF2DACR_DAT_INV 0x0001 /* AIF2DACR_DAT_INV */ 2688 #define WM8994_AIF2DACR_DAT_INV_MASK 0x0001 /* AIF2DACR_DAT_INV */ 2689 #define WM8994_AIF2DACR_DAT_INV_SHIFT 0 /* AIF2DACR_DAT_INV */ 2690 #define WM8994_AIF2DACR_DAT_INV_WIDTH 1 /* AIF2DACR_DAT_INV */ 2691 2692 /* 2693 * R791 (0x317) - AIF2ADC Data 2694 */ 2695 #define WM8994_AIF2ADCL_DAT_INV 0x0002 /* AIF2ADCL_DAT_INV */ 2696 #define WM8994_AIF2ADCL_DAT_INV_MASK 0x0002 /* AIF2ADCL_DAT_INV */ 2697 #define WM8994_AIF2ADCL_DAT_INV_SHIFT 1 /* AIF2ADCL_DAT_INV */ 2698 #define WM8994_AIF2ADCL_DAT_INV_WIDTH 1 /* AIF2ADCL_DAT_INV */ 2699 #define WM8994_AIF2ADCR_DAT_INV 0x0001 /* AIF2ADCR_DAT_INV */ 2700 #define WM8994_AIF2ADCR_DAT_INV_MASK 0x0001 /* AIF2ADCR_DAT_INV */ 2701 #define WM8994_AIF2ADCR_DAT_INV_SHIFT 0 /* AIF2ADCR_DAT_INV */ 2702 #define WM8994_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */ 2703 2704 /* 2705 * R800 (0x320) - AIF3 Control (1) 2706 */ 2707 #define WM8958_AIF3_LRCLK_INV 0x0080 /* AIF3_LRCLK_INV */ 2708 #define WM8958_AIF3_LRCLK_INV_MASK 0x0080 /* AIF3_LRCLK_INV */ 2709 #define WM8958_AIF3_LRCLK_INV_SHIFT 7 /* AIF3_LRCLK_INV */ 2710 #define WM8958_AIF3_LRCLK_INV_WIDTH 1 /* AIF3_LRCLK_INV */ 2711 #define WM8958_AIF3_WL_MASK 0x0060 /* AIF3_WL - [6:5] */ 2712 #define WM8958_AIF3_WL_SHIFT 5 /* AIF3_WL - [6:5] */ 2713 #define WM8958_AIF3_WL_WIDTH 2 /* AIF3_WL - [6:5] */ 2714 #define WM8958_AIF3_FMT_MASK 0x0018 /* AIF3_FMT - [4:3] */ 2715 #define WM8958_AIF3_FMT_SHIFT 3 /* AIF3_FMT - [4:3] */ 2716 #define WM8958_AIF3_FMT_WIDTH 2 /* AIF3_FMT - [4:3] */ 2717 2718 /* 2719 * R801 (0x321) - AIF3 Control (2) 2720 */ 2721 #define WM8958_AIF3DAC_BOOST_MASK 0x0C00 /* AIF3DAC_BOOST - [11:10] */ 2722 #define WM8958_AIF3DAC_BOOST_SHIFT 10 /* AIF3DAC_BOOST - [11:10] */ 2723 #define WM8958_AIF3DAC_BOOST_WIDTH 2 /* AIF3DAC_BOOST - [11:10] */ 2724 #define WM8958_AIF3DAC_COMP 0x0010 /* AIF3DAC_COMP */ 2725 #define WM8958_AIF3DAC_COMP_MASK 0x0010 /* AIF3DAC_COMP */ 2726 #define WM8958_AIF3DAC_COMP_SHIFT 4 /* AIF3DAC_COMP */ 2727 #define WM8958_AIF3DAC_COMP_WIDTH 1 /* AIF3DAC_COMP */ 2728 #define WM8958_AIF3DAC_COMPMODE 0x0008 /* AIF3DAC_COMPMODE */ 2729 #define WM8958_AIF3DAC_COMPMODE_MASK 0x0008 /* AIF3DAC_COMPMODE */ 2730 #define WM8958_AIF3DAC_COMPMODE_SHIFT 3 /* AIF3DAC_COMPMODE */ 2731 #define WM8958_AIF3DAC_COMPMODE_WIDTH 1 /* AIF3DAC_COMPMODE */ 2732 #define WM8958_AIF3ADC_COMP 0x0004 /* AIF3ADC_COMP */ 2733 #define WM8958_AIF3ADC_COMP_MASK 0x0004 /* AIF3ADC_COMP */ 2734 #define WM8958_AIF3ADC_COMP_SHIFT 2 /* AIF3ADC_COMP */ 2735 #define WM8958_AIF3ADC_COMP_WIDTH 1 /* AIF3ADC_COMP */ 2736 #define WM8958_AIF3ADC_COMPMODE 0x0002 /* AIF3ADC_COMPMODE */ 2737 #define WM8958_AIF3ADC_COMPMODE_MASK 0x0002 /* AIF3ADC_COMPMODE */ 2738 #define WM8958_AIF3ADC_COMPMODE_SHIFT 1 /* AIF3ADC_COMPMODE */ 2739 #define WM8958_AIF3ADC_COMPMODE_WIDTH 1 /* AIF3ADC_COMPMODE */ 2740 #define WM8958_AIF3_LOOPBACK 0x0001 /* AIF3_LOOPBACK */ 2741 #define WM8958_AIF3_LOOPBACK_MASK 0x0001 /* AIF3_LOOPBACK */ 2742 #define WM8958_AIF3_LOOPBACK_SHIFT 0 /* AIF3_LOOPBACK */ 2743 #define WM8958_AIF3_LOOPBACK_WIDTH 1 /* AIF3_LOOPBACK */ 2744 2745 /* 2746 * R802 (0x322) - AIF3DAC Data 2747 */ 2748 #define WM8958_AIF3DAC_DAT_INV 0x0001 /* AIF3DAC_DAT_INV */ 2749 #define WM8958_AIF3DAC_DAT_INV_MASK 0x0001 /* AIF3DAC_DAT_INV */ 2750 #define WM8958_AIF3DAC_DAT_INV_SHIFT 0 /* AIF3DAC_DAT_INV */ 2751 #define WM8958_AIF3DAC_DAT_INV_WIDTH 1 /* AIF3DAC_DAT_INV */ 2752 2753 /* 2754 * R803 (0x323) - AIF3ADC Data 2755 */ 2756 #define WM8958_AIF3ADC_DAT_INV 0x0001 /* AIF3ADC_DAT_INV */ 2757 #define WM8958_AIF3ADC_DAT_INV_MASK 0x0001 /* AIF3ADC_DAT_INV */ 2758 #define WM8958_AIF3ADC_DAT_INV_SHIFT 0 /* AIF3ADC_DAT_INV */ 2759 #define WM8958_AIF3ADC_DAT_INV_WIDTH 1 /* AIF3ADC_DAT_INV */ 2760 2761 /* 2762 * R1024 (0x400) - AIF1 ADC1 Left Volume 2763 */ 2764 #define WM8994_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */ 2765 #define WM8994_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */ 2766 #define WM8994_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */ 2767 #define WM8994_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */ 2768 #define WM8994_AIF1ADC1L_VOL_MASK 0x00FF /* AIF1ADC1L_VOL - [7:0] */ 2769 #define WM8994_AIF1ADC1L_VOL_SHIFT 0 /* AIF1ADC1L_VOL - [7:0] */ 2770 #define WM8994_AIF1ADC1L_VOL_WIDTH 8 /* AIF1ADC1L_VOL - [7:0] */ 2771 2772 /* 2773 * R1025 (0x401) - AIF1 ADC1 Right Volume 2774 */ 2775 #define WM8994_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */ 2776 #define WM8994_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */ 2777 #define WM8994_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */ 2778 #define WM8994_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */ 2779 #define WM8994_AIF1ADC1R_VOL_MASK 0x00FF /* AIF1ADC1R_VOL - [7:0] */ 2780 #define WM8994_AIF1ADC1R_VOL_SHIFT 0 /* AIF1ADC1R_VOL - [7:0] */ 2781 #define WM8994_AIF1ADC1R_VOL_WIDTH 8 /* AIF1ADC1R_VOL - [7:0] */ 2782 2783 /* 2784 * R1026 (0x402) - AIF1 DAC1 Left Volume 2785 */ 2786 #define WM8994_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */ 2787 #define WM8994_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */ 2788 #define WM8994_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */ 2789 #define WM8994_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */ 2790 #define WM8994_AIF1DAC1L_VOL_MASK 0x00FF /* AIF1DAC1L_VOL - [7:0] */ 2791 #define WM8994_AIF1DAC1L_VOL_SHIFT 0 /* AIF1DAC1L_VOL - [7:0] */ 2792 #define WM8994_AIF1DAC1L_VOL_WIDTH 8 /* AIF1DAC1L_VOL - [7:0] */ 2793 2794 /* 2795 * R1027 (0x403) - AIF1 DAC1 Right Volume 2796 */ 2797 #define WM8994_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */ 2798 #define WM8994_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */ 2799 #define WM8994_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */ 2800 #define WM8994_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */ 2801 #define WM8994_AIF1DAC1R_VOL_MASK 0x00FF /* AIF1DAC1R_VOL - [7:0] */ 2802 #define WM8994_AIF1DAC1R_VOL_SHIFT 0 /* AIF1DAC1R_VOL - [7:0] */ 2803 #define WM8994_AIF1DAC1R_VOL_WIDTH 8 /* AIF1DAC1R_VOL - [7:0] */ 2804 2805 /* 2806 * R1028 (0x404) - AIF1 ADC2 Left Volume 2807 */ 2808 #define WM8994_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */ 2809 #define WM8994_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */ 2810 #define WM8994_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */ 2811 #define WM8994_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */ 2812 #define WM8994_AIF1ADC2L_VOL_MASK 0x00FF /* AIF1ADC2L_VOL - [7:0] */ 2813 #define WM8994_AIF1ADC2L_VOL_SHIFT 0 /* AIF1ADC2L_VOL - [7:0] */ 2814 #define WM8994_AIF1ADC2L_VOL_WIDTH 8 /* AIF1ADC2L_VOL - [7:0] */ 2815 2816 /* 2817 * R1029 (0x405) - AIF1 ADC2 Right Volume 2818 */ 2819 #define WM8994_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */ 2820 #define WM8994_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */ 2821 #define WM8994_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */ 2822 #define WM8994_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */ 2823 #define WM8994_AIF1ADC2R_VOL_MASK 0x00FF /* AIF1ADC2R_VOL - [7:0] */ 2824 #define WM8994_AIF1ADC2R_VOL_SHIFT 0 /* AIF1ADC2R_VOL - [7:0] */ 2825 #define WM8994_AIF1ADC2R_VOL_WIDTH 8 /* AIF1ADC2R_VOL - [7:0] */ 2826 2827 /* 2828 * R1030 (0x406) - AIF1 DAC2 Left Volume 2829 */ 2830 #define WM8994_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */ 2831 #define WM8994_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */ 2832 #define WM8994_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */ 2833 #define WM8994_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */ 2834 #define WM8994_AIF1DAC2L_VOL_MASK 0x00FF /* AIF1DAC2L_VOL - [7:0] */ 2835 #define WM8994_AIF1DAC2L_VOL_SHIFT 0 /* AIF1DAC2L_VOL - [7:0] */ 2836 #define WM8994_AIF1DAC2L_VOL_WIDTH 8 /* AIF1DAC2L_VOL - [7:0] */ 2837 2838 /* 2839 * R1031 (0x407) - AIF1 DAC2 Right Volume 2840 */ 2841 #define WM8994_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */ 2842 #define WM8994_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */ 2843 #define WM8994_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */ 2844 #define WM8994_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */ 2845 #define WM8994_AIF1DAC2R_VOL_MASK 0x00FF /* AIF1DAC2R_VOL - [7:0] */ 2846 #define WM8994_AIF1DAC2R_VOL_SHIFT 0 /* AIF1DAC2R_VOL - [7:0] */ 2847 #define WM8994_AIF1DAC2R_VOL_WIDTH 8 /* AIF1DAC2R_VOL - [7:0] */ 2848 2849 /* 2850 * R1040 (0x410) - AIF1 ADC1 Filters 2851 */ 2852 #define WM8994_AIF1ADC_4FS 0x8000 /* AIF1ADC_4FS */ 2853 #define WM8994_AIF1ADC_4FS_MASK 0x8000 /* AIF1ADC_4FS */ 2854 #define WM8994_AIF1ADC_4FS_SHIFT 15 /* AIF1ADC_4FS */ 2855 #define WM8994_AIF1ADC_4FS_WIDTH 1 /* AIF1ADC_4FS */ 2856 #define WM8994_AIF1ADC1_HPF_CUT_MASK 0x6000 /* AIF1ADC1_HPF_CUT - [14:13] */ 2857 #define WM8994_AIF1ADC1_HPF_CUT_SHIFT 13 /* AIF1ADC1_HPF_CUT - [14:13] */ 2858 #define WM8994_AIF1ADC1_HPF_CUT_WIDTH 2 /* AIF1ADC1_HPF_CUT - [14:13] */ 2859 #define WM8994_AIF1ADC1L_HPF 0x1000 /* AIF1ADC1L_HPF */ 2860 #define WM8994_AIF1ADC1L_HPF_MASK 0x1000 /* AIF1ADC1L_HPF */ 2861 #define WM8994_AIF1ADC1L_HPF_SHIFT 12 /* AIF1ADC1L_HPF */ 2862 #define WM8994_AIF1ADC1L_HPF_WIDTH 1 /* AIF1ADC1L_HPF */ 2863 #define WM8994_AIF1ADC1R_HPF 0x0800 /* AIF1ADC1R_HPF */ 2864 #define WM8994_AIF1ADC1R_HPF_MASK 0x0800 /* AIF1ADC1R_HPF */ 2865 #define WM8994_AIF1ADC1R_HPF_SHIFT 11 /* AIF1ADC1R_HPF */ 2866 #define WM8994_AIF1ADC1R_HPF_WIDTH 1 /* AIF1ADC1R_HPF */ 2867 2868 /* 2869 * R1041 (0x411) - AIF1 ADC2 Filters 2870 */ 2871 #define WM8994_AIF1ADC2_HPF_CUT_MASK 0x6000 /* AIF1ADC2_HPF_CUT - [14:13] */ 2872 #define WM8994_AIF1ADC2_HPF_CUT_SHIFT 13 /* AIF1ADC2_HPF_CUT - [14:13] */ 2873 #define WM8994_AIF1ADC2_HPF_CUT_WIDTH 2 /* AIF1ADC2_HPF_CUT - [14:13] */ 2874 #define WM8994_AIF1ADC2L_HPF 0x1000 /* AIF1ADC2L_HPF */ 2875 #define WM8994_AIF1ADC2L_HPF_MASK 0x1000 /* AIF1ADC2L_HPF */ 2876 #define WM8994_AIF1ADC2L_HPF_SHIFT 12 /* AIF1ADC2L_HPF */ 2877 #define WM8994_AIF1ADC2L_HPF_WIDTH 1 /* AIF1ADC2L_HPF */ 2878 #define WM8994_AIF1ADC2R_HPF 0x0800 /* AIF1ADC2R_HPF */ 2879 #define WM8994_AIF1ADC2R_HPF_MASK 0x0800 /* AIF1ADC2R_HPF */ 2880 #define WM8994_AIF1ADC2R_HPF_SHIFT 11 /* AIF1ADC2R_HPF */ 2881 #define WM8994_AIF1ADC2R_HPF_WIDTH 1 /* AIF1ADC2R_HPF */ 2882 2883 /* 2884 * R1056 (0x420) - AIF1 DAC1 Filters (1) 2885 */ 2886 #define WM8994_AIF1DAC1_MUTE 0x0200 /* AIF1DAC1_MUTE */ 2887 #define WM8994_AIF1DAC1_MUTE_MASK 0x0200 /* AIF1DAC1_MUTE */ 2888 #define WM8994_AIF1DAC1_MUTE_SHIFT 9 /* AIF1DAC1_MUTE */ 2889 #define WM8994_AIF1DAC1_MUTE_WIDTH 1 /* AIF1DAC1_MUTE */ 2890 #define WM8994_AIF1DAC1_MONO 0x0080 /* AIF1DAC1_MONO */ 2891 #define WM8994_AIF1DAC1_MONO_MASK 0x0080 /* AIF1DAC1_MONO */ 2892 #define WM8994_AIF1DAC1_MONO_SHIFT 7 /* AIF1DAC1_MONO */ 2893 #define WM8994_AIF1DAC1_MONO_WIDTH 1 /* AIF1DAC1_MONO */ 2894 #define WM8994_AIF1DAC1_MUTERATE 0x0020 /* AIF1DAC1_MUTERATE */ 2895 #define WM8994_AIF1DAC1_MUTERATE_MASK 0x0020 /* AIF1DAC1_MUTERATE */ 2896 #define WM8994_AIF1DAC1_MUTERATE_SHIFT 5 /* AIF1DAC1_MUTERATE */ 2897 #define WM8994_AIF1DAC1_MUTERATE_WIDTH 1 /* AIF1DAC1_MUTERATE */ 2898 #define WM8994_AIF1DAC1_UNMUTE_RAMP 0x0010 /* AIF1DAC1_UNMUTE_RAMP */ 2899 #define WM8994_AIF1DAC1_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC1_UNMUTE_RAMP */ 2900 #define WM8994_AIF1DAC1_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC1_UNMUTE_RAMP */ 2901 #define WM8994_AIF1DAC1_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC1_UNMUTE_RAMP */ 2902 #define WM8994_AIF1DAC1_DEEMP_MASK 0x0006 /* AIF1DAC1_DEEMP - [2:1] */ 2903 #define WM8994_AIF1DAC1_DEEMP_SHIFT 1 /* AIF1DAC1_DEEMP - [2:1] */ 2904 #define WM8994_AIF1DAC1_DEEMP_WIDTH 2 /* AIF1DAC1_DEEMP - [2:1] */ 2905 2906 /* 2907 * R1057 (0x421) - AIF1 DAC1 Filters (2) 2908 */ 2909 #define WM8994_AIF1DAC1_3D_GAIN_MASK 0x3E00 /* AIF1DAC1_3D_GAIN - [13:9] */ 2910 #define WM8994_AIF1DAC1_3D_GAIN_SHIFT 9 /* AIF1DAC1_3D_GAIN - [13:9] */ 2911 #define WM8994_AIF1DAC1_3D_GAIN_WIDTH 5 /* AIF1DAC1_3D_GAIN - [13:9] */ 2912 #define WM8994_AIF1DAC1_3D_ENA 0x0100 /* AIF1DAC1_3D_ENA */ 2913 #define WM8994_AIF1DAC1_3D_ENA_MASK 0x0100 /* AIF1DAC1_3D_ENA */ 2914 #define WM8994_AIF1DAC1_3D_ENA_SHIFT 8 /* AIF1DAC1_3D_ENA */ 2915 #define WM8994_AIF1DAC1_3D_ENA_WIDTH 1 /* AIF1DAC1_3D_ENA */ 2916 2917 /* 2918 * R1058 (0x422) - AIF1 DAC2 Filters (1) 2919 */ 2920 #define WM8994_AIF1DAC2_MUTE 0x0200 /* AIF1DAC2_MUTE */ 2921 #define WM8994_AIF1DAC2_MUTE_MASK 0x0200 /* AIF1DAC2_MUTE */ 2922 #define WM8994_AIF1DAC2_MUTE_SHIFT 9 /* AIF1DAC2_MUTE */ 2923 #define WM8994_AIF1DAC2_MUTE_WIDTH 1 /* AIF1DAC2_MUTE */ 2924 #define WM8994_AIF1DAC2_MONO 0x0080 /* AIF1DAC2_MONO */ 2925 #define WM8994_AIF1DAC2_MONO_MASK 0x0080 /* AIF1DAC2_MONO */ 2926 #define WM8994_AIF1DAC2_MONO_SHIFT 7 /* AIF1DAC2_MONO */ 2927 #define WM8994_AIF1DAC2_MONO_WIDTH 1 /* AIF1DAC2_MONO */ 2928 #define WM8994_AIF1DAC2_MUTERATE 0x0020 /* AIF1DAC2_MUTERATE */ 2929 #define WM8994_AIF1DAC2_MUTERATE_MASK 0x0020 /* AIF1DAC2_MUTERATE */ 2930 #define WM8994_AIF1DAC2_MUTERATE_SHIFT 5 /* AIF1DAC2_MUTERATE */ 2931 #define WM8994_AIF1DAC2_MUTERATE_WIDTH 1 /* AIF1DAC2_MUTERATE */ 2932 #define WM8994_AIF1DAC2_UNMUTE_RAMP 0x0010 /* AIF1DAC2_UNMUTE_RAMP */ 2933 #define WM8994_AIF1DAC2_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC2_UNMUTE_RAMP */ 2934 #define WM8994_AIF1DAC2_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC2_UNMUTE_RAMP */ 2935 #define WM8994_AIF1DAC2_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC2_UNMUTE_RAMP */ 2936 #define WM8994_AIF1DAC2_DEEMP_MASK 0x0006 /* AIF1DAC2_DEEMP - [2:1] */ 2937 #define WM8994_AIF1DAC2_DEEMP_SHIFT 1 /* AIF1DAC2_DEEMP - [2:1] */ 2938 #define WM8994_AIF1DAC2_DEEMP_WIDTH 2 /* AIF1DAC2_DEEMP - [2:1] */ 2939 2940 /* 2941 * R1059 (0x423) - AIF1 DAC2 Filters (2) 2942 */ 2943 #define WM8994_AIF1DAC2_3D_GAIN_MASK 0x3E00 /* AIF1DAC2_3D_GAIN - [13:9] */ 2944 #define WM8994_AIF1DAC2_3D_GAIN_SHIFT 9 /* AIF1DAC2_3D_GAIN - [13:9] */ 2945 #define WM8994_AIF1DAC2_3D_GAIN_WIDTH 5 /* AIF1DAC2_3D_GAIN - [13:9] */ 2946 #define WM8994_AIF1DAC2_3D_ENA 0x0100 /* AIF1DAC2_3D_ENA */ 2947 #define WM8994_AIF1DAC2_3D_ENA_MASK 0x0100 /* AIF1DAC2_3D_ENA */ 2948 #define WM8994_AIF1DAC2_3D_ENA_SHIFT 8 /* AIF1DAC2_3D_ENA */ 2949 #define WM8994_AIF1DAC2_3D_ENA_WIDTH 1 /* AIF1DAC2_3D_ENA */ 2950 2951 /* 2952 * R1088 (0x440) - AIF1 DRC1 (1) 2953 */ 2954 #define WM8994_AIF1DRC1_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ 2955 #define WM8994_AIF1DRC1_SIG_DET_RMS_SHIFT 11 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ 2956 #define WM8994_AIF1DRC1_SIG_DET_RMS_WIDTH 5 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ 2957 #define WM8994_AIF1DRC1_SIG_DET_PK_MASK 0x0600 /* AIF1DRC1_SIG_DET_PK - [10:9] */ 2958 #define WM8994_AIF1DRC1_SIG_DET_PK_SHIFT 9 /* AIF1DRC1_SIG_DET_PK - [10:9] */ 2959 #define WM8994_AIF1DRC1_SIG_DET_PK_WIDTH 2 /* AIF1DRC1_SIG_DET_PK - [10:9] */ 2960 #define WM8994_AIF1DRC1_NG_ENA 0x0100 /* AIF1DRC1_NG_ENA */ 2961 #define WM8994_AIF1DRC1_NG_ENA_MASK 0x0100 /* AIF1DRC1_NG_ENA */ 2962 #define WM8994_AIF1DRC1_NG_ENA_SHIFT 8 /* AIF1DRC1_NG_ENA */ 2963 #define WM8994_AIF1DRC1_NG_ENA_WIDTH 1 /* AIF1DRC1_NG_ENA */ 2964 #define WM8994_AIF1DRC1_SIG_DET_MODE 0x0080 /* AIF1DRC1_SIG_DET_MODE */ 2965 #define WM8994_AIF1DRC1_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC1_SIG_DET_MODE */ 2966 #define WM8994_AIF1DRC1_SIG_DET_MODE_SHIFT 7 /* AIF1DRC1_SIG_DET_MODE */ 2967 #define WM8994_AIF1DRC1_SIG_DET_MODE_WIDTH 1 /* AIF1DRC1_SIG_DET_MODE */ 2968 #define WM8994_AIF1DRC1_SIG_DET 0x0040 /* AIF1DRC1_SIG_DET */ 2969 #define WM8994_AIF1DRC1_SIG_DET_MASK 0x0040 /* AIF1DRC1_SIG_DET */ 2970 #define WM8994_AIF1DRC1_SIG_DET_SHIFT 6 /* AIF1DRC1_SIG_DET */ 2971 #define WM8994_AIF1DRC1_SIG_DET_WIDTH 1 /* AIF1DRC1_SIG_DET */ 2972 #define WM8994_AIF1DRC1_KNEE2_OP_ENA 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */ 2973 #define WM8994_AIF1DRC1_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */ 2974 #define WM8994_AIF1DRC1_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC1_KNEE2_OP_ENA */ 2975 #define WM8994_AIF1DRC1_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC1_KNEE2_OP_ENA */ 2976 #define WM8994_AIF1DRC1_QR 0x0010 /* AIF1DRC1_QR */ 2977 #define WM8994_AIF1DRC1_QR_MASK 0x0010 /* AIF1DRC1_QR */ 2978 #define WM8994_AIF1DRC1_QR_SHIFT 4 /* AIF1DRC1_QR */ 2979 #define WM8994_AIF1DRC1_QR_WIDTH 1 /* AIF1DRC1_QR */ 2980 #define WM8994_AIF1DRC1_ANTICLIP 0x0008 /* AIF1DRC1_ANTICLIP */ 2981 #define WM8994_AIF1DRC1_ANTICLIP_MASK 0x0008 /* AIF1DRC1_ANTICLIP */ 2982 #define WM8994_AIF1DRC1_ANTICLIP_SHIFT 3 /* AIF1DRC1_ANTICLIP */ 2983 #define WM8994_AIF1DRC1_ANTICLIP_WIDTH 1 /* AIF1DRC1_ANTICLIP */ 2984 #define WM8994_AIF1DAC1_DRC_ENA 0x0004 /* AIF1DAC1_DRC_ENA */ 2985 #define WM8994_AIF1DAC1_DRC_ENA_MASK 0x0004 /* AIF1DAC1_DRC_ENA */ 2986 #define WM8994_AIF1DAC1_DRC_ENA_SHIFT 2 /* AIF1DAC1_DRC_ENA */ 2987 #define WM8994_AIF1DAC1_DRC_ENA_WIDTH 1 /* AIF1DAC1_DRC_ENA */ 2988 #define WM8994_AIF1ADC1L_DRC_ENA 0x0002 /* AIF1ADC1L_DRC_ENA */ 2989 #define WM8994_AIF1ADC1L_DRC_ENA_MASK 0x0002 /* AIF1ADC1L_DRC_ENA */ 2990 #define WM8994_AIF1ADC1L_DRC_ENA_SHIFT 1 /* AIF1ADC1L_DRC_ENA */ 2991 #define WM8994_AIF1ADC1L_DRC_ENA_WIDTH 1 /* AIF1ADC1L_DRC_ENA */ 2992 #define WM8994_AIF1ADC1R_DRC_ENA 0x0001 /* AIF1ADC1R_DRC_ENA */ 2993 #define WM8994_AIF1ADC1R_DRC_ENA_MASK 0x0001 /* AIF1ADC1R_DRC_ENA */ 2994 #define WM8994_AIF1ADC1R_DRC_ENA_SHIFT 0 /* AIF1ADC1R_DRC_ENA */ 2995 #define WM8994_AIF1ADC1R_DRC_ENA_WIDTH 1 /* AIF1ADC1R_DRC_ENA */ 2996 2997 /* 2998 * R1089 (0x441) - AIF1 DRC1 (2) 2999 */ 3000 #define WM8994_AIF1DRC1_ATK_MASK 0x1E00 /* AIF1DRC1_ATK - [12:9] */ 3001 #define WM8994_AIF1DRC1_ATK_SHIFT 9 /* AIF1DRC1_ATK - [12:9] */ 3002 #define WM8994_AIF1DRC1_ATK_WIDTH 4 /* AIF1DRC1_ATK - [12:9] */ 3003 #define WM8994_AIF1DRC1_DCY_MASK 0x01E0 /* AIF1DRC1_DCY - [8:5] */ 3004 #define WM8994_AIF1DRC1_DCY_SHIFT 5 /* AIF1DRC1_DCY - [8:5] */ 3005 #define WM8994_AIF1DRC1_DCY_WIDTH 4 /* AIF1DRC1_DCY - [8:5] */ 3006 #define WM8994_AIF1DRC1_MINGAIN_MASK 0x001C /* AIF1DRC1_MINGAIN - [4:2] */ 3007 #define WM8994_AIF1DRC1_MINGAIN_SHIFT 2 /* AIF1DRC1_MINGAIN - [4:2] */ 3008 #define WM8994_AIF1DRC1_MINGAIN_WIDTH 3 /* AIF1DRC1_MINGAIN - [4:2] */ 3009 #define WM8994_AIF1DRC1_MAXGAIN_MASK 0x0003 /* AIF1DRC1_MAXGAIN - [1:0] */ 3010 #define WM8994_AIF1DRC1_MAXGAIN_SHIFT 0 /* AIF1DRC1_MAXGAIN - [1:0] */ 3011 #define WM8994_AIF1DRC1_MAXGAIN_WIDTH 2 /* AIF1DRC1_MAXGAIN - [1:0] */ 3012 3013 /* 3014 * R1090 (0x442) - AIF1 DRC1 (3) 3015 */ 3016 #define WM8994_AIF1DRC1_NG_MINGAIN_MASK 0xF000 /* AIF1DRC1_NG_MINGAIN - [15:12] */ 3017 #define WM8994_AIF1DRC1_NG_MINGAIN_SHIFT 12 /* AIF1DRC1_NG_MINGAIN - [15:12] */ 3018 #define WM8994_AIF1DRC1_NG_MINGAIN_WIDTH 4 /* AIF1DRC1_NG_MINGAIN - [15:12] */ 3019 #define WM8994_AIF1DRC1_NG_EXP_MASK 0x0C00 /* AIF1DRC1_NG_EXP - [11:10] */ 3020 #define WM8994_AIF1DRC1_NG_EXP_SHIFT 10 /* AIF1DRC1_NG_EXP - [11:10] */ 3021 #define WM8994_AIF1DRC1_NG_EXP_WIDTH 2 /* AIF1DRC1_NG_EXP - [11:10] */ 3022 #define WM8994_AIF1DRC1_QR_THR_MASK 0x0300 /* AIF1DRC1_QR_THR - [9:8] */ 3023 #define WM8994_AIF1DRC1_QR_THR_SHIFT 8 /* AIF1DRC1_QR_THR - [9:8] */ 3024 #define WM8994_AIF1DRC1_QR_THR_WIDTH 2 /* AIF1DRC1_QR_THR - [9:8] */ 3025 #define WM8994_AIF1DRC1_QR_DCY_MASK 0x00C0 /* AIF1DRC1_QR_DCY - [7:6] */ 3026 #define WM8994_AIF1DRC1_QR_DCY_SHIFT 6 /* AIF1DRC1_QR_DCY - [7:6] */ 3027 #define WM8994_AIF1DRC1_QR_DCY_WIDTH 2 /* AIF1DRC1_QR_DCY - [7:6] */ 3028 #define WM8994_AIF1DRC1_HI_COMP_MASK 0x0038 /* AIF1DRC1_HI_COMP - [5:3] */ 3029 #define WM8994_AIF1DRC1_HI_COMP_SHIFT 3 /* AIF1DRC1_HI_COMP - [5:3] */ 3030 #define WM8994_AIF1DRC1_HI_COMP_WIDTH 3 /* AIF1DRC1_HI_COMP - [5:3] */ 3031 #define WM8994_AIF1DRC1_LO_COMP_MASK 0x0007 /* AIF1DRC1_LO_COMP - [2:0] */ 3032 #define WM8994_AIF1DRC1_LO_COMP_SHIFT 0 /* AIF1DRC1_LO_COMP - [2:0] */ 3033 #define WM8994_AIF1DRC1_LO_COMP_WIDTH 3 /* AIF1DRC1_LO_COMP - [2:0] */ 3034 3035 /* 3036 * R1091 (0x443) - AIF1 DRC1 (4) 3037 */ 3038 #define WM8994_AIF1DRC1_KNEE_IP_MASK 0x07E0 /* AIF1DRC1_KNEE_IP - [10:5] */ 3039 #define WM8994_AIF1DRC1_KNEE_IP_SHIFT 5 /* AIF1DRC1_KNEE_IP - [10:5] */ 3040 #define WM8994_AIF1DRC1_KNEE_IP_WIDTH 6 /* AIF1DRC1_KNEE_IP - [10:5] */ 3041 #define WM8994_AIF1DRC1_KNEE_OP_MASK 0x001F /* AIF1DRC1_KNEE_OP - [4:0] */ 3042 #define WM8994_AIF1DRC1_KNEE_OP_SHIFT 0 /* AIF1DRC1_KNEE_OP - [4:0] */ 3043 #define WM8994_AIF1DRC1_KNEE_OP_WIDTH 5 /* AIF1DRC1_KNEE_OP - [4:0] */ 3044 3045 /* 3046 * R1092 (0x444) - AIF1 DRC1 (5) 3047 */ 3048 #define WM8994_AIF1DRC1_KNEE2_IP_MASK 0x03E0 /* AIF1DRC1_KNEE2_IP - [9:5] */ 3049 #define WM8994_AIF1DRC1_KNEE2_IP_SHIFT 5 /* AIF1DRC1_KNEE2_IP - [9:5] */ 3050 #define WM8994_AIF1DRC1_KNEE2_IP_WIDTH 5 /* AIF1DRC1_KNEE2_IP - [9:5] */ 3051 #define WM8994_AIF1DRC1_KNEE2_OP_MASK 0x001F /* AIF1DRC1_KNEE2_OP - [4:0] */ 3052 #define WM8994_AIF1DRC1_KNEE2_OP_SHIFT 0 /* AIF1DRC1_KNEE2_OP - [4:0] */ 3053 #define WM8994_AIF1DRC1_KNEE2_OP_WIDTH 5 /* AIF1DRC1_KNEE2_OP - [4:0] */ 3054 3055 /* 3056 * R1104 (0x450) - AIF1 DRC2 (1) 3057 */ 3058 #define WM8994_AIF1DRC2_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ 3059 #define WM8994_AIF1DRC2_SIG_DET_RMS_SHIFT 11 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ 3060 #define WM8994_AIF1DRC2_SIG_DET_RMS_WIDTH 5 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ 3061 #define WM8994_AIF1DRC2_SIG_DET_PK_MASK 0x0600 /* AIF1DRC2_SIG_DET_PK - [10:9] */ 3062 #define WM8994_AIF1DRC2_SIG_DET_PK_SHIFT 9 /* AIF1DRC2_SIG_DET_PK - [10:9] */ 3063 #define WM8994_AIF1DRC2_SIG_DET_PK_WIDTH 2 /* AIF1DRC2_SIG_DET_PK - [10:9] */ 3064 #define WM8994_AIF1DRC2_NG_ENA 0x0100 /* AIF1DRC2_NG_ENA */ 3065 #define WM8994_AIF1DRC2_NG_ENA_MASK 0x0100 /* AIF1DRC2_NG_ENA */ 3066 #define WM8994_AIF1DRC2_NG_ENA_SHIFT 8 /* AIF1DRC2_NG_ENA */ 3067 #define WM8994_AIF1DRC2_NG_ENA_WIDTH 1 /* AIF1DRC2_NG_ENA */ 3068 #define WM8994_AIF1DRC2_SIG_DET_MODE 0x0080 /* AIF1DRC2_SIG_DET_MODE */ 3069 #define WM8994_AIF1DRC2_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC2_SIG_DET_MODE */ 3070 #define WM8994_AIF1DRC2_SIG_DET_MODE_SHIFT 7 /* AIF1DRC2_SIG_DET_MODE */ 3071 #define WM8994_AIF1DRC2_SIG_DET_MODE_WIDTH 1 /* AIF1DRC2_SIG_DET_MODE */ 3072 #define WM8994_AIF1DRC2_SIG_DET 0x0040 /* AIF1DRC2_SIG_DET */ 3073 #define WM8994_AIF1DRC2_SIG_DET_MASK 0x0040 /* AIF1DRC2_SIG_DET */ 3074 #define WM8994_AIF1DRC2_SIG_DET_SHIFT 6 /* AIF1DRC2_SIG_DET */ 3075 #define WM8994_AIF1DRC2_SIG_DET_WIDTH 1 /* AIF1DRC2_SIG_DET */ 3076 #define WM8994_AIF1DRC2_KNEE2_OP_ENA 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */ 3077 #define WM8994_AIF1DRC2_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */ 3078 #define WM8994_AIF1DRC2_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC2_KNEE2_OP_ENA */ 3079 #define WM8994_AIF1DRC2_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC2_KNEE2_OP_ENA */ 3080 #define WM8994_AIF1DRC2_QR 0x0010 /* AIF1DRC2_QR */ 3081 #define WM8994_AIF1DRC2_QR_MASK 0x0010 /* AIF1DRC2_QR */ 3082 #define WM8994_AIF1DRC2_QR_SHIFT 4 /* AIF1DRC2_QR */ 3083 #define WM8994_AIF1DRC2_QR_WIDTH 1 /* AIF1DRC2_QR */ 3084 #define WM8994_AIF1DRC2_ANTICLIP 0x0008 /* AIF1DRC2_ANTICLIP */ 3085 #define WM8994_AIF1DRC2_ANTICLIP_MASK 0x0008 /* AIF1DRC2_ANTICLIP */ 3086 #define WM8994_AIF1DRC2_ANTICLIP_SHIFT 3 /* AIF1DRC2_ANTICLIP */ 3087 #define WM8994_AIF1DRC2_ANTICLIP_WIDTH 1 /* AIF1DRC2_ANTICLIP */ 3088 #define WM8994_AIF1DAC2_DRC_ENA 0x0004 /* AIF1DAC2_DRC_ENA */ 3089 #define WM8994_AIF1DAC2_DRC_ENA_MASK 0x0004 /* AIF1DAC2_DRC_ENA */ 3090 #define WM8994_AIF1DAC2_DRC_ENA_SHIFT 2 /* AIF1DAC2_DRC_ENA */ 3091 #define WM8994_AIF1DAC2_DRC_ENA_WIDTH 1 /* AIF1DAC2_DRC_ENA */ 3092 #define WM8994_AIF1ADC2L_DRC_ENA 0x0002 /* AIF1ADC2L_DRC_ENA */ 3093 #define WM8994_AIF1ADC2L_DRC_ENA_MASK 0x0002 /* AIF1ADC2L_DRC_ENA */ 3094 #define WM8994_AIF1ADC2L_DRC_ENA_SHIFT 1 /* AIF1ADC2L_DRC_ENA */ 3095 #define WM8994_AIF1ADC2L_DRC_ENA_WIDTH 1 /* AIF1ADC2L_DRC_ENA */ 3096 #define WM8994_AIF1ADC2R_DRC_ENA 0x0001 /* AIF1ADC2R_DRC_ENA */ 3097 #define WM8994_AIF1ADC2R_DRC_ENA_MASK 0x0001 /* AIF1ADC2R_DRC_ENA */ 3098 #define WM8994_AIF1ADC2R_DRC_ENA_SHIFT 0 /* AIF1ADC2R_DRC_ENA */ 3099 #define WM8994_AIF1ADC2R_DRC_ENA_WIDTH 1 /* AIF1ADC2R_DRC_ENA */ 3100 3101 /* 3102 * R1105 (0x451) - AIF1 DRC2 (2) 3103 */ 3104 #define WM8994_AIF1DRC2_ATK_MASK 0x1E00 /* AIF1DRC2_ATK - [12:9] */ 3105 #define WM8994_AIF1DRC2_ATK_SHIFT 9 /* AIF1DRC2_ATK - [12:9] */ 3106 #define WM8994_AIF1DRC2_ATK_WIDTH 4 /* AIF1DRC2_ATK - [12:9] */ 3107 #define WM8994_AIF1DRC2_DCY_MASK 0x01E0 /* AIF1DRC2_DCY - [8:5] */ 3108 #define WM8994_AIF1DRC2_DCY_SHIFT 5 /* AIF1DRC2_DCY - [8:5] */ 3109 #define WM8994_AIF1DRC2_DCY_WIDTH 4 /* AIF1DRC2_DCY - [8:5] */ 3110 #define WM8994_AIF1DRC2_MINGAIN_MASK 0x001C /* AIF1DRC2_MINGAIN - [4:2] */ 3111 #define WM8994_AIF1DRC2_MINGAIN_SHIFT 2 /* AIF1DRC2_MINGAIN - [4:2] */ 3112 #define WM8994_AIF1DRC2_MINGAIN_WIDTH 3 /* AIF1DRC2_MINGAIN - [4:2] */ 3113 #define WM8994_AIF1DRC2_MAXGAIN_MASK 0x0003 /* AIF1DRC2_MAXGAIN - [1:0] */ 3114 #define WM8994_AIF1DRC2_MAXGAIN_SHIFT 0 /* AIF1DRC2_MAXGAIN - [1:0] */ 3115 #define WM8994_AIF1DRC2_MAXGAIN_WIDTH 2 /* AIF1DRC2_MAXGAIN - [1:0] */ 3116 3117 /* 3118 * R1106 (0x452) - AIF1 DRC2 (3) 3119 */ 3120 #define WM8994_AIF1DRC2_NG_MINGAIN_MASK 0xF000 /* AIF1DRC2_NG_MINGAIN - [15:12] */ 3121 #define WM8994_AIF1DRC2_NG_MINGAIN_SHIFT 12 /* AIF1DRC2_NG_MINGAIN - [15:12] */ 3122 #define WM8994_AIF1DRC2_NG_MINGAIN_WIDTH 4 /* AIF1DRC2_NG_MINGAIN - [15:12] */ 3123 #define WM8994_AIF1DRC2_NG_EXP_MASK 0x0C00 /* AIF1DRC2_NG_EXP - [11:10] */ 3124 #define WM8994_AIF1DRC2_NG_EXP_SHIFT 10 /* AIF1DRC2_NG_EXP - [11:10] */ 3125 #define WM8994_AIF1DRC2_NG_EXP_WIDTH 2 /* AIF1DRC2_NG_EXP - [11:10] */ 3126 #define WM8994_AIF1DRC2_QR_THR_MASK 0x0300 /* AIF1DRC2_QR_THR - [9:8] */ 3127 #define WM8994_AIF1DRC2_QR_THR_SHIFT 8 /* AIF1DRC2_QR_THR - [9:8] */ 3128 #define WM8994_AIF1DRC2_QR_THR_WIDTH 2 /* AIF1DRC2_QR_THR - [9:8] */ 3129 #define WM8994_AIF1DRC2_QR_DCY_MASK 0x00C0 /* AIF1DRC2_QR_DCY - [7:6] */ 3130 #define WM8994_AIF1DRC2_QR_DCY_SHIFT 6 /* AIF1DRC2_QR_DCY - [7:6] */ 3131 #define WM8994_AIF1DRC2_QR_DCY_WIDTH 2 /* AIF1DRC2_QR_DCY - [7:6] */ 3132 #define WM8994_AIF1DRC2_HI_COMP_MASK 0x0038 /* AIF1DRC2_HI_COMP - [5:3] */ 3133 #define WM8994_AIF1DRC2_HI_COMP_SHIFT 3 /* AIF1DRC2_HI_COMP - [5:3] */ 3134 #define WM8994_AIF1DRC2_HI_COMP_WIDTH 3 /* AIF1DRC2_HI_COMP - [5:3] */ 3135 #define WM8994_AIF1DRC2_LO_COMP_MASK 0x0007 /* AIF1DRC2_LO_COMP - [2:0] */ 3136 #define WM8994_AIF1DRC2_LO_COMP_SHIFT 0 /* AIF1DRC2_LO_COMP - [2:0] */ 3137 #define WM8994_AIF1DRC2_LO_COMP_WIDTH 3 /* AIF1DRC2_LO_COMP - [2:0] */ 3138 3139 /* 3140 * R1107 (0x453) - AIF1 DRC2 (4) 3141 */ 3142 #define WM8994_AIF1DRC2_KNEE_IP_MASK 0x07E0 /* AIF1DRC2_KNEE_IP - [10:5] */ 3143 #define WM8994_AIF1DRC2_KNEE_IP_SHIFT 5 /* AIF1DRC2_KNEE_IP - [10:5] */ 3144 #define WM8994_AIF1DRC2_KNEE_IP_WIDTH 6 /* AIF1DRC2_KNEE_IP - [10:5] */ 3145 #define WM8994_AIF1DRC2_KNEE_OP_MASK 0x001F /* AIF1DRC2_KNEE_OP - [4:0] */ 3146 #define WM8994_AIF1DRC2_KNEE_OP_SHIFT 0 /* AIF1DRC2_KNEE_OP - [4:0] */ 3147 #define WM8994_AIF1DRC2_KNEE_OP_WIDTH 5 /* AIF1DRC2_KNEE_OP - [4:0] */ 3148 3149 /* 3150 * R1108 (0x454) - AIF1 DRC2 (5) 3151 */ 3152 #define WM8994_AIF1DRC2_KNEE2_IP_MASK 0x03E0 /* AIF1DRC2_KNEE2_IP - [9:5] */ 3153 #define WM8994_AIF1DRC2_KNEE2_IP_SHIFT 5 /* AIF1DRC2_KNEE2_IP - [9:5] */ 3154 #define WM8994_AIF1DRC2_KNEE2_IP_WIDTH 5 /* AIF1DRC2_KNEE2_IP - [9:5] */ 3155 #define WM8994_AIF1DRC2_KNEE2_OP_MASK 0x001F /* AIF1DRC2_KNEE2_OP - [4:0] */ 3156 #define WM8994_AIF1DRC2_KNEE2_OP_SHIFT 0 /* AIF1DRC2_KNEE2_OP - [4:0] */ 3157 #define WM8994_AIF1DRC2_KNEE2_OP_WIDTH 5 /* AIF1DRC2_KNEE2_OP - [4:0] */ 3158 3159 /* 3160 * R1152 (0x480) - AIF1 DAC1 EQ Gains (1) 3161 */ 3162 #define WM8994_AIF1DAC1_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ 3163 #define WM8994_AIF1DAC1_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ 3164 #define WM8994_AIF1DAC1_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ 3165 #define WM8994_AIF1DAC1_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ 3166 #define WM8994_AIF1DAC1_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ 3167 #define WM8994_AIF1DAC1_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ 3168 #define WM8994_AIF1DAC1_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ 3169 #define WM8994_AIF1DAC1_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ 3170 #define WM8994_AIF1DAC1_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ 3171 #define WM8994_AIF1DAC1_EQ_ENA 0x0001 /* AIF1DAC1_EQ_ENA */ 3172 #define WM8994_AIF1DAC1_EQ_ENA_MASK 0x0001 /* AIF1DAC1_EQ_ENA */ 3173 #define WM8994_AIF1DAC1_EQ_ENA_SHIFT 0 /* AIF1DAC1_EQ_ENA */ 3174 #define WM8994_AIF1DAC1_EQ_ENA_WIDTH 1 /* AIF1DAC1_EQ_ENA */ 3175 3176 /* 3177 * R1153 (0x481) - AIF1 DAC1 EQ Gains (2) 3178 */ 3179 #define WM8994_AIF1DAC1_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ 3180 #define WM8994_AIF1DAC1_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ 3181 #define WM8994_AIF1DAC1_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ 3182 #define WM8994_AIF1DAC1_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ 3183 #define WM8994_AIF1DAC1_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ 3184 #define WM8994_AIF1DAC1_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ 3185 3186 /* 3187 * R1154 (0x482) - AIF1 DAC1 EQ Band 1 A 3188 */ 3189 #define WM8994_AIF1DAC1_EQ_B1_A_MASK 0xFFFF /* AIF1DAC1_EQ_B1_A - [15:0] */ 3190 #define WM8994_AIF1DAC1_EQ_B1_A_SHIFT 0 /* AIF1DAC1_EQ_B1_A - [15:0] */ 3191 #define WM8994_AIF1DAC1_EQ_B1_A_WIDTH 16 /* AIF1DAC1_EQ_B1_A - [15:0] */ 3192 3193 /* 3194 * R1155 (0x483) - AIF1 DAC1 EQ Band 1 B 3195 */ 3196 #define WM8994_AIF1DAC1_EQ_B1_B_MASK 0xFFFF /* AIF1DAC1_EQ_B1_B - [15:0] */ 3197 #define WM8994_AIF1DAC1_EQ_B1_B_SHIFT 0 /* AIF1DAC1_EQ_B1_B - [15:0] */ 3198 #define WM8994_AIF1DAC1_EQ_B1_B_WIDTH 16 /* AIF1DAC1_EQ_B1_B - [15:0] */ 3199 3200 /* 3201 * R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG 3202 */ 3203 #define WM8994_AIF1DAC1_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B1_PG - [15:0] */ 3204 #define WM8994_AIF1DAC1_EQ_B1_PG_SHIFT 0 /* AIF1DAC1_EQ_B1_PG - [15:0] */ 3205 #define WM8994_AIF1DAC1_EQ_B1_PG_WIDTH 16 /* AIF1DAC1_EQ_B1_PG - [15:0] */ 3206 3207 /* 3208 * R1157 (0x485) - AIF1 DAC1 EQ Band 2 A 3209 */ 3210 #define WM8994_AIF1DAC1_EQ_B2_A_MASK 0xFFFF /* AIF1DAC1_EQ_B2_A - [15:0] */ 3211 #define WM8994_AIF1DAC1_EQ_B2_A_SHIFT 0 /* AIF1DAC1_EQ_B2_A - [15:0] */ 3212 #define WM8994_AIF1DAC1_EQ_B2_A_WIDTH 16 /* AIF1DAC1_EQ_B2_A - [15:0] */ 3213 3214 /* 3215 * R1158 (0x486) - AIF1 DAC1 EQ Band 2 B 3216 */ 3217 #define WM8994_AIF1DAC1_EQ_B2_B_MASK 0xFFFF /* AIF1DAC1_EQ_B2_B - [15:0] */ 3218 #define WM8994_AIF1DAC1_EQ_B2_B_SHIFT 0 /* AIF1DAC1_EQ_B2_B - [15:0] */ 3219 #define WM8994_AIF1DAC1_EQ_B2_B_WIDTH 16 /* AIF1DAC1_EQ_B2_B - [15:0] */ 3220 3221 /* 3222 * R1159 (0x487) - AIF1 DAC1 EQ Band 2 C 3223 */ 3224 #define WM8994_AIF1DAC1_EQ_B2_C_MASK 0xFFFF /* AIF1DAC1_EQ_B2_C - [15:0] */ 3225 #define WM8994_AIF1DAC1_EQ_B2_C_SHIFT 0 /* AIF1DAC1_EQ_B2_C - [15:0] */ 3226 #define WM8994_AIF1DAC1_EQ_B2_C_WIDTH 16 /* AIF1DAC1_EQ_B2_C - [15:0] */ 3227 3228 /* 3229 * R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG 3230 */ 3231 #define WM8994_AIF1DAC1_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B2_PG - [15:0] */ 3232 #define WM8994_AIF1DAC1_EQ_B2_PG_SHIFT 0 /* AIF1DAC1_EQ_B2_PG - [15:0] */ 3233 #define WM8994_AIF1DAC1_EQ_B2_PG_WIDTH 16 /* AIF1DAC1_EQ_B2_PG - [15:0] */ 3234 3235 /* 3236 * R1161 (0x489) - AIF1 DAC1 EQ Band 3 A 3237 */ 3238 #define WM8994_AIF1DAC1_EQ_B3_A_MASK 0xFFFF /* AIF1DAC1_EQ_B3_A - [15:0] */ 3239 #define WM8994_AIF1DAC1_EQ_B3_A_SHIFT 0 /* AIF1DAC1_EQ_B3_A - [15:0] */ 3240 #define WM8994_AIF1DAC1_EQ_B3_A_WIDTH 16 /* AIF1DAC1_EQ_B3_A - [15:0] */ 3241 3242 /* 3243 * R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B 3244 */ 3245 #define WM8994_AIF1DAC1_EQ_B3_B_MASK 0xFFFF /* AIF1DAC1_EQ_B3_B - [15:0] */ 3246 #define WM8994_AIF1DAC1_EQ_B3_B_SHIFT 0 /* AIF1DAC1_EQ_B3_B - [15:0] */ 3247 #define WM8994_AIF1DAC1_EQ_B3_B_WIDTH 16 /* AIF1DAC1_EQ_B3_B - [15:0] */ 3248 3249 /* 3250 * R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C 3251 */ 3252 #define WM8994_AIF1DAC1_EQ_B3_C_MASK 0xFFFF /* AIF1DAC1_EQ_B3_C - [15:0] */ 3253 #define WM8994_AIF1DAC1_EQ_B3_C_SHIFT 0 /* AIF1DAC1_EQ_B3_C - [15:0] */ 3254 #define WM8994_AIF1DAC1_EQ_B3_C_WIDTH 16 /* AIF1DAC1_EQ_B3_C - [15:0] */ 3255 3256 /* 3257 * R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG 3258 */ 3259 #define WM8994_AIF1DAC1_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B3_PG - [15:0] */ 3260 #define WM8994_AIF1DAC1_EQ_B3_PG_SHIFT 0 /* AIF1DAC1_EQ_B3_PG - [15:0] */ 3261 #define WM8994_AIF1DAC1_EQ_B3_PG_WIDTH 16 /* AIF1DAC1_EQ_B3_PG - [15:0] */ 3262 3263 /* 3264 * R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A 3265 */ 3266 #define WM8994_AIF1DAC1_EQ_B4_A_MASK 0xFFFF /* AIF1DAC1_EQ_B4_A - [15:0] */ 3267 #define WM8994_AIF1DAC1_EQ_B4_A_SHIFT 0 /* AIF1DAC1_EQ_B4_A - [15:0] */ 3268 #define WM8994_AIF1DAC1_EQ_B4_A_WIDTH 16 /* AIF1DAC1_EQ_B4_A - [15:0] */ 3269 3270 /* 3271 * R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B 3272 */ 3273 #define WM8994_AIF1DAC1_EQ_B4_B_MASK 0xFFFF /* AIF1DAC1_EQ_B4_B - [15:0] */ 3274 #define WM8994_AIF1DAC1_EQ_B4_B_SHIFT 0 /* AIF1DAC1_EQ_B4_B - [15:0] */ 3275 #define WM8994_AIF1DAC1_EQ_B4_B_WIDTH 16 /* AIF1DAC1_EQ_B4_B - [15:0] */ 3276 3277 /* 3278 * R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C 3279 */ 3280 #define WM8994_AIF1DAC1_EQ_B4_C_MASK 0xFFFF /* AIF1DAC1_EQ_B4_C - [15:0] */ 3281 #define WM8994_AIF1DAC1_EQ_B4_C_SHIFT 0 /* AIF1DAC1_EQ_B4_C - [15:0] */ 3282 #define WM8994_AIF1DAC1_EQ_B4_C_WIDTH 16 /* AIF1DAC1_EQ_B4_C - [15:0] */ 3283 3284 /* 3285 * R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG 3286 */ 3287 #define WM8994_AIF1DAC1_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B4_PG - [15:0] */ 3288 #define WM8994_AIF1DAC1_EQ_B4_PG_SHIFT 0 /* AIF1DAC1_EQ_B4_PG - [15:0] */ 3289 #define WM8994_AIF1DAC1_EQ_B4_PG_WIDTH 16 /* AIF1DAC1_EQ_B4_PG - [15:0] */ 3290 3291 /* 3292 * R1169 (0x491) - AIF1 DAC1 EQ Band 5 A 3293 */ 3294 #define WM8994_AIF1DAC1_EQ_B5_A_MASK 0xFFFF /* AIF1DAC1_EQ_B5_A - [15:0] */ 3295 #define WM8994_AIF1DAC1_EQ_B5_A_SHIFT 0 /* AIF1DAC1_EQ_B5_A - [15:0] */ 3296 #define WM8994_AIF1DAC1_EQ_B5_A_WIDTH 16 /* AIF1DAC1_EQ_B5_A - [15:0] */ 3297 3298 /* 3299 * R1170 (0x492) - AIF1 DAC1 EQ Band 5 B 3300 */ 3301 #define WM8994_AIF1DAC1_EQ_B5_B_MASK 0xFFFF /* AIF1DAC1_EQ_B5_B - [15:0] */ 3302 #define WM8994_AIF1DAC1_EQ_B5_B_SHIFT 0 /* AIF1DAC1_EQ_B5_B - [15:0] */ 3303 #define WM8994_AIF1DAC1_EQ_B5_B_WIDTH 16 /* AIF1DAC1_EQ_B5_B - [15:0] */ 3304 3305 /* 3306 * R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG 3307 */ 3308 #define WM8994_AIF1DAC1_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B5_PG - [15:0] */ 3309 #define WM8994_AIF1DAC1_EQ_B5_PG_SHIFT 0 /* AIF1DAC1_EQ_B5_PG - [15:0] */ 3310 #define WM8994_AIF1DAC1_EQ_B5_PG_WIDTH 16 /* AIF1DAC1_EQ_B5_PG - [15:0] */ 3311 3312 /* 3313 * R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1) 3314 */ 3315 #define WM8994_AIF1DAC2_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ 3316 #define WM8994_AIF1DAC2_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ 3317 #define WM8994_AIF1DAC2_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ 3318 #define WM8994_AIF1DAC2_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ 3319 #define WM8994_AIF1DAC2_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ 3320 #define WM8994_AIF1DAC2_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ 3321 #define WM8994_AIF1DAC2_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ 3322 #define WM8994_AIF1DAC2_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ 3323 #define WM8994_AIF1DAC2_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ 3324 #define WM8994_AIF1DAC2_EQ_ENA 0x0001 /* AIF1DAC2_EQ_ENA */ 3325 #define WM8994_AIF1DAC2_EQ_ENA_MASK 0x0001 /* AIF1DAC2_EQ_ENA */ 3326 #define WM8994_AIF1DAC2_EQ_ENA_SHIFT 0 /* AIF1DAC2_EQ_ENA */ 3327 #define WM8994_AIF1DAC2_EQ_ENA_WIDTH 1 /* AIF1DAC2_EQ_ENA */ 3328 3329 /* 3330 * R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2) 3331 */ 3332 #define WM8994_AIF1DAC2_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ 3333 #define WM8994_AIF1DAC2_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ 3334 #define WM8994_AIF1DAC2_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ 3335 #define WM8994_AIF1DAC2_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ 3336 #define WM8994_AIF1DAC2_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ 3337 #define WM8994_AIF1DAC2_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ 3338 3339 /* 3340 * R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A 3341 */ 3342 #define WM8994_AIF1DAC2_EQ_B1_A_MASK 0xFFFF /* AIF1DAC2_EQ_B1_A - [15:0] */ 3343 #define WM8994_AIF1DAC2_EQ_B1_A_SHIFT 0 /* AIF1DAC2_EQ_B1_A - [15:0] */ 3344 #define WM8994_AIF1DAC2_EQ_B1_A_WIDTH 16 /* AIF1DAC2_EQ_B1_A - [15:0] */ 3345 3346 /* 3347 * R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B 3348 */ 3349 #define WM8994_AIF1DAC2_EQ_B1_B_MASK 0xFFFF /* AIF1DAC2_EQ_B1_B - [15:0] */ 3350 #define WM8994_AIF1DAC2_EQ_B1_B_SHIFT 0 /* AIF1DAC2_EQ_B1_B - [15:0] */ 3351 #define WM8994_AIF1DAC2_EQ_B1_B_WIDTH 16 /* AIF1DAC2_EQ_B1_B - [15:0] */ 3352 3353 /* 3354 * R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG 3355 */ 3356 #define WM8994_AIF1DAC2_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B1_PG - [15:0] */ 3357 #define WM8994_AIF1DAC2_EQ_B1_PG_SHIFT 0 /* AIF1DAC2_EQ_B1_PG - [15:0] */ 3358 #define WM8994_AIF1DAC2_EQ_B1_PG_WIDTH 16 /* AIF1DAC2_EQ_B1_PG - [15:0] */ 3359 3360 /* 3361 * R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A 3362 */ 3363 #define WM8994_AIF1DAC2_EQ_B2_A_MASK 0xFFFF /* AIF1DAC2_EQ_B2_A - [15:0] */ 3364 #define WM8994_AIF1DAC2_EQ_B2_A_SHIFT 0 /* AIF1DAC2_EQ_B2_A - [15:0] */ 3365 #define WM8994_AIF1DAC2_EQ_B2_A_WIDTH 16 /* AIF1DAC2_EQ_B2_A - [15:0] */ 3366 3367 /* 3368 * R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B 3369 */ 3370 #define WM8994_AIF1DAC2_EQ_B2_B_MASK 0xFFFF /* AIF1DAC2_EQ_B2_B - [15:0] */ 3371 #define WM8994_AIF1DAC2_EQ_B2_B_SHIFT 0 /* AIF1DAC2_EQ_B2_B - [15:0] */ 3372 #define WM8994_AIF1DAC2_EQ_B2_B_WIDTH 16 /* AIF1DAC2_EQ_B2_B - [15:0] */ 3373 3374 /* 3375 * R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C 3376 */ 3377 #define WM8994_AIF1DAC2_EQ_B2_C_MASK 0xFFFF /* AIF1DAC2_EQ_B2_C - [15:0] */ 3378 #define WM8994_AIF1DAC2_EQ_B2_C_SHIFT 0 /* AIF1DAC2_EQ_B2_C - [15:0] */ 3379 #define WM8994_AIF1DAC2_EQ_B2_C_WIDTH 16 /* AIF1DAC2_EQ_B2_C - [15:0] */ 3380 3381 /* 3382 * R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG 3383 */ 3384 #define WM8994_AIF1DAC2_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B2_PG - [15:0] */ 3385 #define WM8994_AIF1DAC2_EQ_B2_PG_SHIFT 0 /* AIF1DAC2_EQ_B2_PG - [15:0] */ 3386 #define WM8994_AIF1DAC2_EQ_B2_PG_WIDTH 16 /* AIF1DAC2_EQ_B2_PG - [15:0] */ 3387 3388 /* 3389 * R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A 3390 */ 3391 #define WM8994_AIF1DAC2_EQ_B3_A_MASK 0xFFFF /* AIF1DAC2_EQ_B3_A - [15:0] */ 3392 #define WM8994_AIF1DAC2_EQ_B3_A_SHIFT 0 /* AIF1DAC2_EQ_B3_A - [15:0] */ 3393 #define WM8994_AIF1DAC2_EQ_B3_A_WIDTH 16 /* AIF1DAC2_EQ_B3_A - [15:0] */ 3394 3395 /* 3396 * R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B 3397 */ 3398 #define WM8994_AIF1DAC2_EQ_B3_B_MASK 0xFFFF /* AIF1DAC2_EQ_B3_B - [15:0] */ 3399 #define WM8994_AIF1DAC2_EQ_B3_B_SHIFT 0 /* AIF1DAC2_EQ_B3_B - [15:0] */ 3400 #define WM8994_AIF1DAC2_EQ_B3_B_WIDTH 16 /* AIF1DAC2_EQ_B3_B - [15:0] */ 3401 3402 /* 3403 * R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C 3404 */ 3405 #define WM8994_AIF1DAC2_EQ_B3_C_MASK 0xFFFF /* AIF1DAC2_EQ_B3_C - [15:0] */ 3406 #define WM8994_AIF1DAC2_EQ_B3_C_SHIFT 0 /* AIF1DAC2_EQ_B3_C - [15:0] */ 3407 #define WM8994_AIF1DAC2_EQ_B3_C_WIDTH 16 /* AIF1DAC2_EQ_B3_C - [15:0] */ 3408 3409 /* 3410 * R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG 3411 */ 3412 #define WM8994_AIF1DAC2_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B3_PG - [15:0] */ 3413 #define WM8994_AIF1DAC2_EQ_B3_PG_SHIFT 0 /* AIF1DAC2_EQ_B3_PG - [15:0] */ 3414 #define WM8994_AIF1DAC2_EQ_B3_PG_WIDTH 16 /* AIF1DAC2_EQ_B3_PG - [15:0] */ 3415 3416 /* 3417 * R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A 3418 */ 3419 #define WM8994_AIF1DAC2_EQ_B4_A_MASK 0xFFFF /* AIF1DAC2_EQ_B4_A - [15:0] */ 3420 #define WM8994_AIF1DAC2_EQ_B4_A_SHIFT 0 /* AIF1DAC2_EQ_B4_A - [15:0] */ 3421 #define WM8994_AIF1DAC2_EQ_B4_A_WIDTH 16 /* AIF1DAC2_EQ_B4_A - [15:0] */ 3422 3423 /* 3424 * R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B 3425 */ 3426 #define WM8994_AIF1DAC2_EQ_B4_B_MASK 0xFFFF /* AIF1DAC2_EQ_B4_B - [15:0] */ 3427 #define WM8994_AIF1DAC2_EQ_B4_B_SHIFT 0 /* AIF1DAC2_EQ_B4_B - [15:0] */ 3428 #define WM8994_AIF1DAC2_EQ_B4_B_WIDTH 16 /* AIF1DAC2_EQ_B4_B - [15:0] */ 3429 3430 /* 3431 * R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C 3432 */ 3433 #define WM8994_AIF1DAC2_EQ_B4_C_MASK 0xFFFF /* AIF1DAC2_EQ_B4_C - [15:0] */ 3434 #define WM8994_AIF1DAC2_EQ_B4_C_SHIFT 0 /* AIF1DAC2_EQ_B4_C - [15:0] */ 3435 #define WM8994_AIF1DAC2_EQ_B4_C_WIDTH 16 /* AIF1DAC2_EQ_B4_C - [15:0] */ 3436 3437 /* 3438 * R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG 3439 */ 3440 #define WM8994_AIF1DAC2_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B4_PG - [15:0] */ 3441 #define WM8994_AIF1DAC2_EQ_B4_PG_SHIFT 0 /* AIF1DAC2_EQ_B4_PG - [15:0] */ 3442 #define WM8994_AIF1DAC2_EQ_B4_PG_WIDTH 16 /* AIF1DAC2_EQ_B4_PG - [15:0] */ 3443 3444 /* 3445 * R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A 3446 */ 3447 #define WM8994_AIF1DAC2_EQ_B5_A_MASK 0xFFFF /* AIF1DAC2_EQ_B5_A - [15:0] */ 3448 #define WM8994_AIF1DAC2_EQ_B5_A_SHIFT 0 /* AIF1DAC2_EQ_B5_A - [15:0] */ 3449 #define WM8994_AIF1DAC2_EQ_B5_A_WIDTH 16 /* AIF1DAC2_EQ_B5_A - [15:0] */ 3450 3451 /* 3452 * R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B 3453 */ 3454 #define WM8994_AIF1DAC2_EQ_B5_B_MASK 0xFFFF /* AIF1DAC2_EQ_B5_B - [15:0] */ 3455 #define WM8994_AIF1DAC2_EQ_B5_B_SHIFT 0 /* AIF1DAC2_EQ_B5_B - [15:0] */ 3456 #define WM8994_AIF1DAC2_EQ_B5_B_WIDTH 16 /* AIF1DAC2_EQ_B5_B - [15:0] */ 3457 3458 /* 3459 * R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG 3460 */ 3461 #define WM8994_AIF1DAC2_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B5_PG - [15:0] */ 3462 #define WM8994_AIF1DAC2_EQ_B5_PG_SHIFT 0 /* AIF1DAC2_EQ_B5_PG - [15:0] */ 3463 #define WM8994_AIF1DAC2_EQ_B5_PG_WIDTH 16 /* AIF1DAC2_EQ_B5_PG - [15:0] */ 3464 3465 /* 3466 * R1280 (0x500) - AIF2 ADC Left Volume 3467 */ 3468 #define WM8994_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */ 3469 #define WM8994_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */ 3470 #define WM8994_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */ 3471 #define WM8994_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */ 3472 #define WM8994_AIF2ADCL_VOL_MASK 0x00FF /* AIF2ADCL_VOL - [7:0] */ 3473 #define WM8994_AIF2ADCL_VOL_SHIFT 0 /* AIF2ADCL_VOL - [7:0] */ 3474 #define WM8994_AIF2ADCL_VOL_WIDTH 8 /* AIF2ADCL_VOL - [7:0] */ 3475 3476 /* 3477 * R1281 (0x501) - AIF2 ADC Right Volume 3478 */ 3479 #define WM8994_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */ 3480 #define WM8994_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */ 3481 #define WM8994_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */ 3482 #define WM8994_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */ 3483 #define WM8994_AIF2ADCR_VOL_MASK 0x00FF /* AIF2ADCR_VOL - [7:0] */ 3484 #define WM8994_AIF2ADCR_VOL_SHIFT 0 /* AIF2ADCR_VOL - [7:0] */ 3485 #define WM8994_AIF2ADCR_VOL_WIDTH 8 /* AIF2ADCR_VOL - [7:0] */ 3486 3487 /* 3488 * R1282 (0x502) - AIF2 DAC Left Volume 3489 */ 3490 #define WM8994_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */ 3491 #define WM8994_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */ 3492 #define WM8994_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */ 3493 #define WM8994_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */ 3494 #define WM8994_AIF2DACL_VOL_MASK 0x00FF /* AIF2DACL_VOL - [7:0] */ 3495 #define WM8994_AIF2DACL_VOL_SHIFT 0 /* AIF2DACL_VOL - [7:0] */ 3496 #define WM8994_AIF2DACL_VOL_WIDTH 8 /* AIF2DACL_VOL - [7:0] */ 3497 3498 /* 3499 * R1283 (0x503) - AIF2 DAC Right Volume 3500 */ 3501 #define WM8994_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */ 3502 #define WM8994_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */ 3503 #define WM8994_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */ 3504 #define WM8994_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */ 3505 #define WM8994_AIF2DACR_VOL_MASK 0x00FF /* AIF2DACR_VOL - [7:0] */ 3506 #define WM8994_AIF2DACR_VOL_SHIFT 0 /* AIF2DACR_VOL - [7:0] */ 3507 #define WM8994_AIF2DACR_VOL_WIDTH 8 /* AIF2DACR_VOL - [7:0] */ 3508 3509 /* 3510 * R1296 (0x510) - AIF2 ADC Filters 3511 */ 3512 #define WM8994_AIF2ADC_4FS 0x8000 /* AIF2ADC_4FS */ 3513 #define WM8994_AIF2ADC_4FS_MASK 0x8000 /* AIF2ADC_4FS */ 3514 #define WM8994_AIF2ADC_4FS_SHIFT 15 /* AIF2ADC_4FS */ 3515 #define WM8994_AIF2ADC_4FS_WIDTH 1 /* AIF2ADC_4FS */ 3516 #define WM8994_AIF2ADC_HPF_CUT_MASK 0x6000 /* AIF2ADC_HPF_CUT - [14:13] */ 3517 #define WM8994_AIF2ADC_HPF_CUT_SHIFT 13 /* AIF2ADC_HPF_CUT - [14:13] */ 3518 #define WM8994_AIF2ADC_HPF_CUT_WIDTH 2 /* AIF2ADC_HPF_CUT - [14:13] */ 3519 #define WM8994_AIF2ADCL_HPF 0x1000 /* AIF2ADCL_HPF */ 3520 #define WM8994_AIF2ADCL_HPF_MASK 0x1000 /* AIF2ADCL_HPF */ 3521 #define WM8994_AIF2ADCL_HPF_SHIFT 12 /* AIF2ADCL_HPF */ 3522 #define WM8994_AIF2ADCL_HPF_WIDTH 1 /* AIF2ADCL_HPF */ 3523 #define WM8994_AIF2ADCR_HPF 0x0800 /* AIF2ADCR_HPF */ 3524 #define WM8994_AIF2ADCR_HPF_MASK 0x0800 /* AIF2ADCR_HPF */ 3525 #define WM8994_AIF2ADCR_HPF_SHIFT 11 /* AIF2ADCR_HPF */ 3526 #define WM8994_AIF2ADCR_HPF_WIDTH 1 /* AIF2ADCR_HPF */ 3527 3528 /* 3529 * R1312 (0x520) - AIF2 DAC Filters (1) 3530 */ 3531 #define WM8994_AIF2DAC_MUTE 0x0200 /* AIF2DAC_MUTE */ 3532 #define WM8994_AIF2DAC_MUTE_MASK 0x0200 /* AIF2DAC_MUTE */ 3533 #define WM8994_AIF2DAC_MUTE_SHIFT 9 /* AIF2DAC_MUTE */ 3534 #define WM8994_AIF2DAC_MUTE_WIDTH 1 /* AIF2DAC_MUTE */ 3535 #define WM8994_AIF2DAC_MONO 0x0080 /* AIF2DAC_MONO */ 3536 #define WM8994_AIF2DAC_MONO_MASK 0x0080 /* AIF2DAC_MONO */ 3537 #define WM8994_AIF2DAC_MONO_SHIFT 7 /* AIF2DAC_MONO */ 3538 #define WM8994_AIF2DAC_MONO_WIDTH 1 /* AIF2DAC_MONO */ 3539 #define WM8994_AIF2DAC_MUTERATE 0x0020 /* AIF2DAC_MUTERATE */ 3540 #define WM8994_AIF2DAC_MUTERATE_MASK 0x0020 /* AIF2DAC_MUTERATE */ 3541 #define WM8994_AIF2DAC_MUTERATE_SHIFT 5 /* AIF2DAC_MUTERATE */ 3542 #define WM8994_AIF2DAC_MUTERATE_WIDTH 1 /* AIF2DAC_MUTERATE */ 3543 #define WM8994_AIF2DAC_UNMUTE_RAMP 0x0010 /* AIF2DAC_UNMUTE_RAMP */ 3544 #define WM8994_AIF2DAC_UNMUTE_RAMP_MASK 0x0010 /* AIF2DAC_UNMUTE_RAMP */ 3545 #define WM8994_AIF2DAC_UNMUTE_RAMP_SHIFT 4 /* AIF2DAC_UNMUTE_RAMP */ 3546 #define WM8994_AIF2DAC_UNMUTE_RAMP_WIDTH 1 /* AIF2DAC_UNMUTE_RAMP */ 3547 #define WM8994_AIF2DAC_DEEMP_MASK 0x0006 /* AIF2DAC_DEEMP - [2:1] */ 3548 #define WM8994_AIF2DAC_DEEMP_SHIFT 1 /* AIF2DAC_DEEMP - [2:1] */ 3549 #define WM8994_AIF2DAC_DEEMP_WIDTH 2 /* AIF2DAC_DEEMP - [2:1] */ 3550 3551 /* 3552 * R1313 (0x521) - AIF2 DAC Filters (2) 3553 */ 3554 #define WM8994_AIF2DAC_3D_GAIN_MASK 0x3E00 /* AIF2DAC_3D_GAIN - [13:9] */ 3555 #define WM8994_AIF2DAC_3D_GAIN_SHIFT 9 /* AIF2DAC_3D_GAIN - [13:9] */ 3556 #define WM8994_AIF2DAC_3D_GAIN_WIDTH 5 /* AIF2DAC_3D_GAIN - [13:9] */ 3557 #define WM8994_AIF2DAC_3D_ENA 0x0100 /* AIF2DAC_3D_ENA */ 3558 #define WM8994_AIF2DAC_3D_ENA_MASK 0x0100 /* AIF2DAC_3D_ENA */ 3559 #define WM8994_AIF2DAC_3D_ENA_SHIFT 8 /* AIF2DAC_3D_ENA */ 3560 #define WM8994_AIF2DAC_3D_ENA_WIDTH 1 /* AIF2DAC_3D_ENA */ 3561 3562 /* 3563 * R1344 (0x540) - AIF2 DRC (1) 3564 */ 3565 #define WM8994_AIF2DRC_SIG_DET_RMS_MASK 0xF800 /* AIF2DRC_SIG_DET_RMS - [15:11] */ 3566 #define WM8994_AIF2DRC_SIG_DET_RMS_SHIFT 11 /* AIF2DRC_SIG_DET_RMS - [15:11] */ 3567 #define WM8994_AIF2DRC_SIG_DET_RMS_WIDTH 5 /* AIF2DRC_SIG_DET_RMS - [15:11] */ 3568 #define WM8994_AIF2DRC_SIG_DET_PK_MASK 0x0600 /* AIF2DRC_SIG_DET_PK - [10:9] */ 3569 #define WM8994_AIF2DRC_SIG_DET_PK_SHIFT 9 /* AIF2DRC_SIG_DET_PK - [10:9] */ 3570 #define WM8994_AIF2DRC_SIG_DET_PK_WIDTH 2 /* AIF2DRC_SIG_DET_PK - [10:9] */ 3571 #define WM8994_AIF2DRC_NG_ENA 0x0100 /* AIF2DRC_NG_ENA */ 3572 #define WM8994_AIF2DRC_NG_ENA_MASK 0x0100 /* AIF2DRC_NG_ENA */ 3573 #define WM8994_AIF2DRC_NG_ENA_SHIFT 8 /* AIF2DRC_NG_ENA */ 3574 #define WM8994_AIF2DRC_NG_ENA_WIDTH 1 /* AIF2DRC_NG_ENA */ 3575 #define WM8994_AIF2DRC_SIG_DET_MODE 0x0080 /* AIF2DRC_SIG_DET_MODE */ 3576 #define WM8994_AIF2DRC_SIG_DET_MODE_MASK 0x0080 /* AIF2DRC_SIG_DET_MODE */ 3577 #define WM8994_AIF2DRC_SIG_DET_MODE_SHIFT 7 /* AIF2DRC_SIG_DET_MODE */ 3578 #define WM8994_AIF2DRC_SIG_DET_MODE_WIDTH 1 /* AIF2DRC_SIG_DET_MODE */ 3579 #define WM8994_AIF2DRC_SIG_DET 0x0040 /* AIF2DRC_SIG_DET */ 3580 #define WM8994_AIF2DRC_SIG_DET_MASK 0x0040 /* AIF2DRC_SIG_DET */ 3581 #define WM8994_AIF2DRC_SIG_DET_SHIFT 6 /* AIF2DRC_SIG_DET */ 3582 #define WM8994_AIF2DRC_SIG_DET_WIDTH 1 /* AIF2DRC_SIG_DET */ 3583 #define WM8994_AIF2DRC_KNEE2_OP_ENA 0x0020 /* AIF2DRC_KNEE2_OP_ENA */ 3584 #define WM8994_AIF2DRC_KNEE2_OP_ENA_MASK 0x0020 /* AIF2DRC_KNEE2_OP_ENA */ 3585 #define WM8994_AIF2DRC_KNEE2_OP_ENA_SHIFT 5 /* AIF2DRC_KNEE2_OP_ENA */ 3586 #define WM8994_AIF2DRC_KNEE2_OP_ENA_WIDTH 1 /* AIF2DRC_KNEE2_OP_ENA */ 3587 #define WM8994_AIF2DRC_QR 0x0010 /* AIF2DRC_QR */ 3588 #define WM8994_AIF2DRC_QR_MASK 0x0010 /* AIF2DRC_QR */ 3589 #define WM8994_AIF2DRC_QR_SHIFT 4 /* AIF2DRC_QR */ 3590 #define WM8994_AIF2DRC_QR_WIDTH 1 /* AIF2DRC_QR */ 3591 #define WM8994_AIF2DRC_ANTICLIP 0x0008 /* AIF2DRC_ANTICLIP */ 3592 #define WM8994_AIF2DRC_ANTICLIP_MASK 0x0008 /* AIF2DRC_ANTICLIP */ 3593 #define WM8994_AIF2DRC_ANTICLIP_SHIFT 3 /* AIF2DRC_ANTICLIP */ 3594 #define WM8994_AIF2DRC_ANTICLIP_WIDTH 1 /* AIF2DRC_ANTICLIP */ 3595 #define WM8994_AIF2DAC_DRC_ENA 0x0004 /* AIF2DAC_DRC_ENA */ 3596 #define WM8994_AIF2DAC_DRC_ENA_MASK 0x0004 /* AIF2DAC_DRC_ENA */ 3597 #define WM8994_AIF2DAC_DRC_ENA_SHIFT 2 /* AIF2DAC_DRC_ENA */ 3598 #define WM8994_AIF2DAC_DRC_ENA_WIDTH 1 /* AIF2DAC_DRC_ENA */ 3599 #define WM8994_AIF2ADCL_DRC_ENA 0x0002 /* AIF2ADCL_DRC_ENA */ 3600 #define WM8994_AIF2ADCL_DRC_ENA_MASK 0x0002 /* AIF2ADCL_DRC_ENA */ 3601 #define WM8994_AIF2ADCL_DRC_ENA_SHIFT 1 /* AIF2ADCL_DRC_ENA */ 3602 #define WM8994_AIF2ADCL_DRC_ENA_WIDTH 1 /* AIF2ADCL_DRC_ENA */ 3603 #define WM8994_AIF2ADCR_DRC_ENA 0x0001 /* AIF2ADCR_DRC_ENA */ 3604 #define WM8994_AIF2ADCR_DRC_ENA_MASK 0x0001 /* AIF2ADCR_DRC_ENA */ 3605 #define WM8994_AIF2ADCR_DRC_ENA_SHIFT 0 /* AIF2ADCR_DRC_ENA */ 3606 #define WM8994_AIF2ADCR_DRC_ENA_WIDTH 1 /* AIF2ADCR_DRC_ENA */ 3607 3608 /* 3609 * R1345 (0x541) - AIF2 DRC (2) 3610 */ 3611 #define WM8994_AIF2DRC_ATK_MASK 0x1E00 /* AIF2DRC_ATK - [12:9] */ 3612 #define WM8994_AIF2DRC_ATK_SHIFT 9 /* AIF2DRC_ATK - [12:9] */ 3613 #define WM8994_AIF2DRC_ATK_WIDTH 4 /* AIF2DRC_ATK - [12:9] */ 3614 #define WM8994_AIF2DRC_DCY_MASK 0x01E0 /* AIF2DRC_DCY - [8:5] */ 3615 #define WM8994_AIF2DRC_DCY_SHIFT 5 /* AIF2DRC_DCY - [8:5] */ 3616 #define WM8994_AIF2DRC_DCY_WIDTH 4 /* AIF2DRC_DCY - [8:5] */ 3617 #define WM8994_AIF2DRC_MINGAIN_MASK 0x001C /* AIF2DRC_MINGAIN - [4:2] */ 3618 #define WM8994_AIF2DRC_MINGAIN_SHIFT 2 /* AIF2DRC_MINGAIN - [4:2] */ 3619 #define WM8994_AIF2DRC_MINGAIN_WIDTH 3 /* AIF2DRC_MINGAIN - [4:2] */ 3620 #define WM8994_AIF2DRC_MAXGAIN_MASK 0x0003 /* AIF2DRC_MAXGAIN - [1:0] */ 3621 #define WM8994_AIF2DRC_MAXGAIN_SHIFT 0 /* AIF2DRC_MAXGAIN - [1:0] */ 3622 #define WM8994_AIF2DRC_MAXGAIN_WIDTH 2 /* AIF2DRC_MAXGAIN - [1:0] */ 3623 3624 /* 3625 * R1346 (0x542) - AIF2 DRC (3) 3626 */ 3627 #define WM8994_AIF2DRC_NG_MINGAIN_MASK 0xF000 /* AIF2DRC_NG_MINGAIN - [15:12] */ 3628 #define WM8994_AIF2DRC_NG_MINGAIN_SHIFT 12 /* AIF2DRC_NG_MINGAIN - [15:12] */ 3629 #define WM8994_AIF2DRC_NG_MINGAIN_WIDTH 4 /* AIF2DRC_NG_MINGAIN - [15:12] */ 3630 #define WM8994_AIF2DRC_NG_EXP_MASK 0x0C00 /* AIF2DRC_NG_EXP - [11:10] */ 3631 #define WM8994_AIF2DRC_NG_EXP_SHIFT 10 /* AIF2DRC_NG_EXP - [11:10] */ 3632 #define WM8994_AIF2DRC_NG_EXP_WIDTH 2 /* AIF2DRC_NG_EXP - [11:10] */ 3633 #define WM8994_AIF2DRC_QR_THR_MASK 0x0300 /* AIF2DRC_QR_THR - [9:8] */ 3634 #define WM8994_AIF2DRC_QR_THR_SHIFT 8 /* AIF2DRC_QR_THR - [9:8] */ 3635 #define WM8994_AIF2DRC_QR_THR_WIDTH 2 /* AIF2DRC_QR_THR - [9:8] */ 3636 #define WM8994_AIF2DRC_QR_DCY_MASK 0x00C0 /* AIF2DRC_QR_DCY - [7:6] */ 3637 #define WM8994_AIF2DRC_QR_DCY_SHIFT 6 /* AIF2DRC_QR_DCY - [7:6] */ 3638 #define WM8994_AIF2DRC_QR_DCY_WIDTH 2 /* AIF2DRC_QR_DCY - [7:6] */ 3639 #define WM8994_AIF2DRC_HI_COMP_MASK 0x0038 /* AIF2DRC_HI_COMP - [5:3] */ 3640 #define WM8994_AIF2DRC_HI_COMP_SHIFT 3 /* AIF2DRC_HI_COMP - [5:3] */ 3641 #define WM8994_AIF2DRC_HI_COMP_WIDTH 3 /* AIF2DRC_HI_COMP - [5:3] */ 3642 #define WM8994_AIF2DRC_LO_COMP_MASK 0x0007 /* AIF2DRC_LO_COMP - [2:0] */ 3643 #define WM8994_AIF2DRC_LO_COMP_SHIFT 0 /* AIF2DRC_LO_COMP - [2:0] */ 3644 #define WM8994_AIF2DRC_LO_COMP_WIDTH 3 /* AIF2DRC_LO_COMP - [2:0] */ 3645 3646 /* 3647 * R1347 (0x543) - AIF2 DRC (4) 3648 */ 3649 #define WM8994_AIF2DRC_KNEE_IP_MASK 0x07E0 /* AIF2DRC_KNEE_IP - [10:5] */ 3650 #define WM8994_AIF2DRC_KNEE_IP_SHIFT 5 /* AIF2DRC_KNEE_IP - [10:5] */ 3651 #define WM8994_AIF2DRC_KNEE_IP_WIDTH 6 /* AIF2DRC_KNEE_IP - [10:5] */ 3652 #define WM8994_AIF2DRC_KNEE_OP_MASK 0x001F /* AIF2DRC_KNEE_OP - [4:0] */ 3653 #define WM8994_AIF2DRC_KNEE_OP_SHIFT 0 /* AIF2DRC_KNEE_OP - [4:0] */ 3654 #define WM8994_AIF2DRC_KNEE_OP_WIDTH 5 /* AIF2DRC_KNEE_OP - [4:0] */ 3655 3656 /* 3657 * R1348 (0x544) - AIF2 DRC (5) 3658 */ 3659 #define WM8994_AIF2DRC_KNEE2_IP_MASK 0x03E0 /* AIF2DRC_KNEE2_IP - [9:5] */ 3660 #define WM8994_AIF2DRC_KNEE2_IP_SHIFT 5 /* AIF2DRC_KNEE2_IP - [9:5] */ 3661 #define WM8994_AIF2DRC_KNEE2_IP_WIDTH 5 /* AIF2DRC_KNEE2_IP - [9:5] */ 3662 #define WM8994_AIF2DRC_KNEE2_OP_MASK 0x001F /* AIF2DRC_KNEE2_OP - [4:0] */ 3663 #define WM8994_AIF2DRC_KNEE2_OP_SHIFT 0 /* AIF2DRC_KNEE2_OP - [4:0] */ 3664 #define WM8994_AIF2DRC_KNEE2_OP_WIDTH 5 /* AIF2DRC_KNEE2_OP - [4:0] */ 3665 3666 /* 3667 * R1408 (0x580) - AIF2 EQ Gains (1) 3668 */ 3669 #define WM8994_AIF2DAC_EQ_B1_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ 3670 #define WM8994_AIF2DAC_EQ_B1_GAIN_SHIFT 11 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ 3671 #define WM8994_AIF2DAC_EQ_B1_GAIN_WIDTH 5 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ 3672 #define WM8994_AIF2DAC_EQ_B2_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ 3673 #define WM8994_AIF2DAC_EQ_B2_GAIN_SHIFT 6 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ 3674 #define WM8994_AIF2DAC_EQ_B2_GAIN_WIDTH 5 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ 3675 #define WM8994_AIF2DAC_EQ_B3_GAIN_MASK 0x003E /* AIF2DAC_EQ_B3_GAIN - [5:1] */ 3676 #define WM8994_AIF2DAC_EQ_B3_GAIN_SHIFT 1 /* AIF2DAC_EQ_B3_GAIN - [5:1] */ 3677 #define WM8994_AIF2DAC_EQ_B3_GAIN_WIDTH 5 /* AIF2DAC_EQ_B3_GAIN - [5:1] */ 3678 #define WM8994_AIF2DAC_EQ_ENA 0x0001 /* AIF2DAC_EQ_ENA */ 3679 #define WM8994_AIF2DAC_EQ_ENA_MASK 0x0001 /* AIF2DAC_EQ_ENA */ 3680 #define WM8994_AIF2DAC_EQ_ENA_SHIFT 0 /* AIF2DAC_EQ_ENA */ 3681 #define WM8994_AIF2DAC_EQ_ENA_WIDTH 1 /* AIF2DAC_EQ_ENA */ 3682 3683 /* 3684 * R1409 (0x581) - AIF2 EQ Gains (2) 3685 */ 3686 #define WM8994_AIF2DAC_EQ_B4_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ 3687 #define WM8994_AIF2DAC_EQ_B4_GAIN_SHIFT 11 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ 3688 #define WM8994_AIF2DAC_EQ_B4_GAIN_WIDTH 5 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ 3689 #define WM8994_AIF2DAC_EQ_B5_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ 3690 #define WM8994_AIF2DAC_EQ_B5_GAIN_SHIFT 6 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ 3691 #define WM8994_AIF2DAC_EQ_B5_GAIN_WIDTH 5 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ 3692 3693 /* 3694 * R1410 (0x582) - AIF2 EQ Band 1 A 3695 */ 3696 #define WM8994_AIF2DAC_EQ_B1_A_MASK 0xFFFF /* AIF2DAC_EQ_B1_A - [15:0] */ 3697 #define WM8994_AIF2DAC_EQ_B1_A_SHIFT 0 /* AIF2DAC_EQ_B1_A - [15:0] */ 3698 #define WM8994_AIF2DAC_EQ_B1_A_WIDTH 16 /* AIF2DAC_EQ_B1_A - [15:0] */ 3699 3700 /* 3701 * R1411 (0x583) - AIF2 EQ Band 1 B 3702 */ 3703 #define WM8994_AIF2DAC_EQ_B1_B_MASK 0xFFFF /* AIF2DAC_EQ_B1_B - [15:0] */ 3704 #define WM8994_AIF2DAC_EQ_B1_B_SHIFT 0 /* AIF2DAC_EQ_B1_B - [15:0] */ 3705 #define WM8994_AIF2DAC_EQ_B1_B_WIDTH 16 /* AIF2DAC_EQ_B1_B - [15:0] */ 3706 3707 /* 3708 * R1412 (0x584) - AIF2 EQ Band 1 PG 3709 */ 3710 #define WM8994_AIF2DAC_EQ_B1_PG_MASK 0xFFFF /* AIF2DAC_EQ_B1_PG - [15:0] */ 3711 #define WM8994_AIF2DAC_EQ_B1_PG_SHIFT 0 /* AIF2DAC_EQ_B1_PG - [15:0] */ 3712 #define WM8994_AIF2DAC_EQ_B1_PG_WIDTH 16 /* AIF2DAC_EQ_B1_PG - [15:0] */ 3713 3714 /* 3715 * R1413 (0x585) - AIF2 EQ Band 2 A 3716 */ 3717 #define WM8994_AIF2DAC_EQ_B2_A_MASK 0xFFFF /* AIF2DAC_EQ_B2_A - [15:0] */ 3718 #define WM8994_AIF2DAC_EQ_B2_A_SHIFT 0 /* AIF2DAC_EQ_B2_A - [15:0] */ 3719 #define WM8994_AIF2DAC_EQ_B2_A_WIDTH 16 /* AIF2DAC_EQ_B2_A - [15:0] */ 3720 3721 /* 3722 * R1414 (0x586) - AIF2 EQ Band 2 B 3723 */ 3724 #define WM8994_AIF2DAC_EQ_B2_B_MASK 0xFFFF /* AIF2DAC_EQ_B2_B - [15:0] */ 3725 #define WM8994_AIF2DAC_EQ_B2_B_SHIFT 0 /* AIF2DAC_EQ_B2_B - [15:0] */ 3726 #define WM8994_AIF2DAC_EQ_B2_B_WIDTH 16 /* AIF2DAC_EQ_B2_B - [15:0] */ 3727 3728 /* 3729 * R1415 (0x587) - AIF2 EQ Band 2 C 3730 */ 3731 #define WM8994_AIF2DAC_EQ_B2_C_MASK 0xFFFF /* AIF2DAC_EQ_B2_C - [15:0] */ 3732 #define WM8994_AIF2DAC_EQ_B2_C_SHIFT 0 /* AIF2DAC_EQ_B2_C - [15:0] */ 3733 #define WM8994_AIF2DAC_EQ_B2_C_WIDTH 16 /* AIF2DAC_EQ_B2_C - [15:0] */ 3734 3735 /* 3736 * R1416 (0x588) - AIF2 EQ Band 2 PG 3737 */ 3738 #define WM8994_AIF2DAC_EQ_B2_PG_MASK 0xFFFF /* AIF2DAC_EQ_B2_PG - [15:0] */ 3739 #define WM8994_AIF2DAC_EQ_B2_PG_SHIFT 0 /* AIF2DAC_EQ_B2_PG - [15:0] */ 3740 #define WM8994_AIF2DAC_EQ_B2_PG_WIDTH 16 /* AIF2DAC_EQ_B2_PG - [15:0] */ 3741 3742 /* 3743 * R1417 (0x589) - AIF2 EQ Band 3 A 3744 */ 3745 #define WM8994_AIF2DAC_EQ_B3_A_MASK 0xFFFF /* AIF2DAC_EQ_B3_A - [15:0] */ 3746 #define WM8994_AIF2DAC_EQ_B3_A_SHIFT 0 /* AIF2DAC_EQ_B3_A - [15:0] */ 3747 #define WM8994_AIF2DAC_EQ_B3_A_WIDTH 16 /* AIF2DAC_EQ_B3_A - [15:0] */ 3748 3749 /* 3750 * R1418 (0x58A) - AIF2 EQ Band 3 B 3751 */ 3752 #define WM8994_AIF2DAC_EQ_B3_B_MASK 0xFFFF /* AIF2DAC_EQ_B3_B - [15:0] */ 3753 #define WM8994_AIF2DAC_EQ_B3_B_SHIFT 0 /* AIF2DAC_EQ_B3_B - [15:0] */ 3754 #define WM8994_AIF2DAC_EQ_B3_B_WIDTH 16 /* AIF2DAC_EQ_B3_B - [15:0] */ 3755 3756 /* 3757 * R1419 (0x58B) - AIF2 EQ Band 3 C 3758 */ 3759 #define WM8994_AIF2DAC_EQ_B3_C_MASK 0xFFFF /* AIF2DAC_EQ_B3_C - [15:0] */ 3760 #define WM8994_AIF2DAC_EQ_B3_C_SHIFT 0 /* AIF2DAC_EQ_B3_C - [15:0] */ 3761 #define WM8994_AIF2DAC_EQ_B3_C_WIDTH 16 /* AIF2DAC_EQ_B3_C - [15:0] */ 3762 3763 /* 3764 * R1420 (0x58C) - AIF2 EQ Band 3 PG 3765 */ 3766 #define WM8994_AIF2DAC_EQ_B3_PG_MASK 0xFFFF /* AIF2DAC_EQ_B3_PG - [15:0] */ 3767 #define WM8994_AIF2DAC_EQ_B3_PG_SHIFT 0 /* AIF2DAC_EQ_B3_PG - [15:0] */ 3768 #define WM8994_AIF2DAC_EQ_B3_PG_WIDTH 16 /* AIF2DAC_EQ_B3_PG - [15:0] */ 3769 3770 /* 3771 * R1421 (0x58D) - AIF2 EQ Band 4 A 3772 */ 3773 #define WM8994_AIF2DAC_EQ_B4_A_MASK 0xFFFF /* AIF2DAC_EQ_B4_A - [15:0] */ 3774 #define WM8994_AIF2DAC_EQ_B4_A_SHIFT 0 /* AIF2DAC_EQ_B4_A - [15:0] */ 3775 #define WM8994_AIF2DAC_EQ_B4_A_WIDTH 16 /* AIF2DAC_EQ_B4_A - [15:0] */ 3776 3777 /* 3778 * R1422 (0x58E) - AIF2 EQ Band 4 B 3779 */ 3780 #define WM8994_AIF2DAC_EQ_B4_B_MASK 0xFFFF /* AIF2DAC_EQ_B4_B - [15:0] */ 3781 #define WM8994_AIF2DAC_EQ_B4_B_SHIFT 0 /* AIF2DAC_EQ_B4_B - [15:0] */ 3782 #define WM8994_AIF2DAC_EQ_B4_B_WIDTH 16 /* AIF2DAC_EQ_B4_B - [15:0] */ 3783 3784 /* 3785 * R1423 (0x58F) - AIF2 EQ Band 4 C 3786 */ 3787 #define WM8994_AIF2DAC_EQ_B4_C_MASK 0xFFFF /* AIF2DAC_EQ_B4_C - [15:0] */ 3788 #define WM8994_AIF2DAC_EQ_B4_C_SHIFT 0 /* AIF2DAC_EQ_B4_C - [15:0] */ 3789 #define WM8994_AIF2DAC_EQ_B4_C_WIDTH 16 /* AIF2DAC_EQ_B4_C - [15:0] */ 3790 3791 /* 3792 * R1424 (0x590) - AIF2 EQ Band 4 PG 3793 */ 3794 #define WM8994_AIF2DAC_EQ_B4_PG_MASK 0xFFFF /* AIF2DAC_EQ_B4_PG - [15:0] */ 3795 #define WM8994_AIF2DAC_EQ_B4_PG_SHIFT 0 /* AIF2DAC_EQ_B4_PG - [15:0] */ 3796 #define WM8994_AIF2DAC_EQ_B4_PG_WIDTH 16 /* AIF2DAC_EQ_B4_PG - [15:0] */ 3797 3798 /* 3799 * R1425 (0x591) - AIF2 EQ Band 5 A 3800 */ 3801 #define WM8994_AIF2DAC_EQ_B5_A_MASK 0xFFFF /* AIF2DAC_EQ_B5_A - [15:0] */ 3802 #define WM8994_AIF2DAC_EQ_B5_A_SHIFT 0 /* AIF2DAC_EQ_B5_A - [15:0] */ 3803 #define WM8994_AIF2DAC_EQ_B5_A_WIDTH 16 /* AIF2DAC_EQ_B5_A - [15:0] */ 3804 3805 /* 3806 * R1426 (0x592) - AIF2 EQ Band 5 B 3807 */ 3808 #define WM8994_AIF2DAC_EQ_B5_B_MASK 0xFFFF /* AIF2DAC_EQ_B5_B - [15:0] */ 3809 #define WM8994_AIF2DAC_EQ_B5_B_SHIFT 0 /* AIF2DAC_EQ_B5_B - [15:0] */ 3810 #define WM8994_AIF2DAC_EQ_B5_B_WIDTH 16 /* AIF2DAC_EQ_B5_B - [15:0] */ 3811 3812 /* 3813 * R1427 (0x593) - AIF2 EQ Band 5 PG 3814 */ 3815 #define WM8994_AIF2DAC_EQ_B5_PG_MASK 0xFFFF /* AIF2DAC_EQ_B5_PG - [15:0] */ 3816 #define WM8994_AIF2DAC_EQ_B5_PG_SHIFT 0 /* AIF2DAC_EQ_B5_PG - [15:0] */ 3817 #define WM8994_AIF2DAC_EQ_B5_PG_WIDTH 16 /* AIF2DAC_EQ_B5_PG - [15:0] */ 3818 3819 /* 3820 * R1536 (0x600) - DAC1 Mixer Volumes 3821 */ 3822 #define WM8994_ADCR_DAC1_VOL_MASK 0x01E0 /* ADCR_DAC1_VOL - [8:5] */ 3823 #define WM8994_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [8:5] */ 3824 #define WM8994_ADCR_DAC1_VOL_WIDTH 4 /* ADCR_DAC1_VOL - [8:5] */ 3825 #define WM8994_ADCL_DAC1_VOL_MASK 0x000F /* ADCL_DAC1_VOL - [3:0] */ 3826 #define WM8994_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [3:0] */ 3827 #define WM8994_ADCL_DAC1_VOL_WIDTH 4 /* ADCL_DAC1_VOL - [3:0] */ 3828 3829 /* 3830 * R1537 (0x601) - DAC1 Left Mixer Routing 3831 */ 3832 #define WM8994_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */ 3833 #define WM8994_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */ 3834 #define WM8994_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */ 3835 #define WM8994_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */ 3836 #define WM8994_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */ 3837 #define WM8994_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */ 3838 #define WM8994_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */ 3839 #define WM8994_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */ 3840 #define WM8994_AIF2DACL_TO_DAC1L 0x0004 /* AIF2DACL_TO_DAC1L */ 3841 #define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004 /* AIF2DACL_TO_DAC1L */ 3842 #define WM8994_AIF2DACL_TO_DAC1L_SHIFT 2 /* AIF2DACL_TO_DAC1L */ 3843 #define WM8994_AIF2DACL_TO_DAC1L_WIDTH 1 /* AIF2DACL_TO_DAC1L */ 3844 #define WM8994_AIF1DAC2L_TO_DAC1L 0x0002 /* AIF1DAC2L_TO_DAC1L */ 3845 #define WM8994_AIF1DAC2L_TO_DAC1L_MASK 0x0002 /* AIF1DAC2L_TO_DAC1L */ 3846 #define WM8994_AIF1DAC2L_TO_DAC1L_SHIFT 1 /* AIF1DAC2L_TO_DAC1L */ 3847 #define WM8994_AIF1DAC2L_TO_DAC1L_WIDTH 1 /* AIF1DAC2L_TO_DAC1L */ 3848 #define WM8994_AIF1DAC1L_TO_DAC1L 0x0001 /* AIF1DAC1L_TO_DAC1L */ 3849 #define WM8994_AIF1DAC1L_TO_DAC1L_MASK 0x0001 /* AIF1DAC1L_TO_DAC1L */ 3850 #define WM8994_AIF1DAC1L_TO_DAC1L_SHIFT 0 /* AIF1DAC1L_TO_DAC1L */ 3851 #define WM8994_AIF1DAC1L_TO_DAC1L_WIDTH 1 /* AIF1DAC1L_TO_DAC1L */ 3852 3853 /* 3854 * R1538 (0x602) - DAC1 Right Mixer Routing 3855 */ 3856 #define WM8994_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */ 3857 #define WM8994_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */ 3858 #define WM8994_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */ 3859 #define WM8994_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */ 3860 #define WM8994_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */ 3861 #define WM8994_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */ 3862 #define WM8994_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */ 3863 #define WM8994_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */ 3864 #define WM8994_AIF2DACR_TO_DAC1R 0x0004 /* AIF2DACR_TO_DAC1R */ 3865 #define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004 /* AIF2DACR_TO_DAC1R */ 3866 #define WM8994_AIF2DACR_TO_DAC1R_SHIFT 2 /* AIF2DACR_TO_DAC1R */ 3867 #define WM8994_AIF2DACR_TO_DAC1R_WIDTH 1 /* AIF2DACR_TO_DAC1R */ 3868 #define WM8994_AIF1DAC2R_TO_DAC1R 0x0002 /* AIF1DAC2R_TO_DAC1R */ 3869 #define WM8994_AIF1DAC2R_TO_DAC1R_MASK 0x0002 /* AIF1DAC2R_TO_DAC1R */ 3870 #define WM8994_AIF1DAC2R_TO_DAC1R_SHIFT 1 /* AIF1DAC2R_TO_DAC1R */ 3871 #define WM8994_AIF1DAC2R_TO_DAC1R_WIDTH 1 /* AIF1DAC2R_TO_DAC1R */ 3872 #define WM8994_AIF1DAC1R_TO_DAC1R 0x0001 /* AIF1DAC1R_TO_DAC1R */ 3873 #define WM8994_AIF1DAC1R_TO_DAC1R_MASK 0x0001 /* AIF1DAC1R_TO_DAC1R */ 3874 #define WM8994_AIF1DAC1R_TO_DAC1R_SHIFT 0 /* AIF1DAC1R_TO_DAC1R */ 3875 #define WM8994_AIF1DAC1R_TO_DAC1R_WIDTH 1 /* AIF1DAC1R_TO_DAC1R */ 3876 3877 /* 3878 * R1539 (0x603) - DAC2 Mixer Volumes 3879 */ 3880 #define WM8994_ADCR_DAC2_VOL_MASK 0x01E0 /* ADCR_DAC2_VOL - [8:5] */ 3881 #define WM8994_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [8:5] */ 3882 #define WM8994_ADCR_DAC2_VOL_WIDTH 4 /* ADCR_DAC2_VOL - [8:5] */ 3883 #define WM8994_ADCL_DAC2_VOL_MASK 0x000F /* ADCL_DAC2_VOL - [3:0] */ 3884 #define WM8994_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [3:0] */ 3885 #define WM8994_ADCL_DAC2_VOL_WIDTH 4 /* ADCL_DAC2_VOL - [3:0] */ 3886 3887 /* 3888 * R1540 (0x604) - DAC2 Left Mixer Routing 3889 */ 3890 #define WM8994_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */ 3891 #define WM8994_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */ 3892 #define WM8994_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */ 3893 #define WM8994_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */ 3894 #define WM8994_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */ 3895 #define WM8994_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */ 3896 #define WM8994_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */ 3897 #define WM8994_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */ 3898 #define WM8994_AIF2DACL_TO_DAC2L 0x0004 /* AIF2DACL_TO_DAC2L */ 3899 #define WM8994_AIF2DACL_TO_DAC2L_MASK 0x0004 /* AIF2DACL_TO_DAC2L */ 3900 #define WM8994_AIF2DACL_TO_DAC2L_SHIFT 2 /* AIF2DACL_TO_DAC2L */ 3901 #define WM8994_AIF2DACL_TO_DAC2L_WIDTH 1 /* AIF2DACL_TO_DAC2L */ 3902 #define WM8994_AIF1DAC2L_TO_DAC2L 0x0002 /* AIF1DAC2L_TO_DAC2L */ 3903 #define WM8994_AIF1DAC2L_TO_DAC2L_MASK 0x0002 /* AIF1DAC2L_TO_DAC2L */ 3904 #define WM8994_AIF1DAC2L_TO_DAC2L_SHIFT 1 /* AIF1DAC2L_TO_DAC2L */ 3905 #define WM8994_AIF1DAC2L_TO_DAC2L_WIDTH 1 /* AIF1DAC2L_TO_DAC2L */ 3906 #define WM8994_AIF1DAC1L_TO_DAC2L 0x0001 /* AIF1DAC1L_TO_DAC2L */ 3907 #define WM8994_AIF1DAC1L_TO_DAC2L_MASK 0x0001 /* AIF1DAC1L_TO_DAC2L */ 3908 #define WM8994_AIF1DAC1L_TO_DAC2L_SHIFT 0 /* AIF1DAC1L_TO_DAC2L */ 3909 #define WM8994_AIF1DAC1L_TO_DAC2L_WIDTH 1 /* AIF1DAC1L_TO_DAC2L */ 3910 3911 /* 3912 * R1541 (0x605) - DAC2 Right Mixer Routing 3913 */ 3914 #define WM8994_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */ 3915 #define WM8994_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */ 3916 #define WM8994_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */ 3917 #define WM8994_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */ 3918 #define WM8994_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */ 3919 #define WM8994_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */ 3920 #define WM8994_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */ 3921 #define WM8994_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */ 3922 #define WM8994_AIF2DACR_TO_DAC2R 0x0004 /* AIF2DACR_TO_DAC2R */ 3923 #define WM8994_AIF2DACR_TO_DAC2R_MASK 0x0004 /* AIF2DACR_TO_DAC2R */ 3924 #define WM8994_AIF2DACR_TO_DAC2R_SHIFT 2 /* AIF2DACR_TO_DAC2R */ 3925 #define WM8994_AIF2DACR_TO_DAC2R_WIDTH 1 /* AIF2DACR_TO_DAC2R */ 3926 #define WM8994_AIF1DAC2R_TO_DAC2R 0x0002 /* AIF1DAC2R_TO_DAC2R */ 3927 #define WM8994_AIF1DAC2R_TO_DAC2R_MASK 0x0002 /* AIF1DAC2R_TO_DAC2R */ 3928 #define WM8994_AIF1DAC2R_TO_DAC2R_SHIFT 1 /* AIF1DAC2R_TO_DAC2R */ 3929 #define WM8994_AIF1DAC2R_TO_DAC2R_WIDTH 1 /* AIF1DAC2R_TO_DAC2R */ 3930 #define WM8994_AIF1DAC1R_TO_DAC2R 0x0001 /* AIF1DAC1R_TO_DAC2R */ 3931 #define WM8994_AIF1DAC1R_TO_DAC2R_MASK 0x0001 /* AIF1DAC1R_TO_DAC2R */ 3932 #define WM8994_AIF1DAC1R_TO_DAC2R_SHIFT 0 /* AIF1DAC1R_TO_DAC2R */ 3933 #define WM8994_AIF1DAC1R_TO_DAC2R_WIDTH 1 /* AIF1DAC1R_TO_DAC2R */ 3934 3935 /* 3936 * R1542 (0x606) - AIF1 ADC1 Left Mixer Routing 3937 */ 3938 #define WM8994_ADC1L_TO_AIF1ADC1L 0x0002 /* ADC1L_TO_AIF1ADC1L */ 3939 #define WM8994_ADC1L_TO_AIF1ADC1L_MASK 0x0002 /* ADC1L_TO_AIF1ADC1L */ 3940 #define WM8994_ADC1L_TO_AIF1ADC1L_SHIFT 1 /* ADC1L_TO_AIF1ADC1L */ 3941 #define WM8994_ADC1L_TO_AIF1ADC1L_WIDTH 1 /* ADC1L_TO_AIF1ADC1L */ 3942 #define WM8994_AIF2DACL_TO_AIF1ADC1L 0x0001 /* AIF2DACL_TO_AIF1ADC1L */ 3943 #define WM8994_AIF2DACL_TO_AIF1ADC1L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC1L */ 3944 #define WM8994_AIF2DACL_TO_AIF1ADC1L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC1L */ 3945 #define WM8994_AIF2DACL_TO_AIF1ADC1L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC1L */ 3946 3947 /* 3948 * R1543 (0x607) - AIF1 ADC1 Right Mixer Routing 3949 */ 3950 #define WM8994_ADC1R_TO_AIF1ADC1R 0x0002 /* ADC1R_TO_AIF1ADC1R */ 3951 #define WM8994_ADC1R_TO_AIF1ADC1R_MASK 0x0002 /* ADC1R_TO_AIF1ADC1R */ 3952 #define WM8994_ADC1R_TO_AIF1ADC1R_SHIFT 1 /* ADC1R_TO_AIF1ADC1R */ 3953 #define WM8994_ADC1R_TO_AIF1ADC1R_WIDTH 1 /* ADC1R_TO_AIF1ADC1R */ 3954 #define WM8994_AIF2DACR_TO_AIF1ADC1R 0x0001 /* AIF2DACR_TO_AIF1ADC1R */ 3955 #define WM8994_AIF2DACR_TO_AIF1ADC1R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC1R */ 3956 #define WM8994_AIF2DACR_TO_AIF1ADC1R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC1R */ 3957 #define WM8994_AIF2DACR_TO_AIF1ADC1R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC1R */ 3958 3959 /* 3960 * R1544 (0x608) - AIF1 ADC2 Left Mixer Routing 3961 */ 3962 #define WM8994_ADC2L_TO_AIF1ADC2L 0x0002 /* ADC2L_TO_AIF1ADC2L */ 3963 #define WM8994_ADC2L_TO_AIF1ADC2L_MASK 0x0002 /* ADC2L_TO_AIF1ADC2L */ 3964 #define WM8994_ADC2L_TO_AIF1ADC2L_SHIFT 1 /* ADC2L_TO_AIF1ADC2L */ 3965 #define WM8994_ADC2L_TO_AIF1ADC2L_WIDTH 1 /* ADC2L_TO_AIF1ADC2L */ 3966 #define WM8994_AIF2DACL_TO_AIF1ADC2L 0x0001 /* AIF2DACL_TO_AIF1ADC2L */ 3967 #define WM8994_AIF2DACL_TO_AIF1ADC2L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC2L */ 3968 #define WM8994_AIF2DACL_TO_AIF1ADC2L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC2L */ 3969 #define WM8994_AIF2DACL_TO_AIF1ADC2L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC2L */ 3970 3971 /* 3972 * R1545 (0x609) - AIF1 ADC2 Right mixer Routing 3973 */ 3974 #define WM8994_ADC2R_TO_AIF1ADC2R 0x0002 /* ADC2R_TO_AIF1ADC2R */ 3975 #define WM8994_ADC2R_TO_AIF1ADC2R_MASK 0x0002 /* ADC2R_TO_AIF1ADC2R */ 3976 #define WM8994_ADC2R_TO_AIF1ADC2R_SHIFT 1 /* ADC2R_TO_AIF1ADC2R */ 3977 #define WM8994_ADC2R_TO_AIF1ADC2R_WIDTH 1 /* ADC2R_TO_AIF1ADC2R */ 3978 #define WM8994_AIF2DACR_TO_AIF1ADC2R 0x0001 /* AIF2DACR_TO_AIF1ADC2R */ 3979 #define WM8994_AIF2DACR_TO_AIF1ADC2R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC2R */ 3980 #define WM8994_AIF2DACR_TO_AIF1ADC2R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC2R */ 3981 #define WM8994_AIF2DACR_TO_AIF1ADC2R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC2R */ 3982 3983 /* 3984 * R1552 (0x610) - DAC1 Left Volume 3985 */ 3986 #define WM8994_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */ 3987 #define WM8994_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */ 3988 #define WM8994_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */ 3989 #define WM8994_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */ 3990 #define WM8994_DAC1_VU 0x0100 /* DAC1_VU */ 3991 #define WM8994_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 3992 #define WM8994_DAC1_VU_SHIFT 8 /* DAC1_VU */ 3993 #define WM8994_DAC1_VU_WIDTH 1 /* DAC1_VU */ 3994 #define WM8994_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */ 3995 #define WM8994_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */ 3996 #define WM8994_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */ 3997 3998 /* 3999 * R1553 (0x611) - DAC1 Right Volume 4000 */ 4001 #define WM8994_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */ 4002 #define WM8994_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */ 4003 #define WM8994_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */ 4004 #define WM8994_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */ 4005 #define WM8994_DAC1_VU 0x0100 /* DAC1_VU */ 4006 #define WM8994_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 4007 #define WM8994_DAC1_VU_SHIFT 8 /* DAC1_VU */ 4008 #define WM8994_DAC1_VU_WIDTH 1 /* DAC1_VU */ 4009 #define WM8994_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */ 4010 #define WM8994_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */ 4011 #define WM8994_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */ 4012 4013 /* 4014 * R1554 (0x612) - DAC2 Left Volume 4015 */ 4016 #define WM8994_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */ 4017 #define WM8994_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */ 4018 #define WM8994_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */ 4019 #define WM8994_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */ 4020 #define WM8994_DAC2_VU 0x0100 /* DAC2_VU */ 4021 #define WM8994_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 4022 #define WM8994_DAC2_VU_SHIFT 8 /* DAC2_VU */ 4023 #define WM8994_DAC2_VU_WIDTH 1 /* DAC2_VU */ 4024 #define WM8994_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */ 4025 #define WM8994_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */ 4026 #define WM8994_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */ 4027 4028 /* 4029 * R1555 (0x613) - DAC2 Right Volume 4030 */ 4031 #define WM8994_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */ 4032 #define WM8994_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */ 4033 #define WM8994_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */ 4034 #define WM8994_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */ 4035 #define WM8994_DAC2_VU 0x0100 /* DAC2_VU */ 4036 #define WM8994_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 4037 #define WM8994_DAC2_VU_SHIFT 8 /* DAC2_VU */ 4038 #define WM8994_DAC2_VU_WIDTH 1 /* DAC2_VU */ 4039 #define WM8994_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */ 4040 #define WM8994_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */ 4041 #define WM8994_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */ 4042 4043 /* 4044 * R1556 (0x614) - DAC Softmute 4045 */ 4046 #define WM8994_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */ 4047 #define WM8994_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */ 4048 #define WM8994_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */ 4049 #define WM8994_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */ 4050 #define WM8994_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */ 4051 #define WM8994_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */ 4052 #define WM8994_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */ 4053 #define WM8994_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ 4054 4055 /* 4056 * R1568 (0x620) - Oversampling 4057 */ 4058 #define WM8994_ADC_OSR128 0x0002 /* ADC_OSR128 */ 4059 #define WM8994_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */ 4060 #define WM8994_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */ 4061 #define WM8994_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */ 4062 #define WM8994_DAC_OSR128 0x0001 /* DAC_OSR128 */ 4063 #define WM8994_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */ 4064 #define WM8994_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */ 4065 #define WM8994_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */ 4066 4067 /* 4068 * R1569 (0x621) - Sidetone 4069 */ 4070 #define WM8994_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */ 4071 #define WM8994_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */ 4072 #define WM8994_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */ 4073 #define WM8994_ST_HPF 0x0040 /* ST_HPF */ 4074 #define WM8994_ST_HPF_MASK 0x0040 /* ST_HPF */ 4075 #define WM8994_ST_HPF_SHIFT 6 /* ST_HPF */ 4076 #define WM8994_ST_HPF_WIDTH 1 /* ST_HPF */ 4077 #define WM8994_STR_SEL 0x0002 /* STR_SEL */ 4078 #define WM8994_STR_SEL_MASK 0x0002 /* STR_SEL */ 4079 #define WM8994_STR_SEL_SHIFT 1 /* STR_SEL */ 4080 #define WM8994_STR_SEL_WIDTH 1 /* STR_SEL */ 4081 #define WM8994_STL_SEL 0x0001 /* STL_SEL */ 4082 #define WM8994_STL_SEL_MASK 0x0001 /* STL_SEL */ 4083 #define WM8994_STL_SEL_SHIFT 0 /* STL_SEL */ 4084 #define WM8994_STL_SEL_WIDTH 1 /* STL_SEL */ 4085 4086 /* 4087 * R1824 (0x720) - Pull Control (1) 4088 */ 4089 #define WM8994_DMICDAT2_PU 0x0800 /* DMICDAT2_PU */ 4090 #define WM8994_DMICDAT2_PU_MASK 0x0800 /* DMICDAT2_PU */ 4091 #define WM8994_DMICDAT2_PU_SHIFT 11 /* DMICDAT2_PU */ 4092 #define WM8994_DMICDAT2_PU_WIDTH 1 /* DMICDAT2_PU */ 4093 #define WM8994_DMICDAT2_PD 0x0400 /* DMICDAT2_PD */ 4094 #define WM8994_DMICDAT2_PD_MASK 0x0400 /* DMICDAT2_PD */ 4095 #define WM8994_DMICDAT2_PD_SHIFT 10 /* DMICDAT2_PD */ 4096 #define WM8994_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ 4097 #define WM8994_DMICDAT1_PU 0x0200 /* DMICDAT1_PU */ 4098 #define WM8994_DMICDAT1_PU_MASK 0x0200 /* DMICDAT1_PU */ 4099 #define WM8994_DMICDAT1_PU_SHIFT 9 /* DMICDAT1_PU */ 4100 #define WM8994_DMICDAT1_PU_WIDTH 1 /* DMICDAT1_PU */ 4101 #define WM8994_DMICDAT1_PD 0x0100 /* DMICDAT1_PD */ 4102 #define WM8994_DMICDAT1_PD_MASK 0x0100 /* DMICDAT1_PD */ 4103 #define WM8994_DMICDAT1_PD_SHIFT 8 /* DMICDAT1_PD */ 4104 #define WM8994_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ 4105 #define WM8994_MCLK1_PU 0x0080 /* MCLK1_PU */ 4106 #define WM8994_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */ 4107 #define WM8994_MCLK1_PU_SHIFT 7 /* MCLK1_PU */ 4108 #define WM8994_MCLK1_PU_WIDTH 1 /* MCLK1_PU */ 4109 #define WM8994_MCLK1_PD 0x0040 /* MCLK1_PD */ 4110 #define WM8994_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */ 4111 #define WM8994_MCLK1_PD_SHIFT 6 /* MCLK1_PD */ 4112 #define WM8994_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ 4113 #define WM8994_DACDAT1_PU 0x0020 /* DACDAT1_PU */ 4114 #define WM8994_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */ 4115 #define WM8994_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */ 4116 #define WM8994_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */ 4117 #define WM8994_DACDAT1_PD 0x0010 /* DACDAT1_PD */ 4118 #define WM8994_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */ 4119 #define WM8994_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */ 4120 #define WM8994_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */ 4121 #define WM8994_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */ 4122 #define WM8994_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */ 4123 #define WM8994_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */ 4124 #define WM8994_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */ 4125 #define WM8994_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */ 4126 #define WM8994_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */ 4127 #define WM8994_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */ 4128 #define WM8994_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */ 4129 #define WM8994_BCLK1_PU 0x0002 /* BCLK1_PU */ 4130 #define WM8994_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */ 4131 #define WM8994_BCLK1_PU_SHIFT 1 /* BCLK1_PU */ 4132 #define WM8994_BCLK1_PU_WIDTH 1 /* BCLK1_PU */ 4133 #define WM8994_BCLK1_PD 0x0001 /* BCLK1_PD */ 4134 #define WM8994_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */ 4135 #define WM8994_BCLK1_PD_SHIFT 0 /* BCLK1_PD */ 4136 #define WM8994_BCLK1_PD_WIDTH 1 /* BCLK1_PD */ 4137 4138 /* 4139 * R1825 (0x721) - Pull Control (2) 4140 */ 4141 #define WM8994_CSNADDR_PD 0x0100 /* CSNADDR_PD */ 4142 #define WM8994_CSNADDR_PD_MASK 0x0100 /* CSNADDR_PD */ 4143 #define WM8994_CSNADDR_PD_SHIFT 8 /* CSNADDR_PD */ 4144 #define WM8994_CSNADDR_PD_WIDTH 1 /* CSNADDR_PD */ 4145 #define WM8994_LDO2ENA_PD 0x0040 /* LDO2ENA_PD */ 4146 #define WM8994_LDO2ENA_PD_MASK 0x0040 /* LDO2ENA_PD */ 4147 #define WM8994_LDO2ENA_PD_SHIFT 6 /* LDO2ENA_PD */ 4148 #define WM8994_LDO2ENA_PD_WIDTH 1 /* LDO2ENA_PD */ 4149 #define WM8994_LDO1ENA_PD 0x0010 /* LDO1ENA_PD */ 4150 #define WM8994_LDO1ENA_PD_MASK 0x0010 /* LDO1ENA_PD */ 4151 #define WM8994_LDO1ENA_PD_SHIFT 4 /* LDO1ENA_PD */ 4152 #define WM8994_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ 4153 #define WM8994_CIFMODE_PD 0x0004 /* CIFMODE_PD */ 4154 #define WM8994_CIFMODE_PD_MASK 0x0004 /* CIFMODE_PD */ 4155 #define WM8994_CIFMODE_PD_SHIFT 2 /* CIFMODE_PD */ 4156 #define WM8994_CIFMODE_PD_WIDTH 1 /* CIFMODE_PD */ 4157 #define WM8994_SPKMODE_PU 0x0002 /* SPKMODE_PU */ 4158 #define WM8994_SPKMODE_PU_MASK 0x0002 /* SPKMODE_PU */ 4159 #define WM8994_SPKMODE_PU_SHIFT 1 /* SPKMODE_PU */ 4160 #define WM8994_SPKMODE_PU_WIDTH 1 /* SPKMODE_PU */ 4161 4162 /* 4163 * R1840 (0x730) - Interrupt Status 1 4164 */ 4165 #define WM8994_GP11_EINT 0x0400 /* GP11_EINT */ 4166 #define WM8994_GP11_EINT_MASK 0x0400 /* GP11_EINT */ 4167 #define WM8994_GP11_EINT_SHIFT 10 /* GP11_EINT */ 4168 #define WM8994_GP11_EINT_WIDTH 1 /* GP11_EINT */ 4169 #define WM8994_GP10_EINT 0x0200 /* GP10_EINT */ 4170 #define WM8994_GP10_EINT_MASK 0x0200 /* GP10_EINT */ 4171 #define WM8994_GP10_EINT_SHIFT 9 /* GP10_EINT */ 4172 #define WM8994_GP10_EINT_WIDTH 1 /* GP10_EINT */ 4173 #define WM8994_GP9_EINT 0x0100 /* GP9_EINT */ 4174 #define WM8994_GP9_EINT_MASK 0x0100 /* GP9_EINT */ 4175 #define WM8994_GP9_EINT_SHIFT 8 /* GP9_EINT */ 4176 #define WM8994_GP9_EINT_WIDTH 1 /* GP9_EINT */ 4177 #define WM8994_GP8_EINT 0x0080 /* GP8_EINT */ 4178 #define WM8994_GP8_EINT_MASK 0x0080 /* GP8_EINT */ 4179 #define WM8994_GP8_EINT_SHIFT 7 /* GP8_EINT */ 4180 #define WM8994_GP8_EINT_WIDTH 1 /* GP8_EINT */ 4181 #define WM8994_GP7_EINT 0x0040 /* GP7_EINT */ 4182 #define WM8994_GP7_EINT_MASK 0x0040 /* GP7_EINT */ 4183 #define WM8994_GP7_EINT_SHIFT 6 /* GP7_EINT */ 4184 #define WM8994_GP7_EINT_WIDTH 1 /* GP7_EINT */ 4185 #define WM8994_GP6_EINT 0x0020 /* GP6_EINT */ 4186 #define WM8994_GP6_EINT_MASK 0x0020 /* GP6_EINT */ 4187 #define WM8994_GP6_EINT_SHIFT 5 /* GP6_EINT */ 4188 #define WM8994_GP6_EINT_WIDTH 1 /* GP6_EINT */ 4189 #define WM8994_GP5_EINT 0x0010 /* GP5_EINT */ 4190 #define WM8994_GP5_EINT_MASK 0x0010 /* GP5_EINT */ 4191 #define WM8994_GP5_EINT_SHIFT 4 /* GP5_EINT */ 4192 #define WM8994_GP5_EINT_WIDTH 1 /* GP5_EINT */ 4193 #define WM8994_GP4_EINT 0x0008 /* GP4_EINT */ 4194 #define WM8994_GP4_EINT_MASK 0x0008 /* GP4_EINT */ 4195 #define WM8994_GP4_EINT_SHIFT 3 /* GP4_EINT */ 4196 #define WM8994_GP4_EINT_WIDTH 1 /* GP4_EINT */ 4197 #define WM8994_GP3_EINT 0x0004 /* GP3_EINT */ 4198 #define WM8994_GP3_EINT_MASK 0x0004 /* GP3_EINT */ 4199 #define WM8994_GP3_EINT_SHIFT 2 /* GP3_EINT */ 4200 #define WM8994_GP3_EINT_WIDTH 1 /* GP3_EINT */ 4201 #define WM8994_GP2_EINT 0x0002 /* GP2_EINT */ 4202 #define WM8994_GP2_EINT_MASK 0x0002 /* GP2_EINT */ 4203 #define WM8994_GP2_EINT_SHIFT 1 /* GP2_EINT */ 4204 #define WM8994_GP2_EINT_WIDTH 1 /* GP2_EINT */ 4205 #define WM8994_GP1_EINT 0x0001 /* GP1_EINT */ 4206 #define WM8994_GP1_EINT_MASK 0x0001 /* GP1_EINT */ 4207 #define WM8994_GP1_EINT_SHIFT 0 /* GP1_EINT */ 4208 #define WM8994_GP1_EINT_WIDTH 1 /* GP1_EINT */ 4209 4210 /* 4211 * R1841 (0x731) - Interrupt Status 2 4212 */ 4213 #define WM8994_TEMP_WARN_EINT 0x8000 /* TEMP_WARN_EINT */ 4214 #define WM8994_TEMP_WARN_EINT_MASK 0x8000 /* TEMP_WARN_EINT */ 4215 #define WM8994_TEMP_WARN_EINT_SHIFT 15 /* TEMP_WARN_EINT */ 4216 #define WM8994_TEMP_WARN_EINT_WIDTH 1 /* TEMP_WARN_EINT */ 4217 #define WM8994_DCS_DONE_EINT 0x4000 /* DCS_DONE_EINT */ 4218 #define WM8994_DCS_DONE_EINT_MASK 0x4000 /* DCS_DONE_EINT */ 4219 #define WM8994_DCS_DONE_EINT_SHIFT 14 /* DCS_DONE_EINT */ 4220 #define WM8994_DCS_DONE_EINT_WIDTH 1 /* DCS_DONE_EINT */ 4221 #define WM8994_WSEQ_DONE_EINT 0x2000 /* WSEQ_DONE_EINT */ 4222 #define WM8994_WSEQ_DONE_EINT_MASK 0x2000 /* WSEQ_DONE_EINT */ 4223 #define WM8994_WSEQ_DONE_EINT_SHIFT 13 /* WSEQ_DONE_EINT */ 4224 #define WM8994_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */ 4225 #define WM8994_FIFOS_ERR_EINT 0x1000 /* FIFOS_ERR_EINT */ 4226 #define WM8994_FIFOS_ERR_EINT_MASK 0x1000 /* FIFOS_ERR_EINT */ 4227 #define WM8994_FIFOS_ERR_EINT_SHIFT 12 /* FIFOS_ERR_EINT */ 4228 #define WM8994_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */ 4229 #define WM8994_AIF2DRC_SIG_DET_EINT 0x0800 /* AIF2DRC_SIG_DET_EINT */ 4230 #define WM8994_AIF2DRC_SIG_DET_EINT_MASK 0x0800 /* AIF2DRC_SIG_DET_EINT */ 4231 #define WM8994_AIF2DRC_SIG_DET_EINT_SHIFT 11 /* AIF2DRC_SIG_DET_EINT */ 4232 #define WM8994_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* AIF2DRC_SIG_DET_EINT */ 4233 #define WM8994_AIF1DRC2_SIG_DET_EINT 0x0400 /* AIF1DRC2_SIG_DET_EINT */ 4234 #define WM8994_AIF1DRC2_SIG_DET_EINT_MASK 0x0400 /* AIF1DRC2_SIG_DET_EINT */ 4235 #define WM8994_AIF1DRC2_SIG_DET_EINT_SHIFT 10 /* AIF1DRC2_SIG_DET_EINT */ 4236 #define WM8994_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* AIF1DRC2_SIG_DET_EINT */ 4237 #define WM8994_AIF1DRC1_SIG_DET_EINT 0x0200 /* AIF1DRC1_SIG_DET_EINT */ 4238 #define WM8994_AIF1DRC1_SIG_DET_EINT_MASK 0x0200 /* AIF1DRC1_SIG_DET_EINT */ 4239 #define WM8994_AIF1DRC1_SIG_DET_EINT_SHIFT 9 /* AIF1DRC1_SIG_DET_EINT */ 4240 #define WM8994_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* AIF1DRC1_SIG_DET_EINT */ 4241 #define WM8994_SRC2_LOCK_EINT 0x0100 /* SRC2_LOCK_EINT */ 4242 #define WM8994_SRC2_LOCK_EINT_MASK 0x0100 /* SRC2_LOCK_EINT */ 4243 #define WM8994_SRC2_LOCK_EINT_SHIFT 8 /* SRC2_LOCK_EINT */ 4244 #define WM8994_SRC2_LOCK_EINT_WIDTH 1 /* SRC2_LOCK_EINT */ 4245 #define WM8994_SRC1_LOCK_EINT 0x0080 /* SRC1_LOCK_EINT */ 4246 #define WM8994_SRC1_LOCK_EINT_MASK 0x0080 /* SRC1_LOCK_EINT */ 4247 #define WM8994_SRC1_LOCK_EINT_SHIFT 7 /* SRC1_LOCK_EINT */ 4248 #define WM8994_SRC1_LOCK_EINT_WIDTH 1 /* SRC1_LOCK_EINT */ 4249 #define WM8994_FLL2_LOCK_EINT 0x0040 /* FLL2_LOCK_EINT */ 4250 #define WM8994_FLL2_LOCK_EINT_MASK 0x0040 /* FLL2_LOCK_EINT */ 4251 #define WM8994_FLL2_LOCK_EINT_SHIFT 6 /* FLL2_LOCK_EINT */ 4252 #define WM8994_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */ 4253 #define WM8994_FLL1_LOCK_EINT 0x0020 /* FLL1_LOCK_EINT */ 4254 #define WM8994_FLL1_LOCK_EINT_MASK 0x0020 /* FLL1_LOCK_EINT */ 4255 #define WM8994_FLL1_LOCK_EINT_SHIFT 5 /* FLL1_LOCK_EINT */ 4256 #define WM8994_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */ 4257 #define WM8994_MIC2_SHRT_EINT 0x0010 /* MIC2_SHRT_EINT */ 4258 #define WM8994_MIC2_SHRT_EINT_MASK 0x0010 /* MIC2_SHRT_EINT */ 4259 #define WM8994_MIC2_SHRT_EINT_SHIFT 4 /* MIC2_SHRT_EINT */ 4260 #define WM8994_MIC2_SHRT_EINT_WIDTH 1 /* MIC2_SHRT_EINT */ 4261 #define WM8994_MIC2_DET_EINT 0x0008 /* MIC2_DET_EINT */ 4262 #define WM8994_MIC2_DET_EINT_MASK 0x0008 /* MIC2_DET_EINT */ 4263 #define WM8994_MIC2_DET_EINT_SHIFT 3 /* MIC2_DET_EINT */ 4264 #define WM8994_MIC2_DET_EINT_WIDTH 1 /* MIC2_DET_EINT */ 4265 #define WM8994_MIC1_SHRT_EINT 0x0004 /* MIC1_SHRT_EINT */ 4266 #define WM8994_MIC1_SHRT_EINT_MASK 0x0004 /* MIC1_SHRT_EINT */ 4267 #define WM8994_MIC1_SHRT_EINT_SHIFT 2 /* MIC1_SHRT_EINT */ 4268 #define WM8994_MIC1_SHRT_EINT_WIDTH 1 /* MIC1_SHRT_EINT */ 4269 #define WM8994_MIC1_DET_EINT 0x0002 /* MIC1_DET_EINT */ 4270 #define WM8994_MIC1_DET_EINT_MASK 0x0002 /* MIC1_DET_EINT */ 4271 #define WM8994_MIC1_DET_EINT_SHIFT 1 /* MIC1_DET_EINT */ 4272 #define WM8994_MIC1_DET_EINT_WIDTH 1 /* MIC1_DET_EINT */ 4273 #define WM8994_TEMP_SHUT_EINT 0x0001 /* TEMP_SHUT_EINT */ 4274 #define WM8994_TEMP_SHUT_EINT_MASK 0x0001 /* TEMP_SHUT_EINT */ 4275 #define WM8994_TEMP_SHUT_EINT_SHIFT 0 /* TEMP_SHUT_EINT */ 4276 #define WM8994_TEMP_SHUT_EINT_WIDTH 1 /* TEMP_SHUT_EINT */ 4277 4278 /* 4279 * R1842 (0x732) - Interrupt Raw Status 2 4280 */ 4281 #define WM8994_TEMP_WARN_STS 0x8000 /* TEMP_WARN_STS */ 4282 #define WM8994_TEMP_WARN_STS_MASK 0x8000 /* TEMP_WARN_STS */ 4283 #define WM8994_TEMP_WARN_STS_SHIFT 15 /* TEMP_WARN_STS */ 4284 #define WM8994_TEMP_WARN_STS_WIDTH 1 /* TEMP_WARN_STS */ 4285 #define WM8994_DCS_DONE_STS 0x4000 /* DCS_DONE_STS */ 4286 #define WM8994_DCS_DONE_STS_MASK 0x4000 /* DCS_DONE_STS */ 4287 #define WM8994_DCS_DONE_STS_SHIFT 14 /* DCS_DONE_STS */ 4288 #define WM8994_DCS_DONE_STS_WIDTH 1 /* DCS_DONE_STS */ 4289 #define WM8994_WSEQ_DONE_STS 0x2000 /* WSEQ_DONE_STS */ 4290 #define WM8994_WSEQ_DONE_STS_MASK 0x2000 /* WSEQ_DONE_STS */ 4291 #define WM8994_WSEQ_DONE_STS_SHIFT 13 /* WSEQ_DONE_STS */ 4292 #define WM8994_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */ 4293 #define WM8994_FIFOS_ERR_STS 0x1000 /* FIFOS_ERR_STS */ 4294 #define WM8994_FIFOS_ERR_STS_MASK 0x1000 /* FIFOS_ERR_STS */ 4295 #define WM8994_FIFOS_ERR_STS_SHIFT 12 /* FIFOS_ERR_STS */ 4296 #define WM8994_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */ 4297 #define WM8994_AIF2DRC_SIG_DET_STS 0x0800 /* AIF2DRC_SIG_DET_STS */ 4298 #define WM8994_AIF2DRC_SIG_DET_STS_MASK 0x0800 /* AIF2DRC_SIG_DET_STS */ 4299 #define WM8994_AIF2DRC_SIG_DET_STS_SHIFT 11 /* AIF2DRC_SIG_DET_STS */ 4300 #define WM8994_AIF2DRC_SIG_DET_STS_WIDTH 1 /* AIF2DRC_SIG_DET_STS */ 4301 #define WM8994_AIF1DRC2_SIG_DET_STS 0x0400 /* AIF1DRC2_SIG_DET_STS */ 4302 #define WM8994_AIF1DRC2_SIG_DET_STS_MASK 0x0400 /* AIF1DRC2_SIG_DET_STS */ 4303 #define WM8994_AIF1DRC2_SIG_DET_STS_SHIFT 10 /* AIF1DRC2_SIG_DET_STS */ 4304 #define WM8994_AIF1DRC2_SIG_DET_STS_WIDTH 1 /* AIF1DRC2_SIG_DET_STS */ 4305 #define WM8994_AIF1DRC1_SIG_DET_STS 0x0200 /* AIF1DRC1_SIG_DET_STS */ 4306 #define WM8994_AIF1DRC1_SIG_DET_STS_MASK 0x0200 /* AIF1DRC1_SIG_DET_STS */ 4307 #define WM8994_AIF1DRC1_SIG_DET_STS_SHIFT 9 /* AIF1DRC1_SIG_DET_STS */ 4308 #define WM8994_AIF1DRC1_SIG_DET_STS_WIDTH 1 /* AIF1DRC1_SIG_DET_STS */ 4309 #define WM8994_SRC2_LOCK_STS 0x0100 /* SRC2_LOCK_STS */ 4310 #define WM8994_SRC2_LOCK_STS_MASK 0x0100 /* SRC2_LOCK_STS */ 4311 #define WM8994_SRC2_LOCK_STS_SHIFT 8 /* SRC2_LOCK_STS */ 4312 #define WM8994_SRC2_LOCK_STS_WIDTH 1 /* SRC2_LOCK_STS */ 4313 #define WM8994_SRC1_LOCK_STS 0x0080 /* SRC1_LOCK_STS */ 4314 #define WM8994_SRC1_LOCK_STS_MASK 0x0080 /* SRC1_LOCK_STS */ 4315 #define WM8994_SRC1_LOCK_STS_SHIFT 7 /* SRC1_LOCK_STS */ 4316 #define WM8994_SRC1_LOCK_STS_WIDTH 1 /* SRC1_LOCK_STS */ 4317 #define WM8994_FLL2_LOCK_STS 0x0040 /* FLL2_LOCK_STS */ 4318 #define WM8994_FLL2_LOCK_STS_MASK 0x0040 /* FLL2_LOCK_STS */ 4319 #define WM8994_FLL2_LOCK_STS_SHIFT 6 /* FLL2_LOCK_STS */ 4320 #define WM8994_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */ 4321 #define WM8994_FLL1_LOCK_STS 0x0020 /* FLL1_LOCK_STS */ 4322 #define WM8994_FLL1_LOCK_STS_MASK 0x0020 /* FLL1_LOCK_STS */ 4323 #define WM8994_FLL1_LOCK_STS_SHIFT 5 /* FLL1_LOCK_STS */ 4324 #define WM8994_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */ 4325 #define WM8994_MIC2_SHRT_STS 0x0010 /* MIC2_SHRT_STS */ 4326 #define WM8994_MIC2_SHRT_STS_MASK 0x0010 /* MIC2_SHRT_STS */ 4327 #define WM8994_MIC2_SHRT_STS_SHIFT 4 /* MIC2_SHRT_STS */ 4328 #define WM8994_MIC2_SHRT_STS_WIDTH 1 /* MIC2_SHRT_STS */ 4329 #define WM8994_MIC2_DET_STS 0x0008 /* MIC2_DET_STS */ 4330 #define WM8994_MIC2_DET_STS_MASK 0x0008 /* MIC2_DET_STS */ 4331 #define WM8994_MIC2_DET_STS_SHIFT 3 /* MIC2_DET_STS */ 4332 #define WM8994_MIC2_DET_STS_WIDTH 1 /* MIC2_DET_STS */ 4333 #define WM8994_MIC1_SHRT_STS 0x0004 /* MIC1_SHRT_STS */ 4334 #define WM8994_MIC1_SHRT_STS_MASK 0x0004 /* MIC1_SHRT_STS */ 4335 #define WM8994_MIC1_SHRT_STS_SHIFT 2 /* MIC1_SHRT_STS */ 4336 #define WM8994_MIC1_SHRT_STS_WIDTH 1 /* MIC1_SHRT_STS */ 4337 #define WM8994_MIC1_DET_STS 0x0002 /* MIC1_DET_STS */ 4338 #define WM8994_MIC1_DET_STS_MASK 0x0002 /* MIC1_DET_STS */ 4339 #define WM8994_MIC1_DET_STS_SHIFT 1 /* MIC1_DET_STS */ 4340 #define WM8994_MIC1_DET_STS_WIDTH 1 /* MIC1_DET_STS */ 4341 #define WM8994_TEMP_SHUT_STS 0x0001 /* TEMP_SHUT_STS */ 4342 #define WM8994_TEMP_SHUT_STS_MASK 0x0001 /* TEMP_SHUT_STS */ 4343 #define WM8994_TEMP_SHUT_STS_SHIFT 0 /* TEMP_SHUT_STS */ 4344 #define WM8994_TEMP_SHUT_STS_WIDTH 1 /* TEMP_SHUT_STS */ 4345 4346 /* 4347 * R1848 (0x738) - Interrupt Status 1 Mask 4348 */ 4349 #define WM8994_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */ 4350 #define WM8994_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */ 4351 #define WM8994_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */ 4352 #define WM8994_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */ 4353 #define WM8994_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */ 4354 #define WM8994_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */ 4355 #define WM8994_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */ 4356 #define WM8994_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */ 4357 #define WM8994_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */ 4358 #define WM8994_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */ 4359 #define WM8994_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */ 4360 #define WM8994_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */ 4361 #define WM8994_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */ 4362 #define WM8994_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */ 4363 #define WM8994_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */ 4364 #define WM8994_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */ 4365 #define WM8994_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */ 4366 #define WM8994_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */ 4367 #define WM8994_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */ 4368 #define WM8994_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */ 4369 #define WM8994_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */ 4370 #define WM8994_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */ 4371 #define WM8994_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */ 4372 #define WM8994_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */ 4373 #define WM8994_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ 4374 #define WM8994_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ 4375 #define WM8994_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ 4376 #define WM8994_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ 4377 #define WM8994_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ 4378 #define WM8994_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ 4379 #define WM8994_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ 4380 #define WM8994_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ 4381 #define WM8994_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ 4382 #define WM8994_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ 4383 #define WM8994_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ 4384 #define WM8994_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ 4385 #define WM8994_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ 4386 #define WM8994_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ 4387 #define WM8994_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ 4388 #define WM8994_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ 4389 #define WM8994_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ 4390 #define WM8994_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ 4391 #define WM8994_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ 4392 #define WM8994_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ 4393 4394 /* 4395 * R1849 (0x739) - Interrupt Status 2 Mask 4396 */ 4397 #define WM8994_IM_TEMP_WARN_EINT 0x8000 /* IM_TEMP_WARN_EINT */ 4398 #define WM8994_IM_TEMP_WARN_EINT_MASK 0x8000 /* IM_TEMP_WARN_EINT */ 4399 #define WM8994_IM_TEMP_WARN_EINT_SHIFT 15 /* IM_TEMP_WARN_EINT */ 4400 #define WM8994_IM_TEMP_WARN_EINT_WIDTH 1 /* IM_TEMP_WARN_EINT */ 4401 #define WM8994_IM_DCS_DONE_EINT 0x4000 /* IM_DCS_DONE_EINT */ 4402 #define WM8994_IM_DCS_DONE_EINT_MASK 0x4000 /* IM_DCS_DONE_EINT */ 4403 #define WM8994_IM_DCS_DONE_EINT_SHIFT 14 /* IM_DCS_DONE_EINT */ 4404 #define WM8994_IM_DCS_DONE_EINT_WIDTH 1 /* IM_DCS_DONE_EINT */ 4405 #define WM8994_IM_WSEQ_DONE_EINT 0x2000 /* IM_WSEQ_DONE_EINT */ 4406 #define WM8994_IM_WSEQ_DONE_EINT_MASK 0x2000 /* IM_WSEQ_DONE_EINT */ 4407 #define WM8994_IM_WSEQ_DONE_EINT_SHIFT 13 /* IM_WSEQ_DONE_EINT */ 4408 #define WM8994_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */ 4409 #define WM8994_IM_FIFOS_ERR_EINT 0x1000 /* IM_FIFOS_ERR_EINT */ 4410 #define WM8994_IM_FIFOS_ERR_EINT_MASK 0x1000 /* IM_FIFOS_ERR_EINT */ 4411 #define WM8994_IM_FIFOS_ERR_EINT_SHIFT 12 /* IM_FIFOS_ERR_EINT */ 4412 #define WM8994_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */ 4413 #define WM8994_IM_AIF2DRC_SIG_DET_EINT 0x0800 /* IM_AIF2DRC_SIG_DET_EINT */ 4414 #define WM8994_IM_AIF2DRC_SIG_DET_EINT_MASK 0x0800 /* IM_AIF2DRC_SIG_DET_EINT */ 4415 #define WM8994_IM_AIF2DRC_SIG_DET_EINT_SHIFT 11 /* IM_AIF2DRC_SIG_DET_EINT */ 4416 #define WM8994_IM_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* IM_AIF2DRC_SIG_DET_EINT */ 4417 #define WM8994_IM_AIF1DRC2_SIG_DET_EINT 0x0400 /* IM_AIF1DRC2_SIG_DET_EINT */ 4418 #define WM8994_IM_AIF1DRC2_SIG_DET_EINT_MASK 0x0400 /* IM_AIF1DRC2_SIG_DET_EINT */ 4419 #define WM8994_IM_AIF1DRC2_SIG_DET_EINT_SHIFT 10 /* IM_AIF1DRC2_SIG_DET_EINT */ 4420 #define WM8994_IM_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC2_SIG_DET_EINT */ 4421 #define WM8994_IM_AIF1DRC1_SIG_DET_EINT 0x0200 /* IM_AIF1DRC1_SIG_DET_EINT */ 4422 #define WM8994_IM_AIF1DRC1_SIG_DET_EINT_MASK 0x0200 /* IM_AIF1DRC1_SIG_DET_EINT */ 4423 #define WM8994_IM_AIF1DRC1_SIG_DET_EINT_SHIFT 9 /* IM_AIF1DRC1_SIG_DET_EINT */ 4424 #define WM8994_IM_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC1_SIG_DET_EINT */ 4425 #define WM8994_IM_SRC2_LOCK_EINT 0x0100 /* IM_SRC2_LOCK_EINT */ 4426 #define WM8994_IM_SRC2_LOCK_EINT_MASK 0x0100 /* IM_SRC2_LOCK_EINT */ 4427 #define WM8994_IM_SRC2_LOCK_EINT_SHIFT 8 /* IM_SRC2_LOCK_EINT */ 4428 #define WM8994_IM_SRC2_LOCK_EINT_WIDTH 1 /* IM_SRC2_LOCK_EINT */ 4429 #define WM8994_IM_SRC1_LOCK_EINT 0x0080 /* IM_SRC1_LOCK_EINT */ 4430 #define WM8994_IM_SRC1_LOCK_EINT_MASK 0x0080 /* IM_SRC1_LOCK_EINT */ 4431 #define WM8994_IM_SRC1_LOCK_EINT_SHIFT 7 /* IM_SRC1_LOCK_EINT */ 4432 #define WM8994_IM_SRC1_LOCK_EINT_WIDTH 1 /* IM_SRC1_LOCK_EINT */ 4433 #define WM8994_IM_FLL2_LOCK_EINT 0x0040 /* IM_FLL2_LOCK_EINT */ 4434 #define WM8994_IM_FLL2_LOCK_EINT_MASK 0x0040 /* IM_FLL2_LOCK_EINT */ 4435 #define WM8994_IM_FLL2_LOCK_EINT_SHIFT 6 /* IM_FLL2_LOCK_EINT */ 4436 #define WM8994_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */ 4437 #define WM8994_IM_FLL1_LOCK_EINT 0x0020 /* IM_FLL1_LOCK_EINT */ 4438 #define WM8994_IM_FLL1_LOCK_EINT_MASK 0x0020 /* IM_FLL1_LOCK_EINT */ 4439 #define WM8994_IM_FLL1_LOCK_EINT_SHIFT 5 /* IM_FLL1_LOCK_EINT */ 4440 #define WM8994_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */ 4441 #define WM8994_IM_MIC2_SHRT_EINT 0x0010 /* IM_MIC2_SHRT_EINT */ 4442 #define WM8994_IM_MIC2_SHRT_EINT_MASK 0x0010 /* IM_MIC2_SHRT_EINT */ 4443 #define WM8994_IM_MIC2_SHRT_EINT_SHIFT 4 /* IM_MIC2_SHRT_EINT */ 4444 #define WM8994_IM_MIC2_SHRT_EINT_WIDTH 1 /* IM_MIC2_SHRT_EINT */ 4445 #define WM8994_IM_MIC2_DET_EINT 0x0008 /* IM_MIC2_DET_EINT */ 4446 #define WM8994_IM_MIC2_DET_EINT_MASK 0x0008 /* IM_MIC2_DET_EINT */ 4447 #define WM8994_IM_MIC2_DET_EINT_SHIFT 3 /* IM_MIC2_DET_EINT */ 4448 #define WM8994_IM_MIC2_DET_EINT_WIDTH 1 /* IM_MIC2_DET_EINT */ 4449 #define WM8994_IM_MIC1_SHRT_EINT 0x0004 /* IM_MIC1_SHRT_EINT */ 4450 #define WM8994_IM_MIC1_SHRT_EINT_MASK 0x0004 /* IM_MIC1_SHRT_EINT */ 4451 #define WM8994_IM_MIC1_SHRT_EINT_SHIFT 2 /* IM_MIC1_SHRT_EINT */ 4452 #define WM8994_IM_MIC1_SHRT_EINT_WIDTH 1 /* IM_MIC1_SHRT_EINT */ 4453 #define WM8994_IM_MIC1_DET_EINT 0x0002 /* IM_MIC1_DET_EINT */ 4454 #define WM8994_IM_MIC1_DET_EINT_MASK 0x0002 /* IM_MIC1_DET_EINT */ 4455 #define WM8994_IM_MIC1_DET_EINT_SHIFT 1 /* IM_MIC1_DET_EINT */ 4456 #define WM8994_IM_MIC1_DET_EINT_WIDTH 1 /* IM_MIC1_DET_EINT */ 4457 #define WM8994_IM_TEMP_SHUT_EINT 0x0001 /* IM_TEMP_SHUT_EINT */ 4458 #define WM8994_IM_TEMP_SHUT_EINT_MASK 0x0001 /* IM_TEMP_SHUT_EINT */ 4459 #define WM8994_IM_TEMP_SHUT_EINT_SHIFT 0 /* IM_TEMP_SHUT_EINT */ 4460 #define WM8994_IM_TEMP_SHUT_EINT_WIDTH 1 /* IM_TEMP_SHUT_EINT */ 4461 4462 /* 4463 * R1856 (0x740) - Interrupt Control 4464 */ 4465 #define WM8994_IM_IRQ 0x0001 /* IM_IRQ */ 4466 #define WM8994_IM_IRQ_MASK 0x0001 /* IM_IRQ */ 4467 #define WM8994_IM_IRQ_SHIFT 0 /* IM_IRQ */ 4468 #define WM8994_IM_IRQ_WIDTH 1 /* IM_IRQ */ 4469 4470 /* 4471 * R1864 (0x748) - IRQ Debounce 4472 */ 4473 #define WM8994_TEMP_WARN_DB 0x0020 /* TEMP_WARN_DB */ 4474 #define WM8994_TEMP_WARN_DB_MASK 0x0020 /* TEMP_WARN_DB */ 4475 #define WM8994_TEMP_WARN_DB_SHIFT 5 /* TEMP_WARN_DB */ 4476 #define WM8994_TEMP_WARN_DB_WIDTH 1 /* TEMP_WARN_DB */ 4477 #define WM8994_MIC2_SHRT_DB 0x0010 /* MIC2_SHRT_DB */ 4478 #define WM8994_MIC2_SHRT_DB_MASK 0x0010 /* MIC2_SHRT_DB */ 4479 #define WM8994_MIC2_SHRT_DB_SHIFT 4 /* MIC2_SHRT_DB */ 4480 #define WM8994_MIC2_SHRT_DB_WIDTH 1 /* MIC2_SHRT_DB */ 4481 #define WM8994_MIC2_DET_DB 0x0008 /* MIC2_DET_DB */ 4482 #define WM8994_MIC2_DET_DB_MASK 0x0008 /* MIC2_DET_DB */ 4483 #define WM8994_MIC2_DET_DB_SHIFT 3 /* MIC2_DET_DB */ 4484 #define WM8994_MIC2_DET_DB_WIDTH 1 /* MIC2_DET_DB */ 4485 #define WM8994_MIC1_SHRT_DB 0x0004 /* MIC1_SHRT_DB */ 4486 #define WM8994_MIC1_SHRT_DB_MASK 0x0004 /* MIC1_SHRT_DB */ 4487 #define WM8994_MIC1_SHRT_DB_SHIFT 2 /* MIC1_SHRT_DB */ 4488 #define WM8994_MIC1_SHRT_DB_WIDTH 1 /* MIC1_SHRT_DB */ 4489 #define WM8994_MIC1_DET_DB 0x0002 /* MIC1_DET_DB */ 4490 #define WM8994_MIC1_DET_DB_MASK 0x0002 /* MIC1_DET_DB */ 4491 #define WM8994_MIC1_DET_DB_SHIFT 1 /* MIC1_DET_DB */ 4492 #define WM8994_MIC1_DET_DB_WIDTH 1 /* MIC1_DET_DB */ 4493 #define WM8994_TEMP_SHUT_DB 0x0001 /* TEMP_SHUT_DB */ 4494 #define WM8994_TEMP_SHUT_DB_MASK 0x0001 /* TEMP_SHUT_DB */ 4495 #define WM8994_TEMP_SHUT_DB_SHIFT 0 /* TEMP_SHUT_DB */ 4496 #define WM8994_TEMP_SHUT_DB_WIDTH 1 /* TEMP_SHUT_DB */ 4497 4498 /* 4499 * R2304 (0x900) - DSP2_Program 4500 */ 4501 #define WM8958_DSP2_ENA 0x0001 /* DSP2_ENA */ 4502 #define WM8958_DSP2_ENA_MASK 0x0001 /* DSP2_ENA */ 4503 #define WM8958_DSP2_ENA_SHIFT 0 /* DSP2_ENA */ 4504 #define WM8958_DSP2_ENA_WIDTH 1 /* DSP2_ENA */ 4505 4506 /* 4507 * R2305 (0x901) - DSP2_Config 4508 */ 4509 #define WM8958_MBC_SEL_MASK 0x0030 /* MBC_SEL - [5:4] */ 4510 #define WM8958_MBC_SEL_SHIFT 4 /* MBC_SEL - [5:4] */ 4511 #define WM8958_MBC_SEL_WIDTH 2 /* MBC_SEL - [5:4] */ 4512 #define WM8958_MBC_ENA 0x0001 /* MBC_ENA */ 4513 #define WM8958_MBC_ENA_MASK 0x0001 /* MBC_ENA */ 4514 #define WM8958_MBC_ENA_SHIFT 0 /* MBC_ENA */ 4515 #define WM8958_MBC_ENA_WIDTH 1 /* MBC_ENA */ 4516 4517 /* 4518 * R2560 (0xA00) - DSP2_MagicNum 4519 */ 4520 #define WM8958_DSP2_MAGIC_NUM_MASK 0xFFFF /* DSP2_MAGIC_NUM - [15:0] */ 4521 #define WM8958_DSP2_MAGIC_NUM_SHIFT 0 /* DSP2_MAGIC_NUM - [15:0] */ 4522 #define WM8958_DSP2_MAGIC_NUM_WIDTH 16 /* DSP2_MAGIC_NUM - [15:0] */ 4523 4524 /* 4525 * R2561 (0xA01) - DSP2_ReleaseYear 4526 */ 4527 #define WM8958_DSP2_RELEASE_YEAR_MASK 0xFFFF /* DSP2_RELEASE_YEAR - [15:0] */ 4528 #define WM8958_DSP2_RELEASE_YEAR_SHIFT 0 /* DSP2_RELEASE_YEAR - [15:0] */ 4529 #define WM8958_DSP2_RELEASE_YEAR_WIDTH 16 /* DSP2_RELEASE_YEAR - [15:0] */ 4530 4531 /* 4532 * R2562 (0xA02) - DSP2_ReleaseMonthDay 4533 */ 4534 #define WM8958_DSP2_RELEASE_MONTH_MASK 0xFF00 /* DSP2_RELEASE_MONTH - [15:8] */ 4535 #define WM8958_DSP2_RELEASE_MONTH_SHIFT 8 /* DSP2_RELEASE_MONTH - [15:8] */ 4536 #define WM8958_DSP2_RELEASE_MONTH_WIDTH 8 /* DSP2_RELEASE_MONTH - [15:8] */ 4537 #define WM8958_DSP2_RELEASE_DAY_MASK 0x00FF /* DSP2_RELEASE_DAY - [7:0] */ 4538 #define WM8958_DSP2_RELEASE_DAY_SHIFT 0 /* DSP2_RELEASE_DAY - [7:0] */ 4539 #define WM8958_DSP2_RELEASE_DAY_WIDTH 8 /* DSP2_RELEASE_DAY - [7:0] */ 4540 4541 /* 4542 * R2563 (0xA03) - DSP2_ReleaseTime 4543 */ 4544 #define WM8958_DSP2_RELEASE_HOURS_MASK 0xFF00 /* DSP2_RELEASE_HOURS - [15:8] */ 4545 #define WM8958_DSP2_RELEASE_HOURS_SHIFT 8 /* DSP2_RELEASE_HOURS - [15:8] */ 4546 #define WM8958_DSP2_RELEASE_HOURS_WIDTH 8 /* DSP2_RELEASE_HOURS - [15:8] */ 4547 #define WM8958_DSP2_RELEASE_MINS_MASK 0x00FF /* DSP2_RELEASE_MINS - [7:0] */ 4548 #define WM8958_DSP2_RELEASE_MINS_SHIFT 0 /* DSP2_RELEASE_MINS - [7:0] */ 4549 #define WM8958_DSP2_RELEASE_MINS_WIDTH 8 /* DSP2_RELEASE_MINS - [7:0] */ 4550 4551 /* 4552 * R2564 (0xA04) - DSP2_VerMajMin 4553 */ 4554 #define WM8958_DSP2_MAJOR_VER_MASK 0xFF00 /* DSP2_MAJOR_VER - [15:8] */ 4555 #define WM8958_DSP2_MAJOR_VER_SHIFT 8 /* DSP2_MAJOR_VER - [15:8] */ 4556 #define WM8958_DSP2_MAJOR_VER_WIDTH 8 /* DSP2_MAJOR_VER - [15:8] */ 4557 #define WM8958_DSP2_MINOR_VER_MASK 0x00FF /* DSP2_MINOR_VER - [7:0] */ 4558 #define WM8958_DSP2_MINOR_VER_SHIFT 0 /* DSP2_MINOR_VER - [7:0] */ 4559 #define WM8958_DSP2_MINOR_VER_WIDTH 8 /* DSP2_MINOR_VER - [7:0] */ 4560 4561 /* 4562 * R2565 (0xA05) - DSP2_VerBuild 4563 */ 4564 #define WM8958_DSP2_BUILD_VER_MASK 0xFFFF /* DSP2_BUILD_VER - [15:0] */ 4565 #define WM8958_DSP2_BUILD_VER_SHIFT 0 /* DSP2_BUILD_VER - [15:0] */ 4566 #define WM8958_DSP2_BUILD_VER_WIDTH 16 /* DSP2_BUILD_VER - [15:0] */ 4567 4568 /* 4569 * R2573 (0xA0D) - DSP2_ExecControl 4570 */ 4571 #define WM8958_DSP2_STOPC 0x0020 /* DSP2_STOPC */ 4572 #define WM8958_DSP2_STOPC_MASK 0x0020 /* DSP2_STOPC */ 4573 #define WM8958_DSP2_STOPC_SHIFT 5 /* DSP2_STOPC */ 4574 #define WM8958_DSP2_STOPC_WIDTH 1 /* DSP2_STOPC */ 4575 #define WM8958_DSP2_STOPS 0x0010 /* DSP2_STOPS */ 4576 #define WM8958_DSP2_STOPS_MASK 0x0010 /* DSP2_STOPS */ 4577 #define WM8958_DSP2_STOPS_SHIFT 4 /* DSP2_STOPS */ 4578 #define WM8958_DSP2_STOPS_WIDTH 1 /* DSP2_STOPS */ 4579 #define WM8958_DSP2_STOPI 0x0008 /* DSP2_STOPI */ 4580 #define WM8958_DSP2_STOPI_MASK 0x0008 /* DSP2_STOPI */ 4581 #define WM8958_DSP2_STOPI_SHIFT 3 /* DSP2_STOPI */ 4582 #define WM8958_DSP2_STOPI_WIDTH 1 /* DSP2_STOPI */ 4583 #define WM8958_DSP2_STOP 0x0004 /* DSP2_STOP */ 4584 #define WM8958_DSP2_STOP_MASK 0x0004 /* DSP2_STOP */ 4585 #define WM8958_DSP2_STOP_SHIFT 2 /* DSP2_STOP */ 4586 #define WM8958_DSP2_STOP_WIDTH 1 /* DSP2_STOP */ 4587 #define WM8958_DSP2_RUNR 0x0002 /* DSP2_RUNR */ 4588 #define WM8958_DSP2_RUNR_MASK 0x0002 /* DSP2_RUNR */ 4589 #define WM8958_DSP2_RUNR_SHIFT 1 /* DSP2_RUNR */ 4590 #define WM8958_DSP2_RUNR_WIDTH 1 /* DSP2_RUNR */ 4591 #define WM8958_DSP2_RUN 0x0001 /* DSP2_RUN */ 4592 #define WM8958_DSP2_RUN_MASK 0x0001 /* DSP2_RUN */ 4593 #define WM8958_DSP2_RUN_SHIFT 0 /* DSP2_RUN */ 4594 #define WM8958_DSP2_RUN_WIDTH 1 /* DSP2_RUN */ 4595 4596 #endif 4597