1 /*
2 * twl4030.h - header for TWL4030 PM and audio CODEC device
3 *
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
5 *
6 * Based on tlv320aic23.c:
7 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25 #ifndef __TWL_H_
26 #define __TWL_H_
27
28 #include <linux/types.h>
29 #include <linux/input/matrix_keypad.h>
30
31 /*
32 * Using the twl4030 core we address registers using a pair
33 * { module id, relative register offset }
34 * which that core then maps to the relevant
35 * { i2c slave, absolute register address }
36 *
37 * The module IDs are meaningful only to the twl4030 core code,
38 * which uses them as array indices to look up the first register
39 * address each module uses within a given i2c slave.
40 */
41
42 /* Slave 0 (i2c address 0x48) */
43 #define TWL4030_MODULE_USB 0x00
44
45 /* Slave 1 (i2c address 0x49) */
46 #define TWL4030_MODULE_AUDIO_VOICE 0x01
47 #define TWL4030_MODULE_GPIO 0x02
48 #define TWL4030_MODULE_INTBR 0x03
49 #define TWL4030_MODULE_PIH 0x04
50 #define TWL4030_MODULE_TEST 0x05
51
52 /* Slave 2 (i2c address 0x4a) */
53 #define TWL4030_MODULE_KEYPAD 0x06
54 #define TWL4030_MODULE_MADC 0x07
55 #define TWL4030_MODULE_INTERRUPTS 0x08
56 #define TWL4030_MODULE_LED 0x09
57 #define TWL4030_MODULE_MAIN_CHARGE 0x0A
58 #define TWL4030_MODULE_PRECHARGE 0x0B
59 #define TWL4030_MODULE_PWM0 0x0C
60 #define TWL4030_MODULE_PWM1 0x0D
61 #define TWL4030_MODULE_PWMA 0x0E
62 #define TWL4030_MODULE_PWMB 0x0F
63
64 #define TWL5031_MODULE_ACCESSORY 0x10
65 #define TWL5031_MODULE_INTERRUPTS 0x11
66
67 /* Slave 3 (i2c address 0x4b) */
68 #define TWL4030_MODULE_BACKUP 0x12
69 #define TWL4030_MODULE_INT 0x13
70 #define TWL4030_MODULE_PM_MASTER 0x14
71 #define TWL4030_MODULE_PM_RECEIVER 0x15
72 #define TWL4030_MODULE_RTC 0x16
73 #define TWL4030_MODULE_SECURED_REG 0x17
74
75 #define TWL_MODULE_USB TWL4030_MODULE_USB
76 #define TWL_MODULE_AUDIO_VOICE TWL4030_MODULE_AUDIO_VOICE
77 #define TWL_MODULE_PIH TWL4030_MODULE_PIH
78 #define TWL_MODULE_MADC TWL4030_MODULE_MADC
79 #define TWL_MODULE_MAIN_CHARGE TWL4030_MODULE_MAIN_CHARGE
80 #define TWL_MODULE_PM_MASTER TWL4030_MODULE_PM_MASTER
81 #define TWL_MODULE_PM_RECEIVER TWL4030_MODULE_PM_RECEIVER
82 #define TWL_MODULE_RTC TWL4030_MODULE_RTC
83 #define TWL_MODULE_PWM TWL4030_MODULE_PWM0
84
85 #define TWL6030_MODULE_ID0 0x0D
86 #define TWL6030_MODULE_ID1 0x0E
87 #define TWL6030_MODULE_ID2 0x0F
88
89 #define GPIO_INTR_OFFSET 0
90 #define KEYPAD_INTR_OFFSET 1
91 #define BCI_INTR_OFFSET 2
92 #define MADC_INTR_OFFSET 3
93 #define USB_INTR_OFFSET 4
94 #define BCI_PRES_INTR_OFFSET 9
95 #define USB_PRES_INTR_OFFSET 10
96 #define RTC_INTR_OFFSET 11
97
98 /*
99 * Offset from TWL6030_IRQ_BASE / pdata->irq_base
100 */
101 #define PWR_INTR_OFFSET 0
102 #define HOTDIE_INTR_OFFSET 12
103 #define SMPSLDO_INTR_OFFSET 13
104 #define BATDETECT_INTR_OFFSET 14
105 #define SIMDETECT_INTR_OFFSET 15
106 #define MMCDETECT_INTR_OFFSET 16
107 #define GASGAUGE_INTR_OFFSET 17
108 #define USBOTG_INTR_OFFSET 4
109 #define CHARGER_INTR_OFFSET 2
110 #define RSV_INTR_OFFSET 0
111
112 /* INT register offsets */
113 #define REG_INT_STS_A 0x00
114 #define REG_INT_STS_B 0x01
115 #define REG_INT_STS_C 0x02
116
117 #define REG_INT_MSK_LINE_A 0x03
118 #define REG_INT_MSK_LINE_B 0x04
119 #define REG_INT_MSK_LINE_C 0x05
120
121 #define REG_INT_MSK_STS_A 0x06
122 #define REG_INT_MSK_STS_B 0x07
123 #define REG_INT_MSK_STS_C 0x08
124
125 /* MASK INT REG GROUP A */
126 #define TWL6030_PWR_INT_MASK 0x07
127 #define TWL6030_RTC_INT_MASK 0x18
128 #define TWL6030_HOTDIE_INT_MASK 0x20
129 #define TWL6030_SMPSLDOA_INT_MASK 0xC0
130
131 /* MASK INT REG GROUP B */
132 #define TWL6030_SMPSLDOB_INT_MASK 0x01
133 #define TWL6030_BATDETECT_INT_MASK 0x02
134 #define TWL6030_SIMDETECT_INT_MASK 0x04
135 #define TWL6030_MMCDETECT_INT_MASK 0x08
136 #define TWL6030_GPADC_INT_MASK 0x60
137 #define TWL6030_GASGAUGE_INT_MASK 0x80
138
139 /* MASK INT REG GROUP C */
140 #define TWL6030_USBOTG_INT_MASK 0x0F
141 #define TWL6030_CHARGER_CTRL_INT_MASK 0x10
142 #define TWL6030_CHARGER_FAULT_INT_MASK 0x60
143
144 #define TWL6030_MMCCTRL 0xEE
145 #define VMMC_AUTO_OFF (0x1 << 3)
146 #define SW_FC (0x1 << 2)
147 #define STS_MMC 0x1
148
149 #define TWL6030_CFG_INPUT_PUPD3 0xF2
150 #define MMC_PU (0x1 << 3)
151 #define MMC_PD (0x1 << 2)
152
153
154
155 #define TWL4030_CLASS_ID 0x4030
156 #define TWL6030_CLASS_ID 0x6030
157 unsigned int twl_rev(void);
158 #define GET_TWL_REV (twl_rev())
159 #define TWL_CLASS_IS(class, id) \
160 static inline int twl_class_is_ ##class(void) \
161 { \
162 return ((id) == (GET_TWL_REV)) ? 1 : 0; \
163 }
164
165 TWL_CLASS_IS(4030, TWL4030_CLASS_ID)
166 TWL_CLASS_IS(6030, TWL6030_CLASS_ID)
167
168 /*
169 * Read and write single 8-bit registers
170 */
171 int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg);
172 int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg);
173
174 /*
175 * Read and write several 8-bit registers at once.
176 *
177 * IMPORTANT: For twl_i2c_write(), allocate num_bytes + 1
178 * for the value, and populate your data starting at offset 1.
179 */
180 int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
181 int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
182
183 int twl6030_interrupt_unmask(u8 bit_mask, u8 offset);
184 int twl6030_interrupt_mask(u8 bit_mask, u8 offset);
185
186 /* Card detect Configuration for MMC1 Controller on OMAP4 */
187 #ifdef CONFIG_TWL4030_CORE
188 int twl6030_mmc_card_detect_config(void);
189 #else
twl6030_mmc_card_detect_config(void)190 static inline int twl6030_mmc_card_detect_config(void)
191 {
192 pr_debug("twl6030_mmc_card_detect_config not supported\n");
193 return 0;
194 }
195 #endif
196
197 /* MMC1 Controller on OMAP4 uses Phoenix irq for Card detect */
198 #ifdef CONFIG_TWL4030_CORE
199 int twl6030_mmc_card_detect(struct device *dev, int slot);
200 #else
twl6030_mmc_card_detect(struct device * dev,int slot)201 static inline int twl6030_mmc_card_detect(struct device *dev, int slot)
202 {
203 pr_debug("Call back twl6030_mmc_card_detect not supported\n");
204 return -EIO;
205 }
206 #endif
207 /*----------------------------------------------------------------------*/
208
209 /*
210 * NOTE: at up to 1024 registers, this is a big chip.
211 *
212 * Avoid putting register declarations in this file, instead of into
213 * a driver-private file, unless some of the registers in a block
214 * need to be shared with other drivers. One example is blocks that
215 * have Secondary IRQ Handler (SIH) registers.
216 */
217
218 #define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0)
219 #define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1)
220 #define TWL4030_SIH_CTRL_COR_MASK BIT(2)
221
222 /*----------------------------------------------------------------------*/
223
224 /*
225 * GPIO Block Register offsets (use TWL4030_MODULE_GPIO)
226 */
227
228 #define REG_GPIODATAIN1 0x0
229 #define REG_GPIODATAIN2 0x1
230 #define REG_GPIODATAIN3 0x2
231 #define REG_GPIODATADIR1 0x3
232 #define REG_GPIODATADIR2 0x4
233 #define REG_GPIODATADIR3 0x5
234 #define REG_GPIODATAOUT1 0x6
235 #define REG_GPIODATAOUT2 0x7
236 #define REG_GPIODATAOUT3 0x8
237 #define REG_CLEARGPIODATAOUT1 0x9
238 #define REG_CLEARGPIODATAOUT2 0xA
239 #define REG_CLEARGPIODATAOUT3 0xB
240 #define REG_SETGPIODATAOUT1 0xC
241 #define REG_SETGPIODATAOUT2 0xD
242 #define REG_SETGPIODATAOUT3 0xE
243 #define REG_GPIO_DEBEN1 0xF
244 #define REG_GPIO_DEBEN2 0x10
245 #define REG_GPIO_DEBEN3 0x11
246 #define REG_GPIO_CTRL 0x12
247 #define REG_GPIOPUPDCTR1 0x13
248 #define REG_GPIOPUPDCTR2 0x14
249 #define REG_GPIOPUPDCTR3 0x15
250 #define REG_GPIOPUPDCTR4 0x16
251 #define REG_GPIOPUPDCTR5 0x17
252 #define REG_GPIO_ISR1A 0x19
253 #define REG_GPIO_ISR2A 0x1A
254 #define REG_GPIO_ISR3A 0x1B
255 #define REG_GPIO_IMR1A 0x1C
256 #define REG_GPIO_IMR2A 0x1D
257 #define REG_GPIO_IMR3A 0x1E
258 #define REG_GPIO_ISR1B 0x1F
259 #define REG_GPIO_ISR2B 0x20
260 #define REG_GPIO_ISR3B 0x21
261 #define REG_GPIO_IMR1B 0x22
262 #define REG_GPIO_IMR2B 0x23
263 #define REG_GPIO_IMR3B 0x24
264 #define REG_GPIO_EDR1 0x28
265 #define REG_GPIO_EDR2 0x29
266 #define REG_GPIO_EDR3 0x2A
267 #define REG_GPIO_EDR4 0x2B
268 #define REG_GPIO_EDR5 0x2C
269 #define REG_GPIO_SIH_CTRL 0x2D
270
271 /* Up to 18 signals are available as GPIOs, when their
272 * pins are not assigned to another use (such as ULPI/USB).
273 */
274 #define TWL4030_GPIO_MAX 18
275
276 /*----------------------------------------------------------------------*/
277
278 /*Interface Bit Register (INTBR) offsets
279 *(Use TWL_4030_MODULE_INTBR)
280 */
281
282 #define REG_GPPUPDCTR1 0x0F
283
284 /*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */
285
286 #define I2C_SCL_CTRL_PU BIT(0)
287 #define I2C_SDA_CTRL_PU BIT(2)
288 #define SR_I2C_SCL_CTRL_PU BIT(4)
289 #define SR_I2C_SDA_CTRL_PU BIT(6)
290
291 /*----------------------------------------------------------------------*/
292
293 /*
294 * Keypad register offsets (use TWL4030_MODULE_KEYPAD)
295 * ... SIH/interrupt only
296 */
297
298 #define TWL4030_KEYPAD_KEYP_ISR1 0x11
299 #define TWL4030_KEYPAD_KEYP_IMR1 0x12
300 #define TWL4030_KEYPAD_KEYP_ISR2 0x13
301 #define TWL4030_KEYPAD_KEYP_IMR2 0x14
302 #define TWL4030_KEYPAD_KEYP_SIR 0x15 /* test register */
303 #define TWL4030_KEYPAD_KEYP_EDR 0x16
304 #define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
305
306 /*----------------------------------------------------------------------*/
307
308 /*
309 * Multichannel ADC register offsets (use TWL4030_MODULE_MADC)
310 * ... SIH/interrupt only
311 */
312
313 #define TWL4030_MADC_ISR1 0x61
314 #define TWL4030_MADC_IMR1 0x62
315 #define TWL4030_MADC_ISR2 0x63
316 #define TWL4030_MADC_IMR2 0x64
317 #define TWL4030_MADC_SIR 0x65 /* test register */
318 #define TWL4030_MADC_EDR 0x66
319 #define TWL4030_MADC_SIH_CTRL 0x67
320
321 /*----------------------------------------------------------------------*/
322
323 /*
324 * Battery charger register offsets (use TWL4030_MODULE_INTERRUPTS)
325 */
326
327 #define TWL4030_INTERRUPTS_BCIISR1A 0x0
328 #define TWL4030_INTERRUPTS_BCIISR2A 0x1
329 #define TWL4030_INTERRUPTS_BCIIMR1A 0x2
330 #define TWL4030_INTERRUPTS_BCIIMR2A 0x3
331 #define TWL4030_INTERRUPTS_BCIISR1B 0x4
332 #define TWL4030_INTERRUPTS_BCIISR2B 0x5
333 #define TWL4030_INTERRUPTS_BCIIMR1B 0x6
334 #define TWL4030_INTERRUPTS_BCIIMR2B 0x7
335 #define TWL4030_INTERRUPTS_BCISIR1 0x8 /* test register */
336 #define TWL4030_INTERRUPTS_BCISIR2 0x9 /* test register */
337 #define TWL4030_INTERRUPTS_BCIEDR1 0xa
338 #define TWL4030_INTERRUPTS_BCIEDR2 0xb
339 #define TWL4030_INTERRUPTS_BCIEDR3 0xc
340 #define TWL4030_INTERRUPTS_BCISIHCTRL 0xd
341
342 /*----------------------------------------------------------------------*/
343
344 /*
345 * Power Interrupt block register offsets (use TWL4030_MODULE_INT)
346 */
347
348 #define TWL4030_INT_PWR_ISR1 0x0
349 #define TWL4030_INT_PWR_IMR1 0x1
350 #define TWL4030_INT_PWR_ISR2 0x2
351 #define TWL4030_INT_PWR_IMR2 0x3
352 #define TWL4030_INT_PWR_SIR 0x4 /* test register */
353 #define TWL4030_INT_PWR_EDR1 0x5
354 #define TWL4030_INT_PWR_EDR2 0x6
355 #define TWL4030_INT_PWR_SIH_CTRL 0x7
356
357 /*----------------------------------------------------------------------*/
358
359 /*
360 * Accessory Interrupts
361 */
362 #define TWL5031_ACIIMR_LSB 0x05
363 #define TWL5031_ACIIMR_MSB 0x06
364 #define TWL5031_ACIIDR_LSB 0x07
365 #define TWL5031_ACIIDR_MSB 0x08
366 #define TWL5031_ACCISR1 0x0F
367 #define TWL5031_ACCIMR1 0x10
368 #define TWL5031_ACCISR2 0x11
369 #define TWL5031_ACCIMR2 0x12
370 #define TWL5031_ACCSIR 0x13
371 #define TWL5031_ACCEDR1 0x14
372 #define TWL5031_ACCSIHCTRL 0x15
373
374 /*----------------------------------------------------------------------*/
375
376 /*
377 * Battery Charger Controller
378 */
379
380 #define TWL5031_INTERRUPTS_BCIISR1 0x0
381 #define TWL5031_INTERRUPTS_BCIIMR1 0x1
382 #define TWL5031_INTERRUPTS_BCIISR2 0x2
383 #define TWL5031_INTERRUPTS_BCIIMR2 0x3
384 #define TWL5031_INTERRUPTS_BCISIR 0x4
385 #define TWL5031_INTERRUPTS_BCIEDR1 0x5
386 #define TWL5031_INTERRUPTS_BCIEDR2 0x6
387 #define TWL5031_INTERRUPTS_BCISIHCTRL 0x7
388
389 /*----------------------------------------------------------------------*/
390
391 /*
392 * PM Master module register offsets (use TWL4030_MODULE_PM_MASTER)
393 */
394
395 #define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x00
396 #define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x01
397 #define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x02
398 #define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x03
399 #define TWL4030_PM_MASTER_STS_BOOT 0x04
400 #define TWL4030_PM_MASTER_CFG_BOOT 0x05
401 #define TWL4030_PM_MASTER_SHUNDAN 0x06
402 #define TWL4030_PM_MASTER_BOOT_BCI 0x07
403 #define TWL4030_PM_MASTER_CFG_PWRANA1 0x08
404 #define TWL4030_PM_MASTER_CFG_PWRANA2 0x09
405 #define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x0b
406 #define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x0c
407 #define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x0d
408 #define TWL4030_PM_MASTER_PROTECT_KEY 0x0e
409 #define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x0f
410 #define TWL4030_PM_MASTER_P1_SW_EVENTS 0x10
411 #define TWL4030_PM_MASTER_P2_SW_EVENTS 0x11
412 #define TWL4030_PM_MASTER_P3_SW_EVENTS 0x12
413 #define TWL4030_PM_MASTER_STS_P123_STATE 0x13
414 #define TWL4030_PM_MASTER_PB_CFG 0x14
415 #define TWL4030_PM_MASTER_PB_WORD_MSB 0x15
416 #define TWL4030_PM_MASTER_PB_WORD_LSB 0x16
417 #define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x1c
418 #define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x1d
419 #define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x1e
420 #define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x1f
421 #define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x20
422 #define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x21
423 #define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x22
424 #define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x23
425 #define TWL4030_PM_MASTER_MEMORY_DATA 0x24
426
427 #define TWL4030_PM_MASTER_KEY_CFG1 0xc0
428 #define TWL4030_PM_MASTER_KEY_CFG2 0x0c
429
430 #define TWL4030_PM_MASTER_KEY_TST1 0xe0
431 #define TWL4030_PM_MASTER_KEY_TST2 0x0e
432
433 #define TWL4030_PM_MASTER_GLOBAL_TST 0xb6
434
435 /*----------------------------------------------------------------------*/
436
437 /* Power bus message definitions */
438
439 /* The TWL4030/5030 splits its power-management resources (the various
440 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
441 * P3. These groups can then be configured to transition between sleep, wait-on
442 * and active states by sending messages to the power bus. See Section 5.4.2
443 * Power Resources of TWL4030 TRM
444 */
445
446 /* Processor groups */
447 #define DEV_GRP_NULL 0x0
448 #define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
449 #define DEV_GRP_P2 0x2 /* P2: all Modem devices */
450 #define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
451
452 /* Resource groups */
453 #define RES_GRP_RES 0x0 /* Reserved */
454 #define RES_GRP_PP 0x1 /* Power providers */
455 #define RES_GRP_RC 0x2 /* Reset and control */
456 #define RES_GRP_PP_RC 0x3
457 #define RES_GRP_PR 0x4 /* Power references */
458 #define RES_GRP_PP_PR 0x5
459 #define RES_GRP_RC_PR 0x6
460 #define RES_GRP_ALL 0x7 /* All resource groups */
461
462 #define RES_TYPE2_R0 0x0
463
464 #define RES_TYPE_ALL 0x7
465
466 /* Resource states */
467 #define RES_STATE_WRST 0xF
468 #define RES_STATE_ACTIVE 0xE
469 #define RES_STATE_SLEEP 0x8
470 #define RES_STATE_OFF 0x0
471
472 /* Power resources */
473
474 /* Power providers */
475 #define RES_VAUX1 1
476 #define RES_VAUX2 2
477 #define RES_VAUX3 3
478 #define RES_VAUX4 4
479 #define RES_VMMC1 5
480 #define RES_VMMC2 6
481 #define RES_VPLL1 7
482 #define RES_VPLL2 8
483 #define RES_VSIM 9
484 #define RES_VDAC 10
485 #define RES_VINTANA1 11
486 #define RES_VINTANA2 12
487 #define RES_VINTDIG 13
488 #define RES_VIO 14
489 #define RES_VDD1 15
490 #define RES_VDD2 16
491 #define RES_VUSB_1V5 17
492 #define RES_VUSB_1V8 18
493 #define RES_VUSB_3V1 19
494 #define RES_VUSBCP 20
495 #define RES_REGEN 21
496 /* Reset and control */
497 #define RES_NRES_PWRON 22
498 #define RES_CLKEN 23
499 #define RES_SYSEN 24
500 #define RES_HFCLKOUT 25
501 #define RES_32KCLKOUT 26
502 #define RES_RESET 27
503 /* Power Reference */
504 #define RES_Main_Ref 28
505
506 #define TOTAL_RESOURCES 28
507 /*
508 * Power Bus Message Format ... these can be sent individually by Linux,
509 * but are usually part of downloaded scripts that are run when various
510 * power events are triggered.
511 *
512 * Broadcast Message (16 Bits):
513 * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
514 * RES_STATE[3:0]
515 *
516 * Singular Message (16 Bits):
517 * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
518 */
519
520 #define MSG_BROADCAST(devgrp, grp, type, type2, state) \
521 ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
522 | (type) << 4 | (state))
523
524 #define MSG_SINGULAR(devgrp, id, state) \
525 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
526
527 #define MSG_BROADCAST_ALL(devgrp, state) \
528 ((devgrp) << 5 | (state))
529
530 #define MSG_BROADCAST_REF MSG_BROADCAST_ALL
531 #define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
532 #define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
533 /*----------------------------------------------------------------------*/
534
535 struct twl4030_clock_init_data {
536 bool ck32k_lowpwr_enable;
537 };
538
539 struct twl4030_bci_platform_data {
540 int *battery_tmp_tbl;
541 unsigned int tblsize;
542 };
543
544 /* TWL4030_GPIO_MAX (18) GPIOs, with interrupts */
545 struct twl4030_gpio_platform_data {
546 int gpio_base;
547 unsigned irq_base, irq_end;
548
549 /* package the two LED signals as output-only GPIOs? */
550 bool use_leds;
551
552 /* gpio-n should control VMMC(n+1) if BIT(n) in mmc_cd is set */
553 u8 mmc_cd;
554
555 /* if BIT(N) is set, or VMMC(n+1) is linked, debounce GPIO-N */
556 u32 debounce;
557
558 /* For gpio-N, bit (1 << N) in "pullups" is set if that pullup
559 * should be enabled. Else, if that bit is set in "pulldowns",
560 * that pulldown is enabled. Don't waste power by letting any
561 * digital inputs float...
562 */
563 u32 pullups;
564 u32 pulldowns;
565
566 int (*setup)(struct device *dev,
567 unsigned gpio, unsigned ngpio);
568 int (*teardown)(struct device *dev,
569 unsigned gpio, unsigned ngpio);
570 };
571
572 struct twl4030_madc_platform_data {
573 int irq_line;
574 };
575
576 /* Boards have unique mappings of {row, col} --> keycode.
577 * Column and row are 8 bits each, but range only from 0..7.
578 * a PERSISTENT_KEY is "always on" and never reported.
579 */
580 #define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED)
581
582 struct twl4030_keypad_data {
583 const struct matrix_keymap_data *keymap_data;
584 unsigned rows;
585 unsigned cols;
586 bool rep;
587 };
588
589 enum twl4030_usb_mode {
590 T2_USB_MODE_ULPI = 1,
591 T2_USB_MODE_CEA2011_3PIN = 2,
592 };
593
594 struct twl4030_usb_data {
595 enum twl4030_usb_mode usb_mode;
596
597 int (*phy_init)(struct device *dev);
598 int (*phy_exit)(struct device *dev);
599 /* Power on/off the PHY */
600 int (*phy_power)(struct device *dev, int iD, int on);
601 /* enable/disable phy clocks */
602 int (*phy_set_clock)(struct device *dev, int on);
603 /* suspend/resume of phy */
604 int (*phy_suspend)(struct device *dev, int suspend);
605 };
606
607 struct twl4030_ins {
608 u16 pmb_message;
609 u8 delay;
610 };
611
612 struct twl4030_script {
613 struct twl4030_ins *script;
614 unsigned size;
615 u8 flags;
616 #define TWL4030_WRST_SCRIPT (1<<0)
617 #define TWL4030_WAKEUP12_SCRIPT (1<<1)
618 #define TWL4030_WAKEUP3_SCRIPT (1<<2)
619 #define TWL4030_SLEEP_SCRIPT (1<<3)
620 };
621
622 struct twl4030_resconfig {
623 u8 resource;
624 u8 devgroup; /* Processor group that Power resource belongs to */
625 u8 type; /* Power resource addressed, 6 / broadcast message */
626 u8 type2; /* Power resource addressed, 3 / broadcast message */
627 u8 remap_off; /* off state remapping */
628 u8 remap_sleep; /* sleep state remapping */
629 };
630
631 struct twl4030_power_data {
632 struct twl4030_script **scripts;
633 unsigned num;
634 struct twl4030_resconfig *resource_config;
635 #define TWL4030_RESCONFIG_UNDEF ((u8)-1)
636 };
637
638 extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
639 extern int twl4030_remove_script(u8 flags);
640
641 struct twl4030_codec_audio_data {
642 unsigned int digimic_delay; /* in ms */
643 unsigned int ramp_delay_value;
644 unsigned int offset_cncl_path;
645 unsigned int check_defaults:1;
646 unsigned int reset_registers:1;
647 unsigned int hs_extmute:1;
648 void (*set_hs_extmute)(int mute);
649 };
650
651 struct twl4030_codec_vibra_data {
652 unsigned int coexist;
653 };
654
655 struct twl4030_codec_data {
656 unsigned int audio_mclk;
657 struct twl4030_codec_audio_data *audio;
658 struct twl4030_codec_vibra_data *vibra;
659
660 /* twl6040 */
661 int audpwron_gpio; /* audio power-on gpio */
662 int naudint_irq; /* audio interrupt */
663 };
664
665 struct twl4030_platform_data {
666 unsigned irq_base, irq_end;
667 struct twl4030_clock_init_data *clock;
668 struct twl4030_bci_platform_data *bci;
669 struct twl4030_gpio_platform_data *gpio;
670 struct twl4030_madc_platform_data *madc;
671 struct twl4030_keypad_data *keypad;
672 struct twl4030_usb_data *usb;
673 struct twl4030_power_data *power;
674 struct twl4030_codec_data *codec;
675
676 /* Common LDO regulators for TWL4030/TWL6030 */
677 struct regulator_init_data *vdac;
678 struct regulator_init_data *vaux1;
679 struct regulator_init_data *vaux2;
680 struct regulator_init_data *vaux3;
681 /* TWL4030 LDO regulators */
682 struct regulator_init_data *vpll1;
683 struct regulator_init_data *vpll2;
684 struct regulator_init_data *vmmc1;
685 struct regulator_init_data *vmmc2;
686 struct regulator_init_data *vsim;
687 struct regulator_init_data *vaux4;
688 struct regulator_init_data *vio;
689 struct regulator_init_data *vdd1;
690 struct regulator_init_data *vdd2;
691 struct regulator_init_data *vintana1;
692 struct regulator_init_data *vintana2;
693 struct regulator_init_data *vintdig;
694 /* TWL6030 LDO regulators */
695 struct regulator_init_data *vmmc;
696 struct regulator_init_data *vpp;
697 struct regulator_init_data *vusim;
698 struct regulator_init_data *vana;
699 struct regulator_init_data *vcxio;
700 struct regulator_init_data *vusb;
701 struct regulator_init_data *clk32kg;
702 };
703
704 /*----------------------------------------------------------------------*/
705
706 int twl4030_sih_setup(int module);
707
708 /* Offsets to Power Registers */
709 #define TWL4030_VDAC_DEV_GRP 0x3B
710 #define TWL4030_VDAC_DEDICATED 0x3E
711 #define TWL4030_VAUX1_DEV_GRP 0x17
712 #define TWL4030_VAUX1_DEDICATED 0x1A
713 #define TWL4030_VAUX2_DEV_GRP 0x1B
714 #define TWL4030_VAUX2_DEDICATED 0x1E
715 #define TWL4030_VAUX3_DEV_GRP 0x1F
716 #define TWL4030_VAUX3_DEDICATED 0x22
717
twl4030charger_usb_en(int enable)718 static inline int twl4030charger_usb_en(int enable) { return 0; }
719
720 /*----------------------------------------------------------------------*/
721
722 /* Linux-specific regulator identifiers ... for now, we only support
723 * the LDOs, and leave the three buck converters alone. VDD1 and VDD2
724 * need to tie into hardware based voltage scaling (cpufreq etc), while
725 * VIO is generally fixed.
726 */
727
728 /* TWL4030 SMPS/LDO's */
729 /* EXTERNAL dc-to-dc buck converters */
730 #define TWL4030_REG_VDD1 0
731 #define TWL4030_REG_VDD2 1
732 #define TWL4030_REG_VIO 2
733
734 /* EXTERNAL LDOs */
735 #define TWL4030_REG_VDAC 3
736 #define TWL4030_REG_VPLL1 4
737 #define TWL4030_REG_VPLL2 5 /* not on all chips */
738 #define TWL4030_REG_VMMC1 6
739 #define TWL4030_REG_VMMC2 7 /* not on all chips */
740 #define TWL4030_REG_VSIM 8 /* not on all chips */
741 #define TWL4030_REG_VAUX1 9 /* not on all chips */
742 #define TWL4030_REG_VAUX2_4030 10 /* (twl4030-specific) */
743 #define TWL4030_REG_VAUX2 11 /* (twl5030 and newer) */
744 #define TWL4030_REG_VAUX3 12 /* not on all chips */
745 #define TWL4030_REG_VAUX4 13 /* not on all chips */
746
747 /* INTERNAL LDOs */
748 #define TWL4030_REG_VINTANA1 14
749 #define TWL4030_REG_VINTANA2 15
750 #define TWL4030_REG_VINTDIG 16
751 #define TWL4030_REG_VUSB1V5 17
752 #define TWL4030_REG_VUSB1V8 18
753 #define TWL4030_REG_VUSB3V1 19
754
755 /* TWL6030 SMPS/LDO's */
756 /* EXTERNAL dc-to-dc buck convertor controllable via SR */
757 #define TWL6030_REG_VDD1 30
758 #define TWL6030_REG_VDD2 31
759 #define TWL6030_REG_VDD3 32
760
761 /* Non SR compliant dc-to-dc buck convertors */
762 #define TWL6030_REG_VMEM 33
763 #define TWL6030_REG_V2V1 34
764 #define TWL6030_REG_V1V29 35
765 #define TWL6030_REG_V1V8 36
766
767 /* EXTERNAL LDOs */
768 #define TWL6030_REG_VAUX1_6030 37
769 #define TWL6030_REG_VAUX2_6030 38
770 #define TWL6030_REG_VAUX3_6030 39
771 #define TWL6030_REG_VMMC 40
772 #define TWL6030_REG_VPP 41
773 #define TWL6030_REG_VUSIM 42
774 #define TWL6030_REG_VANA 43
775 #define TWL6030_REG_VCXIO 44
776 #define TWL6030_REG_VDAC 45
777 #define TWL6030_REG_VUSB 46
778
779 /* INTERNAL LDOs */
780 #define TWL6030_REG_VRTC 47
781 #define TWL6030_REG_CLK32KG 48
782
783 #endif /* End of __TWL4030_H */
784