1 /*
2  * Copyright © 2008 Keith Packard
3  *
4  * Permission to use, copy, modify, distribute, and sell this software and its
5  * documentation for any purpose is hereby granted without fee, provided that
6  * the above copyright notice appear in all copies and that both that copyright
7  * notice and this permission notice appear in supporting documentation, and
8  * that the name of the copyright holders not be used in advertising or
9  * publicity pertaining to distribution of the software without specific,
10  * written prior permission.  The copyright holders make no representations
11  * about the suitability of this software for any purpose.  It is provided "as
12  * is" without express or implied warranty.
13  *
14  * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16  * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18  * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20  * OF THIS SOFTWARE.
21  */
22 
23 #ifndef _DRM_DP_HELPER_H_
24 #define _DRM_DP_HELPER_H_
25 
26 #include <linux/types.h>
27 #include <linux/i2c.h>
28 
29 /* From the VESA DisplayPort spec */
30 
31 #define AUX_NATIVE_WRITE	0x8
32 #define AUX_NATIVE_READ		0x9
33 #define AUX_I2C_WRITE		0x0
34 #define AUX_I2C_READ		0x1
35 #define AUX_I2C_STATUS		0x2
36 #define AUX_I2C_MOT		0x4
37 
38 #define AUX_NATIVE_REPLY_ACK	(0x0 << 4)
39 #define AUX_NATIVE_REPLY_NACK	(0x1 << 4)
40 #define AUX_NATIVE_REPLY_DEFER	(0x2 << 4)
41 #define AUX_NATIVE_REPLY_MASK	(0x3 << 4)
42 
43 #define AUX_I2C_REPLY_ACK	(0x0 << 6)
44 #define AUX_I2C_REPLY_NACK	(0x1 << 6)
45 #define AUX_I2C_REPLY_DEFER	(0x2 << 6)
46 #define AUX_I2C_REPLY_MASK	(0x3 << 6)
47 
48 /* AUX CH addresses */
49 /* DPCD */
50 #define DP_DPCD_REV                         0x000
51 
52 #define DP_MAX_LINK_RATE                    0x001
53 
54 #define DP_MAX_LANE_COUNT                   0x002
55 # define DP_MAX_LANE_COUNT_MASK		    0x1f
56 # define DP_ENHANCED_FRAME_CAP		    (1 << 7)
57 
58 #define DP_MAX_DOWNSPREAD                   0x003
59 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING  (1 << 6)
60 
61 #define DP_NORP                             0x004
62 
63 #define DP_DOWNSTREAMPORT_PRESENT           0x005
64 # define DP_DWN_STRM_PORT_PRESENT           (1 << 0)
65 # define DP_DWN_STRM_PORT_TYPE_MASK         0x06
66 /* 00b = DisplayPort */
67 /* 01b = Analog */
68 /* 10b = TMDS or HDMI */
69 /* 11b = Other */
70 # define DP_FORMAT_CONVERSION               (1 << 3)
71 
72 #define DP_MAIN_LINK_CHANNEL_CODING         0x006
73 
74 /* link configuration */
75 #define	DP_LINK_BW_SET		            0x100
76 # define DP_LINK_BW_1_62		    0x06
77 # define DP_LINK_BW_2_7			    0x0a
78 
79 #define DP_LANE_COUNT_SET	            0x101
80 # define DP_LANE_COUNT_MASK		    0x0f
81 # define DP_LANE_COUNT_ENHANCED_FRAME_EN    (1 << 7)
82 
83 #define DP_TRAINING_PATTERN_SET	            0x102
84 # define DP_TRAINING_PATTERN_DISABLE	    0
85 # define DP_TRAINING_PATTERN_1		    1
86 # define DP_TRAINING_PATTERN_2		    2
87 # define DP_TRAINING_PATTERN_MASK	    0x3
88 
89 # define DP_LINK_QUAL_PATTERN_DISABLE	    (0 << 2)
90 # define DP_LINK_QUAL_PATTERN_D10_2	    (1 << 2)
91 # define DP_LINK_QUAL_PATTERN_ERROR_RATE    (2 << 2)
92 # define DP_LINK_QUAL_PATTERN_PRBS7	    (3 << 2)
93 # define DP_LINK_QUAL_PATTERN_MASK	    (3 << 2)
94 
95 # define DP_RECOVERED_CLOCK_OUT_EN	    (1 << 4)
96 # define DP_LINK_SCRAMBLING_DISABLE	    (1 << 5)
97 
98 # define DP_SYMBOL_ERROR_COUNT_BOTH	    (0 << 6)
99 # define DP_SYMBOL_ERROR_COUNT_DISPARITY    (1 << 6)
100 # define DP_SYMBOL_ERROR_COUNT_SYMBOL	    (2 << 6)
101 # define DP_SYMBOL_ERROR_COUNT_MASK	    (3 << 6)
102 
103 #define DP_TRAINING_LANE0_SET		    0x103
104 #define DP_TRAINING_LANE1_SET		    0x104
105 #define DP_TRAINING_LANE2_SET		    0x105
106 #define DP_TRAINING_LANE3_SET		    0x106
107 
108 # define DP_TRAIN_VOLTAGE_SWING_MASK	    0x3
109 # define DP_TRAIN_VOLTAGE_SWING_SHIFT	    0
110 # define DP_TRAIN_MAX_SWING_REACHED	    (1 << 2)
111 # define DP_TRAIN_VOLTAGE_SWING_400	    (0 << 0)
112 # define DP_TRAIN_VOLTAGE_SWING_600	    (1 << 0)
113 # define DP_TRAIN_VOLTAGE_SWING_800	    (2 << 0)
114 # define DP_TRAIN_VOLTAGE_SWING_1200	    (3 << 0)
115 
116 # define DP_TRAIN_PRE_EMPHASIS_MASK	    (3 << 3)
117 # define DP_TRAIN_PRE_EMPHASIS_0	    (0 << 3)
118 # define DP_TRAIN_PRE_EMPHASIS_3_5	    (1 << 3)
119 # define DP_TRAIN_PRE_EMPHASIS_6	    (2 << 3)
120 # define DP_TRAIN_PRE_EMPHASIS_9_5	    (3 << 3)
121 
122 # define DP_TRAIN_PRE_EMPHASIS_SHIFT	    3
123 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED  (1 << 5)
124 
125 #define DP_DOWNSPREAD_CTRL		    0x107
126 # define DP_SPREAD_AMP_0_5		    (1 << 4)
127 
128 #define DP_MAIN_LINK_CHANNEL_CODING_SET	    0x108
129 # define DP_SET_ANSI_8B10B		    (1 << 0)
130 
131 #define DP_LANE0_1_STATUS		    0x202
132 #define DP_LANE2_3_STATUS		    0x203
133 # define DP_LANE_CR_DONE		    (1 << 0)
134 # define DP_LANE_CHANNEL_EQ_DONE	    (1 << 1)
135 # define DP_LANE_SYMBOL_LOCKED		    (1 << 2)
136 
137 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE |		\
138 			    DP_LANE_CHANNEL_EQ_DONE |	\
139 			    DP_LANE_SYMBOL_LOCKED)
140 
141 #define DP_LANE_ALIGN_STATUS_UPDATED	    0x204
142 
143 #define DP_INTERLANE_ALIGN_DONE		    (1 << 0)
144 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED   (1 << 6)
145 #define DP_LINK_STATUS_UPDATED		    (1 << 7)
146 
147 #define DP_SINK_STATUS			    0x205
148 
149 #define DP_RECEIVE_PORT_0_STATUS	    (1 << 0)
150 #define DP_RECEIVE_PORT_1_STATUS	    (1 << 1)
151 
152 #define DP_ADJUST_REQUEST_LANE0_1	    0x206
153 #define DP_ADJUST_REQUEST_LANE2_3	    0x207
154 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK  0x03
155 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
156 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK   0x0c
157 # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT  2
158 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK  0x30
159 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
160 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK   0xc0
161 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT  6
162 
163 #define DP_SET_POWER                        0x600
164 # define DP_SET_POWER_D0                    0x1
165 # define DP_SET_POWER_D3                    0x2
166 
167 #define MODE_I2C_START	1
168 #define MODE_I2C_WRITE	2
169 #define MODE_I2C_READ	4
170 #define MODE_I2C_STOP	8
171 
172 struct i2c_algo_dp_aux_data {
173 	bool running;
174 	u16 address;
175 	int (*aux_ch) (struct i2c_adapter *adapter,
176 		       int mode, uint8_t write_byte,
177 		       uint8_t *read_byte);
178 };
179 
180 int
181 i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
182 
183 #endif /* _DRM_DP_HELPER_H_ */
184