1 /*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 #ifndef __LINUX_XHCI_HCD_H
24 #define __LINUX_XHCI_HCD_H
25
26 #include <linux/usb.h>
27 #include <linux/timer.h>
28 #include <linux/kernel.h>
29 #include <linux/usb/hcd.h>
30
31 /* Code sharing between pci-quirks and xhci hcd */
32 #include "xhci-ext-caps.h"
33 #include "pci-quirks.h"
34
35 /* xHCI PCI Configuration Registers */
36 #define XHCI_SBRN_OFFSET (0x60)
37
38 /* Max number of USB devices for any host controller - limit in section 6.1 */
39 #define MAX_HC_SLOTS 256
40 /* Section 5.3.3 - MaxPorts */
41 #define MAX_HC_PORTS 127
42
43 /*
44 * xHCI register interface.
45 * This corresponds to the eXtensible Host Controller Interface (xHCI)
46 * Revision 0.95 specification
47 */
48
49 /**
50 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
51 * @hc_capbase: length of the capabilities register and HC version number
52 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
53 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
54 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
55 * @hcc_params: HCCPARAMS - Capability Parameters
56 * @db_off: DBOFF - Doorbell array offset
57 * @run_regs_off: RTSOFF - Runtime register space offset
58 */
59 struct xhci_cap_regs {
60 u32 hc_capbase;
61 u32 hcs_params1;
62 u32 hcs_params2;
63 u32 hcs_params3;
64 u32 hcc_params;
65 u32 db_off;
66 u32 run_regs_off;
67 /* Reserved up to (CAPLENGTH - 0x1C) */
68 };
69
70 /* hc_capbase bitmasks */
71 /* bits 7:0 - how long is the Capabilities register */
72 #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
73 /* bits 31:16 */
74 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
75
76 /* HCSPARAMS1 - hcs_params1 - bitmasks */
77 /* bits 0:7, Max Device Slots */
78 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
79 #define HCS_SLOTS_MASK 0xff
80 /* bits 8:18, Max Interrupters */
81 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
82 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
83 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
84
85 /* HCSPARAMS2 - hcs_params2 - bitmasks */
86 /* bits 0:3, frames or uframes that SW needs to queue transactions
87 * ahead of the HW to meet periodic deadlines */
88 #define HCS_IST(p) (((p) >> 0) & 0xf)
89 /* bits 4:7, max number of Event Ring segments */
90 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
91 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
92 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
93 #define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f)
94
95 /* HCSPARAMS3 - hcs_params3 - bitmasks */
96 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
97 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
98 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
99 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
100
101 /* HCCPARAMS - hcc_params - bitmasks */
102 /* true: HC can use 64-bit address pointers */
103 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
104 /* true: HC can do bandwidth negotiation */
105 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
106 /* true: HC uses 64-byte Device Context structures
107 * FIXME 64-byte context structures aren't supported yet.
108 */
109 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
110 /* true: HC has port power switches */
111 #define HCC_PPC(p) ((p) & (1 << 3))
112 /* true: HC has port indicators */
113 #define HCS_INDICATOR(p) ((p) & (1 << 4))
114 /* true: HC has Light HC Reset Capability */
115 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
116 /* true: HC supports latency tolerance messaging */
117 #define HCC_LTC(p) ((p) & (1 << 6))
118 /* true: no secondary Stream ID Support */
119 #define HCC_NSS(p) ((p) & (1 << 7))
120 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
121 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
122 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
123 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
124
125 /* db_off bitmask - bits 0:1 reserved */
126 #define DBOFF_MASK (~0x3)
127
128 /* run_regs_off bitmask - bits 0:4 reserved */
129 #define RTSOFF_MASK (~0x1f)
130
131
132 /* Number of registers per port */
133 #define NUM_PORT_REGS 4
134
135 /**
136 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
137 * @command: USBCMD - xHC command register
138 * @status: USBSTS - xHC status register
139 * @page_size: This indicates the page size that the host controller
140 * supports. If bit n is set, the HC supports a page size
141 * of 2^(n+12), up to a 128MB page size.
142 * 4K is the minimum page size.
143 * @cmd_ring: CRP - 64-bit Command Ring Pointer
144 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
145 * @config_reg: CONFIG - Configure Register
146 * @port_status_base: PORTSCn - base address for Port Status and Control
147 * Each port has a Port Status and Control register,
148 * followed by a Port Power Management Status and Control
149 * register, a Port Link Info register, and a reserved
150 * register.
151 * @port_power_base: PORTPMSCn - base address for
152 * Port Power Management Status and Control
153 * @port_link_base: PORTLIn - base address for Port Link Info (current
154 * Link PM state and control) for USB 2.1 and USB 3.0
155 * devices.
156 */
157 struct xhci_op_regs {
158 u32 command;
159 u32 status;
160 u32 page_size;
161 u32 reserved1;
162 u32 reserved2;
163 u32 dev_notification;
164 u64 cmd_ring;
165 /* rsvd: offset 0x20-2F */
166 u32 reserved3[4];
167 u64 dcbaa_ptr;
168 u32 config_reg;
169 /* rsvd: offset 0x3C-3FF */
170 u32 reserved4[241];
171 /* port 1 registers, which serve as a base address for other ports */
172 u32 port_status_base;
173 u32 port_power_base;
174 u32 port_link_base;
175 u32 reserved5;
176 /* registers for ports 2-255 */
177 u32 reserved6[NUM_PORT_REGS*254];
178 };
179
180 /* USBCMD - USB command - command bitmasks */
181 /* start/stop HC execution - do not write unless HC is halted*/
182 #define CMD_RUN XHCI_CMD_RUN
183 /* Reset HC - resets internal HC state machine and all registers (except
184 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
185 * The xHCI driver must reinitialize the xHC after setting this bit.
186 */
187 #define CMD_RESET (1 << 1)
188 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
189 #define CMD_EIE XHCI_CMD_EIE
190 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
191 #define CMD_HSEIE XHCI_CMD_HSEIE
192 /* bits 4:6 are reserved (and should be preserved on writes). */
193 /* light reset (port status stays unchanged) - reset completed when this is 0 */
194 #define CMD_LRESET (1 << 7)
195 /* host controller save/restore state. */
196 #define CMD_CSS (1 << 8)
197 #define CMD_CRS (1 << 9)
198 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
199 #define CMD_EWE XHCI_CMD_EWE
200 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
201 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
202 * '0' means the xHC can power it off if all ports are in the disconnect,
203 * disabled, or powered-off state.
204 */
205 #define CMD_PM_INDEX (1 << 11)
206 /* bits 12:31 are reserved (and should be preserved on writes). */
207
208 /* USBSTS - USB status - status bitmasks */
209 /* HC not running - set to 1 when run/stop bit is cleared. */
210 #define STS_HALT XHCI_STS_HALT
211 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
212 #define STS_FATAL (1 << 2)
213 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
214 #define STS_EINT (1 << 3)
215 /* port change detect */
216 #define STS_PORT (1 << 4)
217 /* bits 5:7 reserved and zeroed */
218 /* save state status - '1' means xHC is saving state */
219 #define STS_SAVE (1 << 8)
220 /* restore state status - '1' means xHC is restoring state */
221 #define STS_RESTORE (1 << 9)
222 /* true: save or restore error */
223 #define STS_SRE (1 << 10)
224 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
225 #define STS_CNR XHCI_STS_CNR
226 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
227 #define STS_HCE (1 << 12)
228 /* bits 13:31 reserved and should be preserved */
229
230 /*
231 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
232 * Generate a device notification event when the HC sees a transaction with a
233 * notification type that matches a bit set in this bit field.
234 */
235 #define DEV_NOTE_MASK (0xffff)
236 #define ENABLE_DEV_NOTE(x) (1 << (x))
237 /* Most of the device notification types should only be used for debug.
238 * SW does need to pay attention to function wake notifications.
239 */
240 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
241
242 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
243 /* bit 0 is the command ring cycle state */
244 /* stop ring operation after completion of the currently executing command */
245 #define CMD_RING_PAUSE (1 << 1)
246 /* stop ring immediately - abort the currently executing command */
247 #define CMD_RING_ABORT (1 << 2)
248 /* true: command ring is running */
249 #define CMD_RING_RUNNING (1 << 3)
250 /* bits 4:5 reserved and should be preserved */
251 /* Command Ring pointer - bit mask for the lower 32 bits. */
252 #define CMD_RING_RSVD_BITS (0x3f)
253
254 /* CONFIG - Configure Register - config_reg bitmasks */
255 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
256 #define MAX_DEVS(p) ((p) & 0xff)
257 /* bits 8:31 - reserved and should be preserved */
258
259 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
260 /* true: device connected */
261 #define PORT_CONNECT (1 << 0)
262 /* true: port enabled */
263 #define PORT_PE (1 << 1)
264 /* bit 2 reserved and zeroed */
265 /* true: port has an over-current condition */
266 #define PORT_OC (1 << 3)
267 /* true: port reset signaling asserted */
268 #define PORT_RESET (1 << 4)
269 /* Port Link State - bits 5:8
270 * A read gives the current link PM state of the port,
271 * a write with Link State Write Strobe set sets the link state.
272 */
273 #define PORT_PLS_MASK (0xf << 5)
274 #define XDEV_U0 (0x0 << 5)
275 #define XDEV_U3 (0x3 << 5)
276 #define XDEV_RESUME (0xf << 5)
277 /* true: port has power (see HCC_PPC) */
278 #define PORT_POWER (1 << 9)
279 /* bits 10:13 indicate device speed:
280 * 0 - undefined speed - port hasn't be initialized by a reset yet
281 * 1 - full speed
282 * 2 - low speed
283 * 3 - high speed
284 * 4 - super speed
285 * 5-15 reserved
286 */
287 #define DEV_SPEED_MASK (0xf << 10)
288 #define XDEV_FS (0x1 << 10)
289 #define XDEV_LS (0x2 << 10)
290 #define XDEV_HS (0x3 << 10)
291 #define XDEV_SS (0x4 << 10)
292 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
293 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
294 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
295 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
296 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
297 /* Bits 20:23 in the Slot Context are the speed for the device */
298 #define SLOT_SPEED_FS (XDEV_FS << 10)
299 #define SLOT_SPEED_LS (XDEV_LS << 10)
300 #define SLOT_SPEED_HS (XDEV_HS << 10)
301 #define SLOT_SPEED_SS (XDEV_SS << 10)
302 /* Port Indicator Control */
303 #define PORT_LED_OFF (0 << 14)
304 #define PORT_LED_AMBER (1 << 14)
305 #define PORT_LED_GREEN (2 << 14)
306 #define PORT_LED_MASK (3 << 14)
307 /* Port Link State Write Strobe - set this when changing link state */
308 #define PORT_LINK_STROBE (1 << 16)
309 /* true: connect status change */
310 #define PORT_CSC (1 << 17)
311 /* true: port enable change */
312 #define PORT_PEC (1 << 18)
313 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
314 * into an enabled state, and the device into the default state. A "warm" reset
315 * also resets the link, forcing the device through the link training sequence.
316 * SW can also look at the Port Reset register to see when warm reset is done.
317 */
318 #define PORT_WRC (1 << 19)
319 /* true: over-current change */
320 #define PORT_OCC (1 << 20)
321 /* true: reset change - 1 to 0 transition of PORT_RESET */
322 #define PORT_RC (1 << 21)
323 /* port link status change - set on some port link state transitions:
324 * Transition Reason
325 * ------------------------------------------------------------------------------
326 * - U3 to Resume Wakeup signaling from a device
327 * - Resume to Recovery to U0 USB 3.0 device resume
328 * - Resume to U0 USB 2.0 device resume
329 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
330 * - U3 to U0 Software resume of USB 2.0 device complete
331 * - U2 to U0 L1 resume of USB 2.1 device complete
332 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
333 * - U0 to disabled L1 entry error with USB 2.1 device
334 * - Any state to inactive Error on USB 3.0 port
335 */
336 #define PORT_PLC (1 << 22)
337 /* port configure error change - port failed to configure its link partner */
338 #define PORT_CEC (1 << 23)
339 /* bit 24 reserved */
340 /* wake on connect (enable) */
341 #define PORT_WKCONN_E (1 << 25)
342 /* wake on disconnect (enable) */
343 #define PORT_WKDISC_E (1 << 26)
344 /* wake on over-current (enable) */
345 #define PORT_WKOC_E (1 << 27)
346 /* bits 28:29 reserved */
347 /* true: device is removable - for USB 3.0 roothub emulation */
348 #define PORT_DEV_REMOVE (1 << 30)
349 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
350 #define PORT_WR (1 << 31)
351
352 /* We mark duplicate entries with -1 */
353 #define DUPLICATE_ENTRY ((u8)(-1))
354
355 /* Port Power Management Status and Control - port_power_base bitmasks */
356 /* Inactivity timer value for transitions into U1, in microseconds.
357 * Timeout can be up to 127us. 0xFF means an infinite timeout.
358 */
359 #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
360 /* Inactivity timer value for transitions into U2 */
361 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
362 /* Bits 24:31 for port testing */
363
364 /* USB2 Protocol PORTSPMSC */
365 #define PORT_RWE (1 << 0x3)
366
367 /**
368 * struct xhci_intr_reg - Interrupt Register Set
369 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
370 * interrupts and check for pending interrupts.
371 * @irq_control: IMOD - Interrupt Moderation Register.
372 * Used to throttle interrupts.
373 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
374 * @erst_base: ERST base address.
375 * @erst_dequeue: Event ring dequeue pointer.
376 *
377 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
378 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
379 * multiple segments of the same size. The HC places events on the ring and
380 * "updates the Cycle bit in the TRBs to indicate to software the current
381 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
382 * updates the dequeue pointer.
383 */
384 struct xhci_intr_reg {
385 u32 irq_pending;
386 u32 irq_control;
387 u32 erst_size;
388 u32 rsvd;
389 u64 erst_base;
390 u64 erst_dequeue;
391 };
392
393 /* irq_pending bitmasks */
394 #define ER_IRQ_PENDING(p) ((p) & 0x1)
395 /* bits 2:31 need to be preserved */
396 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
397 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
398 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
399 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
400
401 /* irq_control bitmasks */
402 /* Minimum interval between interrupts (in 250ns intervals). The interval
403 * between interrupts will be longer if there are no events on the event ring.
404 * Default is 4000 (1 ms).
405 */
406 #define ER_IRQ_INTERVAL_MASK (0xffff)
407 /* Counter used to count down the time to the next interrupt - HW use only */
408 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
409
410 /* erst_size bitmasks */
411 /* Preserve bits 16:31 of erst_size */
412 #define ERST_SIZE_MASK (0xffff << 16)
413
414 /* erst_dequeue bitmasks */
415 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
416 * where the current dequeue pointer lies. This is an optional HW hint.
417 */
418 #define ERST_DESI_MASK (0x7)
419 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
420 * a work queue (or delayed service routine)?
421 */
422 #define ERST_EHB (1 << 3)
423 #define ERST_PTR_MASK (0xf)
424
425 /**
426 * struct xhci_run_regs
427 * @microframe_index:
428 * MFINDEX - current microframe number
429 *
430 * Section 5.5 Host Controller Runtime Registers:
431 * "Software should read and write these registers using only Dword (32 bit)
432 * or larger accesses"
433 */
434 struct xhci_run_regs {
435 u32 microframe_index;
436 u32 rsvd[7];
437 struct xhci_intr_reg ir_set[128];
438 };
439
440 /**
441 * struct doorbell_array
442 *
443 * Bits 0 - 7: Endpoint target
444 * Bits 8 - 15: RsvdZ
445 * Bits 16 - 31: Stream ID
446 *
447 * Section 5.6
448 */
449 struct xhci_doorbell_array {
450 u32 doorbell[256];
451 };
452
453 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
454 #define DB_VALUE_HOST 0x00000000
455
456 /**
457 * struct xhci_protocol_caps
458 * @revision: major revision, minor revision, capability ID,
459 * and next capability pointer.
460 * @name_string: Four ASCII characters to say which spec this xHC
461 * follows, typically "USB ".
462 * @port_info: Port offset, count, and protocol-defined information.
463 */
464 struct xhci_protocol_caps {
465 u32 revision;
466 u32 name_string;
467 u32 port_info;
468 };
469
470 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
471 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
472 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
473
474 /**
475 * struct xhci_container_ctx
476 * @type: Type of context. Used to calculated offsets to contained contexts.
477 * @size: Size of the context data
478 * @bytes: The raw context data given to HW
479 * @dma: dma address of the bytes
480 *
481 * Represents either a Device or Input context. Holds a pointer to the raw
482 * memory used for the context (bytes) and dma address of it (dma).
483 */
484 struct xhci_container_ctx {
485 unsigned type;
486 #define XHCI_CTX_TYPE_DEVICE 0x1
487 #define XHCI_CTX_TYPE_INPUT 0x2
488
489 int size;
490
491 u8 *bytes;
492 dma_addr_t dma;
493 };
494
495 /**
496 * struct xhci_slot_ctx
497 * @dev_info: Route string, device speed, hub info, and last valid endpoint
498 * @dev_info2: Max exit latency for device number, root hub port number
499 * @tt_info: tt_info is used to construct split transaction tokens
500 * @dev_state: slot state and device address
501 *
502 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
503 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
504 * reserved at the end of the slot context for HC internal use.
505 */
506 struct xhci_slot_ctx {
507 u32 dev_info;
508 u32 dev_info2;
509 u32 tt_info;
510 u32 dev_state;
511 /* offset 0x10 to 0x1f reserved for HC internal use */
512 u32 reserved[4];
513 };
514
515 /* dev_info bitmasks */
516 /* Route String - 0:19 */
517 #define ROUTE_STRING_MASK (0xfffff)
518 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
519 #define DEV_SPEED (0xf << 20)
520 /* bit 24 reserved */
521 /* Is this LS/FS device connected through a HS hub? - bit 25 */
522 #define DEV_MTT (0x1 << 25)
523 /* Set if the device is a hub - bit 26 */
524 #define DEV_HUB (0x1 << 26)
525 /* Index of the last valid endpoint context in this device context - 27:31 */
526 #define LAST_CTX_MASK (0x1f << 27)
527 #define LAST_CTX(p) ((p) << 27)
528 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
529 #define SLOT_FLAG (1 << 0)
530 #define EP0_FLAG (1 << 1)
531
532 /* dev_info2 bitmasks */
533 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
534 #define MAX_EXIT (0xffff)
535 /* Root hub port number that is needed to access the USB device */
536 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
537 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
538 /* Maximum number of ports under a hub device */
539 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
540
541 /* tt_info bitmasks */
542 /*
543 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
544 * The Slot ID of the hub that isolates the high speed signaling from
545 * this low or full-speed device. '0' if attached to root hub port.
546 */
547 #define TT_SLOT (0xff)
548 /*
549 * The number of the downstream facing port of the high-speed hub
550 * '0' if the device is not low or full speed.
551 */
552 #define TT_PORT (0xff << 8)
553 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
554
555 /* dev_state bitmasks */
556 /* USB device address - assigned by the HC */
557 #define DEV_ADDR_MASK (0xff)
558 /* bits 8:26 reserved */
559 /* Slot state */
560 #define SLOT_STATE (0x1f << 27)
561 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
562
563
564 /**
565 * struct xhci_ep_ctx
566 * @ep_info: endpoint state, streams, mult, and interval information.
567 * @ep_info2: information on endpoint type, max packet size, max burst size,
568 * error count, and whether the HC will force an event for all
569 * transactions.
570 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
571 * defines one stream, this points to the endpoint transfer ring.
572 * Otherwise, it points to a stream context array, which has a
573 * ring pointer for each flow.
574 * @tx_info:
575 * Average TRB lengths for the endpoint ring and
576 * max payload within an Endpoint Service Interval Time (ESIT).
577 *
578 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
579 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
580 * reserved at the end of the endpoint context for HC internal use.
581 */
582 struct xhci_ep_ctx {
583 u32 ep_info;
584 u32 ep_info2;
585 u64 deq;
586 u32 tx_info;
587 /* offset 0x14 - 0x1f reserved for HC internal use */
588 u32 reserved[3];
589 };
590
591 /* ep_info bitmasks */
592 /*
593 * Endpoint State - bits 0:2
594 * 0 - disabled
595 * 1 - running
596 * 2 - halted due to halt condition - ok to manipulate endpoint ring
597 * 3 - stopped
598 * 4 - TRB error
599 * 5-7 - reserved
600 */
601 #define EP_STATE_MASK (0xf)
602 #define EP_STATE_DISABLED 0
603 #define EP_STATE_RUNNING 1
604 #define EP_STATE_HALTED 2
605 #define EP_STATE_STOPPED 3
606 #define EP_STATE_ERROR 4
607 /* Mult - Max number of burtst within an interval, in EP companion desc. */
608 #define EP_MULT(p) (((p) & 0x3) << 8)
609 /* bits 10:14 are Max Primary Streams */
610 /* bit 15 is Linear Stream Array */
611 /* Interval - period between requests to an endpoint - 125u increments. */
612 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
613 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
614 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
615 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
616 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
617 #define EP_HAS_LSA (1 << 15)
618
619 /* ep_info2 bitmasks */
620 /*
621 * Force Event - generate transfer events for all TRBs for this endpoint
622 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
623 */
624 #define FORCE_EVENT (0x1)
625 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
626 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
627 #define EP_TYPE(p) ((p) << 3)
628 #define ISOC_OUT_EP 1
629 #define BULK_OUT_EP 2
630 #define INT_OUT_EP 3
631 #define CTRL_EP 4
632 #define ISOC_IN_EP 5
633 #define BULK_IN_EP 6
634 #define INT_IN_EP 7
635 /* bit 6 reserved */
636 /* bit 7 is Host Initiate Disable - for disabling stream selection */
637 #define MAX_BURST(p) (((p)&0xff) << 8)
638 #define MAX_PACKET(p) (((p)&0xffff) << 16)
639 #define MAX_PACKET_MASK (0xffff << 16)
640 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
641
642 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
643 * USB2.0 spec 9.6.6.
644 */
645 #define GET_MAX_PACKET(p) ((p) & 0x7ff)
646
647 /* tx_info bitmasks */
648 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
649 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
650
651 /* deq bitmasks */
652 #define EP_CTX_CYCLE_MASK (1 << 0)
653
654
655 /**
656 * struct xhci_input_control_context
657 * Input control context; see section 6.2.5.
658 *
659 * @drop_context: set the bit of the endpoint context you want to disable
660 * @add_context: set the bit of the endpoint context you want to enable
661 */
662 struct xhci_input_control_ctx {
663 u32 drop_flags;
664 u32 add_flags;
665 u32 rsvd2[6];
666 };
667
668 /* Represents everything that is needed to issue a command on the command ring.
669 * It's useful to pre-allocate these for commands that cannot fail due to
670 * out-of-memory errors, like freeing streams.
671 */
672 struct xhci_command {
673 /* Input context for changing device state */
674 struct xhci_container_ctx *in_ctx;
675 u32 status;
676 /* If completion is null, no one is waiting on this command
677 * and the structure can be freed after the command completes.
678 */
679 struct completion *completion;
680 union xhci_trb *command_trb;
681 struct list_head cmd_list;
682 };
683
684 /* drop context bitmasks */
685 #define DROP_EP(x) (0x1 << x)
686 /* add context bitmasks */
687 #define ADD_EP(x) (0x1 << x)
688
689 struct xhci_stream_ctx {
690 /* 64-bit stream ring address, cycle state, and stream type */
691 u64 stream_ring;
692 /* offset 0x14 - 0x1f reserved for HC internal use */
693 u32 reserved[2];
694 };
695
696 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
697 #define SCT_FOR_CTX(p) (((p) << 1) & 0x7)
698 /* Secondary stream array type, dequeue pointer is to a transfer ring */
699 #define SCT_SEC_TR 0
700 /* Primary stream array type, dequeue pointer is to a transfer ring */
701 #define SCT_PRI_TR 1
702 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
703 #define SCT_SSA_8 2
704 #define SCT_SSA_16 3
705 #define SCT_SSA_32 4
706 #define SCT_SSA_64 5
707 #define SCT_SSA_128 6
708 #define SCT_SSA_256 7
709
710 /* Assume no secondary streams for now */
711 struct xhci_stream_info {
712 struct xhci_ring **stream_rings;
713 /* Number of streams, including stream 0 (which drivers can't use) */
714 unsigned int num_streams;
715 /* The stream context array may be bigger than
716 * the number of streams the driver asked for
717 */
718 struct xhci_stream_ctx *stream_ctx_array;
719 unsigned int num_stream_ctxs;
720 dma_addr_t ctx_array_dma;
721 /* For mapping physical TRB addresses to segments in stream rings */
722 struct radix_tree_root trb_address_map;
723 struct xhci_command *free_streams_command;
724 };
725
726 #define SMALL_STREAM_ARRAY_SIZE 256
727 #define MEDIUM_STREAM_ARRAY_SIZE 1024
728
729 struct xhci_virt_ep {
730 struct xhci_ring *ring;
731 /* Related to endpoints that are configured to use stream IDs only */
732 struct xhci_stream_info *stream_info;
733 /* Temporary storage in case the configure endpoint command fails and we
734 * have to restore the device state to the previous state
735 */
736 struct xhci_ring *new_ring;
737 unsigned int ep_state;
738 #define SET_DEQ_PENDING (1 << 0)
739 #define EP_HALTED (1 << 1) /* For stall handling */
740 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */
741 /* Transitioning the endpoint to using streams, don't enqueue URBs */
742 #define EP_GETTING_STREAMS (1 << 3)
743 #define EP_HAS_STREAMS (1 << 4)
744 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
745 #define EP_GETTING_NO_STREAMS (1 << 5)
746 /* ---- Related to URB cancellation ---- */
747 struct list_head cancelled_td_list;
748 /* The TRB that was last reported in a stopped endpoint ring */
749 union xhci_trb *stopped_trb;
750 struct xhci_td *stopped_td;
751 unsigned int stopped_stream;
752 /* Watchdog timer for stop endpoint command to cancel URBs */
753 struct timer_list stop_cmd_timer;
754 int stop_cmds_pending;
755 struct xhci_hcd *xhci;
756 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
757 * command. We'll need to update the ring's dequeue segment and dequeue
758 * pointer after the command completes.
759 */
760 struct xhci_segment *queued_deq_seg;
761 union xhci_trb *queued_deq_ptr;
762 /*
763 * Sometimes the xHC can not process isochronous endpoint ring quickly
764 * enough, and it will miss some isoc tds on the ring and generate
765 * a Missed Service Error Event.
766 * Set skip flag when receive a Missed Service Error Event and
767 * process the missed tds on the endpoint ring.
768 */
769 bool skip;
770 };
771
772 struct xhci_virt_device {
773 struct usb_device *udev;
774 /*
775 * Commands to the hardware are passed an "input context" that
776 * tells the hardware what to change in its data structures.
777 * The hardware will return changes in an "output context" that
778 * software must allocate for the hardware. We need to keep
779 * track of input and output contexts separately because
780 * these commands might fail and we don't trust the hardware.
781 */
782 struct xhci_container_ctx *out_ctx;
783 /* Used for addressing devices and configuration changes */
784 struct xhci_container_ctx *in_ctx;
785 /* Rings saved to ensure old alt settings can be re-instated */
786 struct xhci_ring **ring_cache;
787 int num_rings_cached;
788 /* Store xHC assigned device address */
789 int address;
790 #define XHCI_MAX_RINGS_CACHED 31
791 struct xhci_virt_ep eps[31];
792 struct completion cmd_completion;
793 /* Status of the last command issued for this device */
794 u32 cmd_status;
795 struct list_head cmd_list;
796 u8 port;
797 };
798
799
800 /**
801 * struct xhci_device_context_array
802 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
803 */
804 struct xhci_device_context_array {
805 /* 64-bit device addresses; we only write 32-bit addresses */
806 u64 dev_context_ptrs[MAX_HC_SLOTS];
807 /* private xHCD pointers */
808 dma_addr_t dma;
809 };
810 /* TODO: write function to set the 64-bit device DMA address */
811 /*
812 * TODO: change this to be dynamically sized at HC mem init time since the HC
813 * might not be able to handle the maximum number of devices possible.
814 */
815
816
817 struct xhci_transfer_event {
818 /* 64-bit buffer address, or immediate data */
819 u64 buffer;
820 u32 transfer_len;
821 /* This field is interpreted differently based on the type of TRB */
822 u32 flags;
823 };
824
825 /** Transfer Event bit fields **/
826 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
827
828 /* Completion Code - only applicable for some types of TRBs */
829 #define COMP_CODE_MASK (0xff << 24)
830 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
831 #define COMP_SUCCESS 1
832 /* Data Buffer Error */
833 #define COMP_DB_ERR 2
834 /* Babble Detected Error */
835 #define COMP_BABBLE 3
836 /* USB Transaction Error */
837 #define COMP_TX_ERR 4
838 /* TRB Error - some TRB field is invalid */
839 #define COMP_TRB_ERR 5
840 /* Stall Error - USB device is stalled */
841 #define COMP_STALL 6
842 /* Resource Error - HC doesn't have memory for that device configuration */
843 #define COMP_ENOMEM 7
844 /* Bandwidth Error - not enough room in schedule for this dev config */
845 #define COMP_BW_ERR 8
846 /* No Slots Available Error - HC ran out of device slots */
847 #define COMP_ENOSLOTS 9
848 /* Invalid Stream Type Error */
849 #define COMP_STREAM_ERR 10
850 /* Slot Not Enabled Error - doorbell rung for disabled device slot */
851 #define COMP_EBADSLT 11
852 /* Endpoint Not Enabled Error */
853 #define COMP_EBADEP 12
854 /* Short Packet */
855 #define COMP_SHORT_TX 13
856 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
857 #define COMP_UNDERRUN 14
858 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
859 #define COMP_OVERRUN 15
860 /* Virtual Function Event Ring Full Error */
861 #define COMP_VF_FULL 16
862 /* Parameter Error - Context parameter is invalid */
863 #define COMP_EINVAL 17
864 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
865 #define COMP_BW_OVER 18
866 /* Context State Error - illegal context state transition requested */
867 #define COMP_CTX_STATE 19
868 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
869 #define COMP_PING_ERR 20
870 /* Event Ring is full */
871 #define COMP_ER_FULL 21
872 /* Missed Service Error - HC couldn't service an isoc ep within interval */
873 #define COMP_MISSED_INT 23
874 /* Successfully stopped command ring */
875 #define COMP_CMD_STOP 24
876 /* Successfully aborted current command and stopped command ring */
877 #define COMP_CMD_ABORT 25
878 /* Stopped - transfer was terminated by a stop endpoint command */
879 #define COMP_STOP 26
880 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */
881 #define COMP_STOP_INVAL 27
882 /* Control Abort Error - Debug Capability - control pipe aborted */
883 #define COMP_DBG_ABORT 28
884 /* TRB type 29 and 30 reserved */
885 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
886 #define COMP_BUFF_OVER 31
887 /* Event Lost Error - xHC has an "internal event overrun condition" */
888 #define COMP_ISSUES 32
889 /* Undefined Error - reported when other error codes don't apply */
890 #define COMP_UNKNOWN 33
891 /* Invalid Stream ID Error */
892 #define COMP_STRID_ERR 34
893 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
894 /* FIXME - check for this */
895 #define COMP_2ND_BW_ERR 35
896 /* Split Transaction Error */
897 #define COMP_SPLIT_ERR 36
898
899 struct xhci_link_trb {
900 /* 64-bit segment pointer*/
901 u64 segment_ptr;
902 u32 intr_target;
903 u32 control;
904 };
905
906 /* control bitfields */
907 #define LINK_TOGGLE (0x1<<1)
908
909 /* Command completion event TRB */
910 struct xhci_event_cmd {
911 /* Pointer to command TRB, or the value passed by the event data trb */
912 u64 cmd_trb;
913 u32 status;
914 u32 flags;
915 };
916
917 /* flags bitmasks */
918 /* bits 16:23 are the virtual function ID */
919 /* bits 24:31 are the slot ID */
920 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
921 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
922
923 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
924 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
925 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
926
927 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
928 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
929 #define LAST_EP_INDEX 30
930
931 /* Set TR Dequeue Pointer command TRB fields */
932 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
933 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
934
935
936 /* Port Status Change Event TRB fields */
937 /* Port ID - bits 31:24 */
938 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
939
940 /* Normal TRB fields */
941 /* transfer_len bitmasks - bits 0:16 */
942 #define TRB_LEN(p) ((p) & 0x1ffff)
943 /* Interrupter Target - which MSI-X vector to target the completion event at */
944 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
945 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
946
947 /* Cycle bit - indicates TRB ownership by HC or HCD */
948 #define TRB_CYCLE (1<<0)
949 /*
950 * Force next event data TRB to be evaluated before task switch.
951 * Used to pass OS data back after a TD completes.
952 */
953 #define TRB_ENT (1<<1)
954 /* Interrupt on short packet */
955 #define TRB_ISP (1<<2)
956 /* Set PCIe no snoop attribute */
957 #define TRB_NO_SNOOP (1<<3)
958 /* Chain multiple TRBs into a TD */
959 #define TRB_CHAIN (1<<4)
960 /* Interrupt on completion */
961 #define TRB_IOC (1<<5)
962 /* The buffer pointer contains immediate data */
963 #define TRB_IDT (1<<6)
964
965
966 /* Control transfer TRB specific fields */
967 #define TRB_DIR_IN (1<<16)
968
969 /* Isochronous TRB specific fields */
970 #define TRB_SIA (1<<31)
971
972 struct xhci_generic_trb {
973 u32 field[4];
974 };
975
976 union xhci_trb {
977 struct xhci_link_trb link;
978 struct xhci_transfer_event trans_event;
979 struct xhci_event_cmd event_cmd;
980 struct xhci_generic_trb generic;
981 };
982
983 /* TRB bit mask */
984 #define TRB_TYPE_BITMASK (0xfc00)
985 #define TRB_TYPE(p) ((p) << 10)
986 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
987 /* TRB type IDs */
988 /* bulk, interrupt, isoc scatter/gather, and control data stage */
989 #define TRB_NORMAL 1
990 /* setup stage for control transfers */
991 #define TRB_SETUP 2
992 /* data stage for control transfers */
993 #define TRB_DATA 3
994 /* status stage for control transfers */
995 #define TRB_STATUS 4
996 /* isoc transfers */
997 #define TRB_ISOC 5
998 /* TRB for linking ring segments */
999 #define TRB_LINK 6
1000 #define TRB_EVENT_DATA 7
1001 /* Transfer Ring No-op (not for the command ring) */
1002 #define TRB_TR_NOOP 8
1003 /* Command TRBs */
1004 /* Enable Slot Command */
1005 #define TRB_ENABLE_SLOT 9
1006 /* Disable Slot Command */
1007 #define TRB_DISABLE_SLOT 10
1008 /* Address Device Command */
1009 #define TRB_ADDR_DEV 11
1010 /* Configure Endpoint Command */
1011 #define TRB_CONFIG_EP 12
1012 /* Evaluate Context Command */
1013 #define TRB_EVAL_CONTEXT 13
1014 /* Reset Endpoint Command */
1015 #define TRB_RESET_EP 14
1016 /* Stop Transfer Ring Command */
1017 #define TRB_STOP_RING 15
1018 /* Set Transfer Ring Dequeue Pointer Command */
1019 #define TRB_SET_DEQ 16
1020 /* Reset Device Command */
1021 #define TRB_RESET_DEV 17
1022 /* Force Event Command (opt) */
1023 #define TRB_FORCE_EVENT 18
1024 /* Negotiate Bandwidth Command (opt) */
1025 #define TRB_NEG_BANDWIDTH 19
1026 /* Set Latency Tolerance Value Command (opt) */
1027 #define TRB_SET_LT 20
1028 /* Get port bandwidth Command */
1029 #define TRB_GET_BW 21
1030 /* Force Header Command - generate a transaction or link management packet */
1031 #define TRB_FORCE_HEADER 22
1032 /* No-op Command - not for transfer rings */
1033 #define TRB_CMD_NOOP 23
1034 /* TRB IDs 24-31 reserved */
1035 /* Event TRBS */
1036 /* Transfer Event */
1037 #define TRB_TRANSFER 32
1038 /* Command Completion Event */
1039 #define TRB_COMPLETION 33
1040 /* Port Status Change Event */
1041 #define TRB_PORT_STATUS 34
1042 /* Bandwidth Request Event (opt) */
1043 #define TRB_BANDWIDTH_EVENT 35
1044 /* Doorbell Event (opt) */
1045 #define TRB_DOORBELL 36
1046 /* Host Controller Event */
1047 #define TRB_HC_EVENT 37
1048 /* Device Notification Event - device sent function wake notification */
1049 #define TRB_DEV_NOTE 38
1050 /* MFINDEX Wrap Event - microframe counter wrapped */
1051 #define TRB_MFINDEX_WRAP 39
1052 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1053
1054 /* Nec vendor-specific command completion event. */
1055 #define TRB_NEC_CMD_COMP 48
1056 /* Get NEC firmware revision. */
1057 #define TRB_NEC_GET_FW 49
1058
1059 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1060 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1061
1062 /*
1063 * TRBS_PER_SEGMENT must be a multiple of 4,
1064 * since the command ring is 64-byte aligned.
1065 * It must also be greater than 16.
1066 */
1067 #define TRBS_PER_SEGMENT 64
1068 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1069 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1070 #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1071 /* SEGMENT_SHIFT should be log2(SEGMENT_SIZE).
1072 * Change this if you change TRBS_PER_SEGMENT!
1073 */
1074 #define SEGMENT_SHIFT 10
1075 /* TRB buffer pointers can't cross 64KB boundaries */
1076 #define TRB_MAX_BUFF_SHIFT 16
1077 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1078
1079 struct xhci_segment {
1080 union xhci_trb *trbs;
1081 /* private to HCD */
1082 struct xhci_segment *next;
1083 dma_addr_t dma;
1084 };
1085
1086 struct xhci_td {
1087 struct list_head td_list;
1088 struct list_head cancelled_td_list;
1089 struct urb *urb;
1090 struct xhci_segment *start_seg;
1091 union xhci_trb *first_trb;
1092 union xhci_trb *last_trb;
1093 };
1094
1095 struct xhci_dequeue_state {
1096 struct xhci_segment *new_deq_seg;
1097 union xhci_trb *new_deq_ptr;
1098 int new_cycle_state;
1099 };
1100
1101 struct xhci_ring {
1102 struct xhci_segment *first_seg;
1103 union xhci_trb *enqueue;
1104 struct xhci_segment *enq_seg;
1105 unsigned int enq_updates;
1106 union xhci_trb *dequeue;
1107 struct xhci_segment *deq_seg;
1108 unsigned int deq_updates;
1109 struct list_head td_list;
1110 /*
1111 * Write the cycle state into the TRB cycle field to give ownership of
1112 * the TRB to the host controller (if we are the producer), or to check
1113 * if we own the TRB (if we are the consumer). See section 4.9.1.
1114 */
1115 u32 cycle_state;
1116 unsigned int stream_id;
1117 };
1118
1119 struct xhci_erst_entry {
1120 /* 64-bit event ring segment address */
1121 u64 seg_addr;
1122 u32 seg_size;
1123 /* Set to zero */
1124 u32 rsvd;
1125 };
1126
1127 struct xhci_erst {
1128 struct xhci_erst_entry *entries;
1129 unsigned int num_entries;
1130 /* xhci->event_ring keeps track of segment dma addresses */
1131 dma_addr_t erst_dma_addr;
1132 /* Num entries the ERST can contain */
1133 unsigned int erst_size;
1134 };
1135
1136 struct xhci_scratchpad {
1137 u64 *sp_array;
1138 dma_addr_t sp_dma;
1139 void **sp_buffers;
1140 dma_addr_t *sp_dma_buffers;
1141 };
1142
1143 struct urb_priv {
1144 int length;
1145 int td_cnt;
1146 struct xhci_td *td[0];
1147 };
1148
1149 /*
1150 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1151 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1152 * meaning 64 ring segments.
1153 * Initial allocated size of the ERST, in number of entries */
1154 #define ERST_NUM_SEGS 1
1155 /* Initial allocated size of the ERST, in number of entries */
1156 #define ERST_SIZE 64
1157 /* Initial number of event segment rings allocated */
1158 #define ERST_ENTRIES 1
1159 /* Poll every 60 seconds */
1160 #define POLL_TIMEOUT 60
1161 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1162 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1163 /* XXX: Make these module parameters */
1164
1165 struct s3_save {
1166 u32 command;
1167 u32 dev_nt;
1168 u64 dcbaa_ptr;
1169 u32 config_reg;
1170 u32 irq_pending;
1171 u32 irq_control;
1172 u32 erst_size;
1173 u64 erst_base;
1174 u64 erst_dequeue;
1175 };
1176
1177 struct xhci_bus_state {
1178 unsigned long bus_suspended;
1179 unsigned long next_statechange;
1180
1181 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1182 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1183 u32 port_c_suspend;
1184 u32 suspended_ports;
1185 unsigned long resume_done[USB_MAXCHILDREN];
1186 };
1187
hcd_index(struct usb_hcd * hcd)1188 static inline unsigned int hcd_index(struct usb_hcd *hcd)
1189 {
1190 if (hcd->speed == HCD_USB3)
1191 return 0;
1192 else
1193 return 1;
1194 }
1195
1196 /* There is one ehci_hci structure per controller */
1197 struct xhci_hcd {
1198 struct usb_hcd *main_hcd;
1199 struct usb_hcd *shared_hcd;
1200 /* glue to PCI and HCD framework */
1201 struct xhci_cap_regs __iomem *cap_regs;
1202 struct xhci_op_regs __iomem *op_regs;
1203 struct xhci_run_regs __iomem *run_regs;
1204 struct xhci_doorbell_array __iomem *dba;
1205 /* Our HCD's current interrupter register set */
1206 struct xhci_intr_reg __iomem *ir_set;
1207
1208 /* Cached register copies of read-only HC data */
1209 __u32 hcs_params1;
1210 __u32 hcs_params2;
1211 __u32 hcs_params3;
1212 __u32 hcc_params;
1213
1214 spinlock_t lock;
1215
1216 /* packed release number */
1217 u8 sbrn;
1218 u16 hci_version;
1219 u8 max_slots;
1220 u8 max_interrupters;
1221 u8 max_ports;
1222 u8 isoc_threshold;
1223 int event_ring_max;
1224 int addr_64;
1225 /* 4KB min, 128MB max */
1226 int page_size;
1227 /* Valid values are 12 to 20, inclusive */
1228 int page_shift;
1229 /* msi-x vectors */
1230 int msix_count;
1231 struct msix_entry *msix_entries;
1232 /* data structures */
1233 struct xhci_device_context_array *dcbaa;
1234 struct xhci_ring *cmd_ring;
1235 unsigned int cmd_ring_reserved_trbs;
1236 struct xhci_ring *event_ring;
1237 struct xhci_erst erst;
1238 /* Scratchpad */
1239 struct xhci_scratchpad *scratchpad;
1240
1241 /* slot enabling and address device helpers */
1242 struct completion addr_dev;
1243 int slot_id;
1244 /* Internal mirror of the HW's dcbaa */
1245 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1246
1247 /* DMA pools */
1248 struct dma_pool *device_pool;
1249 struct dma_pool *segment_pool;
1250 struct dma_pool *small_streams_pool;
1251 struct dma_pool *medium_streams_pool;
1252
1253 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1254 /* Poll the rings - for debugging */
1255 struct timer_list event_ring_timer;
1256 int zombie;
1257 #endif
1258 /* Host controller watchdog timer structures */
1259 unsigned int xhc_state;
1260
1261 u32 command;
1262 struct s3_save s3;
1263 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1264 *
1265 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1266 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1267 * that sees this status (other than the timer that set it) should stop touching
1268 * hardware immediately. Interrupt handlers should return immediately when
1269 * they see this status (any time they drop and re-acquire xhci->lock).
1270 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1271 * putting the TD on the canceled list, etc.
1272 *
1273 * There are no reports of xHCI host controllers that display this issue.
1274 */
1275 #define XHCI_STATE_DYING (1 << 0)
1276 #define XHCI_STATE_HALTED (1 << 1)
1277 /* Statistics */
1278 int error_bitmask;
1279 unsigned int quirks;
1280 #define XHCI_LINK_TRB_QUIRK (1 << 0)
1281 #define XHCI_RESET_EP_QUIRK (1 << 1)
1282 #define XHCI_NEC_HOST (1 << 2)
1283 #define XHCI_AMD_PLL_FIX (1 << 3)
1284 /* There are two roothubs to keep track of bus suspend info for */
1285 struct xhci_bus_state bus_state[2];
1286 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
1287 u8 *port_array;
1288 /* Array of pointers to USB 3.0 PORTSC registers */
1289 u32 __iomem **usb3_ports;
1290 unsigned int num_usb3_ports;
1291 /* Array of pointers to USB 2.0 PORTSC registers */
1292 u32 __iomem **usb2_ports;
1293 unsigned int num_usb2_ports;
1294 };
1295
1296 /* convert between an HCD pointer and the corresponding EHCI_HCD */
hcd_to_xhci(struct usb_hcd * hcd)1297 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1298 {
1299 return *((struct xhci_hcd **) (hcd->hcd_priv));
1300 }
1301
xhci_to_hcd(struct xhci_hcd * xhci)1302 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1303 {
1304 return xhci->main_hcd;
1305 }
1306
1307 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1308 #define XHCI_DEBUG 1
1309 #else
1310 #define XHCI_DEBUG 0
1311 #endif
1312
1313 #define xhci_dbg(xhci, fmt, args...) \
1314 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1315 #define xhci_info(xhci, fmt, args...) \
1316 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1317 #define xhci_err(xhci, fmt, args...) \
1318 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1319 #define xhci_warn(xhci, fmt, args...) \
1320 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1321
1322 /* TODO: copied from ehci.h - can be refactored? */
1323 /* xHCI spec says all registers are little endian */
xhci_readl(const struct xhci_hcd * xhci,__u32 __iomem * regs)1324 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
1325 __u32 __iomem *regs)
1326 {
1327 return readl(regs);
1328 }
xhci_writel(struct xhci_hcd * xhci,const unsigned int val,__u32 __iomem * regs)1329 static inline void xhci_writel(struct xhci_hcd *xhci,
1330 const unsigned int val, __u32 __iomem *regs)
1331 {
1332 xhci_dbg(xhci,
1333 "`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n",
1334 regs, val);
1335 writel(val, regs);
1336 }
1337
1338 /*
1339 * Registers should always be accessed with double word or quad word accesses.
1340 *
1341 * Some xHCI implementations may support 64-bit address pointers. Registers
1342 * with 64-bit address pointers should be written to with dword accesses by
1343 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1344 * xHCI implementations that do not support 64-bit address pointers will ignore
1345 * the high dword, and write order is irrelevant.
1346 */
xhci_read_64(const struct xhci_hcd * xhci,__u64 __iomem * regs)1347 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1348 __u64 __iomem *regs)
1349 {
1350 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1351 u64 val_lo = readl(ptr);
1352 u64 val_hi = readl(ptr + 1);
1353 return val_lo + (val_hi << 32);
1354 }
xhci_write_64(struct xhci_hcd * xhci,const u64 val,__u64 __iomem * regs)1355 static inline void xhci_write_64(struct xhci_hcd *xhci,
1356 const u64 val, __u64 __iomem *regs)
1357 {
1358 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1359 u32 val_lo = lower_32_bits(val);
1360 u32 val_hi = upper_32_bits(val);
1361
1362 xhci_dbg(xhci,
1363 "`MEM_WRITE_DWORD(3'b000, 64'h%p, 64'h%0lx, 4'hf);\n",
1364 regs, (long unsigned int) val);
1365 writel(val_lo, ptr);
1366 writel(val_hi, ptr + 1);
1367 }
1368
xhci_link_trb_quirk(struct xhci_hcd * xhci)1369 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1370 {
1371 u32 temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
1372 return ((HC_VERSION(temp) == 0x95) &&
1373 (xhci->quirks & XHCI_LINK_TRB_QUIRK));
1374 }
1375
1376 /* xHCI debugging */
1377 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1378 void xhci_print_registers(struct xhci_hcd *xhci);
1379 void xhci_dbg_regs(struct xhci_hcd *xhci);
1380 void xhci_print_run_regs(struct xhci_hcd *xhci);
1381 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1382 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1383 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1384 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1385 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1386 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1387 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1388 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1389 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1390 struct xhci_container_ctx *ctx);
1391 void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1392 unsigned int slot_id, unsigned int ep_index,
1393 struct xhci_virt_ep *ep);
1394
1395 /* xHCI memory management */
1396 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1397 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1398 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1399 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1400 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1401 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1402 struct usb_device *udev);
1403 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1404 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1405 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1406 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1407 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1408 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1409 struct xhci_container_ctx *in_ctx,
1410 struct xhci_container_ctx *out_ctx,
1411 unsigned int ep_index);
1412 void xhci_slot_copy(struct xhci_hcd *xhci,
1413 struct xhci_container_ctx *in_ctx,
1414 struct xhci_container_ctx *out_ctx);
1415 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1416 struct usb_device *udev, struct usb_host_endpoint *ep,
1417 gfp_t mem_flags);
1418 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1419 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1420 struct xhci_virt_device *virt_dev,
1421 unsigned int ep_index);
1422 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1423 unsigned int num_stream_ctxs,
1424 unsigned int num_streams, gfp_t flags);
1425 void xhci_free_stream_info(struct xhci_hcd *xhci,
1426 struct xhci_stream_info *stream_info);
1427 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1428 struct xhci_ep_ctx *ep_ctx,
1429 struct xhci_stream_info *stream_info);
1430 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
1431 struct xhci_ep_ctx *ep_ctx,
1432 struct xhci_virt_ep *ep);
1433 struct xhci_ring *xhci_dma_to_transfer_ring(
1434 struct xhci_virt_ep *ep,
1435 u64 address);
1436 struct xhci_ring *xhci_stream_id_to_ring(
1437 struct xhci_virt_device *dev,
1438 unsigned int ep_index,
1439 unsigned int stream_id);
1440 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1441 bool allocate_in_ctx, bool allocate_completion,
1442 gfp_t mem_flags);
1443 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv);
1444 void xhci_free_command(struct xhci_hcd *xhci,
1445 struct xhci_command *command);
1446
1447 #ifdef CONFIG_PCI
1448 /* xHCI PCI glue */
1449 int xhci_register_pci(void);
1450 void xhci_unregister_pci(void);
1451 #endif
1452
1453 /* xHCI host controller glue */
1454 void xhci_quiesce(struct xhci_hcd *xhci);
1455 int xhci_halt(struct xhci_hcd *xhci);
1456 int xhci_reset(struct xhci_hcd *xhci);
1457 int xhci_init(struct usb_hcd *hcd);
1458 int xhci_run(struct usb_hcd *hcd);
1459 void xhci_stop(struct usb_hcd *hcd);
1460 void xhci_shutdown(struct usb_hcd *hcd);
1461
1462 #ifdef CONFIG_PM
1463 int xhci_suspend(struct xhci_hcd *xhci);
1464 int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
1465 #else
1466 #define xhci_suspend NULL
1467 #define xhci_resume NULL
1468 #endif
1469
1470 int xhci_get_frame(struct usb_hcd *hcd);
1471 irqreturn_t xhci_irq(struct usb_hcd *hcd);
1472 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd);
1473 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1474 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1475 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1476 struct usb_host_endpoint **eps, unsigned int num_eps,
1477 unsigned int num_streams, gfp_t mem_flags);
1478 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1479 struct usb_host_endpoint **eps, unsigned int num_eps,
1480 gfp_t mem_flags);
1481 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1482 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1483 struct usb_tt *tt, gfp_t mem_flags);
1484 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1485 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1486 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1487 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1488 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1489 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1490 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1491 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1492
1493 /* xHCI ring, segment, TRB, and TD functions */
1494 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1495 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1496 union xhci_trb *start_trb, union xhci_trb *end_trb,
1497 dma_addr_t suspect_dma);
1498 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1499 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1500 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1501 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1502 u32 slot_id);
1503 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
1504 u32 field1, u32 field2, u32 field3, u32 field4);
1505 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1506 unsigned int ep_index, int suspend);
1507 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1508 int slot_id, unsigned int ep_index);
1509 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1510 int slot_id, unsigned int ep_index);
1511 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1512 int slot_id, unsigned int ep_index);
1513 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1514 struct urb *urb, int slot_id, unsigned int ep_index);
1515 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1516 u32 slot_id, bool command_must_succeed);
1517 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1518 u32 slot_id);
1519 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1520 unsigned int ep_index);
1521 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id);
1522 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1523 unsigned int slot_id, unsigned int ep_index,
1524 unsigned int stream_id, struct xhci_td *cur_td,
1525 struct xhci_dequeue_state *state);
1526 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1527 unsigned int slot_id, unsigned int ep_index,
1528 unsigned int stream_id,
1529 struct xhci_dequeue_state *deq_state);
1530 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1531 struct usb_device *udev, unsigned int ep_index);
1532 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1533 unsigned int slot_id, unsigned int ep_index,
1534 struct xhci_dequeue_state *deq_state);
1535 void xhci_stop_endpoint_command_watchdog(unsigned long arg);
1536 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1537 unsigned int ep_index, unsigned int stream_id);
1538
1539 /* xHCI roothub code */
1540 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1541 char *buf, u16 wLength);
1542 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1543
1544 #ifdef CONFIG_PM
1545 int xhci_bus_suspend(struct usb_hcd *hcd);
1546 int xhci_bus_resume(struct usb_hcd *hcd);
1547 #else
1548 #define xhci_bus_suspend NULL
1549 #define xhci_bus_resume NULL
1550 #endif /* CONFIG_PM */
1551
1552 u32 xhci_port_state_to_neutral(u32 state);
1553 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1554 u16 port);
1555 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1556
1557 /* xHCI contexts */
1558 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1559 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1560 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1561
1562 #endif /* __LINUX_XHCI_HCD_H */
1563