1 #ifndef __LINUX_UHCI_HCD_H
2 #define __LINUX_UHCI_HCD_H
3
4 #include <linux/list.h>
5 #include <linux/usb.h>
6
7 #define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT)
8 #define PIPE_DEVEP_MASK 0x0007ff00
9
10
11 /*
12 * Universal Host Controller Interface data structures and defines
13 */
14
15 /* Command register */
16 #define USBCMD 0
17 #define USBCMD_RS 0x0001 /* Run/Stop */
18 #define USBCMD_HCRESET 0x0002 /* Host reset */
19 #define USBCMD_GRESET 0x0004 /* Global reset */
20 #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
21 #define USBCMD_FGR 0x0010 /* Force Global Resume */
22 #define USBCMD_SWDBG 0x0020 /* SW Debug mode */
23 #define USBCMD_CF 0x0040 /* Config Flag (sw only) */
24 #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
25
26 /* Status register */
27 #define USBSTS 2
28 #define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
29 #define USBSTS_ERROR 0x0002 /* Interrupt due to error */
30 #define USBSTS_RD 0x0004 /* Resume Detect */
31 #define USBSTS_HSE 0x0008 /* Host System Error: PCI problems */
32 #define USBSTS_HCPE 0x0010 /* Host Controller Process Error:
33 * the schedule is buggy */
34 #define USBSTS_HCH 0x0020 /* HC Halted */
35
36 /* Interrupt enable register */
37 #define USBINTR 4
38 #define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */
39 #define USBINTR_RESUME 0x0002 /* Resume interrupt enable */
40 #define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */
41 #define USBINTR_SP 0x0008 /* Short packet interrupt enable */
42
43 #define USBFRNUM 6
44 #define USBFLBASEADD 8
45 #define USBSOF 12
46 #define USBSOF_DEFAULT 64 /* Frame length is exactly 1 ms */
47
48 /* USB port status and control registers */
49 #define USBPORTSC1 16
50 #define USBPORTSC2 18
51 #define USBPORTSC_CCS 0x0001 /* Current Connect Status
52 * ("device present") */
53 #define USBPORTSC_CSC 0x0002 /* Connect Status Change */
54 #define USBPORTSC_PE 0x0004 /* Port Enable */
55 #define USBPORTSC_PEC 0x0008 /* Port Enable Change */
56 #define USBPORTSC_DPLUS 0x0010 /* D+ high (line status) */
57 #define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */
58 #define USBPORTSC_RD 0x0040 /* Resume Detect */
59 #define USBPORTSC_RES1 0x0080 /* reserved, always 1 */
60 #define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */
61 #define USBPORTSC_PR 0x0200 /* Port Reset */
62 /* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */
63 #define USBPORTSC_OC 0x0400 /* Over Current condition */
64 #define USBPORTSC_OCC 0x0800 /* Over Current Change R/WC */
65 #define USBPORTSC_SUSP 0x1000 /* Suspend */
66 #define USBPORTSC_RES2 0x2000 /* reserved, write zeroes */
67 #define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */
68 #define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */
69
70 /* PCI legacy support register */
71 #define USBLEGSUP 0xc0
72 #define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
73 #define USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
74 #define USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
75
76 /* PCI Intel-specific resume-enable register */
77 #define USBRES_INTEL 0xc4
78 #define USBPORT1EN 0x01
79 #define USBPORT2EN 0x02
80
81 #define UHCI_PTR_BITS cpu_to_le32(0x000F)
82 #define UHCI_PTR_TERM cpu_to_le32(0x0001)
83 #define UHCI_PTR_QH cpu_to_le32(0x0002)
84 #define UHCI_PTR_DEPTH cpu_to_le32(0x0004)
85 #define UHCI_PTR_BREADTH cpu_to_le32(0x0000)
86
87 #define UHCI_NUMFRAMES 1024 /* in the frame list [array] */
88 #define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */
89 #define CAN_SCHEDULE_FRAMES 1000 /* how far in the future frames
90 * can be scheduled */
91 #define MAX_PHASE 32 /* Periodic scheduling length */
92
93 /* When no queues need Full-Speed Bandwidth Reclamation,
94 * delay this long before turning FSBR off */
95 #define FSBR_OFF_DELAY msecs_to_jiffies(10)
96
97 /* If a queue hasn't advanced after this much time, assume it is stuck */
98 #define QH_WAIT_TIMEOUT msecs_to_jiffies(200)
99
100
101 /*
102 * Queue Headers
103 */
104
105 /*
106 * One role of a QH is to hold a queue of TDs for some endpoint. One QH goes
107 * with each endpoint, and qh->element (updated by the HC) is either:
108 * - the next unprocessed TD in the endpoint's queue, or
109 * - UHCI_PTR_TERM (when there's no more traffic for this endpoint).
110 *
111 * The other role of a QH is to serve as a "skeleton" framelist entry, so we
112 * can easily splice a QH for some endpoint into the schedule at the right
113 * place. Then qh->element is UHCI_PTR_TERM.
114 *
115 * In the schedule, qh->link maintains a list of QHs seen by the HC:
116 * skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ...
117 *
118 * qh->node is the software equivalent of qh->link. The differences
119 * are that the software list is doubly-linked and QHs in the UNLINKING
120 * state are on the software list but not the hardware schedule.
121 *
122 * For bookkeeping purposes we maintain QHs even for Isochronous endpoints,
123 * but they never get added to the hardware schedule.
124 */
125 #define QH_STATE_IDLE 1 /* QH is not being used */
126 #define QH_STATE_UNLINKING 2 /* QH has been removed from the
127 * schedule but the hardware may
128 * still be using it */
129 #define QH_STATE_ACTIVE 3 /* QH is on the schedule */
130
131 struct uhci_qh {
132 /* Hardware fields */
133 __le32 link; /* Next QH in the schedule */
134 __le32 element; /* Queue element (TD) pointer */
135
136 /* Software fields */
137 dma_addr_t dma_handle;
138
139 struct list_head node; /* Node in the list of QHs */
140 struct usb_host_endpoint *hep; /* Endpoint information */
141 struct usb_device *udev;
142 struct list_head queue; /* Queue of urbps for this QH */
143 struct uhci_td *dummy_td; /* Dummy TD to end the queue */
144 struct uhci_td *post_td; /* Last TD completed */
145
146 struct usb_iso_packet_descriptor *iso_packet_desc;
147 /* Next urb->iso_frame_desc entry */
148 unsigned long advance_jiffies; /* Time of last queue advance */
149 unsigned int unlink_frame; /* When the QH was unlinked */
150 unsigned int period; /* For Interrupt and Isochronous QHs */
151 short phase; /* Between 0 and period-1 */
152 short load; /* Periodic time requirement, in us */
153 unsigned int iso_frame; /* Frame # for iso_packet_desc */
154
155 int state; /* QH_STATE_xxx; see above */
156 int type; /* Queue type (control, bulk, etc) */
157 int skel; /* Skeleton queue number */
158
159 unsigned int initial_toggle:1; /* Endpoint's current toggle value */
160 unsigned int needs_fixup:1; /* Must fix the TD toggle values */
161 unsigned int is_stopped:1; /* Queue was stopped by error/unlink */
162 unsigned int wait_expired:1; /* QH_WAIT_TIMEOUT has expired */
163 unsigned int bandwidth_reserved:1; /* Periodic bandwidth has
164 * been allocated */
165 } __attribute__((aligned(16)));
166
167 /*
168 * We need a special accessor for the element pointer because it is
169 * subject to asynchronous updates by the controller.
170 */
qh_element(struct uhci_qh * qh)171 static inline __le32 qh_element(struct uhci_qh *qh) {
172 __le32 element = qh->element;
173
174 barrier();
175 return element;
176 }
177
178 #define LINK_TO_QH(qh) (UHCI_PTR_QH | cpu_to_le32((qh)->dma_handle))
179
180
181 /*
182 * Transfer Descriptors
183 */
184
185 /*
186 * for TD <status>:
187 */
188 #define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */
189 #define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */
190 #define TD_CTRL_C_ERR_SHIFT 27
191 #define TD_CTRL_LS (1 << 26) /* Low Speed Device */
192 #define TD_CTRL_IOS (1 << 25) /* Isochronous Select */
193 #define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */
194 #define TD_CTRL_ACTIVE (1 << 23) /* TD Active */
195 #define TD_CTRL_STALLED (1 << 22) /* TD Stalled */
196 #define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */
197 #define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */
198 #define TD_CTRL_NAK (1 << 19) /* NAK Received */
199 #define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */
200 #define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */
201 #define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */
202
203 #define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
204 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | \
205 TD_CTRL_BITSTUFF)
206
207 #define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT)
208 #define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000)
209 #define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & \
210 TD_CTRL_ACTLEN_MASK) /* 1-based */
211
212 /*
213 * for TD <info>: (a.k.a. Token)
214 */
215 #define td_token(td) le32_to_cpu((td)->token)
216 #define TD_TOKEN_DEVADDR_SHIFT 8
217 #define TD_TOKEN_TOGGLE_SHIFT 19
218 #define TD_TOKEN_TOGGLE (1 << 19)
219 #define TD_TOKEN_EXPLEN_SHIFT 21
220 #define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n-1 */
221 #define TD_TOKEN_PID_MASK 0xFF
222
223 #define uhci_explen(len) ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \
224 TD_TOKEN_EXPLEN_SHIFT)
225
226 #define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \
227 1) & TD_TOKEN_EXPLEN_MASK)
228 #define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1)
229 #define uhci_endpoint(token) (((token) >> 15) & 0xf)
230 #define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f)
231 #define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff)
232 #define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK)
233 #define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN)
234 #define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN)
235
236 /*
237 * The documentation says "4 words for hardware, 4 words for software".
238 *
239 * That's silly, the hardware doesn't care. The hardware only cares that
240 * the hardware words are 16-byte aligned, and we can have any amount of
241 * sw space after the TD entry.
242 *
243 * td->link points to either another TD (not necessarily for the same urb or
244 * even the same endpoint), or nothing (PTR_TERM), or a QH.
245 */
246 struct uhci_td {
247 /* Hardware fields */
248 __le32 link;
249 __le32 status;
250 __le32 token;
251 __le32 buffer;
252
253 /* Software fields */
254 dma_addr_t dma_handle;
255
256 struct list_head list;
257
258 int frame; /* for iso: what frame? */
259 struct list_head fl_list;
260 } __attribute__((aligned(16)));
261
262 /*
263 * We need a special accessor for the control/status word because it is
264 * subject to asynchronous updates by the controller.
265 */
td_status(struct uhci_td * td)266 static inline u32 td_status(struct uhci_td *td) {
267 __le32 status = td->status;
268
269 barrier();
270 return le32_to_cpu(status);
271 }
272
273 #define LINK_TO_TD(td) (cpu_to_le32((td)->dma_handle))
274
275
276 /*
277 * Skeleton Queue Headers
278 */
279
280 /*
281 * The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for
282 * automatic queuing. To make it easy to insert entries into the schedule,
283 * we have a skeleton of QHs for each predefined Interrupt latency.
284 * Asynchronous QHs (low-speed control, full-speed control, and bulk)
285 * go onto the period-1 interrupt list, since they all get accessed on
286 * every frame.
287 *
288 * When we want to add a new QH, we add it to the list starting from the
289 * appropriate skeleton QH. For instance, the schedule can look like this:
290 *
291 * skel int128 QH
292 * dev 1 interrupt QH
293 * dev 5 interrupt QH
294 * skel int64 QH
295 * skel int32 QH
296 * ...
297 * skel int1 + async QH
298 * dev 5 low-speed control QH
299 * dev 1 bulk QH
300 * dev 2 bulk QH
301 *
302 * There is a special terminating QH used to keep full-speed bandwidth
303 * reclamation active when no full-speed control or bulk QHs are linked
304 * into the schedule. It has an inactive TD (to work around a PIIX bug,
305 * see the Intel errata) and it points back to itself.
306 *
307 * There's a special skeleton QH for Isochronous QHs which never appears
308 * on the schedule. Isochronous TDs go on the schedule before the
309 * the skeleton QHs. The hardware accesses them directly rather than
310 * through their QH, which is used only for bookkeeping purposes.
311 * While the UHCI spec doesn't forbid the use of QHs for Isochronous,
312 * it doesn't use them either. And the spec says that queues never
313 * advance on an error completion status, which makes them totally
314 * unsuitable for Isochronous transfers.
315 *
316 * There's also a special skeleton QH used for QHs which are in the process
317 * of unlinking and so may still be in use by the hardware. It too never
318 * appears on the schedule.
319 */
320
321 #define UHCI_NUM_SKELQH 11
322 #define SKEL_UNLINK 0
323 #define skel_unlink_qh skelqh[SKEL_UNLINK]
324 #define SKEL_ISO 1
325 #define skel_iso_qh skelqh[SKEL_ISO]
326 /* int128, int64, ..., int1 = 2, 3, ..., 9 */
327 #define SKEL_INDEX(exponent) (9 - exponent)
328 #define SKEL_ASYNC 9
329 #define skel_async_qh skelqh[SKEL_ASYNC]
330 #define SKEL_TERM 10
331 #define skel_term_qh skelqh[SKEL_TERM]
332
333 /* The following entries refer to sublists of skel_async_qh */
334 #define SKEL_LS_CONTROL 20
335 #define SKEL_FS_CONTROL 21
336 #define SKEL_FSBR SKEL_FS_CONTROL
337 #define SKEL_BULK 22
338
339 /*
340 * The UHCI controller and root hub
341 */
342
343 /*
344 * States for the root hub:
345 *
346 * To prevent "bouncing" in the presence of electrical noise,
347 * when there are no devices attached we delay for 1 second in the
348 * RUNNING_NODEVS state before switching to the AUTO_STOPPED state.
349 *
350 * (Note that the AUTO_STOPPED state won't be necessary once the hub
351 * driver learns to autosuspend.)
352 */
353 enum uhci_rh_state {
354 /* In the following states the HC must be halted.
355 * These two must come first. */
356 UHCI_RH_RESET,
357 UHCI_RH_SUSPENDED,
358
359 UHCI_RH_AUTO_STOPPED,
360 UHCI_RH_RESUMING,
361
362 /* In this state the HC changes from running to halted,
363 * so it can legally appear either way. */
364 UHCI_RH_SUSPENDING,
365
366 /* In the following states it's an error if the HC is halted.
367 * These two must come last. */
368 UHCI_RH_RUNNING, /* The normal state */
369 UHCI_RH_RUNNING_NODEVS, /* Running with no devices attached */
370 };
371
372 /*
373 * The full UHCI controller information:
374 */
375 struct uhci_hcd {
376
377 /* debugfs */
378 struct dentry *dentry;
379
380 /* Grabbed from PCI */
381 unsigned long io_addr;
382
383 struct dma_pool *qh_pool;
384 struct dma_pool *td_pool;
385
386 struct uhci_td *term_td; /* Terminating TD, see UHCI bug */
387 struct uhci_qh *skelqh[UHCI_NUM_SKELQH]; /* Skeleton QHs */
388 struct uhci_qh *next_qh; /* Next QH to scan */
389
390 spinlock_t lock;
391
392 dma_addr_t frame_dma_handle; /* Hardware frame list */
393 __le32 *frame;
394 void **frame_cpu; /* CPU's frame list */
395
396 enum uhci_rh_state rh_state;
397 unsigned long auto_stop_time; /* When to AUTO_STOP */
398
399 unsigned int frame_number; /* As of last check */
400 unsigned int is_stopped;
401 #define UHCI_IS_STOPPED 9999 /* Larger than a frame # */
402 unsigned int last_iso_frame; /* Frame of last scan */
403 unsigned int cur_iso_frame; /* Frame for current scan */
404
405 unsigned int scan_in_progress:1; /* Schedule scan is running */
406 unsigned int need_rescan:1; /* Redo the schedule scan */
407 unsigned int dead:1; /* Controller has died */
408 unsigned int RD_enable:1; /* Suspended root hub with
409 Resume-Detect interrupts
410 enabled */
411 unsigned int is_initialized:1; /* Data structure is usable */
412 unsigned int fsbr_is_on:1; /* FSBR is turned on */
413 unsigned int fsbr_is_wanted:1; /* Does any URB want FSBR? */
414 unsigned int fsbr_expiring:1; /* FSBR is timing out */
415
416 struct timer_list fsbr_timer; /* For turning off FBSR */
417
418 /* Support for port suspend/resume/reset */
419 unsigned long port_c_suspend; /* Bit-arrays of ports */
420 unsigned long resuming_ports;
421 unsigned long ports_timeout; /* Time to stop signalling */
422
423 struct list_head idle_qh_list; /* Where the idle QHs live */
424
425 int rh_numports; /* Number of root-hub ports */
426
427 wait_queue_head_t waitqh; /* endpoint_disable waiters */
428 int num_waiting; /* Number of waiters */
429
430 int total_load; /* Sum of array values */
431 short load[MAX_PHASE]; /* Periodic allocations */
432 };
433
434 /* Convert between a usb_hcd pointer and the corresponding uhci_hcd */
hcd_to_uhci(struct usb_hcd * hcd)435 static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd)
436 {
437 return (struct uhci_hcd *) (hcd->hcd_priv);
438 }
uhci_to_hcd(struct uhci_hcd * uhci)439 static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci)
440 {
441 return container_of((void *) uhci, struct usb_hcd, hcd_priv);
442 }
443
444 #define uhci_dev(u) (uhci_to_hcd(u)->self.controller)
445
446 /* Utility macro for comparing frame numbers */
447 #define uhci_frame_before_eq(f1, f2) (0 <= (int) ((f2) - (f1)))
448
449
450 /*
451 * Private per-URB data
452 */
453 struct urb_priv {
454 struct list_head node; /* Node in the QH's urbp list */
455
456 struct urb *urb;
457
458 struct uhci_qh *qh; /* QH for this URB */
459 struct list_head td_list;
460
461 unsigned fsbr:1; /* URB wants FSBR */
462 };
463
464
465 /* Some special IDs */
466
467 #define PCI_VENDOR_ID_GENESYS 0x17a0
468 #define PCI_DEVICE_ID_GL880S_UHCI 0x8083
469
470 #endif
471