1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8 #include <linux/delay.h>
9 #include <linux/pci.h>
10 #include <scsi/scsi_tcq.h>
11
12 #define MASK(n) ((1ULL<<(n))-1)
13 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
14 ((addr >> 25) & 0x3ff))
15 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17 #define MS_WIN(addr) (addr & 0x0ffc0000)
18 #define QLA82XX_PCI_MN_2M (0)
19 #define QLA82XX_PCI_MS_2M (0x80000)
20 #define QLA82XX_PCI_OCM0_2M (0xc0000)
21 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
22 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
23 #define BLOCK_PROTECT_BITS 0x0F
24
25 /* CRB window related */
26 #define CRB_BLK(off) ((off >> 20) & 0x3f)
27 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
28 #define CRB_WINDOW_2M (0x130060)
29 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
30 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
31 ((off) & 0xf0000))
32 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
33 #define CRB_INDIRECT_2M (0x1e0000UL)
34
35 #define MAX_CRB_XFORM 60
36 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
37 int qla82xx_crb_table_initialized;
38
39 #define qla82xx_crb_addr_transform(name) \
40 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
41 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
42
qla82xx_crb_addr_transform_setup(void)43 static void qla82xx_crb_addr_transform_setup(void)
44 {
45 qla82xx_crb_addr_transform(XDMA);
46 qla82xx_crb_addr_transform(TIMR);
47 qla82xx_crb_addr_transform(SRE);
48 qla82xx_crb_addr_transform(SQN3);
49 qla82xx_crb_addr_transform(SQN2);
50 qla82xx_crb_addr_transform(SQN1);
51 qla82xx_crb_addr_transform(SQN0);
52 qla82xx_crb_addr_transform(SQS3);
53 qla82xx_crb_addr_transform(SQS2);
54 qla82xx_crb_addr_transform(SQS1);
55 qla82xx_crb_addr_transform(SQS0);
56 qla82xx_crb_addr_transform(RPMX7);
57 qla82xx_crb_addr_transform(RPMX6);
58 qla82xx_crb_addr_transform(RPMX5);
59 qla82xx_crb_addr_transform(RPMX4);
60 qla82xx_crb_addr_transform(RPMX3);
61 qla82xx_crb_addr_transform(RPMX2);
62 qla82xx_crb_addr_transform(RPMX1);
63 qla82xx_crb_addr_transform(RPMX0);
64 qla82xx_crb_addr_transform(ROMUSB);
65 qla82xx_crb_addr_transform(SN);
66 qla82xx_crb_addr_transform(QMN);
67 qla82xx_crb_addr_transform(QMS);
68 qla82xx_crb_addr_transform(PGNI);
69 qla82xx_crb_addr_transform(PGND);
70 qla82xx_crb_addr_transform(PGN3);
71 qla82xx_crb_addr_transform(PGN2);
72 qla82xx_crb_addr_transform(PGN1);
73 qla82xx_crb_addr_transform(PGN0);
74 qla82xx_crb_addr_transform(PGSI);
75 qla82xx_crb_addr_transform(PGSD);
76 qla82xx_crb_addr_transform(PGS3);
77 qla82xx_crb_addr_transform(PGS2);
78 qla82xx_crb_addr_transform(PGS1);
79 qla82xx_crb_addr_transform(PGS0);
80 qla82xx_crb_addr_transform(PS);
81 qla82xx_crb_addr_transform(PH);
82 qla82xx_crb_addr_transform(NIU);
83 qla82xx_crb_addr_transform(I2Q);
84 qla82xx_crb_addr_transform(EG);
85 qla82xx_crb_addr_transform(MN);
86 qla82xx_crb_addr_transform(MS);
87 qla82xx_crb_addr_transform(CAS2);
88 qla82xx_crb_addr_transform(CAS1);
89 qla82xx_crb_addr_transform(CAS0);
90 qla82xx_crb_addr_transform(CAM);
91 qla82xx_crb_addr_transform(C2C1);
92 qla82xx_crb_addr_transform(C2C0);
93 qla82xx_crb_addr_transform(SMB);
94 qla82xx_crb_addr_transform(OCM0);
95 /*
96 * Used only in P3 just define it for P2 also.
97 */
98 qla82xx_crb_addr_transform(I2C0);
99
100 qla82xx_crb_table_initialized = 1;
101 }
102
103 struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
104 {{{0, 0, 0, 0} } },
105 {{{1, 0x0100000, 0x0102000, 0x120000},
106 {1, 0x0110000, 0x0120000, 0x130000},
107 {1, 0x0120000, 0x0122000, 0x124000},
108 {1, 0x0130000, 0x0132000, 0x126000},
109 {1, 0x0140000, 0x0142000, 0x128000},
110 {1, 0x0150000, 0x0152000, 0x12a000},
111 {1, 0x0160000, 0x0170000, 0x110000},
112 {1, 0x0170000, 0x0172000, 0x12e000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {1, 0x01e0000, 0x01e0800, 0x122000},
120 {0, 0x0000000, 0x0000000, 0x000000} } } ,
121 {{{1, 0x0200000, 0x0210000, 0x180000} } },
122 {{{0, 0, 0, 0} } },
123 {{{1, 0x0400000, 0x0401000, 0x169000} } },
124 {{{1, 0x0500000, 0x0510000, 0x140000} } },
125 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
126 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
127 {{{1, 0x0800000, 0x0802000, 0x170000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {1, 0x08f0000, 0x08f2000, 0x172000} } },
143 {{{1, 0x0900000, 0x0902000, 0x174000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {1, 0x09f0000, 0x09f2000, 0x176000} } },
159 {{{0, 0x0a00000, 0x0a02000, 0x178000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
175 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
191 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
192 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
193 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
194 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
195 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
196 {{{1, 0x1100000, 0x1101000, 0x160000} } },
197 {{{1, 0x1200000, 0x1201000, 0x161000} } },
198 {{{1, 0x1300000, 0x1301000, 0x162000} } },
199 {{{1, 0x1400000, 0x1401000, 0x163000} } },
200 {{{1, 0x1500000, 0x1501000, 0x165000} } },
201 {{{1, 0x1600000, 0x1601000, 0x166000} } },
202 {{{0, 0, 0, 0} } },
203 {{{0, 0, 0, 0} } },
204 {{{0, 0, 0, 0} } },
205 {{{0, 0, 0, 0} } },
206 {{{0, 0, 0, 0} } },
207 {{{0, 0, 0, 0} } },
208 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
209 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
210 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
211 {{{0} } },
212 {{{1, 0x2100000, 0x2102000, 0x120000},
213 {1, 0x2110000, 0x2120000, 0x130000},
214 {1, 0x2120000, 0x2122000, 0x124000},
215 {1, 0x2130000, 0x2132000, 0x126000},
216 {1, 0x2140000, 0x2142000, 0x128000},
217 {1, 0x2150000, 0x2152000, 0x12a000},
218 {1, 0x2160000, 0x2170000, 0x110000},
219 {1, 0x2170000, 0x2172000, 0x12e000},
220 {0, 0x0000000, 0x0000000, 0x000000},
221 {0, 0x0000000, 0x0000000, 0x000000},
222 {0, 0x0000000, 0x0000000, 0x000000},
223 {0, 0x0000000, 0x0000000, 0x000000},
224 {0, 0x0000000, 0x0000000, 0x000000},
225 {0, 0x0000000, 0x0000000, 0x000000},
226 {0, 0x0000000, 0x0000000, 0x000000},
227 {0, 0x0000000, 0x0000000, 0x000000} } },
228 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
229 {{{0} } },
230 {{{0} } },
231 {{{0} } },
232 {{{0} } },
233 {{{0} } },
234 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
235 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
236 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
237 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
238 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
239 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
240 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
241 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
242 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
243 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
244 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
245 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
246 {{{0} } },
247 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
248 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
249 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
250 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
251 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
252 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
253 {{{0} } },
254 {{{0} } },
255 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
256 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
257 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
258 };
259
260 /*
261 * top 12 bits of crb internal address (hub, agent)
262 */
263 unsigned qla82xx_crb_hub_agt[64] = {
264 0,
265 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
266 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
267 QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
268 0,
269 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
270 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
271 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
272 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
273 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
275 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
291 0,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
293 QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
294 0,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
296 0,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
298 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
299 0,
300 0,
301 0,
302 0,
303 0,
304 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
305 0,
306 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
307 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
308 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
313 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
316 0,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
321 0,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
323 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
324 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
325 0,
326 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
327 0,
328 };
329
330 /* Device states */
331 char *qdev_state[] = {
332 "Unknown",
333 "Cold",
334 "Initializing",
335 "Ready",
336 "Need Reset",
337 "Need Quiescent",
338 "Failed",
339 "Quiescent",
340 };
341
342 /*
343 * In: 'off' is offset from CRB space in 128M pci map
344 * Out: 'off' is 2M pci map addr
345 * side effect: lock crb window
346 */
347 static void
qla82xx_pci_set_crbwindow_2M(struct qla_hw_data * ha,ulong * off)348 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off)
349 {
350 u32 win_read;
351
352 ha->crb_win = CRB_HI(*off);
353 writel(ha->crb_win,
354 (void *)(CRB_WINDOW_2M + ha->nx_pcibase));
355
356 /* Read back value to make sure write has gone through before trying
357 * to use it.
358 */
359 win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase));
360 if (win_read != ha->crb_win) {
361 DEBUG2(qla_printk(KERN_INFO, ha,
362 "%s: Written crbwin (0x%x) != Read crbwin (0x%x), "
363 "off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
364 }
365 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
366 }
367
368 static inline unsigned long
qla82xx_pci_set_crbwindow(struct qla_hw_data * ha,u64 off)369 qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
370 {
371 /* See if we are currently pointing to the region we want to use next */
372 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) {
373 /* No need to change window. PCIX and PCIEregs are in both
374 * regs are in both windows.
375 */
376 return off;
377 }
378
379 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) {
380 /* We are in first CRB window */
381 if (ha->curr_window != 0)
382 WARN_ON(1);
383 return off;
384 }
385
386 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) {
387 /* We are in second CRB window */
388 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST;
389
390 if (ha->curr_window != 1)
391 return off;
392
393 /* We are in the QM or direct access
394 * register region - do nothing
395 */
396 if ((off >= QLA82XX_PCI_DIRECT_CRB) &&
397 (off < QLA82XX_PCI_CAMQM_MAX))
398 return off;
399 }
400 /* strange address given */
401 qla_printk(KERN_WARNING, ha,
402 "%s: Warning: unm_nic_pci_set_crbwindow called with"
403 " an unknown address(%llx)\n", QLA2XXX_DRIVER_NAME, off);
404 return off;
405 }
406
407 static int
qla82xx_pci_get_crb_addr_2M(struct qla_hw_data * ha,ulong * off)408 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off)
409 {
410 struct crb_128M_2M_sub_block_map *m;
411
412 if (*off >= QLA82XX_CRB_MAX)
413 return -1;
414
415 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
416 *off = (*off - QLA82XX_PCI_CAMQM) +
417 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
418 return 0;
419 }
420
421 if (*off < QLA82XX_PCI_CRBSPACE)
422 return -1;
423
424 *off -= QLA82XX_PCI_CRBSPACE;
425
426 /* Try direct map */
427 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
428
429 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
430 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
431 return 0;
432 }
433 /* Not in direct map, use crb window */
434 return 1;
435 }
436
437 #define CRB_WIN_LOCK_TIMEOUT 100000000
qla82xx_crb_win_lock(struct qla_hw_data * ha)438 static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
439 {
440 int done = 0, timeout = 0;
441
442 while (!done) {
443 /* acquire semaphore3 from PCI HW block */
444 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
445 if (done == 1)
446 break;
447 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
448 return -1;
449 timeout++;
450 }
451 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
452 return 0;
453 }
454
455 int
qla82xx_wr_32(struct qla_hw_data * ha,ulong off,u32 data)456 qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data)
457 {
458 unsigned long flags = 0;
459 int rv;
460
461 rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
462
463 BUG_ON(rv == -1);
464
465 if (rv == 1) {
466 write_lock_irqsave(&ha->hw_lock, flags);
467 qla82xx_crb_win_lock(ha);
468 qla82xx_pci_set_crbwindow_2M(ha, &off);
469 }
470
471 writel(data, (void __iomem *)off);
472
473 if (rv == 1) {
474 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
475 write_unlock_irqrestore(&ha->hw_lock, flags);
476 }
477 return 0;
478 }
479
480 int
qla82xx_rd_32(struct qla_hw_data * ha,ulong off)481 qla82xx_rd_32(struct qla_hw_data *ha, ulong off)
482 {
483 unsigned long flags = 0;
484 int rv;
485 u32 data;
486
487 rv = qla82xx_pci_get_crb_addr_2M(ha, &off);
488
489 BUG_ON(rv == -1);
490
491 if (rv == 1) {
492 write_lock_irqsave(&ha->hw_lock, flags);
493 qla82xx_crb_win_lock(ha);
494 qla82xx_pci_set_crbwindow_2M(ha, &off);
495 }
496 data = RD_REG_DWORD((void __iomem *)off);
497
498 if (rv == 1) {
499 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
500 write_unlock_irqrestore(&ha->hw_lock, flags);
501 }
502 return data;
503 }
504
505 #define IDC_LOCK_TIMEOUT 100000000
qla82xx_idc_lock(struct qla_hw_data * ha)506 int qla82xx_idc_lock(struct qla_hw_data *ha)
507 {
508 int i;
509 int done = 0, timeout = 0;
510
511 while (!done) {
512 /* acquire semaphore5 from PCI HW block */
513 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
514 if (done == 1)
515 break;
516 if (timeout >= IDC_LOCK_TIMEOUT)
517 return -1;
518
519 timeout++;
520
521 /* Yield CPU */
522 if (!in_interrupt())
523 schedule();
524 else {
525 for (i = 0; i < 20; i++)
526 cpu_relax();
527 }
528 }
529
530 return 0;
531 }
532
qla82xx_idc_unlock(struct qla_hw_data * ha)533 void qla82xx_idc_unlock(struct qla_hw_data *ha)
534 {
535 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
536 }
537
538 /* PCI Windowing for DDR regions. */
539 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
540 (((addr) <= (high)) && ((addr) >= (low)))
541 /*
542 * check memory access boundary.
543 * used by test agent. support ddr access only for now
544 */
545 static unsigned long
qla82xx_pci_mem_bound_check(struct qla_hw_data * ha,unsigned long long addr,int size)546 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
547 unsigned long long addr, int size)
548 {
549 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
550 QLA82XX_ADDR_DDR_NET_MAX) ||
551 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET,
552 QLA82XX_ADDR_DDR_NET_MAX) ||
553 ((size != 1) && (size != 2) && (size != 4) && (size != 8)))
554 return 0;
555 else
556 return 1;
557 }
558
559 int qla82xx_pci_set_window_warning_count;
560
561 static unsigned long
qla82xx_pci_set_window(struct qla_hw_data * ha,unsigned long long addr)562 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
563 {
564 int window;
565 u32 win_read;
566
567 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
568 QLA82XX_ADDR_DDR_NET_MAX)) {
569 /* DDR network side */
570 window = MN_WIN(addr);
571 ha->ddr_mn_window = window;
572 qla82xx_wr_32(ha,
573 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
574 win_read = qla82xx_rd_32(ha,
575 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
576 if ((win_read << 17) != window) {
577 qla_printk(KERN_WARNING, ha,
578 "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
579 __func__, window, win_read);
580 }
581 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
582 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
583 QLA82XX_ADDR_OCM0_MAX)) {
584 unsigned int temp1;
585 if ((addr & 0x00ff800) == 0xff800) {
586 qla_printk(KERN_WARNING, ha,
587 "%s: QM access not handled.\n", __func__);
588 addr = -1UL;
589 }
590 window = OCM_WIN(addr);
591 ha->ddr_mn_window = window;
592 qla82xx_wr_32(ha,
593 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
594 win_read = qla82xx_rd_32(ha,
595 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
596 temp1 = ((window & 0x1FF) << 7) |
597 ((window & 0x0FFFE0000) >> 17);
598 if (win_read != temp1) {
599 qla_printk(KERN_WARNING, ha,
600 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x)\n",
601 __func__, temp1, win_read);
602 }
603 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
604
605 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
606 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
607 /* QDR network side */
608 window = MS_WIN(addr);
609 ha->qdr_sn_window = window;
610 qla82xx_wr_32(ha,
611 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
612 win_read = qla82xx_rd_32(ha,
613 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
614 if (win_read != window) {
615 qla_printk(KERN_WARNING, ha,
616 "%s: Written MSwin (0x%x) != Read MSwin (0x%x)\n",
617 __func__, window, win_read);
618 }
619 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
620 } else {
621 /*
622 * peg gdb frequently accesses memory that doesn't exist,
623 * this limits the chit chat so debugging isn't slowed down.
624 */
625 if ((qla82xx_pci_set_window_warning_count++ < 8) ||
626 (qla82xx_pci_set_window_warning_count%64 == 0)) {
627 qla_printk(KERN_WARNING, ha,
628 "%s: Warning:%s Unknown address range!\n", __func__,
629 QLA2XXX_DRIVER_NAME);
630 }
631 addr = -1UL;
632 }
633 return addr;
634 }
635
636 /* check if address is in the same windows as the previous access */
qla82xx_pci_is_same_window(struct qla_hw_data * ha,unsigned long long addr)637 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
638 unsigned long long addr)
639 {
640 int window;
641 unsigned long long qdr_max;
642
643 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
644
645 /* DDR network side */
646 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
647 QLA82XX_ADDR_DDR_NET_MAX))
648 BUG();
649 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
650 QLA82XX_ADDR_OCM0_MAX))
651 return 1;
652 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1,
653 QLA82XX_ADDR_OCM1_MAX))
654 return 1;
655 else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
656 /* QDR network side */
657 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
658 if (ha->qdr_sn_window == window)
659 return 1;
660 }
661 return 0;
662 }
663
qla82xx_pci_mem_read_direct(struct qla_hw_data * ha,u64 off,void * data,int size)664 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
665 u64 off, void *data, int size)
666 {
667 unsigned long flags;
668 void *addr = NULL;
669 int ret = 0;
670 u64 start;
671 uint8_t *mem_ptr = NULL;
672 unsigned long mem_base;
673 unsigned long mem_page;
674
675 write_lock_irqsave(&ha->hw_lock, flags);
676
677 /*
678 * If attempting to access unknown address or straddle hw windows,
679 * do not access.
680 */
681 start = qla82xx_pci_set_window(ha, off);
682 if ((start == -1UL) ||
683 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
684 write_unlock_irqrestore(&ha->hw_lock, flags);
685 qla_printk(KERN_ERR, ha,
686 "%s out of bound pci memory access. "
687 "offset is 0x%llx\n", QLA2XXX_DRIVER_NAME, off);
688 return -1;
689 }
690
691 write_unlock_irqrestore(&ha->hw_lock, flags);
692 mem_base = pci_resource_start(ha->pdev, 0);
693 mem_page = start & PAGE_MASK;
694 /* Map two pages whenever user tries to access addresses in two
695 * consecutive pages.
696 */
697 if (mem_page != ((start + size - 1) & PAGE_MASK))
698 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
699 else
700 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
701 if (mem_ptr == 0UL) {
702 *(u8 *)data = 0;
703 return -1;
704 }
705 addr = mem_ptr;
706 addr += start & (PAGE_SIZE - 1);
707 write_lock_irqsave(&ha->hw_lock, flags);
708
709 switch (size) {
710 case 1:
711 *(u8 *)data = readb(addr);
712 break;
713 case 2:
714 *(u16 *)data = readw(addr);
715 break;
716 case 4:
717 *(u32 *)data = readl(addr);
718 break;
719 case 8:
720 *(u64 *)data = readq(addr);
721 break;
722 default:
723 ret = -1;
724 break;
725 }
726 write_unlock_irqrestore(&ha->hw_lock, flags);
727
728 if (mem_ptr)
729 iounmap(mem_ptr);
730 return ret;
731 }
732
733 static int
qla82xx_pci_mem_write_direct(struct qla_hw_data * ha,u64 off,void * data,int size)734 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
735 u64 off, void *data, int size)
736 {
737 unsigned long flags;
738 void *addr = NULL;
739 int ret = 0;
740 u64 start;
741 uint8_t *mem_ptr = NULL;
742 unsigned long mem_base;
743 unsigned long mem_page;
744
745 write_lock_irqsave(&ha->hw_lock, flags);
746
747 /*
748 * If attempting to access unknown address or straddle hw windows,
749 * do not access.
750 */
751 start = qla82xx_pci_set_window(ha, off);
752 if ((start == -1UL) ||
753 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
754 write_unlock_irqrestore(&ha->hw_lock, flags);
755 qla_printk(KERN_ERR, ha,
756 "%s out of bound pci memory access. "
757 "offset is 0x%llx\n", QLA2XXX_DRIVER_NAME, off);
758 return -1;
759 }
760
761 write_unlock_irqrestore(&ha->hw_lock, flags);
762 mem_base = pci_resource_start(ha->pdev, 0);
763 mem_page = start & PAGE_MASK;
764 /* Map two pages whenever user tries to access addresses in two
765 * consecutive pages.
766 */
767 if (mem_page != ((start + size - 1) & PAGE_MASK))
768 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
769 else
770 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
771 if (mem_ptr == 0UL)
772 return -1;
773
774 addr = mem_ptr;
775 addr += start & (PAGE_SIZE - 1);
776 write_lock_irqsave(&ha->hw_lock, flags);
777
778 switch (size) {
779 case 1:
780 writeb(*(u8 *)data, addr);
781 break;
782 case 2:
783 writew(*(u16 *)data, addr);
784 break;
785 case 4:
786 writel(*(u32 *)data, addr);
787 break;
788 case 8:
789 writeq(*(u64 *)data, addr);
790 break;
791 default:
792 ret = -1;
793 break;
794 }
795 write_unlock_irqrestore(&ha->hw_lock, flags);
796 if (mem_ptr)
797 iounmap(mem_ptr);
798 return ret;
799 }
800
801 #define MTU_FUDGE_FACTOR 100
802 static unsigned long
qla82xx_decode_crb_addr(unsigned long addr)803 qla82xx_decode_crb_addr(unsigned long addr)
804 {
805 int i;
806 unsigned long base_addr, offset, pci_base;
807
808 if (!qla82xx_crb_table_initialized)
809 qla82xx_crb_addr_transform_setup();
810
811 pci_base = ADDR_ERROR;
812 base_addr = addr & 0xfff00000;
813 offset = addr & 0x000fffff;
814
815 for (i = 0; i < MAX_CRB_XFORM; i++) {
816 if (crb_addr_xform[i] == base_addr) {
817 pci_base = i << 20;
818 break;
819 }
820 }
821 if (pci_base == ADDR_ERROR)
822 return pci_base;
823 return pci_base + offset;
824 }
825
826 static long rom_max_timeout = 100;
827 static long qla82xx_rom_lock_timeout = 100;
828
829 static int
qla82xx_rom_lock(struct qla_hw_data * ha)830 qla82xx_rom_lock(struct qla_hw_data *ha)
831 {
832 int done = 0, timeout = 0;
833
834 while (!done) {
835 /* acquire semaphore2 from PCI HW block */
836 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
837 if (done == 1)
838 break;
839 if (timeout >= qla82xx_rom_lock_timeout)
840 return -1;
841 timeout++;
842 }
843 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
844 return 0;
845 }
846
847 static int
qla82xx_wait_rom_busy(struct qla_hw_data * ha)848 qla82xx_wait_rom_busy(struct qla_hw_data *ha)
849 {
850 long timeout = 0;
851 long done = 0 ;
852
853 while (done == 0) {
854 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
855 done &= 4;
856 timeout++;
857 if (timeout >= rom_max_timeout) {
858 DEBUG(qla_printk(KERN_INFO, ha,
859 "%s: Timeout reached waiting for rom busy",
860 QLA2XXX_DRIVER_NAME));
861 return -1;
862 }
863 }
864 return 0;
865 }
866
867 static int
qla82xx_wait_rom_done(struct qla_hw_data * ha)868 qla82xx_wait_rom_done(struct qla_hw_data *ha)
869 {
870 long timeout = 0;
871 long done = 0 ;
872
873 while (done == 0) {
874 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
875 done &= 2;
876 timeout++;
877 if (timeout >= rom_max_timeout) {
878 DEBUG(qla_printk(KERN_INFO, ha,
879 "%s: Timeout reached waiting for rom done",
880 QLA2XXX_DRIVER_NAME));
881 return -1;
882 }
883 }
884 return 0;
885 }
886
887 static int
qla82xx_do_rom_fast_read(struct qla_hw_data * ha,int addr,int * valp)888 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
889 {
890 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
891 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
892 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
893 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
894 qla82xx_wait_rom_busy(ha);
895 if (qla82xx_wait_rom_done(ha)) {
896 qla_printk(KERN_WARNING, ha,
897 "%s: Error waiting for rom done\n",
898 QLA2XXX_DRIVER_NAME);
899 return -1;
900 }
901 /* Reset abyte_cnt and dummy_byte_cnt */
902 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
903 udelay(10);
904 cond_resched();
905 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
906 *valp = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
907 return 0;
908 }
909
910 static int
qla82xx_rom_fast_read(struct qla_hw_data * ha,int addr,int * valp)911 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
912 {
913 int ret, loops = 0;
914
915 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
916 udelay(100);
917 schedule();
918 loops++;
919 }
920 if (loops >= 50000) {
921 qla_printk(KERN_INFO, ha,
922 "%s: qla82xx_rom_lock failed\n",
923 QLA2XXX_DRIVER_NAME);
924 return -1;
925 }
926 ret = qla82xx_do_rom_fast_read(ha, addr, valp);
927 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
928 return ret;
929 }
930
931 static int
qla82xx_read_status_reg(struct qla_hw_data * ha,uint32_t * val)932 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
933 {
934 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
935 qla82xx_wait_rom_busy(ha);
936 if (qla82xx_wait_rom_done(ha)) {
937 qla_printk(KERN_WARNING, ha,
938 "Error waiting for rom done\n");
939 return -1;
940 }
941 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
942 return 0;
943 }
944
945 static int
qla82xx_flash_wait_write_finish(struct qla_hw_data * ha)946 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
947 {
948 long timeout = 0;
949 uint32_t done = 1 ;
950 uint32_t val;
951 int ret = 0;
952
953 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
954 while ((done != 0) && (ret == 0)) {
955 ret = qla82xx_read_status_reg(ha, &val);
956 done = val & 1;
957 timeout++;
958 udelay(10);
959 cond_resched();
960 if (timeout >= 50000) {
961 qla_printk(KERN_WARNING, ha,
962 "Timeout reached waiting for write finish");
963 return -1;
964 }
965 }
966 return ret;
967 }
968
969 static int
qla82xx_flash_set_write_enable(struct qla_hw_data * ha)970 qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
971 {
972 uint32_t val;
973 qla82xx_wait_rom_busy(ha);
974 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
975 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
976 qla82xx_wait_rom_busy(ha);
977 if (qla82xx_wait_rom_done(ha))
978 return -1;
979 if (qla82xx_read_status_reg(ha, &val) != 0)
980 return -1;
981 if ((val & 2) != 2)
982 return -1;
983 return 0;
984 }
985
986 static int
qla82xx_write_status_reg(struct qla_hw_data * ha,uint32_t val)987 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
988 {
989 if (qla82xx_flash_set_write_enable(ha))
990 return -1;
991 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
992 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1);
993 if (qla82xx_wait_rom_done(ha)) {
994 qla_printk(KERN_WARNING, ha,
995 "Error waiting for rom done\n");
996 return -1;
997 }
998 return qla82xx_flash_wait_write_finish(ha);
999 }
1000
1001 static int
qla82xx_write_disable_flash(struct qla_hw_data * ha)1002 qla82xx_write_disable_flash(struct qla_hw_data *ha)
1003 {
1004 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
1005 if (qla82xx_wait_rom_done(ha)) {
1006 qla_printk(KERN_WARNING, ha,
1007 "Error waiting for rom done\n");
1008 return -1;
1009 }
1010 return 0;
1011 }
1012
1013 static int
ql82xx_rom_lock_d(struct qla_hw_data * ha)1014 ql82xx_rom_lock_d(struct qla_hw_data *ha)
1015 {
1016 int loops = 0;
1017 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1018 udelay(100);
1019 cond_resched();
1020 loops++;
1021 }
1022 if (loops >= 50000) {
1023 qla_printk(KERN_WARNING, ha, "ROM lock failed\n");
1024 return -1;
1025 }
1026 return 0;;
1027 }
1028
1029 static int
qla82xx_write_flash_dword(struct qla_hw_data * ha,uint32_t flashaddr,uint32_t data)1030 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
1031 uint32_t data)
1032 {
1033 int ret = 0;
1034
1035 ret = ql82xx_rom_lock_d(ha);
1036 if (ret < 0) {
1037 qla_printk(KERN_WARNING, ha, "ROM Lock failed\n");
1038 return ret;
1039 }
1040
1041 if (qla82xx_flash_set_write_enable(ha))
1042 goto done_write;
1043
1044 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data);
1045 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr);
1046 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1047 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP);
1048 qla82xx_wait_rom_busy(ha);
1049 if (qla82xx_wait_rom_done(ha)) {
1050 qla_printk(KERN_WARNING, ha,
1051 "Error waiting for rom done\n");
1052 ret = -1;
1053 goto done_write;
1054 }
1055
1056 ret = qla82xx_flash_wait_write_finish(ha);
1057
1058 done_write:
1059 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
1060 return ret;
1061 }
1062
1063 /* This routine does CRB initialize sequence
1064 * to put the ISP into operational state
1065 */
1066 static int
qla82xx_pinit_from_rom(scsi_qla_host_t * vha)1067 qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
1068 {
1069 int addr, val;
1070 int i ;
1071 struct crb_addr_pair *buf;
1072 unsigned long off;
1073 unsigned offset, n;
1074 struct qla_hw_data *ha = vha->hw;
1075
1076 struct crb_addr_pair {
1077 long addr;
1078 long data;
1079 };
1080
1081 /* Halt all the indiviual PEGs and other blocks of the ISP */
1082 qla82xx_rom_lock(ha);
1083
1084 /* mask all niu interrupts */
1085 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1086 /* disable xge rx/tx */
1087 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1088 /* disable xg1 rx/tx */
1089 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
1090
1091 /* halt sre */
1092 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1093 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1094
1095 /* halt epg */
1096 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1097
1098 /* halt timers */
1099 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1100 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1101 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1102 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1103 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1104
1105 /* halt pegs */
1106 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1107 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1108 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1109 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1110 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1111
1112 /* big hammer */
1113 msleep(1000);
1114 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
1115 /* don't reset CAM block on reset */
1116 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1117 else
1118 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1119
1120 /* reset ms */
1121 val = qla82xx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4);
1122 val |= (1 << 1);
1123 qla82xx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val);
1124 msleep(20);
1125
1126 /* unreset ms */
1127 val = qla82xx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4);
1128 val &= ~(1 << 1);
1129 qla82xx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val);
1130 msleep(20);
1131
1132 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
1133
1134 /* Read the signature value from the flash.
1135 * Offset 0: Contain signature (0xcafecafe)
1136 * Offset 4: Offset and number of addr/value pairs
1137 * that present in CRB initialize sequence
1138 */
1139 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1140 qla82xx_rom_fast_read(ha, 4, &n) != 0) {
1141 qla_printk(KERN_WARNING, ha,
1142 "[ERROR] Reading crb_init area: n: %08x\n", n);
1143 return -1;
1144 }
1145
1146 /* Offset in flash = lower 16 bits
1147 * Number of enteries = upper 16 bits
1148 */
1149 offset = n & 0xffffU;
1150 n = (n >> 16) & 0xffffU;
1151
1152 /* number of addr/value pair should not exceed 1024 enteries */
1153 if (n >= 1024) {
1154 qla_printk(KERN_WARNING, ha,
1155 "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
1156 QLA2XXX_DRIVER_NAME, __func__, n);
1157 return -1;
1158 }
1159
1160 qla_printk(KERN_INFO, ha,
1161 "%s: %d CRB init values found in ROM.\n", QLA2XXX_DRIVER_NAME, n);
1162
1163 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1164 if (buf == NULL) {
1165 qla_printk(KERN_WARNING, ha,
1166 "%s: [ERROR] Unable to malloc memory.\n",
1167 QLA2XXX_DRIVER_NAME);
1168 return -1;
1169 }
1170
1171 for (i = 0; i < n; i++) {
1172 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1173 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
1174 kfree(buf);
1175 return -1;
1176 }
1177
1178 buf[i].addr = addr;
1179 buf[i].data = val;
1180 }
1181
1182 for (i = 0; i < n; i++) {
1183 /* Translate internal CRB initialization
1184 * address to PCI bus address
1185 */
1186 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1187 QLA82XX_PCI_CRBSPACE;
1188 /* Not all CRB addr/value pair to be written,
1189 * some of them are skipped
1190 */
1191
1192 /* skipping cold reboot MAGIC */
1193 if (off == QLA82XX_CAM_RAM(0x1fc))
1194 continue;
1195
1196 /* do not reset PCI */
1197 if (off == (ROMUSB_GLB + 0xbc))
1198 continue;
1199
1200 /* skip core clock, so that firmware can increase the clock */
1201 if (off == (ROMUSB_GLB + 0xc8))
1202 continue;
1203
1204 /* skip the function enable register */
1205 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1206 continue;
1207
1208 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1209 continue;
1210
1211 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1212 continue;
1213
1214 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1215 continue;
1216
1217 if (off == ADDR_ERROR) {
1218 qla_printk(KERN_WARNING, ha,
1219 "%s: [ERROR] Unknown addr: 0x%08lx\n",
1220 QLA2XXX_DRIVER_NAME, buf[i].addr);
1221 continue;
1222 }
1223
1224 qla82xx_wr_32(ha, off, buf[i].data);
1225
1226 /* ISP requires much bigger delay to settle down,
1227 * else crb_window returns 0xffffffff
1228 */
1229 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1230 msleep(1000);
1231
1232 /* ISP requires millisec delay between
1233 * successive CRB register updation
1234 */
1235 msleep(1);
1236 }
1237
1238 kfree(buf);
1239
1240 /* Resetting the data and instruction cache */
1241 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1242 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1243 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1244
1245 /* Clear all protocol processing engines */
1246 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1247 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1248 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1249 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1250 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1251 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1252 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1253 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1254 return 0;
1255 }
1256
1257 static int
qla82xx_pci_mem_write_2M(struct qla_hw_data * ha,u64 off,void * data,int size)1258 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
1259 u64 off, void *data, int size)
1260 {
1261 int i, j, ret = 0, loop, sz[2], off0;
1262 int scale, shift_amount, startword;
1263 uint32_t temp;
1264 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1265
1266 /*
1267 * If not MN, go check for MS or invalid.
1268 */
1269 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1270 mem_crb = QLA82XX_CRB_QDR_NET;
1271 else {
1272 mem_crb = QLA82XX_CRB_DDR_NET;
1273 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1274 return qla82xx_pci_mem_write_direct(ha,
1275 off, data, size);
1276 }
1277
1278 off0 = off & 0x7;
1279 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1280 sz[1] = size - sz[0];
1281
1282 off8 = off & 0xfffffff0;
1283 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1284 shift_amount = 4;
1285 scale = 2;
1286 startword = (off & 0xf)/8;
1287
1288 for (i = 0; i < loop; i++) {
1289 if (qla82xx_pci_mem_read_2M(ha, off8 +
1290 (i << shift_amount), &word[i * scale], 8))
1291 return -1;
1292 }
1293
1294 switch (size) {
1295 case 1:
1296 tmpw = *((uint8_t *)data);
1297 break;
1298 case 2:
1299 tmpw = *((uint16_t *)data);
1300 break;
1301 case 4:
1302 tmpw = *((uint32_t *)data);
1303 break;
1304 case 8:
1305 default:
1306 tmpw = *((uint64_t *)data);
1307 break;
1308 }
1309
1310 if (sz[0] == 8) {
1311 word[startword] = tmpw;
1312 } else {
1313 word[startword] &=
1314 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1315 word[startword] |= tmpw << (off0 * 8);
1316 }
1317 if (sz[1] != 0) {
1318 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1319 word[startword+1] |= tmpw >> (sz[0] * 8);
1320 }
1321
1322 for (i = 0; i < loop; i++) {
1323 temp = off8 + (i << shift_amount);
1324 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1325 temp = 0;
1326 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1327 temp = word[i * scale] & 0xffffffff;
1328 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1329 temp = (word[i * scale] >> 32) & 0xffffffff;
1330 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1331 temp = word[i*scale + 1] & 0xffffffff;
1332 qla82xx_wr_32(ha, mem_crb +
1333 MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
1334 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1335 qla82xx_wr_32(ha, mem_crb +
1336 MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
1337
1338 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1339 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1340 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1341 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1342
1343 for (j = 0; j < MAX_CTL_CHECK; j++) {
1344 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1345 if ((temp & MIU_TA_CTL_BUSY) == 0)
1346 break;
1347 }
1348
1349 if (j >= MAX_CTL_CHECK) {
1350 if (printk_ratelimit())
1351 dev_err(&ha->pdev->dev,
1352 "failed to write through agent\n");
1353 ret = -1;
1354 break;
1355 }
1356 }
1357
1358 return ret;
1359 }
1360
1361 static int
qla82xx_fw_load_from_flash(struct qla_hw_data * ha)1362 qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
1363 {
1364 int i;
1365 long size = 0;
1366 long flashaddr = ha->flt_region_bootload << 2;
1367 long memaddr = BOOTLD_START;
1368 u64 data;
1369 u32 high, low;
1370 size = (IMAGE_START - BOOTLD_START) / 8;
1371
1372 for (i = 0; i < size; i++) {
1373 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1374 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) {
1375 return -1;
1376 }
1377 data = ((u64)high << 32) | low ;
1378 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1379 flashaddr += 8;
1380 memaddr += 8;
1381
1382 if (i % 0x1000 == 0)
1383 msleep(1);
1384 }
1385 udelay(100);
1386 read_lock(&ha->hw_lock);
1387 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1388 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1389 read_unlock(&ha->hw_lock);
1390 return 0;
1391 }
1392
1393 int
qla82xx_pci_mem_read_2M(struct qla_hw_data * ha,u64 off,void * data,int size)1394 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
1395 u64 off, void *data, int size)
1396 {
1397 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1398 int shift_amount;
1399 uint32_t temp;
1400 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1401
1402 /*
1403 * If not MN, go check for MS or invalid.
1404 */
1405
1406 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1407 mem_crb = QLA82XX_CRB_QDR_NET;
1408 else {
1409 mem_crb = QLA82XX_CRB_DDR_NET;
1410 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1411 return qla82xx_pci_mem_read_direct(ha,
1412 off, data, size);
1413 }
1414
1415 off8 = off & 0xfffffff0;
1416 off0[0] = off & 0xf;
1417 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1418 shift_amount = 4;
1419 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1420 off0[1] = 0;
1421 sz[1] = size - sz[0];
1422
1423 for (i = 0; i < loop; i++) {
1424 temp = off8 + (i << shift_amount);
1425 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1426 temp = 0;
1427 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1428 temp = MIU_TA_CTL_ENABLE;
1429 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1430 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1431 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1432
1433 for (j = 0; j < MAX_CTL_CHECK; j++) {
1434 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1435 if ((temp & MIU_TA_CTL_BUSY) == 0)
1436 break;
1437 }
1438
1439 if (j >= MAX_CTL_CHECK) {
1440 if (printk_ratelimit())
1441 dev_err(&ha->pdev->dev,
1442 "failed to read through agent\n");
1443 break;
1444 }
1445
1446 start = off0[i] >> 2;
1447 end = (off0[i] + sz[i] - 1) >> 2;
1448 for (k = start; k <= end; k++) {
1449 temp = qla82xx_rd_32(ha,
1450 mem_crb + MIU_TEST_AGT_RDDATA(k));
1451 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1452 }
1453 }
1454
1455 if (j >= MAX_CTL_CHECK)
1456 return -1;
1457
1458 if ((off0[0] & 7) == 0) {
1459 val = word[0];
1460 } else {
1461 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1462 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1463 }
1464
1465 switch (size) {
1466 case 1:
1467 *(uint8_t *)data = val;
1468 break;
1469 case 2:
1470 *(uint16_t *)data = val;
1471 break;
1472 case 4:
1473 *(uint32_t *)data = val;
1474 break;
1475 case 8:
1476 *(uint64_t *)data = val;
1477 break;
1478 }
1479 return 0;
1480 }
1481
1482
1483 static struct qla82xx_uri_table_desc *
qla82xx_get_table_desc(const u8 * unirom,int section)1484 qla82xx_get_table_desc(const u8 *unirom, int section)
1485 {
1486 uint32_t i;
1487 struct qla82xx_uri_table_desc *directory =
1488 (struct qla82xx_uri_table_desc *)&unirom[0];
1489 __le32 offset;
1490 __le32 tab_type;
1491 __le32 entries = cpu_to_le32(directory->num_entries);
1492
1493 for (i = 0; i < entries; i++) {
1494 offset = cpu_to_le32(directory->findex) +
1495 (i * cpu_to_le32(directory->entry_size));
1496 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8));
1497
1498 if (tab_type == section)
1499 return (struct qla82xx_uri_table_desc *)&unirom[offset];
1500 }
1501
1502 return NULL;
1503 }
1504
1505 static struct qla82xx_uri_data_desc *
qla82xx_get_data_desc(struct qla_hw_data * ha,u32 section,u32 idx_offset)1506 qla82xx_get_data_desc(struct qla_hw_data *ha,
1507 u32 section, u32 idx_offset)
1508 {
1509 const u8 *unirom = ha->hablob->fw->data;
1510 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset));
1511 struct qla82xx_uri_table_desc *tab_desc = NULL;
1512 __le32 offset;
1513
1514 tab_desc = qla82xx_get_table_desc(unirom, section);
1515 if (!tab_desc)
1516 return NULL;
1517
1518 offset = cpu_to_le32(tab_desc->findex) +
1519 (cpu_to_le32(tab_desc->entry_size) * idx);
1520
1521 return (struct qla82xx_uri_data_desc *)&unirom[offset];
1522 }
1523
1524 static u8 *
qla82xx_get_bootld_offset(struct qla_hw_data * ha)1525 qla82xx_get_bootld_offset(struct qla_hw_data *ha)
1526 {
1527 u32 offset = BOOTLD_START;
1528 struct qla82xx_uri_data_desc *uri_desc = NULL;
1529
1530 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1531 uri_desc = qla82xx_get_data_desc(ha,
1532 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
1533 if (uri_desc)
1534 offset = cpu_to_le32(uri_desc->findex);
1535 }
1536
1537 return (u8 *)&ha->hablob->fw->data[offset];
1538 }
1539
1540 static __le32
qla82xx_get_fw_size(struct qla_hw_data * ha)1541 qla82xx_get_fw_size(struct qla_hw_data *ha)
1542 {
1543 struct qla82xx_uri_data_desc *uri_desc = NULL;
1544
1545 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1546 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1547 QLA82XX_URI_FIRMWARE_IDX_OFF);
1548 if (uri_desc)
1549 return cpu_to_le32(uri_desc->size);
1550 }
1551
1552 return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]);
1553 }
1554
1555 static u8 *
qla82xx_get_fw_offs(struct qla_hw_data * ha)1556 qla82xx_get_fw_offs(struct qla_hw_data *ha)
1557 {
1558 u32 offset = IMAGE_START;
1559 struct qla82xx_uri_data_desc *uri_desc = NULL;
1560
1561 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1562 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1563 QLA82XX_URI_FIRMWARE_IDX_OFF);
1564 if (uri_desc)
1565 offset = cpu_to_le32(uri_desc->findex);
1566 }
1567
1568 return (u8 *)&ha->hablob->fw->data[offset];
1569 }
1570
1571 /* PCI related functions */
1572 char *
qla82xx_pci_info_str(struct scsi_qla_host * vha,char * str)1573 qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str)
1574 {
1575 int pcie_reg;
1576 struct qla_hw_data *ha = vha->hw;
1577 char lwstr[6];
1578 uint16_t lnk;
1579
1580 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
1581 pci_read_config_word(ha->pdev, pcie_reg + PCI_EXP_LNKSTA, &lnk);
1582 ha->link_width = (lnk >> 4) & 0x3f;
1583
1584 strcpy(str, "PCIe (");
1585 strcat(str, "2.5Gb/s ");
1586 snprintf(lwstr, sizeof(lwstr), "x%d)", ha->link_width);
1587 strcat(str, lwstr);
1588 return str;
1589 }
1590
qla82xx_pci_region_offset(struct pci_dev * pdev,int region)1591 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region)
1592 {
1593 unsigned long val = 0;
1594 u32 control;
1595
1596 switch (region) {
1597 case 0:
1598 val = 0;
1599 break;
1600 case 1:
1601 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1602 val = control + QLA82XX_MSIX_TBL_SPACE;
1603 break;
1604 }
1605 return val;
1606 }
1607
1608
1609 int
qla82xx_iospace_config(struct qla_hw_data * ha)1610 qla82xx_iospace_config(struct qla_hw_data *ha)
1611 {
1612 uint32_t len = 0;
1613
1614 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) {
1615 qla_printk(KERN_WARNING, ha,
1616 "Failed to reserve selected regions (%s)\n",
1617 pci_name(ha->pdev));
1618 goto iospace_error_exit;
1619 }
1620
1621 /* Use MMIO operations for all accesses. */
1622 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1623 qla_printk(KERN_ERR, ha,
1624 "region #0 not an MMIO resource (%s), aborting\n",
1625 pci_name(ha->pdev));
1626 goto iospace_error_exit;
1627 }
1628
1629 len = pci_resource_len(ha->pdev, 0);
1630 ha->nx_pcibase =
1631 (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len);
1632 if (!ha->nx_pcibase) {
1633 qla_printk(KERN_ERR, ha,
1634 "cannot remap pcibase MMIO (%s), aborting\n",
1635 pci_name(ha->pdev));
1636 pci_release_regions(ha->pdev);
1637 goto iospace_error_exit;
1638 }
1639
1640 /* Mapping of IO base pointer */
1641 ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase +
1642 0xbc000 + (ha->pdev->devfn << 11));
1643
1644 if (!ql2xdbwr) {
1645 ha->nxdb_wr_ptr =
1646 (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) +
1647 (ha->pdev->devfn << 12)), 4);
1648 if (!ha->nxdb_wr_ptr) {
1649 qla_printk(KERN_ERR, ha,
1650 "cannot remap MMIO (%s), aborting\n",
1651 pci_name(ha->pdev));
1652 pci_release_regions(ha->pdev);
1653 goto iospace_error_exit;
1654 }
1655
1656 /* Mapping of IO base pointer,
1657 * door bell read and write pointer
1658 */
1659 ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) +
1660 (ha->pdev->devfn * 8);
1661 } else {
1662 ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ?
1663 QLA82XX_CAMRAM_DB1 :
1664 QLA82XX_CAMRAM_DB2);
1665 }
1666
1667 ha->max_req_queues = ha->max_rsp_queues = 1;
1668 ha->msix_count = ha->max_rsp_queues + 1;
1669 return 0;
1670
1671 iospace_error_exit:
1672 return -ENOMEM;
1673 }
1674
1675 /* GS related functions */
1676
1677 /* Initialization related functions */
1678
1679 /**
1680 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1681 * @ha: HA context
1682 *
1683 * Returns 0 on success.
1684 */
1685 int
qla82xx_pci_config(scsi_qla_host_t * vha)1686 qla82xx_pci_config(scsi_qla_host_t *vha)
1687 {
1688 struct qla_hw_data *ha = vha->hw;
1689 int ret;
1690
1691 pci_set_master(ha->pdev);
1692 ret = pci_set_mwi(ha->pdev);
1693 ha->chip_revision = ha->pdev->revision;
1694 return 0;
1695 }
1696
1697 /**
1698 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1699 * @ha: HA context
1700 *
1701 * Returns 0 on success.
1702 */
1703 void
qla82xx_reset_chip(scsi_qla_host_t * vha)1704 qla82xx_reset_chip(scsi_qla_host_t *vha)
1705 {
1706 struct qla_hw_data *ha = vha->hw;
1707 ha->isp_ops->disable_intrs(ha);
1708 }
1709
qla82xx_config_rings(struct scsi_qla_host * vha)1710 void qla82xx_config_rings(struct scsi_qla_host *vha)
1711 {
1712 struct qla_hw_data *ha = vha->hw;
1713 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1714 struct init_cb_81xx *icb;
1715 struct req_que *req = ha->req_q_map[0];
1716 struct rsp_que *rsp = ha->rsp_q_map[0];
1717
1718 /* Setup ring parameters in initialization control block. */
1719 icb = (struct init_cb_81xx *)ha->init_cb;
1720 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1721 icb->response_q_inpointer = __constant_cpu_to_le16(0);
1722 icb->request_q_length = cpu_to_le16(req->length);
1723 icb->response_q_length = cpu_to_le16(rsp->length);
1724 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1725 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1726 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1727 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1728
1729 WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0);
1730 WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0);
1731 WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0);
1732 }
1733
qla82xx_reset_adapter(struct scsi_qla_host * vha)1734 void qla82xx_reset_adapter(struct scsi_qla_host *vha)
1735 {
1736 struct qla_hw_data *ha = vha->hw;
1737 vha->flags.online = 0;
1738 qla2x00_try_to_stop_firmware(vha);
1739 ha->isp_ops->disable_intrs(ha);
1740 }
1741
1742 static int
qla82xx_fw_load_from_blob(struct qla_hw_data * ha)1743 qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
1744 {
1745 u64 *ptr64;
1746 u32 i, flashaddr, size;
1747 __le64 data;
1748
1749 size = (IMAGE_START - BOOTLD_START) / 8;
1750
1751 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha);
1752 flashaddr = BOOTLD_START;
1753
1754 for (i = 0; i < size; i++) {
1755 data = cpu_to_le64(ptr64[i]);
1756 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1757 return -EIO;
1758 flashaddr += 8;
1759 }
1760
1761 flashaddr = FLASH_ADDR_START;
1762 size = (__force u32)qla82xx_get_fw_size(ha) / 8;
1763 ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
1764
1765 for (i = 0; i < size; i++) {
1766 data = cpu_to_le64(ptr64[i]);
1767
1768 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1769 return -EIO;
1770 flashaddr += 8;
1771 }
1772 udelay(100);
1773
1774 /* Write a magic value to CAMRAM register
1775 * at a specified offset to indicate
1776 * that all data is written and
1777 * ready for firmware to initialize.
1778 */
1779 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC);
1780
1781 read_lock(&ha->hw_lock);
1782 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1783 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1784 read_unlock(&ha->hw_lock);
1785 return 0;
1786 }
1787
1788 static int
qla82xx_set_product_offset(struct qla_hw_data * ha)1789 qla82xx_set_product_offset(struct qla_hw_data *ha)
1790 {
1791 struct qla82xx_uri_table_desc *ptab_desc = NULL;
1792 const uint8_t *unirom = ha->hablob->fw->data;
1793 uint32_t i;
1794 __le32 entries;
1795 __le32 flags, file_chiprev, offset;
1796 uint8_t chiprev = ha->chip_revision;
1797 /* Hardcoding mn_present flag for P3P */
1798 int mn_present = 0;
1799 uint32_t flagbit;
1800
1801 ptab_desc = qla82xx_get_table_desc(unirom,
1802 QLA82XX_URI_DIR_SECT_PRODUCT_TBL);
1803 if (!ptab_desc)
1804 return -1;
1805
1806 entries = cpu_to_le32(ptab_desc->num_entries);
1807
1808 for (i = 0; i < entries; i++) {
1809 offset = cpu_to_le32(ptab_desc->findex) +
1810 (i * cpu_to_le32(ptab_desc->entry_size));
1811 flags = cpu_to_le32(*((int *)&unirom[offset] +
1812 QLA82XX_URI_FLAGS_OFF));
1813 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] +
1814 QLA82XX_URI_CHIP_REV_OFF));
1815
1816 flagbit = mn_present ? 1 : 2;
1817
1818 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
1819 ha->file_prd_off = offset;
1820 return 0;
1821 }
1822 }
1823 return -1;
1824 }
1825
1826 int
qla82xx_validate_firmware_blob(scsi_qla_host_t * vha,uint8_t fw_type)1827 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
1828 {
1829 __le32 val;
1830 uint32_t min_size;
1831 struct qla_hw_data *ha = vha->hw;
1832 const struct firmware *fw = ha->hablob->fw;
1833
1834 ha->fw_type = fw_type;
1835
1836 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1837 if (qla82xx_set_product_offset(ha))
1838 return -EINVAL;
1839
1840 min_size = QLA82XX_URI_FW_MIN_SIZE;
1841 } else {
1842 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
1843 if ((__force u32)val != QLA82XX_BDINFO_MAGIC)
1844 return -EINVAL;
1845
1846 min_size = QLA82XX_FW_MIN_SIZE;
1847 }
1848
1849 if (fw->size < min_size)
1850 return -EINVAL;
1851 return 0;
1852 }
1853
1854 static int
qla82xx_check_cmdpeg_state(struct qla_hw_data * ha)1855 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
1856 {
1857 u32 val = 0;
1858 int retries = 60;
1859
1860 do {
1861 read_lock(&ha->hw_lock);
1862 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE);
1863 read_unlock(&ha->hw_lock);
1864
1865 switch (val) {
1866 case PHAN_INITIALIZE_COMPLETE:
1867 case PHAN_INITIALIZE_ACK:
1868 return QLA_SUCCESS;
1869 case PHAN_INITIALIZE_FAILED:
1870 break;
1871 default:
1872 break;
1873 }
1874 qla_printk(KERN_WARNING, ha,
1875 "CRB_CMDPEG_STATE: 0x%x and retries: 0x%x\n",
1876 val, retries);
1877
1878 msleep(500);
1879
1880 } while (--retries);
1881
1882 qla_printk(KERN_INFO, ha,
1883 "Cmd Peg initialization failed: 0x%x.\n", val);
1884
1885 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1886 read_lock(&ha->hw_lock);
1887 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
1888 read_unlock(&ha->hw_lock);
1889 return QLA_FUNCTION_FAILED;
1890 }
1891
1892 static int
qla82xx_check_rcvpeg_state(struct qla_hw_data * ha)1893 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
1894 {
1895 u32 val = 0;
1896 int retries = 60;
1897
1898 do {
1899 read_lock(&ha->hw_lock);
1900 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE);
1901 read_unlock(&ha->hw_lock);
1902
1903 switch (val) {
1904 case PHAN_INITIALIZE_COMPLETE:
1905 case PHAN_INITIALIZE_ACK:
1906 return QLA_SUCCESS;
1907 case PHAN_INITIALIZE_FAILED:
1908 break;
1909 default:
1910 break;
1911 }
1912
1913 qla_printk(KERN_WARNING, ha,
1914 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x\n",
1915 val, retries);
1916
1917 msleep(500);
1918
1919 } while (--retries);
1920
1921 qla_printk(KERN_INFO, ha,
1922 "Rcv Peg initialization failed: 0x%x.\n", val);
1923 read_lock(&ha->hw_lock);
1924 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED);
1925 read_unlock(&ha->hw_lock);
1926 return QLA_FUNCTION_FAILED;
1927 }
1928
1929 /* ISR related functions */
1930 uint32_t qla82xx_isr_int_target_mask_enable[8] = {
1931 ISR_INT_TARGET_MASK, ISR_INT_TARGET_MASK_F1,
1932 ISR_INT_TARGET_MASK_F2, ISR_INT_TARGET_MASK_F3,
1933 ISR_INT_TARGET_MASK_F4, ISR_INT_TARGET_MASK_F5,
1934 ISR_INT_TARGET_MASK_F7, ISR_INT_TARGET_MASK_F7
1935 };
1936
1937 uint32_t qla82xx_isr_int_target_status[8] = {
1938 ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1,
1939 ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3,
1940 ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5,
1941 ISR_INT_TARGET_STATUS_F7, ISR_INT_TARGET_STATUS_F7
1942 };
1943
1944 static struct qla82xx_legacy_intr_set legacy_intr[] = \
1945 QLA82XX_LEGACY_INTR_CONFIG;
1946
1947 /*
1948 * qla82xx_mbx_completion() - Process mailbox command completions.
1949 * @ha: SCSI driver HA context
1950 * @mb0: Mailbox0 register
1951 */
1952 static void
qla82xx_mbx_completion(scsi_qla_host_t * vha,uint16_t mb0)1953 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
1954 {
1955 uint16_t cnt;
1956 uint16_t __iomem *wptr;
1957 struct qla_hw_data *ha = vha->hw;
1958 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1959 wptr = (uint16_t __iomem *)®->mailbox_out[1];
1960
1961 /* Load return mailbox registers. */
1962 ha->flags.mbox_int = 1;
1963 ha->mailbox_out[0] = mb0;
1964
1965 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
1966 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
1967 wptr++;
1968 }
1969
1970 if (ha->mcp) {
1971 DEBUG3_11(printk(KERN_INFO "%s(%ld): "
1972 "Got mailbox completion. cmd=%x.\n",
1973 __func__, vha->host_no, ha->mcp->mb[0]));
1974 } else {
1975 qla_printk(KERN_INFO, ha,
1976 "%s(%ld): MBX pointer ERROR!\n",
1977 __func__, vha->host_no);
1978 }
1979 }
1980
1981 /*
1982 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
1983 * @irq:
1984 * @dev_id: SCSI driver HA context
1985 * @regs:
1986 *
1987 * Called by system whenever the host adapter generates an interrupt.
1988 *
1989 * Returns handled flag.
1990 */
1991 irqreturn_t
qla82xx_intr_handler(int irq,void * dev_id)1992 qla82xx_intr_handler(int irq, void *dev_id)
1993 {
1994 scsi_qla_host_t *vha;
1995 struct qla_hw_data *ha;
1996 struct rsp_que *rsp;
1997 struct device_reg_82xx __iomem *reg;
1998 int status = 0, status1 = 0;
1999 unsigned long flags;
2000 unsigned long iter;
2001 uint32_t stat;
2002 uint16_t mb[4];
2003
2004 rsp = (struct rsp_que *) dev_id;
2005 if (!rsp) {
2006 printk(KERN_INFO
2007 "%s(): NULL response queue pointer\n", __func__);
2008 return IRQ_NONE;
2009 }
2010 ha = rsp->hw;
2011
2012 if (!ha->flags.msi_enabled) {
2013 status = qla82xx_rd_32(ha, ISR_INT_VECTOR);
2014 if (!(status & ha->nx_legacy_intr.int_vec_bit))
2015 return IRQ_NONE;
2016
2017 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG);
2018 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1))
2019 return IRQ_NONE;
2020 }
2021
2022 /* clear the interrupt */
2023 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
2024
2025 /* read twice to ensure write is flushed */
2026 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2027 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2028
2029 reg = &ha->iobase->isp82;
2030
2031 spin_lock_irqsave(&ha->hardware_lock, flags);
2032 vha = pci_get_drvdata(ha->pdev);
2033 for (iter = 1; iter--; ) {
2034
2035 if (RD_REG_DWORD(®->host_int)) {
2036 stat = RD_REG_DWORD(®->host_status);
2037
2038 switch (stat & 0xff) {
2039 case 0x1:
2040 case 0x2:
2041 case 0x10:
2042 case 0x11:
2043 qla82xx_mbx_completion(vha, MSW(stat));
2044 status |= MBX_INTERRUPT;
2045 break;
2046 case 0x12:
2047 mb[0] = MSW(stat);
2048 mb[1] = RD_REG_WORD(®->mailbox_out[1]);
2049 mb[2] = RD_REG_WORD(®->mailbox_out[2]);
2050 mb[3] = RD_REG_WORD(®->mailbox_out[3]);
2051 qla2x00_async_event(vha, rsp, mb);
2052 break;
2053 case 0x13:
2054 qla24xx_process_response_queue(vha, rsp);
2055 break;
2056 default:
2057 DEBUG2(printk("scsi(%ld): "
2058 " Unrecognized interrupt type (%d).\n",
2059 vha->host_no, stat & 0xff));
2060 break;
2061 }
2062 }
2063 WRT_REG_DWORD(®->host_int, 0);
2064 }
2065 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2066 if (!ha->flags.msi_enabled)
2067 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2068
2069 #ifdef QL_DEBUG_LEVEL_17
2070 if (!irq && ha->flags.eeh_busy)
2071 qla_printk(KERN_WARNING, ha,
2072 "isr: status %x, cmd_flags %lx, mbox_int %x, stat %x\n",
2073 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat);
2074 #endif
2075
2076 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
2077 (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
2078 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
2079 complete(&ha->mbx_intr_comp);
2080 }
2081 return IRQ_HANDLED;
2082 }
2083
2084 irqreturn_t
qla82xx_msix_default(int irq,void * dev_id)2085 qla82xx_msix_default(int irq, void *dev_id)
2086 {
2087 scsi_qla_host_t *vha;
2088 struct qla_hw_data *ha;
2089 struct rsp_que *rsp;
2090 struct device_reg_82xx __iomem *reg;
2091 int status = 0;
2092 unsigned long flags;
2093 uint32_t stat;
2094 uint16_t mb[4];
2095
2096 rsp = (struct rsp_que *) dev_id;
2097 if (!rsp) {
2098 printk(KERN_INFO
2099 "%s(): NULL response queue pointer\n", __func__);
2100 return IRQ_NONE;
2101 }
2102 ha = rsp->hw;
2103
2104 reg = &ha->iobase->isp82;
2105
2106 spin_lock_irqsave(&ha->hardware_lock, flags);
2107 vha = pci_get_drvdata(ha->pdev);
2108 do {
2109 if (RD_REG_DWORD(®->host_int)) {
2110 stat = RD_REG_DWORD(®->host_status);
2111
2112 switch (stat & 0xff) {
2113 case 0x1:
2114 case 0x2:
2115 case 0x10:
2116 case 0x11:
2117 qla82xx_mbx_completion(vha, MSW(stat));
2118 status |= MBX_INTERRUPT;
2119 break;
2120 case 0x12:
2121 mb[0] = MSW(stat);
2122 mb[1] = RD_REG_WORD(®->mailbox_out[1]);
2123 mb[2] = RD_REG_WORD(®->mailbox_out[2]);
2124 mb[3] = RD_REG_WORD(®->mailbox_out[3]);
2125 qla2x00_async_event(vha, rsp, mb);
2126 break;
2127 case 0x13:
2128 qla24xx_process_response_queue(vha, rsp);
2129 break;
2130 default:
2131 DEBUG2(printk("scsi(%ld): "
2132 " Unrecognized interrupt type (%d).\n",
2133 vha->host_no, stat & 0xff));
2134 break;
2135 }
2136 }
2137 WRT_REG_DWORD(®->host_int, 0);
2138 } while (0);
2139
2140 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2141
2142 #ifdef QL_DEBUG_LEVEL_17
2143 if (!irq && ha->flags.eeh_busy)
2144 qla_printk(KERN_WARNING, ha,
2145 "isr: status %x, cmd_flags %lx, mbox_int %x, stat %x\n",
2146 status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat);
2147 #endif
2148
2149 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
2150 (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
2151 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
2152 complete(&ha->mbx_intr_comp);
2153 }
2154 return IRQ_HANDLED;
2155 }
2156
2157 irqreturn_t
qla82xx_msix_rsp_q(int irq,void * dev_id)2158 qla82xx_msix_rsp_q(int irq, void *dev_id)
2159 {
2160 scsi_qla_host_t *vha;
2161 struct qla_hw_data *ha;
2162 struct rsp_que *rsp;
2163 struct device_reg_82xx __iomem *reg;
2164
2165 rsp = (struct rsp_que *) dev_id;
2166 if (!rsp) {
2167 printk(KERN_INFO
2168 "%s(): NULL response queue pointer\n", __func__);
2169 return IRQ_NONE;
2170 }
2171
2172 ha = rsp->hw;
2173 reg = &ha->iobase->isp82;
2174 spin_lock_irq(&ha->hardware_lock);
2175 vha = pci_get_drvdata(ha->pdev);
2176 qla24xx_process_response_queue(vha, rsp);
2177 WRT_REG_DWORD(®->host_int, 0);
2178 spin_unlock_irq(&ha->hardware_lock);
2179 return IRQ_HANDLED;
2180 }
2181
2182 void
qla82xx_poll(int irq,void * dev_id)2183 qla82xx_poll(int irq, void *dev_id)
2184 {
2185 scsi_qla_host_t *vha;
2186 struct qla_hw_data *ha;
2187 struct rsp_que *rsp;
2188 struct device_reg_82xx __iomem *reg;
2189 int status = 0;
2190 uint32_t stat;
2191 uint16_t mb[4];
2192 unsigned long flags;
2193
2194 rsp = (struct rsp_que *) dev_id;
2195 if (!rsp) {
2196 printk(KERN_INFO
2197 "%s(): NULL response queue pointer\n", __func__);
2198 return;
2199 }
2200 ha = rsp->hw;
2201
2202 reg = &ha->iobase->isp82;
2203 spin_lock_irqsave(&ha->hardware_lock, flags);
2204 vha = pci_get_drvdata(ha->pdev);
2205
2206 if (RD_REG_DWORD(®->host_int)) {
2207 stat = RD_REG_DWORD(®->host_status);
2208 switch (stat & 0xff) {
2209 case 0x1:
2210 case 0x2:
2211 case 0x10:
2212 case 0x11:
2213 qla82xx_mbx_completion(vha, MSW(stat));
2214 status |= MBX_INTERRUPT;
2215 break;
2216 case 0x12:
2217 mb[0] = MSW(stat);
2218 mb[1] = RD_REG_WORD(®->mailbox_out[1]);
2219 mb[2] = RD_REG_WORD(®->mailbox_out[2]);
2220 mb[3] = RD_REG_WORD(®->mailbox_out[3]);
2221 qla2x00_async_event(vha, rsp, mb);
2222 break;
2223 case 0x13:
2224 qla24xx_process_response_queue(vha, rsp);
2225 break;
2226 default:
2227 DEBUG2(printk("scsi(%ld): Unrecognized interrupt type "
2228 "(%d).\n",
2229 vha->host_no, stat & 0xff));
2230 break;
2231 }
2232 }
2233 WRT_REG_DWORD(®->host_int, 0);
2234 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2235 }
2236
2237 void
qla82xx_enable_intrs(struct qla_hw_data * ha)2238 qla82xx_enable_intrs(struct qla_hw_data *ha)
2239 {
2240 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2241 qla82xx_mbx_intr_enable(vha);
2242 spin_lock_irq(&ha->hardware_lock);
2243 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2244 spin_unlock_irq(&ha->hardware_lock);
2245 ha->interrupts_on = 1;
2246 }
2247
2248 void
qla82xx_disable_intrs(struct qla_hw_data * ha)2249 qla82xx_disable_intrs(struct qla_hw_data *ha)
2250 {
2251 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2252 qla82xx_mbx_intr_disable(vha);
2253 spin_lock_irq(&ha->hardware_lock);
2254 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2255 spin_unlock_irq(&ha->hardware_lock);
2256 ha->interrupts_on = 0;
2257 }
2258
qla82xx_init_flags(struct qla_hw_data * ha)2259 void qla82xx_init_flags(struct qla_hw_data *ha)
2260 {
2261 struct qla82xx_legacy_intr_set *nx_legacy_intr;
2262
2263 /* ISP 8021 initializations */
2264 rwlock_init(&ha->hw_lock);
2265 ha->qdr_sn_window = -1;
2266 ha->ddr_mn_window = -1;
2267 ha->curr_window = 255;
2268 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2269 nx_legacy_intr = &legacy_intr[ha->portnum];
2270 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit;
2271 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg;
2272 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg;
2273 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg;
2274 }
2275
2276 inline void
qla82xx_set_drv_active(scsi_qla_host_t * vha)2277 qla82xx_set_drv_active(scsi_qla_host_t *vha)
2278 {
2279 uint32_t drv_active;
2280 struct qla_hw_data *ha = vha->hw;
2281
2282 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2283
2284 /* If reset value is all FF's, initialize DRV_ACTIVE */
2285 if (drv_active == 0xffffffff) {
2286 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE,
2287 QLA82XX_DRV_NOT_ACTIVE);
2288 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2289 }
2290 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2291 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2292 }
2293
2294 inline void
qla82xx_clear_drv_active(struct qla_hw_data * ha)2295 qla82xx_clear_drv_active(struct qla_hw_data *ha)
2296 {
2297 uint32_t drv_active;
2298
2299 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2300 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2301 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2302 }
2303
2304 static inline int
qla82xx_need_reset(struct qla_hw_data * ha)2305 qla82xx_need_reset(struct qla_hw_data *ha)
2306 {
2307 uint32_t drv_state;
2308 int rval;
2309
2310 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2311 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2312 return rval;
2313 }
2314
2315 static inline void
qla82xx_set_rst_ready(struct qla_hw_data * ha)2316 qla82xx_set_rst_ready(struct qla_hw_data *ha)
2317 {
2318 uint32_t drv_state;
2319 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2320
2321 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2322
2323 /* If reset value is all FF's, initialize DRV_STATE */
2324 if (drv_state == 0xffffffff) {
2325 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY);
2326 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2327 }
2328 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2329 qla_printk(KERN_INFO, ha,
2330 "%s(%ld):drv_state = 0x%x\n",
2331 __func__, vha->host_no, drv_state);
2332 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2333 }
2334
2335 static inline void
qla82xx_clear_rst_ready(struct qla_hw_data * ha)2336 qla82xx_clear_rst_ready(struct qla_hw_data *ha)
2337 {
2338 uint32_t drv_state;
2339
2340 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2341 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2342 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2343 }
2344
2345 static inline void
qla82xx_set_qsnt_ready(struct qla_hw_data * ha)2346 qla82xx_set_qsnt_ready(struct qla_hw_data *ha)
2347 {
2348 uint32_t qsnt_state;
2349
2350 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2351 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2352 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2353 }
2354
2355 void
qla82xx_clear_qsnt_ready(scsi_qla_host_t * vha)2356 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha)
2357 {
2358 struct qla_hw_data *ha = vha->hw;
2359 uint32_t qsnt_state;
2360
2361 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2362 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2363 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2364 }
2365
2366 static int
qla82xx_load_fw(scsi_qla_host_t * vha)2367 qla82xx_load_fw(scsi_qla_host_t *vha)
2368 {
2369 int rst;
2370 struct fw_blob *blob;
2371 struct qla_hw_data *ha = vha->hw;
2372
2373 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) {
2374 qla_printk(KERN_ERR, ha,
2375 "%s: Error during CRB Initialization\n", __func__);
2376 return QLA_FUNCTION_FAILED;
2377 }
2378 udelay(500);
2379
2380 /* Bring QM and CAMRAM out of reset */
2381 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
2382 rst &= ~((1 << 28) | (1 << 24));
2383 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
2384
2385 /*
2386 * FW Load priority:
2387 * 1) Operational firmware residing in flash.
2388 * 2) Firmware via request-firmware interface (.bin file).
2389 */
2390 if (ql2xfwloadbin == 2)
2391 goto try_blob_fw;
2392
2393 qla_printk(KERN_INFO, ha,
2394 "Attempting to load firmware from flash\n");
2395
2396 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) {
2397 qla_printk(KERN_ERR, ha,
2398 "Firmware loaded successfully from flash\n");
2399 return QLA_SUCCESS;
2400 }
2401 try_blob_fw:
2402 qla_printk(KERN_INFO, ha,
2403 "Attempting to load firmware from blob\n");
2404
2405 /* Load firmware blob. */
2406 blob = ha->hablob = qla2x00_request_firmware(vha);
2407 if (!blob) {
2408 qla_printk(KERN_ERR, ha,
2409 "Firmware image not present.\n");
2410 goto fw_load_failed;
2411 }
2412
2413 /* Validating firmware blob */
2414 if (qla82xx_validate_firmware_blob(vha,
2415 QLA82XX_FLASH_ROMIMAGE)) {
2416 /* Fallback to URI format */
2417 if (qla82xx_validate_firmware_blob(vha,
2418 QLA82XX_UNIFIED_ROMIMAGE)) {
2419 qla_printk(KERN_ERR, ha,
2420 "No valid firmware image found!!!");
2421 return QLA_FUNCTION_FAILED;
2422 }
2423 }
2424
2425 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) {
2426 qla_printk(KERN_ERR, ha,
2427 "%s: Firmware loaded successfully "
2428 " from binary blob\n", __func__);
2429 return QLA_SUCCESS;
2430 } else {
2431 qla_printk(KERN_ERR, ha,
2432 "Firmware load failed from binary blob\n");
2433 blob->fw = NULL;
2434 blob = NULL;
2435 goto fw_load_failed;
2436 }
2437 return QLA_SUCCESS;
2438
2439 fw_load_failed:
2440 return QLA_FUNCTION_FAILED;
2441 }
2442
2443 int
qla82xx_start_firmware(scsi_qla_host_t * vha)2444 qla82xx_start_firmware(scsi_qla_host_t *vha)
2445 {
2446 int pcie_cap;
2447 uint16_t lnk;
2448 struct qla_hw_data *ha = vha->hw;
2449
2450 /* scrub dma mask expansion register */
2451 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE);
2452
2453 /* Put both the PEG CMD and RCV PEG to default state
2454 * of 0 before resetting the hardware
2455 */
2456 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
2457 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
2458
2459 /* Overwrite stale initialization register values */
2460 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
2461 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
2462
2463 if (qla82xx_load_fw(vha) != QLA_SUCCESS) {
2464 qla_printk(KERN_INFO, ha,
2465 "%s: Error trying to start fw!\n", __func__);
2466 return QLA_FUNCTION_FAILED;
2467 }
2468
2469 /* Handshake with the card before we register the devices. */
2470 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) {
2471 qla_printk(KERN_INFO, ha,
2472 "%s: Error during card handshake!\n", __func__);
2473 return QLA_FUNCTION_FAILED;
2474 }
2475
2476 /* Negotiated Link width */
2477 pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
2478 pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk);
2479 ha->link_width = (lnk >> 4) & 0x3f;
2480
2481 /* Synchronize with Receive peg */
2482 return qla82xx_check_rcvpeg_state(ha);
2483 }
2484
2485 static inline int
qla2xx_build_scsi_type_6_iocbs(srb_t * sp,struct cmd_type_6 * cmd_pkt,uint16_t tot_dsds)2486 qla2xx_build_scsi_type_6_iocbs(srb_t *sp, struct cmd_type_6 *cmd_pkt,
2487 uint16_t tot_dsds)
2488 {
2489 uint32_t *cur_dsd = NULL;
2490 scsi_qla_host_t *vha;
2491 struct qla_hw_data *ha;
2492 struct scsi_cmnd *cmd;
2493 struct scatterlist *cur_seg;
2494 uint32_t *dsd_seg;
2495 void *next_dsd;
2496 uint8_t avail_dsds;
2497 uint8_t first_iocb = 1;
2498 uint32_t dsd_list_len;
2499 struct dsd_dma *dsd_ptr;
2500 struct ct6_dsd *ctx;
2501
2502 cmd = sp->cmd;
2503
2504 /* Update entry type to indicate Command Type 3 IOCB */
2505 *((uint32_t *)(&cmd_pkt->entry_type)) =
2506 __constant_cpu_to_le32(COMMAND_TYPE_6);
2507
2508 /* No data transfer */
2509 if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
2510 cmd_pkt->byte_count = __constant_cpu_to_le32(0);
2511 return 0;
2512 }
2513
2514 vha = sp->fcport->vha;
2515 ha = vha->hw;
2516
2517 /* Set transfer direction */
2518 if (cmd->sc_data_direction == DMA_TO_DEVICE) {
2519 cmd_pkt->control_flags =
2520 __constant_cpu_to_le16(CF_WRITE_DATA);
2521 ha->qla_stats.output_bytes += scsi_bufflen(cmd);
2522 } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) {
2523 cmd_pkt->control_flags =
2524 __constant_cpu_to_le16(CF_READ_DATA);
2525 ha->qla_stats.input_bytes += scsi_bufflen(cmd);
2526 }
2527
2528 cur_seg = scsi_sglist(cmd);
2529 ctx = sp->ctx;
2530
2531 while (tot_dsds) {
2532 avail_dsds = (tot_dsds > QLA_DSDS_PER_IOCB) ?
2533 QLA_DSDS_PER_IOCB : tot_dsds;
2534 tot_dsds -= avail_dsds;
2535 dsd_list_len = (avail_dsds + 1) * QLA_DSD_SIZE;
2536
2537 dsd_ptr = list_first_entry(&ha->gbl_dsd_list,
2538 struct dsd_dma, list);
2539 next_dsd = dsd_ptr->dsd_addr;
2540 list_del(&dsd_ptr->list);
2541 ha->gbl_dsd_avail--;
2542 list_add_tail(&dsd_ptr->list, &ctx->dsd_list);
2543 ctx->dsd_use_cnt++;
2544 ha->gbl_dsd_inuse++;
2545
2546 if (first_iocb) {
2547 first_iocb = 0;
2548 dsd_seg = (uint32_t *)&cmd_pkt->fcp_data_dseg_address;
2549 *dsd_seg++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma));
2550 *dsd_seg++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma));
2551 cmd_pkt->fcp_data_dseg_len = dsd_list_len;
2552 } else {
2553 *cur_dsd++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma));
2554 *cur_dsd++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma));
2555 *cur_dsd++ = dsd_list_len;
2556 }
2557 cur_dsd = (uint32_t *)next_dsd;
2558 while (avail_dsds) {
2559 dma_addr_t sle_dma;
2560
2561 sle_dma = sg_dma_address(cur_seg);
2562 *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
2563 *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
2564 *cur_dsd++ = cpu_to_le32(sg_dma_len(cur_seg));
2565 cur_seg = sg_next(cur_seg);
2566 avail_dsds--;
2567 }
2568 }
2569
2570 /* Null termination */
2571 *cur_dsd++ = 0;
2572 *cur_dsd++ = 0;
2573 *cur_dsd++ = 0;
2574 cmd_pkt->control_flags |= CF_DATA_SEG_DESCR_ENABLE;
2575 return 0;
2576 }
2577
2578 /*
2579 * qla82xx_calc_dsd_lists() - Determine number of DSD list required
2580 * for Command Type 6.
2581 *
2582 * @dsds: number of data segment decriptors needed
2583 *
2584 * Returns the number of dsd list needed to store @dsds.
2585 */
2586 inline uint16_t
qla82xx_calc_dsd_lists(uint16_t dsds)2587 qla82xx_calc_dsd_lists(uint16_t dsds)
2588 {
2589 uint16_t dsd_lists = 0;
2590
2591 dsd_lists = (dsds/QLA_DSDS_PER_IOCB);
2592 if (dsds % QLA_DSDS_PER_IOCB)
2593 dsd_lists++;
2594 return dsd_lists;
2595 }
2596
2597 /*
2598 * qla82xx_start_scsi() - Send a SCSI command to the ISP
2599 * @sp: command to send to the ISP
2600 *
2601 * Returns non-zero if a failure occurred, else zero.
2602 */
2603 int
qla82xx_start_scsi(srb_t * sp)2604 qla82xx_start_scsi(srb_t *sp)
2605 {
2606 int ret, nseg;
2607 unsigned long flags;
2608 struct scsi_cmnd *cmd;
2609 uint32_t *clr_ptr;
2610 uint32_t index;
2611 uint32_t handle;
2612 uint16_t cnt;
2613 uint16_t req_cnt;
2614 uint16_t tot_dsds;
2615 struct device_reg_82xx __iomem *reg;
2616 uint32_t dbval;
2617 uint32_t *fcp_dl;
2618 uint8_t additional_cdb_len;
2619 struct ct6_dsd *ctx;
2620 struct scsi_qla_host *vha = sp->fcport->vha;
2621 struct qla_hw_data *ha = vha->hw;
2622 struct req_que *req = NULL;
2623 struct rsp_que *rsp = NULL;
2624 char tag[2];
2625
2626 /* Setup device pointers. */
2627 ret = 0;
2628 reg = &ha->iobase->isp82;
2629 cmd = sp->cmd;
2630 req = vha->req;
2631 rsp = ha->rsp_q_map[0];
2632
2633 /* So we know we haven't pci_map'ed anything yet */
2634 tot_dsds = 0;
2635
2636 dbval = 0x04 | (ha->portnum << 5);
2637
2638 /* Send marker if required */
2639 if (vha->marker_needed != 0) {
2640 if (qla2x00_marker(vha, req,
2641 rsp, 0, 0, MK_SYNC_ALL) != QLA_SUCCESS)
2642 return QLA_FUNCTION_FAILED;
2643 vha->marker_needed = 0;
2644 }
2645
2646 /* Acquire ring specific lock */
2647 spin_lock_irqsave(&ha->hardware_lock, flags);
2648
2649 /* Check for room in outstanding command list. */
2650 handle = req->current_outstanding_cmd;
2651 for (index = 1; index < MAX_OUTSTANDING_COMMANDS; index++) {
2652 handle++;
2653 if (handle == MAX_OUTSTANDING_COMMANDS)
2654 handle = 1;
2655 if (!req->outstanding_cmds[handle])
2656 break;
2657 }
2658 if (index == MAX_OUTSTANDING_COMMANDS)
2659 goto queuing_error;
2660
2661 /* Map the sg table so we have an accurate count of sg entries needed */
2662 if (scsi_sg_count(cmd)) {
2663 nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd),
2664 scsi_sg_count(cmd), cmd->sc_data_direction);
2665 if (unlikely(!nseg))
2666 goto queuing_error;
2667 } else
2668 nseg = 0;
2669
2670 tot_dsds = nseg;
2671
2672 if (tot_dsds > ql2xshiftctondsd) {
2673 struct cmd_type_6 *cmd_pkt;
2674 uint16_t more_dsd_lists = 0;
2675 struct dsd_dma *dsd_ptr;
2676 uint16_t i;
2677
2678 more_dsd_lists = qla82xx_calc_dsd_lists(tot_dsds);
2679 if ((more_dsd_lists + ha->gbl_dsd_inuse) >= NUM_DSD_CHAIN)
2680 goto queuing_error;
2681
2682 if (more_dsd_lists <= ha->gbl_dsd_avail)
2683 goto sufficient_dsds;
2684 else
2685 more_dsd_lists -= ha->gbl_dsd_avail;
2686
2687 for (i = 0; i < more_dsd_lists; i++) {
2688 dsd_ptr = kzalloc(sizeof(struct dsd_dma), GFP_ATOMIC);
2689 if (!dsd_ptr)
2690 goto queuing_error;
2691
2692 dsd_ptr->dsd_addr = dma_pool_alloc(ha->dl_dma_pool,
2693 GFP_ATOMIC, &dsd_ptr->dsd_list_dma);
2694 if (!dsd_ptr->dsd_addr) {
2695 kfree(dsd_ptr);
2696 goto queuing_error;
2697 }
2698 list_add_tail(&dsd_ptr->list, &ha->gbl_dsd_list);
2699 ha->gbl_dsd_avail++;
2700 }
2701
2702 sufficient_dsds:
2703 req_cnt = 1;
2704
2705 if (req->cnt < (req_cnt + 2)) {
2706 cnt = (uint16_t)RD_REG_DWORD_RELAXED(
2707 ®->req_q_out[0]);
2708 if (req->ring_index < cnt)
2709 req->cnt = cnt - req->ring_index;
2710 else
2711 req->cnt = req->length -
2712 (req->ring_index - cnt);
2713 }
2714
2715 if (req->cnt < (req_cnt + 2))
2716 goto queuing_error;
2717
2718 ctx = sp->ctx = mempool_alloc(ha->ctx_mempool, GFP_ATOMIC);
2719 if (!sp->ctx) {
2720 DEBUG(printk(KERN_INFO
2721 "%s(%ld): failed to allocate"
2722 " ctx.\n", __func__, vha->host_no));
2723 goto queuing_error;
2724 }
2725 memset(ctx, 0, sizeof(struct ct6_dsd));
2726 ctx->fcp_cmnd = dma_pool_alloc(ha->fcp_cmnd_dma_pool,
2727 GFP_ATOMIC, &ctx->fcp_cmnd_dma);
2728 if (!ctx->fcp_cmnd) {
2729 DEBUG2_3(printk("%s(%ld): failed to allocate"
2730 " fcp_cmnd.\n", __func__, vha->host_no));
2731 goto queuing_error_fcp_cmnd;
2732 }
2733
2734 /* Initialize the DSD list and dma handle */
2735 INIT_LIST_HEAD(&ctx->dsd_list);
2736 ctx->dsd_use_cnt = 0;
2737
2738 if (cmd->cmd_len > 16) {
2739 additional_cdb_len = cmd->cmd_len - 16;
2740 if ((cmd->cmd_len % 4) != 0) {
2741 /* SCSI command bigger than 16 bytes must be
2742 * multiple of 4
2743 */
2744 goto queuing_error_fcp_cmnd;
2745 }
2746 ctx->fcp_cmnd_len = 12 + cmd->cmd_len + 4;
2747 } else {
2748 additional_cdb_len = 0;
2749 ctx->fcp_cmnd_len = 12 + 16 + 4;
2750 }
2751
2752 cmd_pkt = (struct cmd_type_6 *)req->ring_ptr;
2753 cmd_pkt->handle = MAKE_HANDLE(req->id, handle);
2754
2755 /* Zero out remaining portion of packet. */
2756 /* tagged queuing modifier -- default is TSK_SIMPLE (0). */
2757 clr_ptr = (uint32_t *)cmd_pkt + 2;
2758 memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8);
2759 cmd_pkt->dseg_count = cpu_to_le16(tot_dsds);
2760
2761 /* Set NPORT-ID and LUN number*/
2762 cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id);
2763 cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa;
2764 cmd_pkt->port_id[1] = sp->fcport->d_id.b.area;
2765 cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain;
2766 cmd_pkt->vp_index = sp->fcport->vp_idx;
2767
2768 /* Build IOCB segments */
2769 if (qla2xx_build_scsi_type_6_iocbs(sp, cmd_pkt, tot_dsds))
2770 goto queuing_error_fcp_cmnd;
2771
2772 int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun);
2773 host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, sizeof(cmd_pkt->lun));
2774
2775 /*
2776 * Update tagged queuing modifier -- default is TSK_SIMPLE (0).
2777 */
2778 if (scsi_populate_tag_msg(cmd, tag)) {
2779 switch (tag[0]) {
2780 case HEAD_OF_QUEUE_TAG:
2781 ctx->fcp_cmnd->task_attribute =
2782 TSK_HEAD_OF_QUEUE;
2783 break;
2784 case ORDERED_QUEUE_TAG:
2785 ctx->fcp_cmnd->task_attribute =
2786 TSK_ORDERED;
2787 break;
2788 }
2789 }
2790
2791 /* build FCP_CMND IU */
2792 memset(ctx->fcp_cmnd, 0, sizeof(struct fcp_cmnd));
2793 int_to_scsilun(sp->cmd->device->lun, &ctx->fcp_cmnd->lun);
2794 ctx->fcp_cmnd->additional_cdb_len = additional_cdb_len;
2795
2796 if (cmd->sc_data_direction == DMA_TO_DEVICE)
2797 ctx->fcp_cmnd->additional_cdb_len |= 1;
2798 else if (cmd->sc_data_direction == DMA_FROM_DEVICE)
2799 ctx->fcp_cmnd->additional_cdb_len |= 2;
2800
2801 memcpy(ctx->fcp_cmnd->cdb, cmd->cmnd, cmd->cmd_len);
2802
2803 fcp_dl = (uint32_t *)(ctx->fcp_cmnd->cdb + 16 +
2804 additional_cdb_len);
2805 *fcp_dl = htonl((uint32_t)scsi_bufflen(cmd));
2806
2807 cmd_pkt->fcp_cmnd_dseg_len = cpu_to_le16(ctx->fcp_cmnd_len);
2808 cmd_pkt->fcp_cmnd_dseg_address[0] =
2809 cpu_to_le32(LSD(ctx->fcp_cmnd_dma));
2810 cmd_pkt->fcp_cmnd_dseg_address[1] =
2811 cpu_to_le32(MSD(ctx->fcp_cmnd_dma));
2812
2813 sp->flags |= SRB_FCP_CMND_DMA_VALID;
2814 cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
2815 /* Set total data segment count. */
2816 cmd_pkt->entry_count = (uint8_t)req_cnt;
2817 /* Specify response queue number where
2818 * completion should happen
2819 */
2820 cmd_pkt->entry_status = (uint8_t) rsp->id;
2821 } else {
2822 struct cmd_type_7 *cmd_pkt;
2823 req_cnt = qla24xx_calc_iocbs(tot_dsds);
2824 if (req->cnt < (req_cnt + 2)) {
2825 cnt = (uint16_t)RD_REG_DWORD_RELAXED(
2826 ®->req_q_out[0]);
2827 if (req->ring_index < cnt)
2828 req->cnt = cnt - req->ring_index;
2829 else
2830 req->cnt = req->length -
2831 (req->ring_index - cnt);
2832 }
2833 if (req->cnt < (req_cnt + 2))
2834 goto queuing_error;
2835
2836 cmd_pkt = (struct cmd_type_7 *)req->ring_ptr;
2837 cmd_pkt->handle = MAKE_HANDLE(req->id, handle);
2838
2839 /* Zero out remaining portion of packet. */
2840 /* tagged queuing modifier -- default is TSK_SIMPLE (0).*/
2841 clr_ptr = (uint32_t *)cmd_pkt + 2;
2842 memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8);
2843 cmd_pkt->dseg_count = cpu_to_le16(tot_dsds);
2844
2845 /* Set NPORT-ID and LUN number*/
2846 cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id);
2847 cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa;
2848 cmd_pkt->port_id[1] = sp->fcport->d_id.b.area;
2849 cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain;
2850 cmd_pkt->vp_index = sp->fcport->vp_idx;
2851
2852 int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun);
2853 host_to_fcp_swap((uint8_t *)&cmd_pkt->lun,
2854 sizeof(cmd_pkt->lun));
2855
2856 /*
2857 * Update tagged queuing modifier -- default is TSK_SIMPLE (0).
2858 */
2859 if (scsi_populate_tag_msg(cmd, tag)) {
2860 switch (tag[0]) {
2861 case HEAD_OF_QUEUE_TAG:
2862 cmd_pkt->task = TSK_HEAD_OF_QUEUE;
2863 break;
2864 case ORDERED_QUEUE_TAG:
2865 cmd_pkt->task = TSK_ORDERED;
2866 break;
2867 }
2868 }
2869
2870 /* Load SCSI command packet. */
2871 memcpy(cmd_pkt->fcp_cdb, cmd->cmnd, cmd->cmd_len);
2872 host_to_fcp_swap(cmd_pkt->fcp_cdb, sizeof(cmd_pkt->fcp_cdb));
2873
2874 cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
2875
2876 /* Build IOCB segments */
2877 qla24xx_build_scsi_iocbs(sp, cmd_pkt, tot_dsds);
2878
2879 /* Set total data segment count. */
2880 cmd_pkt->entry_count = (uint8_t)req_cnt;
2881 /* Specify response queue number where
2882 * completion should happen.
2883 */
2884 cmd_pkt->entry_status = (uint8_t) rsp->id;
2885
2886 }
2887 /* Build command packet. */
2888 req->current_outstanding_cmd = handle;
2889 req->outstanding_cmds[handle] = sp;
2890 sp->handle = handle;
2891 sp->cmd->host_scribble = (unsigned char *)(unsigned long)handle;
2892 req->cnt -= req_cnt;
2893 wmb();
2894
2895 /* Adjust ring index. */
2896 req->ring_index++;
2897 if (req->ring_index == req->length) {
2898 req->ring_index = 0;
2899 req->ring_ptr = req->ring;
2900 } else
2901 req->ring_ptr++;
2902
2903 sp->flags |= SRB_DMA_VALID;
2904
2905 /* Set chip new ring index. */
2906 /* write, read and verify logic */
2907 dbval = dbval | (req->id << 8) | (req->ring_index << 16);
2908 if (ql2xdbwr)
2909 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval);
2910 else {
2911 WRT_REG_DWORD(
2912 (unsigned long __iomem *)ha->nxdb_wr_ptr,
2913 dbval);
2914 wmb();
2915 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) {
2916 WRT_REG_DWORD(
2917 (unsigned long __iomem *)ha->nxdb_wr_ptr,
2918 dbval);
2919 wmb();
2920 }
2921 }
2922
2923 /* Manage unprocessed RIO/ZIO commands in response queue. */
2924 if (vha->flags.process_response_queue &&
2925 rsp->ring_ptr->signature != RESPONSE_PROCESSED)
2926 qla24xx_process_response_queue(vha, rsp);
2927
2928 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2929 return QLA_SUCCESS;
2930
2931 queuing_error_fcp_cmnd:
2932 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd, ctx->fcp_cmnd_dma);
2933 queuing_error:
2934 if (tot_dsds)
2935 scsi_dma_unmap(cmd);
2936
2937 if (sp->ctx) {
2938 mempool_free(sp->ctx, ha->ctx_mempool);
2939 sp->ctx = NULL;
2940 }
2941 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2942
2943 return QLA_FUNCTION_FAILED;
2944 }
2945
2946 static uint32_t *
qla82xx_read_flash_data(scsi_qla_host_t * vha,uint32_t * dwptr,uint32_t faddr,uint32_t length)2947 qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
2948 uint32_t length)
2949 {
2950 uint32_t i;
2951 uint32_t val;
2952 struct qla_hw_data *ha = vha->hw;
2953
2954 /* Dword reads to flash. */
2955 for (i = 0; i < length/4; i++, faddr += 4) {
2956 if (qla82xx_rom_fast_read(ha, faddr, &val)) {
2957 qla_printk(KERN_WARNING, ha,
2958 "Do ROM fast read failed\n");
2959 goto done_read;
2960 }
2961 dwptr[i] = __constant_cpu_to_le32(val);
2962 }
2963 done_read:
2964 return dwptr;
2965 }
2966
2967 static int
qla82xx_unprotect_flash(struct qla_hw_data * ha)2968 qla82xx_unprotect_flash(struct qla_hw_data *ha)
2969 {
2970 int ret;
2971 uint32_t val;
2972
2973 ret = ql82xx_rom_lock_d(ha);
2974 if (ret < 0) {
2975 qla_printk(KERN_WARNING, ha, "ROM Lock failed\n");
2976 return ret;
2977 }
2978
2979 ret = qla82xx_read_status_reg(ha, &val);
2980 if (ret < 0)
2981 goto done_unprotect;
2982
2983 val &= ~(BLOCK_PROTECT_BITS << 2);
2984 ret = qla82xx_write_status_reg(ha, val);
2985 if (ret < 0) {
2986 val |= (BLOCK_PROTECT_BITS << 2);
2987 qla82xx_write_status_reg(ha, val);
2988 }
2989
2990 if (qla82xx_write_disable_flash(ha) != 0)
2991 qla_printk(KERN_WARNING, ha, "Write disable failed\n");
2992
2993 done_unprotect:
2994 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
2995 return ret;
2996 }
2997
2998 static int
qla82xx_protect_flash(struct qla_hw_data * ha)2999 qla82xx_protect_flash(struct qla_hw_data *ha)
3000 {
3001 int ret;
3002 uint32_t val;
3003
3004 ret = ql82xx_rom_lock_d(ha);
3005 if (ret < 0) {
3006 qla_printk(KERN_WARNING, ha, "ROM Lock failed\n");
3007 return ret;
3008 }
3009
3010 ret = qla82xx_read_status_reg(ha, &val);
3011 if (ret < 0)
3012 goto done_protect;
3013
3014 val |= (BLOCK_PROTECT_BITS << 2);
3015 /* LOCK all sectors */
3016 ret = qla82xx_write_status_reg(ha, val);
3017 if (ret < 0)
3018 qla_printk(KERN_WARNING, ha, "Write status register failed\n");
3019
3020 if (qla82xx_write_disable_flash(ha) != 0)
3021 qla_printk(KERN_WARNING, ha, "Write disable failed\n");
3022 done_protect:
3023 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
3024 return ret;
3025 }
3026
3027 static int
qla82xx_erase_sector(struct qla_hw_data * ha,int addr)3028 qla82xx_erase_sector(struct qla_hw_data *ha, int addr)
3029 {
3030 int ret = 0;
3031
3032 ret = ql82xx_rom_lock_d(ha);
3033 if (ret < 0) {
3034 qla_printk(KERN_WARNING, ha, "ROM Lock failed\n");
3035 return ret;
3036 }
3037
3038 qla82xx_flash_set_write_enable(ha);
3039 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
3040 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
3041 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE);
3042
3043 if (qla82xx_wait_rom_done(ha)) {
3044 qla_printk(KERN_WARNING, ha,
3045 "Error waiting for rom done\n");
3046 ret = -1;
3047 goto done;
3048 }
3049 ret = qla82xx_flash_wait_write_finish(ha);
3050 done:
3051 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
3052 return ret;
3053 }
3054
3055 /*
3056 * Address and length are byte address
3057 */
3058 uint8_t *
qla82xx_read_optrom_data(struct scsi_qla_host * vha,uint8_t * buf,uint32_t offset,uint32_t length)3059 qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
3060 uint32_t offset, uint32_t length)
3061 {
3062 scsi_block_requests(vha->host);
3063 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length);
3064 scsi_unblock_requests(vha->host);
3065 return buf;
3066 }
3067
3068 static int
qla82xx_write_flash_data(struct scsi_qla_host * vha,uint32_t * dwptr,uint32_t faddr,uint32_t dwords)3069 qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr,
3070 uint32_t faddr, uint32_t dwords)
3071 {
3072 int ret;
3073 uint32_t liter;
3074 uint32_t sec_mask, rest_addr;
3075 dma_addr_t optrom_dma;
3076 void *optrom = NULL;
3077 int page_mode = 0;
3078 struct qla_hw_data *ha = vha->hw;
3079
3080 ret = -1;
3081
3082 /* Prepare burst-capable write on supported ISPs. */
3083 if (page_mode && !(faddr & 0xfff) &&
3084 dwords > OPTROM_BURST_DWORDS) {
3085 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
3086 &optrom_dma, GFP_KERNEL);
3087 if (!optrom) {
3088 qla_printk(KERN_DEBUG, ha,
3089 "Unable to allocate memory for optrom "
3090 "burst write (%x KB).\n",
3091 OPTROM_BURST_SIZE / 1024);
3092 }
3093 }
3094
3095 rest_addr = ha->fdt_block_size - 1;
3096 sec_mask = ~rest_addr;
3097
3098 ret = qla82xx_unprotect_flash(ha);
3099 if (ret) {
3100 qla_printk(KERN_WARNING, ha,
3101 "Unable to unprotect flash for update.\n");
3102 goto write_done;
3103 }
3104
3105 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
3106 /* Are we at the beginning of a sector? */
3107 if ((faddr & rest_addr) == 0) {
3108
3109 ret = qla82xx_erase_sector(ha, faddr);
3110 if (ret) {
3111 DEBUG9(qla_printk(KERN_ERR, ha,
3112 "Unable to erase sector: "
3113 "address=%x.\n", faddr));
3114 break;
3115 }
3116 }
3117
3118 /* Go with burst-write. */
3119 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
3120 /* Copy data to DMA'ble buffer. */
3121 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
3122
3123 ret = qla2x00_load_ram(vha, optrom_dma,
3124 (ha->flash_data_off | faddr),
3125 OPTROM_BURST_DWORDS);
3126 if (ret != QLA_SUCCESS) {
3127 qla_printk(KERN_WARNING, ha,
3128 "Unable to burst-write optrom segment "
3129 "(%x/%x/%llx).\n", ret,
3130 (ha->flash_data_off | faddr),
3131 (unsigned long long)optrom_dma);
3132 qla_printk(KERN_WARNING, ha,
3133 "Reverting to slow-write.\n");
3134
3135 dma_free_coherent(&ha->pdev->dev,
3136 OPTROM_BURST_SIZE, optrom, optrom_dma);
3137 optrom = NULL;
3138 } else {
3139 liter += OPTROM_BURST_DWORDS - 1;
3140 faddr += OPTROM_BURST_DWORDS - 1;
3141 dwptr += OPTROM_BURST_DWORDS - 1;
3142 continue;
3143 }
3144 }
3145
3146 ret = qla82xx_write_flash_dword(ha, faddr,
3147 cpu_to_le32(*dwptr));
3148 if (ret) {
3149 DEBUG9(printk(KERN_DEBUG "%s(%ld) Unable to program"
3150 "flash address=%x data=%x.\n", __func__,
3151 ha->host_no, faddr, *dwptr));
3152 break;
3153 }
3154 }
3155
3156 ret = qla82xx_protect_flash(ha);
3157 if (ret)
3158 qla_printk(KERN_WARNING, ha,
3159 "Unable to protect flash after update.\n");
3160 write_done:
3161 if (optrom)
3162 dma_free_coherent(&ha->pdev->dev,
3163 OPTROM_BURST_SIZE, optrom, optrom_dma);
3164 return ret;
3165 }
3166
3167 int
qla82xx_write_optrom_data(struct scsi_qla_host * vha,uint8_t * buf,uint32_t offset,uint32_t length)3168 qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
3169 uint32_t offset, uint32_t length)
3170 {
3171 int rval;
3172
3173 /* Suspend HBA. */
3174 scsi_block_requests(vha->host);
3175 rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset,
3176 length >> 2);
3177 scsi_unblock_requests(vha->host);
3178
3179 /* Convert return ISP82xx to generic */
3180 if (rval)
3181 rval = QLA_FUNCTION_FAILED;
3182 else
3183 rval = QLA_SUCCESS;
3184 return rval;
3185 }
3186
3187 void
qla82xx_start_iocbs(srb_t * sp)3188 qla82xx_start_iocbs(srb_t *sp)
3189 {
3190 struct qla_hw_data *ha = sp->fcport->vha->hw;
3191 struct req_que *req = ha->req_q_map[0];
3192 struct device_reg_82xx __iomem *reg;
3193 uint32_t dbval;
3194
3195 /* Adjust ring index. */
3196 req->ring_index++;
3197 if (req->ring_index == req->length) {
3198 req->ring_index = 0;
3199 req->ring_ptr = req->ring;
3200 } else
3201 req->ring_ptr++;
3202
3203 reg = &ha->iobase->isp82;
3204 dbval = 0x04 | (ha->portnum << 5);
3205
3206 dbval = dbval | (req->id << 8) | (req->ring_index << 16);
3207 if (ql2xdbwr)
3208 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval);
3209 else {
3210 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval);
3211 wmb();
3212 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) {
3213 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr,
3214 dbval);
3215 wmb();
3216 }
3217 }
3218 }
3219
qla82xx_rom_lock_recovery(struct qla_hw_data * ha)3220 void qla82xx_rom_lock_recovery(struct qla_hw_data *ha)
3221 {
3222 if (qla82xx_rom_lock(ha))
3223 /* Someone else is holding the lock. */
3224 qla_printk(KERN_INFO, ha, "Resetting rom_lock\n");
3225
3226 /*
3227 * Either we got the lock, or someone
3228 * else died while holding it.
3229 * In either case, unlock.
3230 */
3231 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
3232 }
3233
3234 /*
3235 * qla82xx_device_bootstrap
3236 * Initialize device, set DEV_READY, start fw
3237 *
3238 * Note:
3239 * IDC lock must be held upon entry
3240 *
3241 * Return:
3242 * Success : 0
3243 * Failed : 1
3244 */
3245 static int
qla82xx_device_bootstrap(scsi_qla_host_t * vha)3246 qla82xx_device_bootstrap(scsi_qla_host_t *vha)
3247 {
3248 int rval = QLA_SUCCESS;
3249 int i, timeout;
3250 uint32_t old_count, count;
3251 struct qla_hw_data *ha = vha->hw;
3252 int need_reset = 0, peg_stuck = 1;
3253
3254 need_reset = qla82xx_need_reset(ha);
3255
3256 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
3257
3258 for (i = 0; i < 10; i++) {
3259 timeout = msleep_interruptible(200);
3260 if (timeout) {
3261 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3262 QLA82XX_DEV_FAILED);
3263 return QLA_FUNCTION_FAILED;
3264 }
3265
3266 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
3267 if (count != old_count)
3268 peg_stuck = 0;
3269 }
3270
3271 if (need_reset) {
3272 /* We are trying to perform a recovery here. */
3273 if (peg_stuck)
3274 qla82xx_rom_lock_recovery(ha);
3275 goto dev_initialize;
3276 } else {
3277 /* Start of day for this ha context. */
3278 if (peg_stuck) {
3279 /* Either we are the first or recovery in progress. */
3280 qla82xx_rom_lock_recovery(ha);
3281 goto dev_initialize;
3282 } else
3283 /* Firmware already running. */
3284 goto dev_ready;
3285 }
3286
3287 return rval;
3288
3289 dev_initialize:
3290 /* set to DEV_INITIALIZING */
3291 qla_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
3292 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING);
3293
3294 /* Driver that sets device state to initializating sets IDC version */
3295 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION);
3296
3297 qla82xx_idc_unlock(ha);
3298 rval = qla82xx_start_firmware(vha);
3299 qla82xx_idc_lock(ha);
3300
3301 if (rval != QLA_SUCCESS) {
3302 qla_printk(KERN_INFO, ha, "HW State: FAILED\n");
3303 qla82xx_clear_drv_active(ha);
3304 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED);
3305 return rval;
3306 }
3307
3308 dev_ready:
3309 qla_printk(KERN_INFO, ha, "HW State: READY\n");
3310 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY);
3311
3312 return QLA_SUCCESS;
3313 }
3314
3315 /*
3316 * qla82xx_need_qsnt_handler
3317 * Code to start quiescence sequence
3318 *
3319 * Note:
3320 * IDC lock must be held upon entry
3321 *
3322 * Return: void
3323 */
3324
3325 static void
qla82xx_need_qsnt_handler(scsi_qla_host_t * vha)3326 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha)
3327 {
3328 struct qla_hw_data *ha = vha->hw;
3329 uint32_t dev_state, drv_state, drv_active;
3330 unsigned long reset_timeout;
3331
3332 if (vha->flags.online) {
3333 /*Block any further I/O and wait for pending cmnds to complete*/
3334 qla82xx_quiescent_state_cleanup(vha);
3335 }
3336
3337 /* Set the quiescence ready bit */
3338 qla82xx_set_qsnt_ready(ha);
3339
3340 /*wait for 30 secs for other functions to ack */
3341 reset_timeout = jiffies + (30 * HZ);
3342
3343 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3344 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3345 /* Its 2 that is written when qsnt is acked, moving one bit */
3346 drv_active = drv_active << 0x01;
3347
3348 while (drv_state != drv_active) {
3349
3350 if (time_after_eq(jiffies, reset_timeout)) {
3351 /* quiescence timeout, other functions didn't ack
3352 * changing the state to DEV_READY
3353 */
3354 qla_printk(KERN_INFO, ha,
3355 "%s: QUIESCENT TIMEOUT\n", QLA2XXX_DRIVER_NAME);
3356 qla_printk(KERN_INFO, ha,
3357 "DRV_ACTIVE:%d DRV_STATE:%d\n", drv_active,
3358 drv_state);
3359 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3360 QLA82XX_DEV_READY);
3361 qla_printk(KERN_INFO, ha,
3362 "HW State: DEV_READY\n");
3363 qla82xx_idc_unlock(ha);
3364 qla2x00_perform_loop_resync(vha);
3365 qla82xx_idc_lock(ha);
3366
3367 qla82xx_clear_qsnt_ready(vha);
3368 return;
3369 }
3370
3371 qla82xx_idc_unlock(ha);
3372 msleep(1000);
3373 qla82xx_idc_lock(ha);
3374
3375 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3376 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3377 drv_active = drv_active << 0x01;
3378 }
3379 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3380 /* everyone acked so set the state to DEV_QUIESCENCE */
3381 if (dev_state == QLA82XX_DEV_NEED_QUIESCENT) {
3382 qla_printk(KERN_INFO, ha, "HW State: DEV_QUIESCENT\n");
3383 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_QUIESCENT);
3384 }
3385 }
3386
3387 /*
3388 * qla82xx_wait_for_state_change
3389 * Wait for device state to change from given current state
3390 *
3391 * Note:
3392 * IDC lock must not be held upon entry
3393 *
3394 * Return:
3395 * Changed device state.
3396 */
3397 uint32_t
qla82xx_wait_for_state_change(scsi_qla_host_t * vha,uint32_t curr_state)3398 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state)
3399 {
3400 struct qla_hw_data *ha = vha->hw;
3401 uint32_t dev_state;
3402
3403 do {
3404 msleep(1000);
3405 qla82xx_idc_lock(ha);
3406 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3407 qla82xx_idc_unlock(ha);
3408 } while (dev_state == curr_state);
3409
3410 return dev_state;
3411 }
3412
3413 static void
qla82xx_dev_failed_handler(scsi_qla_host_t * vha)3414 qla82xx_dev_failed_handler(scsi_qla_host_t *vha)
3415 {
3416 struct qla_hw_data *ha = vha->hw;
3417
3418 /* Disable the board */
3419 qla_printk(KERN_INFO, ha, "Disabling the board\n");
3420
3421 qla82xx_idc_lock(ha);
3422 qla82xx_clear_drv_active(ha);
3423 qla82xx_idc_unlock(ha);
3424
3425 /* Set DEV_FAILED flag to disable timer */
3426 vha->device_flags |= DFLG_DEV_FAILED;
3427 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3428 qla2x00_mark_all_devices_lost(vha, 0);
3429 vha->flags.online = 0;
3430 vha->flags.init_done = 0;
3431 }
3432
3433 /*
3434 * qla82xx_need_reset_handler
3435 * Code to start reset sequence
3436 *
3437 * Note:
3438 * IDC lock must be held upon entry
3439 *
3440 * Return:
3441 * Success : 0
3442 * Failed : 1
3443 */
3444 static void
qla82xx_need_reset_handler(scsi_qla_host_t * vha)3445 qla82xx_need_reset_handler(scsi_qla_host_t *vha)
3446 {
3447 uint32_t dev_state, drv_state, drv_active;
3448 unsigned long reset_timeout;
3449 struct qla_hw_data *ha = vha->hw;
3450 struct req_que *req = ha->req_q_map[0];
3451
3452 if (vha->flags.online) {
3453 qla82xx_idc_unlock(ha);
3454 qla2x00_abort_isp_cleanup(vha);
3455 ha->isp_ops->get_flash_version(vha, req->ring);
3456 ha->isp_ops->nvram_config(vha);
3457 qla82xx_idc_lock(ha);
3458 }
3459
3460 qla82xx_set_rst_ready(ha);
3461
3462 /* wait for 10 seconds for reset ack from all functions */
3463 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
3464
3465 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3466 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3467
3468 while (drv_state != drv_active) {
3469 if (time_after_eq(jiffies, reset_timeout)) {
3470 qla_printk(KERN_INFO, ha,
3471 "%s: RESET TIMEOUT!\n", QLA2XXX_DRIVER_NAME);
3472 break;
3473 }
3474 qla82xx_idc_unlock(ha);
3475 msleep(1000);
3476 qla82xx_idc_lock(ha);
3477 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3478 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3479 }
3480
3481 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3482 qla_printk(KERN_INFO, ha, "3:Device state is 0x%x = %s\n", dev_state,
3483 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
3484
3485 /* Force to DEV_COLD unless someone else is starting a reset */
3486 if (dev_state != QLA82XX_DEV_INITIALIZING) {
3487 qla_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
3488 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD);
3489 }
3490 }
3491
3492 int
qla82xx_check_fw_alive(scsi_qla_host_t * vha)3493 qla82xx_check_fw_alive(scsi_qla_host_t *vha)
3494 {
3495 uint32_t fw_heartbeat_counter;
3496 int status = 0;
3497
3498 fw_heartbeat_counter = qla82xx_rd_32(vha->hw,
3499 QLA82XX_PEG_ALIVE_COUNTER);
3500 /* all 0xff, assume AER/EEH in progress, ignore */
3501 if (fw_heartbeat_counter == 0xffffffff)
3502 return status;
3503 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
3504 vha->seconds_since_last_heartbeat++;
3505 /* FW not alive after 2 seconds */
3506 if (vha->seconds_since_last_heartbeat == 2) {
3507 vha->seconds_since_last_heartbeat = 0;
3508 status = 1;
3509 }
3510 } else
3511 vha->seconds_since_last_heartbeat = 0;
3512 vha->fw_heartbeat_counter = fw_heartbeat_counter;
3513 return status;
3514 }
3515
3516 /*
3517 * qla82xx_device_state_handler
3518 * Main state handler
3519 *
3520 * Note:
3521 * IDC lock must be held upon entry
3522 *
3523 * Return:
3524 * Success : 0
3525 * Failed : 1
3526 */
3527 int
qla82xx_device_state_handler(scsi_qla_host_t * vha)3528 qla82xx_device_state_handler(scsi_qla_host_t *vha)
3529 {
3530 uint32_t dev_state;
3531 int rval = QLA_SUCCESS;
3532 unsigned long dev_init_timeout;
3533 struct qla_hw_data *ha = vha->hw;
3534
3535 qla82xx_idc_lock(ha);
3536 if (!vha->flags.init_done)
3537 qla82xx_set_drv_active(vha);
3538
3539 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3540 qla_printk(KERN_INFO, ha, "1:Device state is 0x%x = %s\n", dev_state,
3541 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
3542
3543 /* wait for 30 seconds for device to go ready */
3544 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
3545
3546 while (1) {
3547
3548 if (time_after_eq(jiffies, dev_init_timeout)) {
3549 DEBUG(qla_printk(KERN_INFO, ha,
3550 "%s: device init failed!\n",
3551 QLA2XXX_DRIVER_NAME));
3552 rval = QLA_FUNCTION_FAILED;
3553 break;
3554 }
3555 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3556 qla_printk(KERN_INFO, ha,
3557 "2:Device state is 0x%x = %s\n", dev_state,
3558 dev_state < MAX_STATES ?
3559 qdev_state[dev_state] : "Unknown");
3560
3561 switch (dev_state) {
3562 case QLA82XX_DEV_READY:
3563 goto exit;
3564 case QLA82XX_DEV_COLD:
3565 rval = qla82xx_device_bootstrap(vha);
3566 goto exit;
3567 case QLA82XX_DEV_INITIALIZING:
3568 qla82xx_idc_unlock(ha);
3569 msleep(1000);
3570 qla82xx_idc_lock(ha);
3571 break;
3572 case QLA82XX_DEV_NEED_RESET:
3573 qla82xx_need_reset_handler(vha);
3574 dev_init_timeout = jiffies +
3575 (ha->nx_dev_init_timeout * HZ);
3576 break;
3577 case QLA82XX_DEV_NEED_QUIESCENT:
3578 qla82xx_need_qsnt_handler(vha);
3579 /* Reset timeout value after quiescence handler */
3580 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\
3581 * HZ);
3582 break;
3583 case QLA82XX_DEV_QUIESCENT:
3584 /* Owner will exit and other will wait for the state
3585 * to get changed
3586 */
3587 if (ha->flags.quiesce_owner)
3588 goto exit;
3589
3590 qla82xx_idc_unlock(ha);
3591 msleep(1000);
3592 qla82xx_idc_lock(ha);
3593
3594 /* Reset timeout value after quiescence handler */
3595 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout\
3596 * HZ);
3597 break;
3598 case QLA82XX_DEV_FAILED:
3599 qla82xx_dev_failed_handler(vha);
3600 rval = QLA_FUNCTION_FAILED;
3601 goto exit;
3602 default:
3603 qla82xx_idc_unlock(ha);
3604 msleep(1000);
3605 qla82xx_idc_lock(ha);
3606 }
3607 }
3608 exit:
3609 qla82xx_idc_unlock(ha);
3610 return rval;
3611 }
3612
qla82xx_watchdog(scsi_qla_host_t * vha)3613 void qla82xx_watchdog(scsi_qla_host_t *vha)
3614 {
3615 uint32_t dev_state, halt_status;
3616 struct qla_hw_data *ha = vha->hw;
3617
3618 /* don't poll if reset is going on */
3619 if (!ha->flags.isp82xx_reset_hdlr_active) {
3620 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3621 if (dev_state == QLA82XX_DEV_NEED_RESET &&
3622 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
3623 qla_printk(KERN_WARNING, ha,
3624 "%s(): Adapter reset needed!\n", __func__);
3625 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3626 qla2xxx_wake_dpc(vha);
3627 } else if (dev_state == QLA82XX_DEV_NEED_QUIESCENT &&
3628 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
3629 DEBUG(qla_printk(KERN_INFO, ha,
3630 "scsi(%ld) %s - detected quiescence needed\n",
3631 vha->host_no, __func__));
3632 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
3633 qla2xxx_wake_dpc(vha);
3634 } else {
3635 qla82xx_check_fw_alive(vha);
3636 if (qla82xx_check_fw_alive(vha)) {
3637 halt_status = qla82xx_rd_32(ha,
3638 QLA82XX_PEG_HALT_STATUS1);
3639 if (halt_status & HALT_STATUS_UNRECOVERABLE) {
3640 set_bit(ISP_UNRECOVERABLE,
3641 &vha->dpc_flags);
3642 } else {
3643 qla_printk(KERN_INFO, ha,
3644 "scsi(%ld): %s - detect abort needed\n",
3645 vha->host_no, __func__);
3646 set_bit(ISP_ABORT_NEEDED,
3647 &vha->dpc_flags);
3648 }
3649 qla2xxx_wake_dpc(vha);
3650 ha->flags.isp82xx_fw_hung = 1;
3651 if (ha->flags.mbox_busy) {
3652 ha->flags.mbox_int = 1;
3653 DEBUG2(qla_printk(KERN_ERR, ha,
3654 "Due to fw hung, doing premature "
3655 "completion of mbx command\n"));
3656 if (test_bit(MBX_INTR_WAIT,
3657 &ha->mbx_cmd_flags))
3658 complete(&ha->mbx_intr_comp);
3659 }
3660 }
3661 }
3662 }
3663 }
3664
qla82xx_load_risc(scsi_qla_host_t * vha,uint32_t * srisc_addr)3665 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
3666 {
3667 int rval;
3668 rval = qla82xx_device_state_handler(vha);
3669 return rval;
3670 }
3671
3672 /*
3673 * qla82xx_abort_isp
3674 * Resets ISP and aborts all outstanding commands.
3675 *
3676 * Input:
3677 * ha = adapter block pointer.
3678 *
3679 * Returns:
3680 * 0 = success
3681 */
3682 int
qla82xx_abort_isp(scsi_qla_host_t * vha)3683 qla82xx_abort_isp(scsi_qla_host_t *vha)
3684 {
3685 int rval;
3686 struct qla_hw_data *ha = vha->hw;
3687 uint32_t dev_state;
3688
3689 if (vha->device_flags & DFLG_DEV_FAILED) {
3690 qla_printk(KERN_WARNING, ha,
3691 "%s(%ld): Device in failed state, "
3692 "Exiting.\n", __func__, vha->host_no);
3693 return QLA_SUCCESS;
3694 }
3695 ha->flags.isp82xx_reset_hdlr_active = 1;
3696
3697 qla82xx_idc_lock(ha);
3698 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3699 if (dev_state == QLA82XX_DEV_READY) {
3700 qla_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
3701 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3702 QLA82XX_DEV_NEED_RESET);
3703 } else
3704 qla_printk(KERN_INFO, ha, "HW State: %s\n",
3705 dev_state < MAX_STATES ?
3706 qdev_state[dev_state] : "Unknown");
3707 qla82xx_idc_unlock(ha);
3708
3709 rval = qla82xx_device_state_handler(vha);
3710
3711 qla82xx_idc_lock(ha);
3712 qla82xx_clear_rst_ready(ha);
3713 qla82xx_idc_unlock(ha);
3714
3715 if (rval == QLA_SUCCESS) {
3716 ha->flags.isp82xx_fw_hung = 0;
3717 ha->flags.isp82xx_reset_hdlr_active = 0;
3718 qla82xx_restart_isp(vha);
3719 }
3720
3721 if (rval) {
3722 vha->flags.online = 1;
3723 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
3724 if (ha->isp_abort_cnt == 0) {
3725 qla_printk(KERN_WARNING, ha,
3726 "ISP error recovery failed - "
3727 "board disabled\n");
3728 /*
3729 * The next call disables the board
3730 * completely.
3731 */
3732 ha->isp_ops->reset_adapter(vha);
3733 vha->flags.online = 0;
3734 clear_bit(ISP_ABORT_RETRY,
3735 &vha->dpc_flags);
3736 rval = QLA_SUCCESS;
3737 } else { /* schedule another ISP abort */
3738 ha->isp_abort_cnt--;
3739 DEBUG(qla_printk(KERN_INFO, ha,
3740 "qla%ld: ISP abort - retry remaining %d\n",
3741 vha->host_no, ha->isp_abort_cnt));
3742 rval = QLA_FUNCTION_FAILED;
3743 }
3744 } else {
3745 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
3746 DEBUG(qla_printk(KERN_INFO, ha,
3747 "(%ld): ISP error recovery - retrying (%d) "
3748 "more times\n", vha->host_no, ha->isp_abort_cnt));
3749 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3750 rval = QLA_FUNCTION_FAILED;
3751 }
3752 }
3753 return rval;
3754 }
3755
3756 /*
3757 * qla82xx_fcoe_ctx_reset
3758 * Perform a quick reset and aborts all outstanding commands.
3759 * This will only perform an FCoE context reset and avoids a full blown
3760 * chip reset.
3761 *
3762 * Input:
3763 * ha = adapter block pointer.
3764 * is_reset_path = flag for identifying the reset path.
3765 *
3766 * Returns:
3767 * 0 = success
3768 */
qla82xx_fcoe_ctx_reset(scsi_qla_host_t * vha)3769 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha)
3770 {
3771 int rval = QLA_FUNCTION_FAILED;
3772
3773 if (vha->flags.online) {
3774 /* Abort all outstanding commands, so as to be requeued later */
3775 qla2x00_abort_isp_cleanup(vha);
3776 }
3777
3778 /* Stop currently executing firmware.
3779 * This will destroy existing FCoE context at the F/W end.
3780 */
3781 qla2x00_try_to_stop_firmware(vha);
3782
3783 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3784 rval = qla82xx_restart_isp(vha);
3785
3786 return rval;
3787 }
3788
3789 /*
3790 * qla2x00_wait_for_fcoe_ctx_reset
3791 * Wait till the FCoE context is reset.
3792 *
3793 * Note:
3794 * Does context switching here.
3795 * Release SPIN_LOCK (if any) before calling this routine.
3796 *
3797 * Return:
3798 * Success (fcoe_ctx reset is done) : 0
3799 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1
3800 */
qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t * vha)3801 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha)
3802 {
3803 int status = QLA_FUNCTION_FAILED;
3804 unsigned long wait_reset;
3805
3806 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
3807 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
3808 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
3809 && time_before(jiffies, wait_reset)) {
3810
3811 set_current_state(TASK_UNINTERRUPTIBLE);
3812 schedule_timeout(HZ);
3813
3814 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) &&
3815 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
3816 status = QLA_SUCCESS;
3817 break;
3818 }
3819 }
3820 DEBUG2(printk(KERN_INFO
3821 "%s status=%d\n", __func__, status));
3822
3823 return status;
3824 }
3825
3826 void
qla82xx_chip_reset_cleanup(scsi_qla_host_t * vha)3827 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha)
3828 {
3829 int i;
3830 unsigned long flags;
3831 struct qla_hw_data *ha = vha->hw;
3832
3833 /* Check if 82XX firmware is alive or not
3834 * We may have arrived here from NEED_RESET
3835 * detection only
3836 */
3837 if (!ha->flags.isp82xx_fw_hung) {
3838 for (i = 0; i < 2; i++) {
3839 msleep(1000);
3840 if (qla82xx_check_fw_alive(vha)) {
3841 ha->flags.isp82xx_fw_hung = 1;
3842 if (ha->flags.mbox_busy) {
3843 ha->flags.mbox_int = 1;
3844 complete(&ha->mbx_intr_comp);
3845 }
3846 break;
3847 }
3848 }
3849 }
3850
3851 /* Abort all commands gracefully if fw NOT hung */
3852 if (!ha->flags.isp82xx_fw_hung) {
3853 int cnt, que;
3854 srb_t *sp;
3855 struct req_que *req;
3856
3857 spin_lock_irqsave(&ha->hardware_lock, flags);
3858 for (que = 0; que < ha->max_req_queues; que++) {
3859 req = ha->req_q_map[que];
3860 if (!req)
3861 continue;
3862 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
3863 sp = req->outstanding_cmds[cnt];
3864 if (sp) {
3865 if (!sp->ctx ||
3866 (sp->flags & SRB_FCP_CMND_DMA_VALID)) {
3867 spin_unlock_irqrestore(
3868 &ha->hardware_lock, flags);
3869 if (ha->isp_ops->abort_command(sp)) {
3870 qla_printk(KERN_INFO, ha,
3871 "scsi(%ld): mbx abort command failed in %s\n",
3872 vha->host_no, __func__);
3873 } else {
3874 qla_printk(KERN_INFO, ha,
3875 "scsi(%ld): mbx abort command success in %s\n",
3876 vha->host_no, __func__);
3877 }
3878 spin_lock_irqsave(&ha->hardware_lock, flags);
3879 }
3880 }
3881 }
3882 }
3883 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3884
3885 /* Wait for pending cmds (physical and virtual) to complete */
3886 if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
3887 WAIT_HOST) == QLA_SUCCESS) {
3888 DEBUG2(qla_printk(KERN_INFO, ha,
3889 "Done wait for pending commands\n"));
3890 }
3891 }
3892 }
3893