1 /* 2 * Copyright (c) 2000-2010 LSI Corporation. 3 * 4 * 5 * Name: mpi2_ioc.h 6 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 7 * Creation Date: October 11, 2006 8 * 9 * mpi2_ioc.h Version: 02.00.15 10 * 11 * Version History 12 * --------------- 13 * 14 * Date Version Description 15 * -------- -------- ------------------------------------------------------ 16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 17 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to 18 * MaxTargets. 19 * Added TotalImageSize field to FWDownload Request. 20 * Added reserved words to FWUpload Request. 21 * 06-26-07 02.00.02 Added IR Configuration Change List Event. 22 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit 23 * request and replaced it with 24 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth. 25 * Replaced the MinReplyQueueDepth field of the IOCFacts 26 * reply with MaxReplyDescriptorPostQueueDepth. 27 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum 28 * depth for the Reply Descriptor Post Queue. 29 * Added SASAddress field to Initiator Device Table 30 * Overflow Event data. 31 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING 32 * for SAS Initiator Device Status Change Event data. 33 * Modified Reason Code defines for SAS Topology Change 34 * List Event data, including adding a bit for PHY Vacant 35 * status, and adding a mask for the Reason Code. 36 * Added define for 37 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING. 38 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID. 39 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of 40 * the IOCFacts Reply. 41 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 42 * Moved MPI2_VERSION_UNION to mpi2.h. 43 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks 44 * instead of enables, and added SASBroadcastPrimitiveMasks 45 * field. 46 * Added Log Entry Added Event and related structure. 47 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID. 48 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET. 49 * Added MaxVolumes and MaxPersistentEntries fields to 50 * IOCFacts reply. 51 * Added ProtocalFlags and IOCCapabilities fields to 52 * MPI2_FW_IMAGE_HEADER. 53 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT. 54 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to 55 * a U16 (from a U32). 56 * Removed extra 's' from EventMasks name. 57 * 06-27-08 02.00.08 Fixed an offset in a comment. 58 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST. 59 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and 60 * renamed MinReplyFrameSize to ReplyFrameSize. 61 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX. 62 * Added two new RAIDOperation values for Integrated RAID 63 * Operations Status Event data. 64 * Added four new IR Configuration Change List Event data 65 * ReasonCode values. 66 * Added two new ReasonCode defines for SAS Device Status 67 * Change Event data. 68 * Added three new DiscoveryStatus bits for the SAS 69 * Discovery event data. 70 * Added Multiplexing Status Change bit to the PhyStatus 71 * field of the SAS Topology Change List event data. 72 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY. 73 * BootFlags are now product-specific. 74 * Added defines for the indivdual signature bytes 75 * for MPI2_INIT_IMAGE_FOOTER. 76 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define. 77 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR 78 * define. 79 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE 80 * define. 81 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define. 82 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define. 83 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define. 84 * Added two new reason codes for SAS Device Status Change 85 * Event. 86 * Added new event: SAS PHY Counter. 87 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure. 88 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 89 * Added new product id family for 2208. 90 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST. 91 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY. 92 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY. 93 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY. 94 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define. 95 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define. 96 * Added Host Based Discovery Phy Event data. 97 * Added defines for ProductID Product field 98 * (MPI2_FW_HEADER_PID_). 99 * Modified values for SAS ProductID Family 100 * (MPI2_FW_HEADER_PID_FAMILY_). 101 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines. 102 * Added PowerManagementControl Request structures and 103 * defines. 104 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete. 105 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define. 106 * -------------------------------------------------------------------------- 107 */ 108 109 #ifndef MPI2_IOC_H 110 #define MPI2_IOC_H 111 112 /***************************************************************************** 113 * 114 * IOC Messages 115 * 116 *****************************************************************************/ 117 118 /**************************************************************************** 119 * IOCInit message 120 ****************************************************************************/ 121 122 /* IOCInit Request message */ 123 typedef struct _MPI2_IOC_INIT_REQUEST 124 { 125 U8 WhoInit; /* 0x00 */ 126 U8 Reserved1; /* 0x01 */ 127 U8 ChainOffset; /* 0x02 */ 128 U8 Function; /* 0x03 */ 129 U16 Reserved2; /* 0x04 */ 130 U8 Reserved3; /* 0x06 */ 131 U8 MsgFlags; /* 0x07 */ 132 U8 VP_ID; /* 0x08 */ 133 U8 VF_ID; /* 0x09 */ 134 U16 Reserved4; /* 0x0A */ 135 U16 MsgVersion; /* 0x0C */ 136 U16 HeaderVersion; /* 0x0E */ 137 U32 Reserved5; /* 0x10 */ 138 U16 Reserved6; /* 0x14 */ 139 U8 Reserved7; /* 0x16 */ 140 U8 HostMSIxVectors; /* 0x17 */ 141 U16 Reserved8; /* 0x18 */ 142 U16 SystemRequestFrameSize; /* 0x1A */ 143 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */ 144 U16 ReplyFreeQueueDepth; /* 0x1E */ 145 U32 SenseBufferAddressHigh; /* 0x20 */ 146 U32 SystemReplyAddressHigh; /* 0x24 */ 147 U64 SystemRequestFrameBaseAddress; /* 0x28 */ 148 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */ 149 U64 ReplyFreeQueueAddress; /* 0x38 */ 150 U64 TimeStamp; /* 0x40 */ 151 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 152 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 153 154 /* WhoInit values */ 155 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 156 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 157 #define MPI2_WHOINIT_ROM_BIOS (0x02) 158 #define MPI2_WHOINIT_PCI_PEER (0x03) 159 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 160 #define MPI2_WHOINIT_MANUFACTURER (0x05) 161 162 /* MsgVersion */ 163 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00) 164 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8) 165 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF) 166 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0) 167 168 /* HeaderVersion */ 169 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00) 170 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8) 171 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF) 172 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0) 173 174 /* minimum depth for the Reply Descriptor Post Queue */ 175 #define MPI2_RDPQ_DEPTH_MIN (16) 176 177 178 /* IOCInit Reply message */ 179 typedef struct _MPI2_IOC_INIT_REPLY 180 { 181 U8 WhoInit; /* 0x00 */ 182 U8 Reserved1; /* 0x01 */ 183 U8 MsgLength; /* 0x02 */ 184 U8 Function; /* 0x03 */ 185 U16 Reserved2; /* 0x04 */ 186 U8 Reserved3; /* 0x06 */ 187 U8 MsgFlags; /* 0x07 */ 188 U8 VP_ID; /* 0x08 */ 189 U8 VF_ID; /* 0x09 */ 190 U16 Reserved4; /* 0x0A */ 191 U16 Reserved5; /* 0x0C */ 192 U16 IOCStatus; /* 0x0E */ 193 U32 IOCLogInfo; /* 0x10 */ 194 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY, 195 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t; 196 197 198 /**************************************************************************** 199 * IOCFacts message 200 ****************************************************************************/ 201 202 /* IOCFacts Request message */ 203 typedef struct _MPI2_IOC_FACTS_REQUEST 204 { 205 U16 Reserved1; /* 0x00 */ 206 U8 ChainOffset; /* 0x02 */ 207 U8 Function; /* 0x03 */ 208 U16 Reserved2; /* 0x04 */ 209 U8 Reserved3; /* 0x06 */ 210 U8 MsgFlags; /* 0x07 */ 211 U8 VP_ID; /* 0x08 */ 212 U8 VF_ID; /* 0x09 */ 213 U16 Reserved4; /* 0x0A */ 214 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST, 215 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t; 216 217 218 /* IOCFacts Reply message */ 219 typedef struct _MPI2_IOC_FACTS_REPLY 220 { 221 U16 MsgVersion; /* 0x00 */ 222 U8 MsgLength; /* 0x02 */ 223 U8 Function; /* 0x03 */ 224 U16 HeaderVersion; /* 0x04 */ 225 U8 IOCNumber; /* 0x06 */ 226 U8 MsgFlags; /* 0x07 */ 227 U8 VP_ID; /* 0x08 */ 228 U8 VF_ID; /* 0x09 */ 229 U16 Reserved1; /* 0x0A */ 230 U16 IOCExceptions; /* 0x0C */ 231 U16 IOCStatus; /* 0x0E */ 232 U32 IOCLogInfo; /* 0x10 */ 233 U8 MaxChainDepth; /* 0x14 */ 234 U8 WhoInit; /* 0x15 */ 235 U8 NumberOfPorts; /* 0x16 */ 236 U8 MaxMSIxVectors; /* 0x17 */ 237 U16 RequestCredit; /* 0x18 */ 238 U16 ProductID; /* 0x1A */ 239 U32 IOCCapabilities; /* 0x1C */ 240 MPI2_VERSION_UNION FWVersion; /* 0x20 */ 241 U16 IOCRequestFrameSize; /* 0x24 */ 242 U16 Reserved3; /* 0x26 */ 243 U16 MaxInitiators; /* 0x28 */ 244 U16 MaxTargets; /* 0x2A */ 245 U16 MaxSasExpanders; /* 0x2C */ 246 U16 MaxEnclosures; /* 0x2E */ 247 U16 ProtocolFlags; /* 0x30 */ 248 U16 HighPriorityCredit; /* 0x32 */ 249 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */ 250 U8 ReplyFrameSize; /* 0x36 */ 251 U8 MaxVolumes; /* 0x37 */ 252 U16 MaxDevHandle; /* 0x38 */ 253 U16 MaxPersistentEntries; /* 0x3A */ 254 U16 MinDevHandle; /* 0x3C */ 255 U16 Reserved4; /* 0x3E */ 256 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY, 257 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t; 258 259 /* MsgVersion */ 260 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 261 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8) 262 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 263 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0) 264 265 /* HeaderVersion */ 266 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00) 267 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8) 268 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF) 269 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0) 270 271 /* IOCExceptions */ 272 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100) 273 274 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0) 275 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000) 276 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020) 277 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040) 278 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060) 279 280 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010) 281 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008) 282 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004) 283 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) 284 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 285 286 /* defines for WhoInit field are after the IOCInit Request */ 287 288 /* ProductID field uses MPI2_FW_HEADER_PID_ */ 289 290 /* IOCCapabilities */ 291 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000) 292 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000) 293 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000) 294 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000) 295 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000) 296 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800) 297 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) 298 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080) 299 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040) 300 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020) 301 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) 302 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) 303 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004) 304 305 /* ProtocolFlags */ 306 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 307 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 308 309 310 /**************************************************************************** 311 * PortFacts message 312 ****************************************************************************/ 313 314 /* PortFacts Request message */ 315 typedef struct _MPI2_PORT_FACTS_REQUEST 316 { 317 U16 Reserved1; /* 0x00 */ 318 U8 ChainOffset; /* 0x02 */ 319 U8 Function; /* 0x03 */ 320 U16 Reserved2; /* 0x04 */ 321 U8 PortNumber; /* 0x06 */ 322 U8 MsgFlags; /* 0x07 */ 323 U8 VP_ID; /* 0x08 */ 324 U8 VF_ID; /* 0x09 */ 325 U16 Reserved3; /* 0x0A */ 326 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST, 327 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t; 328 329 /* PortFacts Reply message */ 330 typedef struct _MPI2_PORT_FACTS_REPLY 331 { 332 U16 Reserved1; /* 0x00 */ 333 U8 MsgLength; /* 0x02 */ 334 U8 Function; /* 0x03 */ 335 U16 Reserved2; /* 0x04 */ 336 U8 PortNumber; /* 0x06 */ 337 U8 MsgFlags; /* 0x07 */ 338 U8 VP_ID; /* 0x08 */ 339 U8 VF_ID; /* 0x09 */ 340 U16 Reserved3; /* 0x0A */ 341 U16 Reserved4; /* 0x0C */ 342 U16 IOCStatus; /* 0x0E */ 343 U32 IOCLogInfo; /* 0x10 */ 344 U8 Reserved5; /* 0x14 */ 345 U8 PortType; /* 0x15 */ 346 U16 Reserved6; /* 0x16 */ 347 U16 MaxPostedCmdBuffers; /* 0x18 */ 348 U16 Reserved7; /* 0x1A */ 349 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY, 350 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t; 351 352 /* PortType values */ 353 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00) 354 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10) 355 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20) 356 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) 357 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) 358 359 360 /**************************************************************************** 361 * PortEnable message 362 ****************************************************************************/ 363 364 /* PortEnable Request message */ 365 typedef struct _MPI2_PORT_ENABLE_REQUEST 366 { 367 U16 Reserved1; /* 0x00 */ 368 U8 ChainOffset; /* 0x02 */ 369 U8 Function; /* 0x03 */ 370 U8 Reserved2; /* 0x04 */ 371 U8 PortFlags; /* 0x05 */ 372 U8 Reserved3; /* 0x06 */ 373 U8 MsgFlags; /* 0x07 */ 374 U8 VP_ID; /* 0x08 */ 375 U8 VF_ID; /* 0x09 */ 376 U16 Reserved4; /* 0x0A */ 377 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST, 378 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t; 379 380 381 /* PortEnable Reply message */ 382 typedef struct _MPI2_PORT_ENABLE_REPLY 383 { 384 U16 Reserved1; /* 0x00 */ 385 U8 MsgLength; /* 0x02 */ 386 U8 Function; /* 0x03 */ 387 U8 Reserved2; /* 0x04 */ 388 U8 PortFlags; /* 0x05 */ 389 U8 Reserved3; /* 0x06 */ 390 U8 MsgFlags; /* 0x07 */ 391 U8 VP_ID; /* 0x08 */ 392 U8 VF_ID; /* 0x09 */ 393 U16 Reserved4; /* 0x0A */ 394 U16 Reserved5; /* 0x0C */ 395 U16 IOCStatus; /* 0x0E */ 396 U32 IOCLogInfo; /* 0x10 */ 397 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY, 398 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t; 399 400 401 /**************************************************************************** 402 * EventNotification message 403 ****************************************************************************/ 404 405 /* EventNotification Request message */ 406 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4) 407 408 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST 409 { 410 U16 Reserved1; /* 0x00 */ 411 U8 ChainOffset; /* 0x02 */ 412 U8 Function; /* 0x03 */ 413 U16 Reserved2; /* 0x04 */ 414 U8 Reserved3; /* 0x06 */ 415 U8 MsgFlags; /* 0x07 */ 416 U8 VP_ID; /* 0x08 */ 417 U8 VF_ID; /* 0x09 */ 418 U16 Reserved4; /* 0x0A */ 419 U32 Reserved5; /* 0x0C */ 420 U32 Reserved6; /* 0x10 */ 421 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */ 422 U16 SASBroadcastPrimitiveMasks; /* 0x24 */ 423 U16 Reserved7; /* 0x26 */ 424 U32 Reserved8; /* 0x28 */ 425 } MPI2_EVENT_NOTIFICATION_REQUEST, 426 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST, 427 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t; 428 429 430 /* EventNotification Reply message */ 431 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY 432 { 433 U16 EventDataLength; /* 0x00 */ 434 U8 MsgLength; /* 0x02 */ 435 U8 Function; /* 0x03 */ 436 U16 Reserved1; /* 0x04 */ 437 U8 AckRequired; /* 0x06 */ 438 U8 MsgFlags; /* 0x07 */ 439 U8 VP_ID; /* 0x08 */ 440 U8 VF_ID; /* 0x09 */ 441 U16 Reserved2; /* 0x0A */ 442 U16 Reserved3; /* 0x0C */ 443 U16 IOCStatus; /* 0x0E */ 444 U32 IOCLogInfo; /* 0x10 */ 445 U16 Event; /* 0x14 */ 446 U16 Reserved4; /* 0x16 */ 447 U32 EventContext; /* 0x18 */ 448 U32 EventData[1]; /* 0x1C */ 449 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY, 450 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t; 451 452 /* AckRequired */ 453 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 454 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 455 456 /* Event */ 457 #define MPI2_EVENT_LOG_DATA (0x0001) 458 #define MPI2_EVENT_STATE_CHANGE (0x0002) 459 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005) 460 #define MPI2_EVENT_EVENT_CHANGE (0x000A) 461 #define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */ 462 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F) 463 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014) 464 #define MPI2_EVENT_SAS_DISCOVERY (0x0016) 465 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017) 466 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018) 467 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019) 468 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C) 469 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D) 470 #define MPI2_EVENT_IR_VOLUME (0x001E) 471 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F) 472 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020) 473 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021) 474 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022) 475 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023) 476 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024) 477 #define MPI2_EVENT_SAS_QUIESCE (0x0025) 478 479 480 /* Log Entry Added Event data */ 481 482 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */ 483 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C) 484 485 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED 486 { 487 U64 TimeStamp; /* 0x00 */ 488 U32 Reserved1; /* 0x08 */ 489 U16 LogSequence; /* 0x0C */ 490 U16 LogEntryQualifier; /* 0x0E */ 491 U8 VP_ID; /* 0x10 */ 492 U8 VF_ID; /* 0x11 */ 493 U16 Reserved2; /* 0x12 */ 494 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */ 495 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 496 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 497 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t; 498 499 /* GPIO Interrupt Event data */ 500 501 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT { 502 U8 GPIONum; /* 0x00 */ 503 U8 Reserved1; /* 0x01 */ 504 U16 Reserved2; /* 0x02 */ 505 } MPI2_EVENT_DATA_GPIO_INTERRUPT, 506 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT, 507 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t; 508 509 /* Hard Reset Received Event data */ 510 511 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED 512 { 513 U8 Reserved1; /* 0x00 */ 514 U8 Port; /* 0x01 */ 515 U16 Reserved2; /* 0x02 */ 516 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 517 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 518 Mpi2EventDataHardResetReceived_t, 519 MPI2_POINTER pMpi2EventDataHardResetReceived_t; 520 521 /* Task Set Full Event data */ 522 /* this event is obsolete */ 523 524 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL 525 { 526 U16 DevHandle; /* 0x00 */ 527 U16 CurrentDepth; /* 0x02 */ 528 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL, 529 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t; 530 531 532 /* SAS Device Status Change Event data */ 533 534 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE 535 { 536 U16 TaskTag; /* 0x00 */ 537 U8 ReasonCode; /* 0x02 */ 538 U8 Reserved1; /* 0x03 */ 539 U8 ASC; /* 0x04 */ 540 U8 ASCQ; /* 0x05 */ 541 U16 DevHandle; /* 0x06 */ 542 U32 Reserved2; /* 0x08 */ 543 U64 SASAddress; /* 0x0C */ 544 U8 LUN[8]; /* 0x14 */ 545 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 546 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 547 Mpi2EventDataSasDeviceStatusChange_t, 548 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t; 549 550 /* SAS Device Status Change Event data ReasonCode values */ 551 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05) 552 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07) 553 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 554 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 555 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 556 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 557 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 558 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 559 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) 560 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) 561 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10) 562 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11) 563 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12) 564 565 566 /* Integrated RAID Operation Status Event data */ 567 568 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS 569 { 570 U16 VolDevHandle; /* 0x00 */ 571 U16 Reserved1; /* 0x02 */ 572 U8 RAIDOperation; /* 0x04 */ 573 U8 PercentComplete; /* 0x05 */ 574 U16 Reserved2; /* 0x06 */ 575 U32 Resereved3; /* 0x08 */ 576 } MPI2_EVENT_DATA_IR_OPERATION_STATUS, 577 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS, 578 Mpi2EventDataIrOperationStatus_t, 579 MPI2_POINTER pMpi2EventDataIrOperationStatus_t; 580 581 /* Integrated RAID Operation Status Event data RAIDOperation values */ 582 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00) 583 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01) 584 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02) 585 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03) 586 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04) 587 588 589 /* Integrated RAID Volume Event data */ 590 591 typedef struct _MPI2_EVENT_DATA_IR_VOLUME 592 { 593 U16 VolDevHandle; /* 0x00 */ 594 U8 ReasonCode; /* 0x02 */ 595 U8 Reserved1; /* 0x03 */ 596 U32 NewValue; /* 0x04 */ 597 U32 PreviousValue; /* 0x08 */ 598 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME, 599 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t; 600 601 /* Integrated RAID Volume Event data ReasonCode values */ 602 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01) 603 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02) 604 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03) 605 606 607 /* Integrated RAID Physical Disk Event data */ 608 609 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK 610 { 611 U16 Reserved1; /* 0x00 */ 612 U8 ReasonCode; /* 0x02 */ 613 U8 PhysDiskNum; /* 0x03 */ 614 U16 PhysDiskDevHandle; /* 0x04 */ 615 U16 Reserved2; /* 0x06 */ 616 U16 Slot; /* 0x08 */ 617 U16 EnclosureHandle; /* 0x0A */ 618 U32 NewValue; /* 0x0C */ 619 U32 PreviousValue; /* 0x10 */ 620 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 621 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 622 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t; 623 624 /* Integrated RAID Physical Disk Event data ReasonCode values */ 625 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01) 626 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02) 627 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03) 628 629 630 /* Integrated RAID Configuration Change List Event data */ 631 632 /* 633 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 634 * one and check NumElements at runtime. 635 */ 636 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT 637 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1) 638 #endif 639 640 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT 641 { 642 U16 ElementFlags; /* 0x00 */ 643 U16 VolDevHandle; /* 0x02 */ 644 U8 ReasonCode; /* 0x04 */ 645 U8 PhysDiskNum; /* 0x05 */ 646 U16 PhysDiskDevHandle; /* 0x06 */ 647 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT, 648 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t; 649 650 /* IR Configuration Change List Event data ElementFlags values */ 651 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F) 652 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000) 653 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001) 654 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002) 655 656 /* IR Configuration Change List Event data ReasonCode values */ 657 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01) 658 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02) 659 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03) 660 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04) 661 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05) 662 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06) 663 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07) 664 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08) 665 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09) 666 667 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST 668 { 669 U8 NumElements; /* 0x00 */ 670 U8 Reserved1; /* 0x01 */ 671 U8 Reserved2; /* 0x02 */ 672 U8 ConfigNum; /* 0x03 */ 673 U32 Flags; /* 0x04 */ 674 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */ 675 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 676 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 677 Mpi2EventDataIrConfigChangeList_t, 678 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t; 679 680 /* IR Configuration Change List Event data Flags values */ 681 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001) 682 683 684 /* SAS Discovery Event data */ 685 686 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY 687 { 688 U8 Flags; /* 0x00 */ 689 U8 ReasonCode; /* 0x01 */ 690 U8 PhysicalPort; /* 0x02 */ 691 U8 Reserved1; /* 0x03 */ 692 U32 DiscoveryStatus; /* 0x04 */ 693 } MPI2_EVENT_DATA_SAS_DISCOVERY, 694 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY, 695 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t; 696 697 /* SAS Discovery Event data Flags values */ 698 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02) 699 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01) 700 701 /* SAS Discovery Event data ReasonCode values */ 702 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01) 703 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02) 704 705 /* SAS Discovery Event data DiscoveryStatus values */ 706 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 707 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000) 708 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000) 709 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 710 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000) 711 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 712 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 713 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000) 714 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 715 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800) 716 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400) 717 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200) 718 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100) 719 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080) 720 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040) 721 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020) 722 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010) 723 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004) 724 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002) 725 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001) 726 727 728 /* SAS Broadcast Primitive Event data */ 729 730 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE 731 { 732 U8 PhyNum; /* 0x00 */ 733 U8 Port; /* 0x01 */ 734 U8 PortWidth; /* 0x02 */ 735 U8 Primitive; /* 0x03 */ 736 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 737 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 738 Mpi2EventDataSasBroadcastPrimitive_t, 739 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t; 740 741 /* defines for the Primitive field */ 742 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01) 743 #define MPI2_EVENT_PRIMITIVE_SES (0x02) 744 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03) 745 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 746 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05) 747 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06) 748 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07) 749 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08) 750 751 752 /* SAS Initiator Device Status Change Event data */ 753 754 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE 755 { 756 U8 ReasonCode; /* 0x00 */ 757 U8 PhysicalPort; /* 0x01 */ 758 U16 DevHandle; /* 0x02 */ 759 U64 SASAddress; /* 0x04 */ 760 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 761 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 762 Mpi2EventDataSasInitDevStatusChange_t, 763 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t; 764 765 /* SAS Initiator Device Status Change event ReasonCode values */ 766 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01) 767 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 768 769 770 /* SAS Initiator Device Table Overflow Event data */ 771 772 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW 773 { 774 U16 MaxInit; /* 0x00 */ 775 U16 CurrentInit; /* 0x02 */ 776 U64 SASAddress; /* 0x04 */ 777 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 778 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 779 Mpi2EventDataSasInitTableOverflow_t, 780 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t; 781 782 783 /* SAS Topology Change List Event data */ 784 785 /* 786 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 787 * one and check NumEntries at runtime. 788 */ 789 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT 790 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1) 791 #endif 792 793 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY 794 { 795 U16 AttachedDevHandle; /* 0x00 */ 796 U8 LinkRate; /* 0x02 */ 797 U8 PhyStatus; /* 0x03 */ 798 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY, 799 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t; 800 801 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST 802 { 803 U16 EnclosureHandle; /* 0x00 */ 804 U16 ExpanderDevHandle; /* 0x02 */ 805 U8 NumPhys; /* 0x04 */ 806 U8 Reserved1; /* 0x05 */ 807 U16 Reserved2; /* 0x06 */ 808 U8 NumEntries; /* 0x08 */ 809 U8 StartPhyNum; /* 0x09 */ 810 U8 ExpStatus; /* 0x0A */ 811 U8 PhysicalPort; /* 0x0B */ 812 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/ 813 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 814 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 815 Mpi2EventDataSasTopologyChangeList_t, 816 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t; 817 818 /* values for the ExpStatus field */ 819 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 820 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01) 821 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 822 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 823 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 824 825 /* defines for the LinkRate field */ 826 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0) 827 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 828 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F) 829 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 830 831 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 832 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 833 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 834 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 835 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 836 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 837 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 838 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08) 839 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09) 840 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A) 841 842 /* values for the PhyStatus field */ 843 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80) 844 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10) 845 /* values for the PhyStatus ReasonCode sub-field */ 846 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F) 847 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01) 848 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02) 849 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03) 850 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04) 851 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05) 852 853 854 /* SAS Enclosure Device Status Change Event data */ 855 856 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE 857 { 858 U16 EnclosureHandle; /* 0x00 */ 859 U8 ReasonCode; /* 0x02 */ 860 U8 PhysicalPort; /* 0x03 */ 861 U64 EnclosureLogicalID; /* 0x04 */ 862 U16 NumSlots; /* 0x0C */ 863 U16 StartSlot; /* 0x0E */ 864 U32 PhyBits; /* 0x10 */ 865 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 866 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 867 Mpi2EventDataSasEnclDevStatusChange_t, 868 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t; 869 870 /* SAS Enclosure Device Status Change event ReasonCode values */ 871 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01) 872 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02) 873 874 875 /* SAS PHY Counter Event data */ 876 877 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER { 878 U64 TimeStamp; /* 0x00 */ 879 U32 Reserved1; /* 0x08 */ 880 U8 PhyEventCode; /* 0x0C */ 881 U8 PhyNum; /* 0x0D */ 882 U16 Reserved2; /* 0x0E */ 883 U32 PhyEventInfo; /* 0x10 */ 884 U8 CounterType; /* 0x14 */ 885 U8 ThresholdWindow; /* 0x15 */ 886 U8 TimeUnits; /* 0x16 */ 887 U8 Reserved3; /* 0x17 */ 888 U32 EventThreshold; /* 0x18 */ 889 U16 ThresholdFlags; /* 0x1C */ 890 U16 Reserved4; /* 0x1E */ 891 } MPI2_EVENT_DATA_SAS_PHY_COUNTER, 892 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER, 893 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t; 894 895 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the 896 * PhyEventCode field 897 * use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the 898 * CounterType field 899 * use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the 900 * TimeUnits field 901 * use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the 902 * ThresholdFlags field 903 * */ 904 905 906 /* SAS Quiesce Event data */ 907 908 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE { 909 U8 ReasonCode; /* 0x00 */ 910 U8 Reserved1; /* 0x01 */ 911 U16 Reserved2; /* 0x02 */ 912 U32 Reserved3; /* 0x04 */ 913 } MPI2_EVENT_DATA_SAS_QUIESCE, 914 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE, 915 Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t; 916 917 /* SAS Quiesce Event data ReasonCode values */ 918 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01) 919 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02) 920 921 922 /* Host Based Discovery Phy Event data */ 923 924 typedef struct _MPI2_EVENT_HBD_PHY_SAS { 925 U8 Flags; /* 0x00 */ 926 U8 NegotiatedLinkRate; /* 0x01 */ 927 U8 PhyNum; /* 0x02 */ 928 U8 PhysicalPort; /* 0x03 */ 929 U32 Reserved1; /* 0x04 */ 930 U8 InitialFrame[28]; /* 0x08 */ 931 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS, 932 Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t; 933 934 /* values for the Flags field */ 935 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02) 936 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01) 937 938 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for 939 * the NegotiatedLinkRate field */ 940 941 typedef union _MPI2_EVENT_HBD_DESCRIPTOR { 942 MPI2_EVENT_HBD_PHY_SAS Sas; 943 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR, 944 Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t; 945 946 typedef struct _MPI2_EVENT_DATA_HBD_PHY { 947 U8 DescriptorType; /* 0x00 */ 948 U8 Reserved1; /* 0x01 */ 949 U16 Reserved2; /* 0x02 */ 950 U32 Reserved3; /* 0x04 */ 951 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */ 952 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY, 953 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t; 954 955 /* values for the DescriptorType field */ 956 #define MPI2_EVENT_HBD_DT_SAS (0x01) 957 958 959 960 /**************************************************************************** 961 * EventAck message 962 ****************************************************************************/ 963 964 /* EventAck Request message */ 965 typedef struct _MPI2_EVENT_ACK_REQUEST 966 { 967 U16 Reserved1; /* 0x00 */ 968 U8 ChainOffset; /* 0x02 */ 969 U8 Function; /* 0x03 */ 970 U16 Reserved2; /* 0x04 */ 971 U8 Reserved3; /* 0x06 */ 972 U8 MsgFlags; /* 0x07 */ 973 U8 VP_ID; /* 0x08 */ 974 U8 VF_ID; /* 0x09 */ 975 U16 Reserved4; /* 0x0A */ 976 U16 Event; /* 0x0C */ 977 U16 Reserved5; /* 0x0E */ 978 U32 EventContext; /* 0x10 */ 979 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST, 980 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t; 981 982 983 /* EventAck Reply message */ 984 typedef struct _MPI2_EVENT_ACK_REPLY 985 { 986 U16 Reserved1; /* 0x00 */ 987 U8 MsgLength; /* 0x02 */ 988 U8 Function; /* 0x03 */ 989 U16 Reserved2; /* 0x04 */ 990 U8 Reserved3; /* 0x06 */ 991 U8 MsgFlags; /* 0x07 */ 992 U8 VP_ID; /* 0x08 */ 993 U8 VF_ID; /* 0x09 */ 994 U16 Reserved4; /* 0x0A */ 995 U16 Reserved5; /* 0x0C */ 996 U16 IOCStatus; /* 0x0E */ 997 U32 IOCLogInfo; /* 0x10 */ 998 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY, 999 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t; 1000 1001 1002 /**************************************************************************** 1003 * FWDownload message 1004 ****************************************************************************/ 1005 1006 /* FWDownload Request message */ 1007 typedef struct _MPI2_FW_DOWNLOAD_REQUEST 1008 { 1009 U8 ImageType; /* 0x00 */ 1010 U8 Reserved1; /* 0x01 */ 1011 U8 ChainOffset; /* 0x02 */ 1012 U8 Function; /* 0x03 */ 1013 U16 Reserved2; /* 0x04 */ 1014 U8 Reserved3; /* 0x06 */ 1015 U8 MsgFlags; /* 0x07 */ 1016 U8 VP_ID; /* 0x08 */ 1017 U8 VF_ID; /* 0x09 */ 1018 U16 Reserved4; /* 0x0A */ 1019 U32 TotalImageSize; /* 0x0C */ 1020 U32 Reserved5; /* 0x10 */ 1021 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1022 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST, 1023 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest; 1024 1025 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01) 1026 1027 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01) 1028 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02) 1029 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06) 1030 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07) 1031 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08) 1032 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09) 1033 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A) 1034 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1035 1036 /* FWDownload TransactionContext Element */ 1037 typedef struct _MPI2_FW_DOWNLOAD_TCSGE 1038 { 1039 U8 Reserved1; /* 0x00 */ 1040 U8 ContextSize; /* 0x01 */ 1041 U8 DetailsLength; /* 0x02 */ 1042 U8 Flags; /* 0x03 */ 1043 U32 Reserved2; /* 0x04 */ 1044 U32 ImageOffset; /* 0x08 */ 1045 U32 ImageSize; /* 0x0C */ 1046 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE, 1047 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t; 1048 1049 /* FWDownload Reply message */ 1050 typedef struct _MPI2_FW_DOWNLOAD_REPLY 1051 { 1052 U8 ImageType; /* 0x00 */ 1053 U8 Reserved1; /* 0x01 */ 1054 U8 MsgLength; /* 0x02 */ 1055 U8 Function; /* 0x03 */ 1056 U16 Reserved2; /* 0x04 */ 1057 U8 Reserved3; /* 0x06 */ 1058 U8 MsgFlags; /* 0x07 */ 1059 U8 VP_ID; /* 0x08 */ 1060 U8 VF_ID; /* 0x09 */ 1061 U16 Reserved4; /* 0x0A */ 1062 U16 Reserved5; /* 0x0C */ 1063 U16 IOCStatus; /* 0x0E */ 1064 U32 IOCLogInfo; /* 0x10 */ 1065 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY, 1066 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t; 1067 1068 1069 /**************************************************************************** 1070 * FWUpload message 1071 ****************************************************************************/ 1072 1073 /* FWUpload Request message */ 1074 typedef struct _MPI2_FW_UPLOAD_REQUEST 1075 { 1076 U8 ImageType; /* 0x00 */ 1077 U8 Reserved1; /* 0x01 */ 1078 U8 ChainOffset; /* 0x02 */ 1079 U8 Function; /* 0x03 */ 1080 U16 Reserved2; /* 0x04 */ 1081 U8 Reserved3; /* 0x06 */ 1082 U8 MsgFlags; /* 0x07 */ 1083 U8 VP_ID; /* 0x08 */ 1084 U8 VF_ID; /* 0x09 */ 1085 U16 Reserved4; /* 0x0A */ 1086 U32 Reserved5; /* 0x0C */ 1087 U32 Reserved6; /* 0x10 */ 1088 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1089 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST, 1090 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t; 1091 1092 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00) 1093 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 1094 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 1095 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05) 1096 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06) 1097 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07) 1098 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08) 1099 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09) 1100 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A) 1101 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1102 1103 typedef struct _MPI2_FW_UPLOAD_TCSGE 1104 { 1105 U8 Reserved1; /* 0x00 */ 1106 U8 ContextSize; /* 0x01 */ 1107 U8 DetailsLength; /* 0x02 */ 1108 U8 Flags; /* 0x03 */ 1109 U32 Reserved2; /* 0x04 */ 1110 U32 ImageOffset; /* 0x08 */ 1111 U32 ImageSize; /* 0x0C */ 1112 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE, 1113 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t; 1114 1115 /* FWUpload Reply message */ 1116 typedef struct _MPI2_FW_UPLOAD_REPLY 1117 { 1118 U8 ImageType; /* 0x00 */ 1119 U8 Reserved1; /* 0x01 */ 1120 U8 MsgLength; /* 0x02 */ 1121 U8 Function; /* 0x03 */ 1122 U16 Reserved2; /* 0x04 */ 1123 U8 Reserved3; /* 0x06 */ 1124 U8 MsgFlags; /* 0x07 */ 1125 U8 VP_ID; /* 0x08 */ 1126 U8 VF_ID; /* 0x09 */ 1127 U16 Reserved4; /* 0x0A */ 1128 U16 Reserved5; /* 0x0C */ 1129 U16 IOCStatus; /* 0x0E */ 1130 U32 IOCLogInfo; /* 0x10 */ 1131 U32 ActualImageSize; /* 0x14 */ 1132 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY, 1133 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t; 1134 1135 1136 /* FW Image Header */ 1137 typedef struct _MPI2_FW_IMAGE_HEADER 1138 { 1139 U32 Signature; /* 0x00 */ 1140 U32 Signature0; /* 0x04 */ 1141 U32 Signature1; /* 0x08 */ 1142 U32 Signature2; /* 0x0C */ 1143 MPI2_VERSION_UNION MPIVersion; /* 0x10 */ 1144 MPI2_VERSION_UNION FWVersion; /* 0x14 */ 1145 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */ 1146 MPI2_VERSION_UNION PackageVersion; /* 0x1C */ 1147 U16 VendorID; /* 0x20 */ 1148 U16 ProductID; /* 0x22 */ 1149 U16 ProtocolFlags; /* 0x24 */ 1150 U16 Reserved26; /* 0x26 */ 1151 U32 IOCCapabilities; /* 0x28 */ 1152 U32 ImageSize; /* 0x2C */ 1153 U32 NextImageHeaderOffset; /* 0x30 */ 1154 U32 Checksum; /* 0x34 */ 1155 U32 Reserved38; /* 0x38 */ 1156 U32 Reserved3C; /* 0x3C */ 1157 U32 Reserved40; /* 0x40 */ 1158 U32 Reserved44; /* 0x44 */ 1159 U32 Reserved48; /* 0x48 */ 1160 U32 Reserved4C; /* 0x4C */ 1161 U32 Reserved50; /* 0x50 */ 1162 U32 Reserved54; /* 0x54 */ 1163 U32 Reserved58; /* 0x58 */ 1164 U32 Reserved5C; /* 0x5C */ 1165 U32 Reserved60; /* 0x60 */ 1166 U32 FirmwareVersionNameWhat; /* 0x64 */ 1167 U8 FirmwareVersionName[32]; /* 0x68 */ 1168 U32 VendorNameWhat; /* 0x88 */ 1169 U8 VendorName[32]; /* 0x8C */ 1170 U32 PackageNameWhat; /* 0x88 */ 1171 U8 PackageName[32]; /* 0x8C */ 1172 U32 ReservedD0; /* 0xD0 */ 1173 U32 ReservedD4; /* 0xD4 */ 1174 U32 ReservedD8; /* 0xD8 */ 1175 U32 ReservedDC; /* 0xDC */ 1176 U32 ReservedE0; /* 0xE0 */ 1177 U32 ReservedE4; /* 0xE4 */ 1178 U32 ReservedE8; /* 0xE8 */ 1179 U32 ReservedEC; /* 0xEC */ 1180 U32 ReservedF0; /* 0xF0 */ 1181 U32 ReservedF4; /* 0xF4 */ 1182 U32 ReservedF8; /* 0xF8 */ 1183 U32 ReservedFC; /* 0xFC */ 1184 } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER, 1185 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t; 1186 1187 /* Signature field */ 1188 #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00) 1189 #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000) 1190 #define MPI2_FW_HEADER_SIGNATURE (0xEA000000) 1191 1192 /* Signature0 field */ 1193 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04) 1194 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A) 1195 1196 /* Signature1 field */ 1197 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08) 1198 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5) 1199 1200 /* Signature2 field */ 1201 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C) 1202 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA) 1203 1204 1205 /* defines for using the ProductID field */ 1206 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000) 1207 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000) 1208 1209 #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00) 1210 #define MPI2_FW_HEADER_PID_PROD_A (0x0000) 1211 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) 1212 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700) 1213 1214 1215 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF) 1216 /* SAS */ 1217 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013) 1218 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014) 1219 1220 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */ 1221 1222 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */ 1223 1224 1225 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C) 1226 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30) 1227 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64) 1228 1229 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840) 1230 1231 #define MPI2_FW_HEADER_SIZE (0x100) 1232 1233 1234 /* Extended Image Header */ 1235 typedef struct _MPI2_EXT_IMAGE_HEADER 1236 1237 { 1238 U8 ImageType; /* 0x00 */ 1239 U8 Reserved1; /* 0x01 */ 1240 U16 Reserved2; /* 0x02 */ 1241 U32 Checksum; /* 0x04 */ 1242 U32 ImageSize; /* 0x08 */ 1243 U32 NextImageHeaderOffset; /* 0x0C */ 1244 U32 PackageVersion; /* 0x10 */ 1245 U32 Reserved3; /* 0x14 */ 1246 U32 Reserved4; /* 0x18 */ 1247 U32 Reserved5; /* 0x1C */ 1248 U8 IdentifyString[32]; /* 0x20 */ 1249 } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER, 1250 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t; 1251 1252 /* useful offsets */ 1253 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00) 1254 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08) 1255 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C) 1256 1257 #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40) 1258 1259 /* defines for the ImageType field */ 1260 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) 1261 #define MPI2_EXT_IMAGE_TYPE_FW (0x01) 1262 #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03) 1263 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04) 1264 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05) 1265 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06) 1266 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07) 1267 #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08) 1268 1269 #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MEGARAID) 1270 1271 1272 1273 /* FLASH Layout Extended Image Data */ 1274 1275 /* 1276 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1277 * one and check RegionsPerLayout at runtime. 1278 */ 1279 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS 1280 #define MPI2_FLASH_NUMBER_OF_REGIONS (1) 1281 #endif 1282 1283 /* 1284 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1285 * one and check NumberOfLayouts at runtime. 1286 */ 1287 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS 1288 #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1) 1289 #endif 1290 1291 typedef struct _MPI2_FLASH_REGION 1292 { 1293 U8 RegionType; /* 0x00 */ 1294 U8 Reserved1; /* 0x01 */ 1295 U16 Reserved2; /* 0x02 */ 1296 U32 RegionOffset; /* 0x04 */ 1297 U32 RegionSize; /* 0x08 */ 1298 U32 Reserved3; /* 0x0C */ 1299 } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION, 1300 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t; 1301 1302 typedef struct _MPI2_FLASH_LAYOUT 1303 { 1304 U32 FlashSize; /* 0x00 */ 1305 U32 Reserved1; /* 0x04 */ 1306 U32 Reserved2; /* 0x08 */ 1307 U32 Reserved3; /* 0x0C */ 1308 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */ 1309 } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT, 1310 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t; 1311 1312 typedef struct _MPI2_FLASH_LAYOUT_DATA 1313 { 1314 U8 ImageRevision; /* 0x00 */ 1315 U8 Reserved1; /* 0x01 */ 1316 U8 SizeOfRegion; /* 0x02 */ 1317 U8 Reserved2; /* 0x03 */ 1318 U16 NumberOfLayouts; /* 0x04 */ 1319 U16 RegionsPerLayout; /* 0x06 */ 1320 U16 MinimumSectorAlignment; /* 0x08 */ 1321 U16 Reserved3; /* 0x0A */ 1322 U32 Reserved4; /* 0x0C */ 1323 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */ 1324 } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA, 1325 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t; 1326 1327 /* defines for the RegionType field */ 1328 #define MPI2_FLASH_REGION_UNUSED (0x00) 1329 #define MPI2_FLASH_REGION_FIRMWARE (0x01) 1330 #define MPI2_FLASH_REGION_BIOS (0x02) 1331 #define MPI2_FLASH_REGION_NVDATA (0x03) 1332 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05) 1333 #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06) 1334 #define MPI2_FLASH_REGION_CONFIG_1 (0x07) 1335 #define MPI2_FLASH_REGION_CONFIG_2 (0x08) 1336 #define MPI2_FLASH_REGION_MEGARAID (0x09) 1337 #define MPI2_FLASH_REGION_INIT (0x0A) 1338 1339 /* ImageRevision */ 1340 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00) 1341 1342 1343 1344 /* Supported Devices Extended Image Data */ 1345 1346 /* 1347 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1348 * one and check NumberOfDevices at runtime. 1349 */ 1350 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES 1351 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1) 1352 #endif 1353 1354 typedef struct _MPI2_SUPPORTED_DEVICE 1355 { 1356 U16 DeviceID; /* 0x00 */ 1357 U16 VendorID; /* 0x02 */ 1358 U16 DeviceIDMask; /* 0x04 */ 1359 U16 Reserved1; /* 0x06 */ 1360 U8 LowPCIRev; /* 0x08 */ 1361 U8 HighPCIRev; /* 0x09 */ 1362 U16 Reserved2; /* 0x0A */ 1363 U32 Reserved3; /* 0x0C */ 1364 } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE, 1365 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t; 1366 1367 typedef struct _MPI2_SUPPORTED_DEVICES_DATA 1368 { 1369 U8 ImageRevision; /* 0x00 */ 1370 U8 Reserved1; /* 0x01 */ 1371 U8 NumberOfDevices; /* 0x02 */ 1372 U8 Reserved2; /* 0x03 */ 1373 U32 Reserved3; /* 0x04 */ 1374 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */ 1375 } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA, 1376 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t; 1377 1378 /* ImageRevision */ 1379 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00) 1380 1381 1382 /* Init Extended Image Data */ 1383 1384 typedef struct _MPI2_INIT_IMAGE_FOOTER 1385 1386 { 1387 U32 BootFlags; /* 0x00 */ 1388 U32 ImageSize; /* 0x04 */ 1389 U32 Signature0; /* 0x08 */ 1390 U32 Signature1; /* 0x0C */ 1391 U32 Signature2; /* 0x10 */ 1392 U32 ResetVector; /* 0x14 */ 1393 } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER, 1394 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t; 1395 1396 /* defines for the BootFlags field */ 1397 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00) 1398 1399 /* defines for the ImageSize field */ 1400 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04) 1401 1402 /* defines for the Signature0 field */ 1403 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08) 1404 #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA) 1405 1406 /* defines for the Signature1 field */ 1407 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C) 1408 #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5) 1409 1410 /* defines for the Signature2 field */ 1411 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10) 1412 #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A) 1413 1414 /* Signature fields as individual bytes */ 1415 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA) 1416 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A) 1417 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5) 1418 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A) 1419 1420 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5) 1421 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA) 1422 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A) 1423 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5) 1424 1425 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A) 1426 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5) 1427 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA) 1428 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A) 1429 1430 /* defines for the ResetVector field */ 1431 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14) 1432 1433 1434 /**************************************************************************** 1435 * PowerManagementControl message 1436 ****************************************************************************/ 1437 1438 /* PowerManagementControl Request message */ 1439 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST { 1440 U8 Feature; /* 0x00 */ 1441 U8 Reserved1; /* 0x01 */ 1442 U8 ChainOffset; /* 0x02 */ 1443 U8 Function; /* 0x03 */ 1444 U16 Reserved2; /* 0x04 */ 1445 U8 Reserved3; /* 0x06 */ 1446 U8 MsgFlags; /* 0x07 */ 1447 U8 VP_ID; /* 0x08 */ 1448 U8 VF_ID; /* 0x09 */ 1449 U16 Reserved4; /* 0x0A */ 1450 U8 Parameter1; /* 0x0C */ 1451 U8 Parameter2; /* 0x0D */ 1452 U8 Parameter3; /* 0x0E */ 1453 U8 Parameter4; /* 0x0F */ 1454 U32 Reserved5; /* 0x10 */ 1455 U32 Reserved6; /* 0x14 */ 1456 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST, 1457 Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t; 1458 1459 /* defines for the Feature field */ 1460 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01) 1461 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02) 1462 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) 1463 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04) 1464 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80) 1465 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF) 1466 1467 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */ 1468 /* Parameter1 contains a PHY number */ 1469 /* Parameter2 indicates power condition action using these defines */ 1470 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01) 1471 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02) 1472 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03) 1473 /* Parameter3 and Parameter4 are reserved */ 1474 1475 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION 1476 * Feature */ 1477 /* Parameter1 contains SAS port width modulation group number */ 1478 /* Parameter2 indicates IOC action using these defines */ 1479 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01) 1480 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02) 1481 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03) 1482 /* Parameter3 indicates desired modulation level using these defines */ 1483 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00) 1484 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01) 1485 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02) 1486 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03) 1487 /* Parameter4 is reserved */ 1488 1489 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */ 1490 /* Parameter1 indicates desired PCIe link speed using these defines */ 1491 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) 1492 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) 1493 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) 1494 /* Parameter2 indicates desired PCIe link width using these defines */ 1495 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) 1496 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) 1497 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) 1498 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) 1499 /* Parameter3 and Parameter4 are reserved */ 1500 1501 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */ 1502 /* Parameter1 indicates desired IOC hardware clock speed using these defines */ 1503 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01) 1504 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02) 1505 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04) 1506 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08) 1507 /* Parameter2, Parameter3, and Parameter4 are reserved */ 1508 1509 1510 /* PowerManagementControl Reply message */ 1511 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY { 1512 U8 Feature; /* 0x00 */ 1513 U8 Reserved1; /* 0x01 */ 1514 U8 MsgLength; /* 0x02 */ 1515 U8 Function; /* 0x03 */ 1516 U16 Reserved2; /* 0x04 */ 1517 U8 Reserved3; /* 0x06 */ 1518 U8 MsgFlags; /* 0x07 */ 1519 U8 VP_ID; /* 0x08 */ 1520 U8 VF_ID; /* 0x09 */ 1521 U16 Reserved4; /* 0x0A */ 1522 U16 Reserved5; /* 0x0C */ 1523 U16 IOCStatus; /* 0x0E */ 1524 U32 IOCLogInfo; /* 0x10 */ 1525 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY, 1526 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t; 1527 1528 1529 #endif 1530 1531