1 /* 2 * This file is part of wl1271 3 * 4 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved. 5 * Copyright (C) 2008-2010 Nokia Corporation 6 * 7 * Contact: Luciano Coelho <luciano.coelho@nokia.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * 02110-1301 USA 22 * 23 */ 24 25 #ifndef __ACX_H__ 26 #define __ACX_H__ 27 28 #include "wl12xx.h" 29 #include "cmd.h" 30 31 /************************************************************************* 32 33 Host Interrupt Register (WiLink -> Host) 34 35 **************************************************************************/ 36 /* HW Initiated interrupt Watchdog timer expiration */ 37 #define WL1271_ACX_INTR_WATCHDOG BIT(0) 38 /* Init sequence is done (masked interrupt, detection through polling only ) */ 39 #define WL1271_ACX_INTR_INIT_COMPLETE BIT(1) 40 /* Event was entered to Event MBOX #A*/ 41 #define WL1271_ACX_INTR_EVENT_A BIT(2) 42 /* Event was entered to Event MBOX #B*/ 43 #define WL1271_ACX_INTR_EVENT_B BIT(3) 44 /* Command processing completion*/ 45 #define WL1271_ACX_INTR_CMD_COMPLETE BIT(4) 46 /* Signaling the host on HW wakeup */ 47 #define WL1271_ACX_INTR_HW_AVAILABLE BIT(5) 48 /* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */ 49 #define WL1271_ACX_INTR_DATA BIT(6) 50 /* Trace message on MBOX #A */ 51 #define WL1271_ACX_INTR_TRACE_A BIT(7) 52 /* Trace message on MBOX #B */ 53 #define WL1271_ACX_INTR_TRACE_B BIT(8) 54 55 #define WL1271_ACX_INTR_ALL 0xFFFFFFFF 56 #define WL1271_ACX_ALL_EVENTS_VECTOR (WL1271_ACX_INTR_WATCHDOG | \ 57 WL1271_ACX_INTR_INIT_COMPLETE | \ 58 WL1271_ACX_INTR_EVENT_A | \ 59 WL1271_ACX_INTR_EVENT_B | \ 60 WL1271_ACX_INTR_CMD_COMPLETE | \ 61 WL1271_ACX_INTR_HW_AVAILABLE | \ 62 WL1271_ACX_INTR_DATA) 63 64 #define WL1271_INTR_MASK (WL1271_ACX_INTR_WATCHDOG | \ 65 WL1271_ACX_INTR_EVENT_A | \ 66 WL1271_ACX_INTR_EVENT_B | \ 67 WL1271_ACX_INTR_HW_AVAILABLE | \ 68 WL1271_ACX_INTR_DATA) 69 70 /* Target's information element */ 71 struct acx_header { 72 struct wl1271_cmd_header cmd; 73 74 /* acx (or information element) header */ 75 __le16 id; 76 77 /* payload length (not including headers */ 78 __le16 len; 79 } __packed; 80 81 struct acx_error_counter { 82 struct acx_header header; 83 84 /* The number of PLCP errors since the last time this */ 85 /* information element was interrogated. This field is */ 86 /* automatically cleared when it is interrogated.*/ 87 __le32 PLCP_error; 88 89 /* The number of FCS errors since the last time this */ 90 /* information element was interrogated. This field is */ 91 /* automatically cleared when it is interrogated.*/ 92 __le32 FCS_error; 93 94 /* The number of MPDUs without PLCP header errors received*/ 95 /* since the last time this information element was interrogated. */ 96 /* This field is automatically cleared when it is interrogated.*/ 97 __le32 valid_frame; 98 99 /* the number of missed sequence numbers in the squentially */ 100 /* values of frames seq numbers */ 101 __le32 seq_num_miss; 102 } __packed; 103 104 enum wl1271_psm_mode { 105 /* Active mode */ 106 WL1271_PSM_CAM = 0, 107 108 /* Power save mode */ 109 WL1271_PSM_PS = 1, 110 111 /* Extreme low power */ 112 WL1271_PSM_ELP = 2, 113 }; 114 115 struct acx_sleep_auth { 116 struct acx_header header; 117 118 /* The sleep level authorization of the device. */ 119 /* 0 - Always active*/ 120 /* 1 - Power down mode: light / fast sleep*/ 121 /* 2 - ELP mode: Deep / Max sleep*/ 122 u8 sleep_auth; 123 u8 padding[3]; 124 } __packed; 125 126 enum { 127 HOSTIF_PCI_MASTER_HOST_INDIRECT, 128 HOSTIF_PCI_MASTER_HOST_DIRECT, 129 HOSTIF_SLAVE, 130 HOSTIF_PKT_RING, 131 HOSTIF_DONTCARE = 0xFF 132 }; 133 134 #define DEFAULT_UCAST_PRIORITY 0 135 #define DEFAULT_RX_Q_PRIORITY 0 136 #define DEFAULT_RXQ_PRIORITY 0 /* low 0 .. 15 high */ 137 #define DEFAULT_RXQ_TYPE 0x07 /* All frames, Data/Ctrl/Mgmt */ 138 #define TRACE_BUFFER_MAX_SIZE 256 139 140 #define DP_RX_PACKET_RING_CHUNK_SIZE 1600 141 #define DP_TX_PACKET_RING_CHUNK_SIZE 1600 142 #define DP_RX_PACKET_RING_CHUNK_NUM 2 143 #define DP_TX_PACKET_RING_CHUNK_NUM 2 144 #define DP_TX_COMPLETE_TIME_OUT 20 145 146 #define TX_MSDU_LIFETIME_MIN 0 147 #define TX_MSDU_LIFETIME_MAX 3000 148 #define TX_MSDU_LIFETIME_DEF 512 149 #define RX_MSDU_LIFETIME_MIN 0 150 #define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF 151 #define RX_MSDU_LIFETIME_DEF 512000 152 153 struct acx_rx_msdu_lifetime { 154 struct acx_header header; 155 156 /* 157 * The maximum amount of time, in TU, before the 158 * firmware discards the MSDU. 159 */ 160 __le32 lifetime; 161 } __packed; 162 163 /* 164 * RX Config Options Table 165 * Bit Definition 166 * === ========== 167 * 31:14 Reserved 168 * 13 Copy RX Status - when set, write three receive status words 169 * to top of rx'd MPDUs. 170 * When cleared, do not write three status words (added rev 1.5) 171 * 12 Reserved 172 * 11 RX Complete upon FCS error - when set, give rx complete 173 * interrupt for FCS errors, after the rx filtering, e.g. unicast 174 * frames not to us with FCS error will not generate an interrupt. 175 * 10 SSID Filter Enable - When set, the WiLink discards all beacon, 176 * probe request, and probe response frames with an SSID that does 177 * not match the SSID specified by the host in the START/JOIN 178 * command. 179 * When clear, the WiLink receives frames with any SSID. 180 * 9 Broadcast Filter Enable - When set, the WiLink discards all 181 * broadcast frames. When clear, the WiLink receives all received 182 * broadcast frames. 183 * 8:6 Reserved 184 * 5 BSSID Filter Enable - When set, the WiLink discards any frames 185 * with a BSSID that does not match the BSSID specified by the 186 * host. 187 * When clear, the WiLink receives frames from any BSSID. 188 * 4 MAC Addr Filter - When set, the WiLink discards any frames 189 * with a destination address that does not match the MAC address 190 * of the adaptor. 191 * When clear, the WiLink receives frames destined to any MAC 192 * address. 193 * 3 Promiscuous - When set, the WiLink receives all valid frames 194 * (i.e., all frames that pass the FCS check). 195 * When clear, only frames that pass the other filters specified 196 * are received. 197 * 2 FCS - When set, the WiLink includes the FCS with the received 198 * frame. 199 * When cleared, the FCS is discarded. 200 * 1 PLCP header - When set, write all data from baseband to frame 201 * buffer including PHY header. 202 * 0 Reserved - Always equal to 0. 203 * 204 * RX Filter Options Table 205 * Bit Definition 206 * === ========== 207 * 31:12 Reserved - Always equal to 0. 208 * 11 Association - When set, the WiLink receives all association 209 * related frames (association request/response, reassocation 210 * request/response, and disassociation). When clear, these frames 211 * are discarded. 212 * 10 Auth/De auth - When set, the WiLink receives all authentication 213 * and de-authentication frames. When clear, these frames are 214 * discarded. 215 * 9 Beacon - When set, the WiLink receives all beacon frames. 216 * When clear, these frames are discarded. 217 * 8 Contention Free - When set, the WiLink receives all contention 218 * free frames. 219 * When clear, these frames are discarded. 220 * 7 Control - When set, the WiLink receives all control frames. 221 * When clear, these frames are discarded. 222 * 6 Data - When set, the WiLink receives all data frames. 223 * When clear, these frames are discarded. 224 * 5 FCS Error - When set, the WiLink receives frames that have FCS 225 * errors. 226 * When clear, these frames are discarded. 227 * 4 Management - When set, the WiLink receives all management 228 * frames. 229 * When clear, these frames are discarded. 230 * 3 Probe Request - When set, the WiLink receives all probe request 231 * frames. 232 * When clear, these frames are discarded. 233 * 2 Probe Response - When set, the WiLink receives all probe 234 * response frames. 235 * When clear, these frames are discarded. 236 * 1 RTS/CTS/ACK - When set, the WiLink receives all RTS, CTS and ACK 237 * frames. 238 * When clear, these frames are discarded. 239 * 0 Rsvd Type/Sub Type - When set, the WiLink receives all frames 240 * that have reserved frame types and sub types as defined by the 241 * 802.11 specification. 242 * When clear, these frames are discarded. 243 */ 244 struct acx_rx_config { 245 struct acx_header header; 246 247 __le32 config_options; 248 __le32 filter_options; 249 } __packed; 250 251 struct acx_packet_detection { 252 struct acx_header header; 253 254 __le32 threshold; 255 } __packed; 256 257 258 enum acx_slot_type { 259 SLOT_TIME_LONG = 0, 260 SLOT_TIME_SHORT = 1, 261 DEFAULT_SLOT_TIME = SLOT_TIME_SHORT, 262 MAX_SLOT_TIMES = 0xFF 263 }; 264 265 #define STATION_WONE_INDEX 0 266 267 struct acx_slot { 268 struct acx_header header; 269 270 u8 wone_index; /* Reserved */ 271 u8 slot_time; 272 u8 reserved[6]; 273 } __packed; 274 275 276 #define ACX_MC_ADDRESS_GROUP_MAX (8) 277 #define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX) 278 279 struct acx_dot11_grp_addr_tbl { 280 struct acx_header header; 281 282 u8 enabled; 283 u8 num_groups; 284 u8 pad[2]; 285 u8 mac_table[ADDRESS_GROUP_MAX_LEN]; 286 } __packed; 287 288 struct acx_rx_timeout { 289 struct acx_header header; 290 291 __le16 ps_poll_timeout; 292 __le16 upsd_timeout; 293 } __packed; 294 295 struct acx_rts_threshold { 296 struct acx_header header; 297 298 __le16 threshold; 299 u8 pad[2]; 300 } __packed; 301 302 struct acx_beacon_filter_option { 303 struct acx_header header; 304 305 u8 enable; 306 307 /* 308 * The number of beacons without the unicast TIM 309 * bit set that the firmware buffers before 310 * signaling the host about ready frames. 311 * When set to 0 and the filter is enabled, beacons 312 * without the unicast TIM bit set are dropped. 313 */ 314 u8 max_num_beacons; 315 u8 pad[2]; 316 } __packed; 317 318 /* 319 * ACXBeaconFilterEntry (not 221) 320 * Byte Offset Size (Bytes) Definition 321 * =========== ============ ========== 322 * 0 1 IE identifier 323 * 1 1 Treatment bit mask 324 * 325 * ACXBeaconFilterEntry (221) 326 * Byte Offset Size (Bytes) Definition 327 * =========== ============ ========== 328 * 0 1 IE identifier 329 * 1 1 Treatment bit mask 330 * 2 3 OUI 331 * 5 1 Type 332 * 6 2 Version 333 * 334 * 335 * Treatment bit mask - The information element handling: 336 * bit 0 - The information element is compared and transferred 337 * in case of change. 338 * bit 1 - The information element is transferred to the host 339 * with each appearance or disappearance. 340 * Note that both bits can be set at the same time. 341 */ 342 #define BEACON_FILTER_TABLE_MAX_IE_NUM (32) 343 #define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6) 344 #define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2) 345 #define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6) 346 #define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \ 347 BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \ 348 (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \ 349 BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE)) 350 351 struct acx_beacon_filter_ie_table { 352 struct acx_header header; 353 354 u8 num_ie; 355 u8 pad[3]; 356 u8 table[BEACON_FILTER_TABLE_MAX_SIZE]; 357 } __packed; 358 359 struct acx_conn_monit_params { 360 struct acx_header header; 361 362 __le32 synch_fail_thold; /* number of beacons missed */ 363 __le32 bss_lose_timeout; /* number of TU's from synch fail */ 364 } __packed; 365 366 struct acx_bt_wlan_coex { 367 struct acx_header header; 368 369 u8 enable; 370 u8 pad[3]; 371 } __packed; 372 373 struct acx_bt_wlan_coex_param { 374 struct acx_header header; 375 376 __le32 params[CONF_SG_PARAMS_MAX]; 377 u8 param_idx; 378 u8 padding[3]; 379 } __packed; 380 381 struct acx_dco_itrim_params { 382 struct acx_header header; 383 384 u8 enable; 385 u8 padding[3]; 386 __le32 timeout; 387 } __packed; 388 389 struct acx_energy_detection { 390 struct acx_header header; 391 392 /* The RX Clear Channel Assessment threshold in the PHY */ 393 __le16 rx_cca_threshold; 394 u8 tx_energy_detection; 395 u8 pad; 396 } __packed; 397 398 struct acx_beacon_broadcast { 399 struct acx_header header; 400 401 __le16 beacon_rx_timeout; 402 __le16 broadcast_timeout; 403 404 /* Enables receiving of broadcast packets in PS mode */ 405 u8 rx_broadcast_in_ps; 406 407 /* Consecutive PS Poll failures before updating the host */ 408 u8 ps_poll_threshold; 409 u8 pad[2]; 410 } __packed; 411 412 struct acx_event_mask { 413 struct acx_header header; 414 415 __le32 event_mask; 416 __le32 high_event_mask; /* Unused */ 417 } __packed; 418 419 #define CFG_RX_FCS BIT(2) 420 #define CFG_RX_ALL_GOOD BIT(3) 421 #define CFG_UNI_FILTER_EN BIT(4) 422 #define CFG_BSSID_FILTER_EN BIT(5) 423 #define CFG_MC_FILTER_EN BIT(6) 424 #define CFG_MC_ADDR0_EN BIT(7) 425 #define CFG_MC_ADDR1_EN BIT(8) 426 #define CFG_BC_REJECT_EN BIT(9) 427 #define CFG_SSID_FILTER_EN BIT(10) 428 #define CFG_RX_INT_FCS_ERROR BIT(11) 429 #define CFG_RX_INT_ENCRYPTED BIT(12) 430 #define CFG_RX_WR_RX_STATUS BIT(13) 431 #define CFG_RX_FILTER_NULTI BIT(14) 432 #define CFG_RX_RESERVE BIT(15) 433 #define CFG_RX_TIMESTAMP_TSF BIT(16) 434 435 #define CFG_RX_RSV_EN BIT(0) 436 #define CFG_RX_RCTS_ACK BIT(1) 437 #define CFG_RX_PRSP_EN BIT(2) 438 #define CFG_RX_PREQ_EN BIT(3) 439 #define CFG_RX_MGMT_EN BIT(4) 440 #define CFG_RX_FCS_ERROR BIT(5) 441 #define CFG_RX_DATA_EN BIT(6) 442 #define CFG_RX_CTL_EN BIT(7) 443 #define CFG_RX_CF_EN BIT(8) 444 #define CFG_RX_BCN_EN BIT(9) 445 #define CFG_RX_AUTH_EN BIT(10) 446 #define CFG_RX_ASSOC_EN BIT(11) 447 448 #define SCAN_PASSIVE BIT(0) 449 #define SCAN_5GHZ_BAND BIT(1) 450 #define SCAN_TRIGGERED BIT(2) 451 #define SCAN_PRIORITY_HIGH BIT(3) 452 453 /* When set, disable HW encryption */ 454 #define DF_ENCRYPTION_DISABLE 0x01 455 #define DF_SNIFF_MODE_ENABLE 0x80 456 457 struct acx_feature_config { 458 struct acx_header header; 459 460 __le32 options; 461 __le32 data_flow_options; 462 } __packed; 463 464 struct acx_current_tx_power { 465 struct acx_header header; 466 467 u8 current_tx_power; 468 u8 padding[3]; 469 } __packed; 470 471 struct acx_wake_up_condition { 472 struct acx_header header; 473 474 u8 wake_up_event; /* Only one bit can be set */ 475 u8 listen_interval; 476 u8 pad[2]; 477 } __packed; 478 479 struct acx_aid { 480 struct acx_header header; 481 482 /* 483 * To be set when associated with an AP. 484 */ 485 __le16 aid; 486 u8 pad[2]; 487 } __packed; 488 489 enum acx_preamble_type { 490 ACX_PREAMBLE_LONG = 0, 491 ACX_PREAMBLE_SHORT = 1 492 }; 493 494 struct acx_preamble { 495 struct acx_header header; 496 497 /* 498 * When set, the WiLink transmits the frames with a short preamble and 499 * when cleared, the WiLink transmits the frames with a long preamble. 500 */ 501 u8 preamble; 502 u8 padding[3]; 503 } __packed; 504 505 enum acx_ctsprotect_type { 506 CTSPROTECT_DISABLE = 0, 507 CTSPROTECT_ENABLE = 1 508 }; 509 510 struct acx_ctsprotect { 511 struct acx_header header; 512 u8 ctsprotect; 513 u8 padding[3]; 514 } __packed; 515 516 struct acx_tx_statistics { 517 __le32 internal_desc_overflow; 518 } __packed; 519 520 struct acx_rx_statistics { 521 __le32 out_of_mem; 522 __le32 hdr_overflow; 523 __le32 hw_stuck; 524 __le32 dropped; 525 __le32 fcs_err; 526 __le32 xfr_hint_trig; 527 __le32 path_reset; 528 __le32 reset_counter; 529 } __packed; 530 531 struct acx_dma_statistics { 532 __le32 rx_requested; 533 __le32 rx_errors; 534 __le32 tx_requested; 535 __le32 tx_errors; 536 } __packed; 537 538 struct acx_isr_statistics { 539 /* host command complete */ 540 __le32 cmd_cmplt; 541 542 /* fiqisr() */ 543 __le32 fiqs; 544 545 /* (INT_STS_ND & INT_TRIG_RX_HEADER) */ 546 __le32 rx_headers; 547 548 /* (INT_STS_ND & INT_TRIG_RX_CMPLT) */ 549 __le32 rx_completes; 550 551 /* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */ 552 __le32 rx_mem_overflow; 553 554 /* (INT_STS_ND & INT_TRIG_S_RX_RDY) */ 555 __le32 rx_rdys; 556 557 /* irqisr() */ 558 __le32 irqs; 559 560 /* (INT_STS_ND & INT_TRIG_TX_PROC) */ 561 __le32 tx_procs; 562 563 /* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */ 564 __le32 decrypt_done; 565 566 /* (INT_STS_ND & INT_TRIG_DMA0) */ 567 __le32 dma0_done; 568 569 /* (INT_STS_ND & INT_TRIG_DMA1) */ 570 __le32 dma1_done; 571 572 /* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */ 573 __le32 tx_exch_complete; 574 575 /* (INT_STS_ND & INT_TRIG_COMMAND) */ 576 __le32 commands; 577 578 /* (INT_STS_ND & INT_TRIG_RX_PROC) */ 579 __le32 rx_procs; 580 581 /* (INT_STS_ND & INT_TRIG_PM_802) */ 582 __le32 hw_pm_mode_changes; 583 584 /* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */ 585 __le32 host_acknowledges; 586 587 /* (INT_STS_ND & INT_TRIG_PM_PCI) */ 588 __le32 pci_pm; 589 590 /* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */ 591 __le32 wakeups; 592 593 /* (INT_STS_ND & INT_TRIG_LOW_RSSI) */ 594 __le32 low_rssi; 595 } __packed; 596 597 struct acx_wep_statistics { 598 /* WEP address keys configured */ 599 __le32 addr_key_count; 600 601 /* default keys configured */ 602 __le32 default_key_count; 603 604 __le32 reserved; 605 606 /* number of times that WEP key not found on lookup */ 607 __le32 key_not_found; 608 609 /* number of times that WEP key decryption failed */ 610 __le32 decrypt_fail; 611 612 /* WEP packets decrypted */ 613 __le32 packets; 614 615 /* WEP decrypt interrupts */ 616 __le32 interrupt; 617 } __packed; 618 619 #define ACX_MISSED_BEACONS_SPREAD 10 620 621 struct acx_pwr_statistics { 622 /* the amount of enters into power save mode (both PD & ELP) */ 623 __le32 ps_enter; 624 625 /* the amount of enters into ELP mode */ 626 __le32 elp_enter; 627 628 /* the amount of missing beacon interrupts to the host */ 629 __le32 missing_bcns; 630 631 /* the amount of wake on host-access times */ 632 __le32 wake_on_host; 633 634 /* the amount of wake on timer-expire */ 635 __le32 wake_on_timer_exp; 636 637 /* the number of packets that were transmitted with PS bit set */ 638 __le32 tx_with_ps; 639 640 /* the number of packets that were transmitted with PS bit clear */ 641 __le32 tx_without_ps; 642 643 /* the number of received beacons */ 644 __le32 rcvd_beacons; 645 646 /* the number of entering into PowerOn (power save off) */ 647 __le32 power_save_off; 648 649 /* the number of entries into power save mode */ 650 __le16 enable_ps; 651 652 /* 653 * the number of exits from power save, not including failed PS 654 * transitions 655 */ 656 __le16 disable_ps; 657 658 /* 659 * the number of times the TSF counter was adjusted because 660 * of drift 661 */ 662 __le32 fix_tsf_ps; 663 664 /* Gives statistics about the spread continuous missed beacons. 665 * The 16 LSB are dedicated for the PS mode. 666 * The 16 MSB are dedicated for the PS mode. 667 * cont_miss_bcns_spread[0] - single missed beacon. 668 * cont_miss_bcns_spread[1] - two continuous missed beacons. 669 * cont_miss_bcns_spread[2] - three continuous missed beacons. 670 * ... 671 * cont_miss_bcns_spread[9] - ten and more continuous missed beacons. 672 */ 673 __le32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD]; 674 675 /* the number of beacons in awake mode */ 676 __le32 rcvd_awake_beacons; 677 } __packed; 678 679 struct acx_mic_statistics { 680 __le32 rx_pkts; 681 __le32 calc_failure; 682 } __packed; 683 684 struct acx_aes_statistics { 685 __le32 encrypt_fail; 686 __le32 decrypt_fail; 687 __le32 encrypt_packets; 688 __le32 decrypt_packets; 689 __le32 encrypt_interrupt; 690 __le32 decrypt_interrupt; 691 } __packed; 692 693 struct acx_event_statistics { 694 __le32 heart_beat; 695 __le32 calibration; 696 __le32 rx_mismatch; 697 __le32 rx_mem_empty; 698 __le32 rx_pool; 699 __le32 oom_late; 700 __le32 phy_transmit_error; 701 __le32 tx_stuck; 702 } __packed; 703 704 struct acx_ps_statistics { 705 __le32 pspoll_timeouts; 706 __le32 upsd_timeouts; 707 __le32 upsd_max_sptime; 708 __le32 upsd_max_apturn; 709 __le32 pspoll_max_apturn; 710 __le32 pspoll_utilization; 711 __le32 upsd_utilization; 712 } __packed; 713 714 struct acx_rxpipe_statistics { 715 __le32 rx_prep_beacon_drop; 716 __le32 descr_host_int_trig_rx_data; 717 __le32 beacon_buffer_thres_host_int_trig_rx_data; 718 __le32 missed_beacon_host_int_trig_rx_data; 719 __le32 tx_xfr_host_int_trig_rx_data; 720 } __packed; 721 722 struct acx_statistics { 723 struct acx_header header; 724 725 struct acx_tx_statistics tx; 726 struct acx_rx_statistics rx; 727 struct acx_dma_statistics dma; 728 struct acx_isr_statistics isr; 729 struct acx_wep_statistics wep; 730 struct acx_pwr_statistics pwr; 731 struct acx_aes_statistics aes; 732 struct acx_mic_statistics mic; 733 struct acx_event_statistics event; 734 struct acx_ps_statistics ps; 735 struct acx_rxpipe_statistics rxpipe; 736 } __packed; 737 738 struct acx_rate_class { 739 __le32 enabled_rates; 740 u8 short_retry_limit; 741 u8 long_retry_limit; 742 u8 aflags; 743 u8 reserved; 744 }; 745 746 #define ACX_TX_BASIC_RATE 0 747 #define ACX_TX_AP_FULL_RATE 1 748 #define ACX_TX_RATE_POLICY_CNT 2 749 struct acx_sta_rate_policy { 750 struct acx_header header; 751 752 __le32 rate_class_cnt; 753 struct acx_rate_class rate_class[CONF_TX_MAX_RATE_CLASSES]; 754 } __packed; 755 756 757 #define ACX_TX_AP_MODE_MGMT_RATE 4 758 #define ACX_TX_AP_MODE_BCST_RATE 5 759 struct acx_ap_rate_policy { 760 struct acx_header header; 761 762 __le32 rate_policy_idx; 763 struct acx_rate_class rate_policy; 764 } __packed; 765 766 struct acx_ac_cfg { 767 struct acx_header header; 768 u8 ac; 769 u8 cw_min; 770 __le16 cw_max; 771 u8 aifsn; 772 u8 reserved; 773 __le16 tx_op_limit; 774 } __packed; 775 776 struct acx_tid_config { 777 struct acx_header header; 778 u8 queue_id; 779 u8 channel_type; 780 u8 tsid; 781 u8 ps_scheme; 782 u8 ack_policy; 783 u8 padding[3]; 784 __le32 apsd_conf[2]; 785 } __packed; 786 787 struct acx_frag_threshold { 788 struct acx_header header; 789 __le16 frag_threshold; 790 u8 padding[2]; 791 } __packed; 792 793 struct acx_tx_config_options { 794 struct acx_header header; 795 __le16 tx_compl_timeout; /* msec */ 796 __le16 tx_compl_threshold; /* number of packets */ 797 } __packed; 798 799 #define ACX_TX_DESCRIPTORS 32 800 801 struct wl1271_acx_ap_config_memory { 802 struct acx_header header; 803 804 u8 rx_mem_block_num; 805 u8 tx_min_mem_block_num; 806 u8 num_stations; 807 u8 num_ssid_profiles; 808 __le32 total_tx_descriptors; 809 } __packed; 810 811 struct wl1271_acx_sta_config_memory { 812 struct acx_header header; 813 814 u8 rx_mem_block_num; 815 u8 tx_min_mem_block_num; 816 u8 num_stations; 817 u8 num_ssid_profiles; 818 __le32 total_tx_descriptors; 819 u8 dyn_mem_enable; 820 u8 tx_free_req; 821 u8 rx_free_req; 822 u8 tx_min; 823 } __packed; 824 825 struct wl1271_acx_mem_map { 826 struct acx_header header; 827 828 __le32 code_start; 829 __le32 code_end; 830 831 __le32 wep_defkey_start; 832 __le32 wep_defkey_end; 833 834 __le32 sta_table_start; 835 __le32 sta_table_end; 836 837 __le32 packet_template_start; 838 __le32 packet_template_end; 839 840 /* Address of the TX result interface (control block) */ 841 __le32 tx_result; 842 __le32 tx_result_queue_start; 843 844 __le32 queue_memory_start; 845 __le32 queue_memory_end; 846 847 __le32 packet_memory_pool_start; 848 __le32 packet_memory_pool_end; 849 850 __le32 debug_buffer1_start; 851 __le32 debug_buffer1_end; 852 853 __le32 debug_buffer2_start; 854 __le32 debug_buffer2_end; 855 856 /* Number of blocks FW allocated for TX packets */ 857 __le32 num_tx_mem_blocks; 858 859 /* Number of blocks FW allocated for RX packets */ 860 __le32 num_rx_mem_blocks; 861 862 /* the following 4 fields are valid in SLAVE mode only */ 863 u8 *tx_cbuf; 864 u8 *rx_cbuf; 865 __le32 rx_ctrl; 866 __le32 tx_ctrl; 867 } __packed; 868 869 struct wl1271_acx_rx_config_opt { 870 struct acx_header header; 871 872 __le16 mblk_threshold; 873 __le16 threshold; 874 __le16 timeout; 875 u8 queue_type; 876 u8 reserved; 877 } __packed; 878 879 880 struct wl1271_acx_bet_enable { 881 struct acx_header header; 882 883 u8 enable; 884 u8 max_consecutive; 885 u8 padding[2]; 886 } __packed; 887 888 #define ACX_IPV4_VERSION 4 889 #define ACX_IPV6_VERSION 6 890 #define ACX_IPV4_ADDR_SIZE 4 891 892 /* bitmap of enabled arp_filter features */ 893 #define ACX_ARP_FILTER_ARP_FILTERING BIT(0) 894 #define ACX_ARP_FILTER_AUTO_ARP BIT(1) 895 896 struct wl1271_acx_arp_filter { 897 struct acx_header header; 898 u8 version; /* ACX_IPV4_VERSION, ACX_IPV6_VERSION */ 899 u8 enable; /* bitmap of enabled ARP filtering features */ 900 u8 padding[2]; 901 u8 address[16]; /* The configured device IP address - all ARP 902 requests directed to this IP address will pass 903 through. For IPv4, the first four bytes are 904 used. */ 905 } __packed; 906 907 struct wl1271_acx_pm_config { 908 struct acx_header header; 909 910 __le32 host_clk_settling_time; 911 u8 host_fast_wakeup_support; 912 u8 padding[3]; 913 } __packed; 914 915 struct wl1271_acx_keep_alive_mode { 916 struct acx_header header; 917 918 u8 enabled; 919 u8 padding[3]; 920 } __packed; 921 922 enum { 923 ACX_KEEP_ALIVE_NO_TX = 0, 924 ACX_KEEP_ALIVE_PERIOD_ONLY 925 }; 926 927 enum { 928 ACX_KEEP_ALIVE_TPL_INVALID = 0, 929 ACX_KEEP_ALIVE_TPL_VALID 930 }; 931 932 struct wl1271_acx_keep_alive_config { 933 struct acx_header header; 934 935 __le32 period; 936 u8 index; 937 u8 tpl_validation; 938 u8 trigger; 939 u8 padding; 940 } __packed; 941 942 enum { 943 WL1271_ACX_TRIG_TYPE_LEVEL = 0, 944 WL1271_ACX_TRIG_TYPE_EDGE, 945 }; 946 947 enum { 948 WL1271_ACX_TRIG_DIR_LOW = 0, 949 WL1271_ACX_TRIG_DIR_HIGH, 950 WL1271_ACX_TRIG_DIR_BIDIR, 951 }; 952 953 enum { 954 WL1271_ACX_TRIG_ENABLE = 1, 955 WL1271_ACX_TRIG_DISABLE, 956 }; 957 958 enum { 959 WL1271_ACX_TRIG_METRIC_RSSI_BEACON = 0, 960 WL1271_ACX_TRIG_METRIC_RSSI_DATA, 961 WL1271_ACX_TRIG_METRIC_SNR_BEACON, 962 WL1271_ACX_TRIG_METRIC_SNR_DATA, 963 }; 964 965 enum { 966 WL1271_ACX_TRIG_IDX_RSSI = 0, 967 WL1271_ACX_TRIG_COUNT = 8, 968 }; 969 970 struct wl1271_acx_rssi_snr_trigger { 971 struct acx_header header; 972 973 __le16 threshold; 974 __le16 pacing; /* 0 - 60000 ms */ 975 u8 metric; 976 u8 type; 977 u8 dir; 978 u8 hysteresis; 979 u8 index; 980 u8 enable; 981 u8 padding[2]; 982 }; 983 984 struct wl1271_acx_rssi_snr_avg_weights { 985 struct acx_header header; 986 987 u8 rssi_beacon; 988 u8 rssi_data; 989 u8 snr_beacon; 990 u8 snr_data; 991 }; 992 993 /* 994 * ACX_PEER_HT_CAP 995 * Configure HT capabilities - declare the capabilities of the peer 996 * we are connected to. 997 */ 998 struct wl1271_acx_ht_capabilities { 999 struct acx_header header; 1000 1001 /* 1002 * bit 0 - Allow HT Operation 1003 * bit 1 - Allow Greenfield format in TX 1004 * bit 2 - Allow Short GI in TX 1005 * bit 3 - Allow L-SIG TXOP Protection in TX 1006 * bit 4 - Allow HT Control fields in TX. 1007 * Note, driver will still leave space for HT control in packets 1008 * regardless of the value of this field. FW will be responsible 1009 * to drop the HT field from any frame when this Bit set to 0. 1010 * bit 5 - Allow RD initiation in TXOP. FW is allowed to initate RD. 1011 * Exact policy setting for this feature is TBD. 1012 * Note, this bit can only be set to 1 if bit 3 is set to 1. 1013 */ 1014 __le32 ht_capabilites; 1015 1016 /* 1017 * Indicates to which peer these capabilities apply. 1018 * For infrastructure use ff:ff:ff:ff:ff:ff that indicates relevance 1019 * for all peers. 1020 * Only valid for IBSS/DLS operation. 1021 */ 1022 u8 mac_address[ETH_ALEN]; 1023 1024 /* 1025 * This the maximum A-MPDU length supported by the AP. The FW may not 1026 * exceed this length when sending A-MPDUs 1027 */ 1028 u8 ampdu_max_length; 1029 1030 /* This is the minimal spacing required when sending A-MPDUs to the AP*/ 1031 u8 ampdu_min_spacing; 1032 } __packed; 1033 1034 /* HT Capabilites Fw Bit Mask Mapping */ 1035 #define WL1271_ACX_FW_CAP_HT_OPERATION BIT(0) 1036 #define WL1271_ACX_FW_CAP_GREENFIELD_FRAME_FORMAT BIT(1) 1037 #define WL1271_ACX_FW_CAP_SHORT_GI_FOR_20MHZ_PACKETS BIT(2) 1038 #define WL1271_ACX_FW_CAP_LSIG_TXOP_PROTECTION BIT(3) 1039 #define WL1271_ACX_FW_CAP_HT_CONTROL_FIELDS BIT(4) 1040 #define WL1271_ACX_FW_CAP_RD_INITIATION BIT(5) 1041 1042 1043 /* 1044 * ACX_HT_BSS_OPERATION 1045 * Configure HT capabilities - AP rules for behavior in the BSS. 1046 */ 1047 struct wl1271_acx_ht_information { 1048 struct acx_header header; 1049 1050 /* Values: 0 - RIFS not allowed, 1 - RIFS allowed */ 1051 u8 rifs_mode; 1052 1053 /* Values: 0 - 3 like in spec */ 1054 u8 ht_protection; 1055 1056 /* Values: 0 - GF protection not required, 1 - GF protection required */ 1057 u8 gf_protection; 1058 1059 /*Values: 0 - TX Burst limit not required, 1 - TX Burst Limit required*/ 1060 u8 ht_tx_burst_limit; 1061 1062 /* 1063 * Values: 0 - Dual CTS protection not required, 1064 * 1 - Dual CTS Protection required 1065 * Note: When this value is set to 1 FW will protect all TXOP with RTS 1066 * frame and will not use CTS-to-self regardless of the value of the 1067 * ACX_CTS_PROTECTION information element 1068 */ 1069 u8 dual_cts_protection; 1070 1071 u8 padding[3]; 1072 } __packed; 1073 1074 #define RX_BA_WIN_SIZE 8 1075 1076 struct wl1271_acx_ba_session_policy { 1077 struct acx_header header; 1078 /* 1079 * Specifies role Id, Range 0-7, 0xFF means ANY role. 1080 * Future use. For now this field is irrelevant 1081 */ 1082 u8 role_id; 1083 /* 1084 * Specifies Link Id, Range 0-31, 0xFF means ANY Link Id. 1085 * Not applicable if Role Id is set to ANY. 1086 */ 1087 u8 link_id; 1088 1089 u8 tid; 1090 1091 u8 enable; 1092 1093 /* Windows size in number of packets */ 1094 u16 win_size; 1095 1096 /* 1097 * As initiator inactivity timeout in time units(TU) of 1024us. 1098 * As receiver reserved 1099 */ 1100 u16 inactivity_timeout; 1101 1102 /* Initiator = 1/Receiver = 0 */ 1103 u8 ba_direction; 1104 1105 u8 padding[3]; 1106 } __packed; 1107 1108 struct wl1271_acx_ba_receiver_setup { 1109 struct acx_header header; 1110 1111 /* Specifies Link Id, Range 0-31, 0xFF means ANY Link Id */ 1112 u8 link_id; 1113 1114 u8 tid; 1115 1116 u8 enable; 1117 1118 u8 padding[1]; 1119 1120 /* Windows size in number of packets */ 1121 u16 win_size; 1122 1123 /* BA session starting sequence number. RANGE 0-FFF */ 1124 u16 ssn; 1125 } __packed; 1126 1127 struct wl1271_acx_fw_tsf_information { 1128 struct acx_header header; 1129 1130 __le32 current_tsf_high; 1131 __le32 current_tsf_low; 1132 __le32 last_bttt_high; 1133 __le32 last_tbtt_low; 1134 u8 last_dtim_count; 1135 u8 padding[3]; 1136 } __packed; 1137 1138 struct wl1271_acx_max_tx_retry { 1139 struct acx_header header; 1140 1141 /* 1142 * the number of frames transmission failures before 1143 * issuing the aging event. 1144 */ 1145 __le16 max_tx_retry; 1146 u8 padding_1[2]; 1147 } __packed; 1148 1149 struct wl1271_acx_config_ps { 1150 struct acx_header header; 1151 1152 u8 exit_retries; 1153 u8 enter_retries; 1154 u8 padding[2]; 1155 __le32 null_data_rate; 1156 } __packed; 1157 1158 struct wl1271_acx_inconnection_sta { 1159 struct acx_header header; 1160 1161 u8 addr[ETH_ALEN]; 1162 u8 padding1[2]; 1163 } __packed; 1164 1165 enum { 1166 ACX_WAKE_UP_CONDITIONS = 0x0002, 1167 ACX_MEM_CFG = 0x0003, 1168 ACX_SLOT = 0x0004, 1169 ACX_AC_CFG = 0x0007, 1170 ACX_MEM_MAP = 0x0008, 1171 ACX_AID = 0x000A, 1172 /* ACX_FW_REV is missing in the ref driver, but seems to work */ 1173 ACX_FW_REV = 0x000D, 1174 ACX_MEDIUM_USAGE = 0x000F, 1175 ACX_RX_CFG = 0x0010, 1176 ACX_TX_QUEUE_CFG = 0x0011, /* FIXME: only used by wl1251 */ 1177 ACX_STATISTICS = 0x0013, /* Debug API */ 1178 ACX_PWR_CONSUMPTION_STATISTICS = 0x0014, 1179 ACX_FEATURE_CFG = 0x0015, 1180 ACX_TID_CFG = 0x001A, 1181 ACX_PS_RX_STREAMING = 0x001B, 1182 ACX_BEACON_FILTER_OPT = 0x001F, 1183 ACX_NOISE_HIST = 0x0021, 1184 ACX_HDK_VERSION = 0x0022, /* ??? */ 1185 ACX_PD_THRESHOLD = 0x0023, 1186 ACX_TX_CONFIG_OPT = 0x0024, 1187 ACX_CCA_THRESHOLD = 0x0025, 1188 ACX_EVENT_MBOX_MASK = 0x0026, 1189 ACX_CONN_MONIT_PARAMS = 0x002D, 1190 ACX_CONS_TX_FAILURE = 0x002F, 1191 ACX_BCN_DTIM_OPTIONS = 0x0031, 1192 ACX_SG_ENABLE = 0x0032, 1193 ACX_SG_CFG = 0x0033, 1194 ACX_BEACON_FILTER_TABLE = 0x0038, 1195 ACX_ARP_IP_FILTER = 0x0039, 1196 ACX_ROAMING_STATISTICS_TBL = 0x003B, 1197 ACX_RATE_POLICY = 0x003D, 1198 ACX_CTS_PROTECTION = 0x003E, 1199 ACX_SLEEP_AUTH = 0x003F, 1200 ACX_PREAMBLE_TYPE = 0x0040, 1201 ACX_ERROR_CNT = 0x0041, 1202 ACX_IBSS_FILTER = 0x0044, 1203 ACX_SERVICE_PERIOD_TIMEOUT = 0x0045, 1204 ACX_TSF_INFO = 0x0046, 1205 ACX_CONFIG_PS_WMM = 0x0049, 1206 ACX_ENABLE_RX_DATA_FILTER = 0x004A, 1207 ACX_SET_RX_DATA_FILTER = 0x004B, 1208 ACX_GET_DATA_FILTER_STATISTICS = 0x004C, 1209 ACX_RX_CONFIG_OPT = 0x004E, 1210 ACX_FRAG_CFG = 0x004F, 1211 ACX_BET_ENABLE = 0x0050, 1212 ACX_RSSI_SNR_TRIGGER = 0x0051, 1213 ACX_RSSI_SNR_WEIGHTS = 0x0052, 1214 ACX_KEEP_ALIVE_MODE = 0x0053, 1215 ACX_SET_KEEP_ALIVE_CONFIG = 0x0054, 1216 ACX_BA_SESSION_POLICY_CFG = 0x0055, 1217 ACX_BA_SESSION_RX_SETUP = 0x0056, 1218 ACX_PEER_HT_CAP = 0x0057, 1219 ACX_HT_BSS_OPERATION = 0x0058, 1220 ACX_COEX_ACTIVITY = 0x0059, 1221 ACX_SET_DCO_ITRIM_PARAMS = 0x0061, 1222 ACX_GEN_FW_CMD = 0x0070, 1223 ACX_HOST_IF_CFG_BITMAP = 0x0071, 1224 ACX_MAX_TX_FAILURE = 0x0072, 1225 ACX_UPDATE_INCONNECTION_STA_LIST = 0x0073, 1226 DOT11_RX_MSDU_LIFE_TIME = 0x1004, 1227 DOT11_CUR_TX_PWR = 0x100D, 1228 DOT11_RX_DOT11_MODE = 0x1012, 1229 DOT11_RTS_THRESHOLD = 0x1013, 1230 DOT11_GROUP_ADDRESS_TBL = 0x1014, 1231 ACX_PM_CONFIG = 0x1016, 1232 ACX_CONFIG_PS = 0x1017, 1233 ACX_CONFIG_HANGOVER = 0x1018, 1234 }; 1235 1236 1237 int wl1271_acx_wake_up_conditions(struct wl1271 *wl); 1238 int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth); 1239 int wl1271_acx_tx_power(struct wl1271 *wl, int power); 1240 int wl1271_acx_feature_cfg(struct wl1271 *wl); 1241 int wl1271_acx_mem_map(struct wl1271 *wl, 1242 struct acx_header *mem_map, size_t len); 1243 int wl1271_acx_rx_msdu_life_time(struct wl1271 *wl); 1244 int wl1271_acx_rx_config(struct wl1271 *wl, u32 config, u32 filter); 1245 int wl1271_acx_pd_threshold(struct wl1271 *wl); 1246 int wl1271_acx_slot(struct wl1271 *wl, enum acx_slot_type slot_time); 1247 int wl1271_acx_group_address_tbl(struct wl1271 *wl, bool enable, 1248 void *mc_list, u32 mc_list_len); 1249 int wl1271_acx_service_period_timeout(struct wl1271 *wl); 1250 int wl1271_acx_rts_threshold(struct wl1271 *wl, u16 rts_threshold); 1251 int wl1271_acx_dco_itrim_params(struct wl1271 *wl); 1252 int wl1271_acx_beacon_filter_opt(struct wl1271 *wl, bool enable_filter); 1253 int wl1271_acx_beacon_filter_table(struct wl1271 *wl); 1254 int wl1271_acx_conn_monit_params(struct wl1271 *wl, bool enable); 1255 int wl1271_acx_sg_enable(struct wl1271 *wl, bool enable); 1256 int wl1271_acx_sg_cfg(struct wl1271 *wl); 1257 int wl1271_acx_cca_threshold(struct wl1271 *wl); 1258 int wl1271_acx_bcn_dtim_options(struct wl1271 *wl); 1259 int wl1271_acx_aid(struct wl1271 *wl, u16 aid); 1260 int wl1271_acx_event_mbox_mask(struct wl1271 *wl, u32 event_mask); 1261 int wl1271_acx_set_preamble(struct wl1271 *wl, enum acx_preamble_type preamble); 1262 int wl1271_acx_cts_protect(struct wl1271 *wl, 1263 enum acx_ctsprotect_type ctsprotect); 1264 int wl1271_acx_statistics(struct wl1271 *wl, struct acx_statistics *stats); 1265 int wl1271_acx_sta_rate_policies(struct wl1271 *wl); 1266 int wl1271_acx_ap_rate_policy(struct wl1271 *wl, struct conf_tx_rate_class *c, 1267 u8 idx); 1268 int wl1271_acx_ac_cfg(struct wl1271 *wl, u8 ac, u8 cw_min, u16 cw_max, 1269 u8 aifsn, u16 txop); 1270 int wl1271_acx_tid_cfg(struct wl1271 *wl, u8 queue_id, u8 channel_type, 1271 u8 tsid, u8 ps_scheme, u8 ack_policy, 1272 u32 apsd_conf0, u32 apsd_conf1); 1273 int wl1271_acx_frag_threshold(struct wl1271 *wl, u16 frag_threshold); 1274 int wl1271_acx_tx_config_options(struct wl1271 *wl); 1275 int wl1271_acx_ap_mem_cfg(struct wl1271 *wl); 1276 int wl1271_acx_sta_mem_cfg(struct wl1271 *wl); 1277 int wl1271_acx_init_mem_config(struct wl1271 *wl); 1278 int wl1271_acx_init_rx_interrupt(struct wl1271 *wl); 1279 int wl1271_acx_smart_reflex(struct wl1271 *wl); 1280 int wl1271_acx_bet_enable(struct wl1271 *wl, bool enable); 1281 int wl1271_acx_arp_ip_filter(struct wl1271 *wl, u8 enable, __be32 address); 1282 int wl1271_acx_pm_config(struct wl1271 *wl); 1283 int wl1271_acx_keep_alive_mode(struct wl1271 *wl, bool enable); 1284 int wl1271_acx_keep_alive_config(struct wl1271 *wl, u8 index, u8 tpl_valid); 1285 int wl1271_acx_rssi_snr_trigger(struct wl1271 *wl, bool enable, 1286 s16 thold, u8 hyst); 1287 int wl1271_acx_rssi_snr_avg_weights(struct wl1271 *wl); 1288 int wl1271_acx_set_ht_capabilities(struct wl1271 *wl, 1289 struct ieee80211_sta_ht_cap *ht_cap, 1290 bool allow_ht_operation); 1291 int wl1271_acx_set_ht_information(struct wl1271 *wl, 1292 u16 ht_operation_mode); 1293 int wl1271_acx_set_ba_session(struct wl1271 *wl, 1294 enum ieee80211_back_parties direction, 1295 u8 tid_index, u8 policy); 1296 int wl1271_acx_set_ba_receiver_session(struct wl1271 *wl, u8 tid_index, u16 ssn, 1297 bool enable); 1298 int wl1271_acx_tsf_info(struct wl1271 *wl, u64 *mactime); 1299 int wl1271_acx_max_tx_retry(struct wl1271 *wl); 1300 int wl1271_acx_config_ps(struct wl1271 *wl); 1301 int wl1271_acx_set_inconnection_sta(struct wl1271 *wl, u8 *addr); 1302 1303 #endif /* __WL1271_ACX_H__ */ 1304