1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #ifndef __RTL92C_DEF_H__
31 #define __RTL92C_DEF_H__
32
33 #define HAL_RETRY_LIMIT_INFRA 48
34 #define HAL_RETRY_LIMIT_AP_ADHOC 7
35
36 #define PHY_RSSI_SLID_WIN_MAX 100
37 #define PHY_LINKQUALITY_SLID_WIN_MAX 20
38 #define PHY_BEACON_RSSI_SLID_WIN_MAX 10
39
40 #define RESET_DELAY_8185 20
41
42 #define RT_IBSS_INT_MASKS (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
43 #define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
44
45 #define NUM_OF_FIRMWARE_QUEUE 10
46 #define NUM_OF_PAGES_IN_FW 0x100
47 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x07
48 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x07
49 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x07
50 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x07
51 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0x0
52 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
53 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x02
54 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0x02
55 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x2
56 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xA1
57
58 #define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026
59 #define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048
60 #define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048
61 #define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026
62 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00
63
64 #define MAX_LINES_HWCONFIG_TXT 1000
65 #define MAX_BYTES_LINE_HWCONFIG_TXT 256
66
67 #define SW_THREE_WIRE 0
68 #define HW_THREE_WIRE 2
69
70 #define BT_DEMO_BOARD 0
71 #define BT_QA_BOARD 1
72 #define BT_FPGA 2
73
74 #define RX_SMOOTH_FACTOR 20
75
76 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
77 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
78 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
79
80 #define MAX_H2C_QUEUE_NUM 10
81
82 #define RX_MPDU_QUEUE 0
83 #define RX_CMD_QUEUE 1
84 #define RX_MAX_QUEUE 2
85 #define AC2QUEUEID(_AC) (_AC)
86
87 #define C2H_RX_CMD_HDR_LEN 8
88 #define GET_C2H_CMD_CMD_LEN(__prxhdr) \
89 LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
90 #define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
91 LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
92 #define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
93 LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
94 #define GET_C2H_CMD_CONTINUE(__prxhdr) \
95 LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
96 #define GET_C2H_CMD_CONTENT(__prxhdr) \
97 ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
98
99 #define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
100 LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
101 #define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
102 LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
103 #define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
104 LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
105 #define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
106 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
107 #define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
108 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
109 #define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
110 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
111 #define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
112 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
113 #define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
114 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
115 #define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
116 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
117
118 #define CHIP_VER_B BIT(4)
119 #define CHIP_92C_BITMASK BIT(0)
120 #define CHIP_92C_1T2R 0x03
121 #define CHIP_92C 0x01
122 #define CHIP_88C 0x00
123
124 /* Add vendor information into chip version definition.
125 * Add UMC B-Cut and RTL8723 chip info definition.
126 *
127 * BIT 7 Reserved
128 * BIT 6 UMC BCut
129 * BIT 5 Manufacturer(TSMC/UMC)
130 * BIT 4 TEST/NORMAL
131 * BIT 3 8723 Version
132 * BIT 2 8723?
133 * BIT 1 1T2R?
134 * BIT 0 88C/92C
135 */
136
137 enum version_8192c {
138 VERSION_A_CHIP_92C = 0x01,
139 VERSION_A_CHIP_88C = 0x00,
140 VERSION_B_CHIP_92C = 0x11,
141 VERSION_B_CHIP_88C = 0x10,
142 VERSION_TEST_CHIP_88C = 0x00,
143 VERSION_TEST_CHIP_92C = 0x01,
144 VERSION_NORMAL_TSMC_CHIP_88C = 0x10,
145 VERSION_NORMAL_TSMC_CHIP_92C = 0x11,
146 VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x13,
147 VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x30,
148 VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x31,
149 VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x33,
150 VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT = 0x34,
151 VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT = 0x3c,
152 VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x70,
153 VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x71,
154 VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x73,
155 VERSION_UNKNOWN = 0x88,
156 };
157
158 #define IS_CHIP_VER_B(version) ((version & CHIP_VER_B) ? true : false)
159 #define IS_92C_SERIAL(version) ((version & CHIP_92C_BITMASK) ? true : false)
160
161 enum rtl819x_loopback_e {
162 RTL819X_NO_LOOPBACK = 0,
163 RTL819X_MAC_LOOPBACK = 1,
164 RTL819X_DMA_LOOPBACK = 2,
165 RTL819X_CCK_LOOPBACK = 3,
166 };
167
168 enum rf_optype {
169 RF_OP_BY_SW_3WIRE = 0,
170 RF_OP_BY_FW,
171 RF_OP_MAX
172 };
173
174 enum rf_power_state {
175 RF_ON,
176 RF_OFF,
177 RF_SLEEP,
178 RF_SHUT_DOWN,
179 };
180
181 enum power_save_mode {
182 POWER_SAVE_MODE_ACTIVE,
183 POWER_SAVE_MODE_SAVE,
184 };
185
186 enum power_polocy_config {
187 POWERCFG_MAX_POWER_SAVINGS,
188 POWERCFG_GLOBAL_POWER_SAVINGS,
189 POWERCFG_LOCAL_POWER_SAVINGS,
190 POWERCFG_LENOVO,
191 };
192
193 enum interface_select_pci {
194 INTF_SEL1_MINICARD = 0,
195 INTF_SEL0_PCIE = 1,
196 INTF_SEL2_RSV = 2,
197 INTF_SEL3_RSV = 3,
198 };
199
200 enum hal_fw_c2h_cmd_id {
201 HAL_FW_C2H_CMD_Read_MACREG = 0,
202 HAL_FW_C2H_CMD_Read_BBREG = 1,
203 HAL_FW_C2H_CMD_Read_RFREG = 2,
204 HAL_FW_C2H_CMD_Read_EEPROM = 3,
205 HAL_FW_C2H_CMD_Read_EFUSE = 4,
206 HAL_FW_C2H_CMD_Read_CAM = 5,
207 HAL_FW_C2H_CMD_Get_BasicRate = 6,
208 HAL_FW_C2H_CMD_Get_DataRate = 7,
209 HAL_FW_C2H_CMD_Survey = 8,
210 HAL_FW_C2H_CMD_SurveyDone = 9,
211 HAL_FW_C2H_CMD_JoinBss = 10,
212 HAL_FW_C2H_CMD_AddSTA = 11,
213 HAL_FW_C2H_CMD_DelSTA = 12,
214 HAL_FW_C2H_CMD_AtimDone = 13,
215 HAL_FW_C2H_CMD_TX_Report = 14,
216 HAL_FW_C2H_CMD_CCX_Report = 15,
217 HAL_FW_C2H_CMD_DTM_Report = 16,
218 HAL_FW_C2H_CMD_TX_Rate_Statistics = 17,
219 HAL_FW_C2H_CMD_C2HLBK = 18,
220 HAL_FW_C2H_CMD_C2HDBG = 19,
221 HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
222 HAL_FW_C2H_CMD_MAX
223 };
224
225 enum rtl_desc_qsel {
226 QSLT_BK = 0x2,
227 QSLT_BE = 0x0,
228 QSLT_VI = 0x5,
229 QSLT_VO = 0x7,
230 QSLT_BEACON = 0x10,
231 QSLT_HIGH = 0x11,
232 QSLT_MGNT = 0x12,
233 QSLT_CMD = 0x13,
234 };
235
236 enum rtl_desc92c_rate {
237 DESC92C_RATE1M = 0x00,
238 DESC92C_RATE2M = 0x01,
239 DESC92C_RATE5_5M = 0x02,
240 DESC92C_RATE11M = 0x03,
241
242 DESC92C_RATE6M = 0x04,
243 DESC92C_RATE9M = 0x05,
244 DESC92C_RATE12M = 0x06,
245 DESC92C_RATE18M = 0x07,
246 DESC92C_RATE24M = 0x08,
247 DESC92C_RATE36M = 0x09,
248 DESC92C_RATE48M = 0x0a,
249 DESC92C_RATE54M = 0x0b,
250
251 DESC92C_RATEMCS0 = 0x0c,
252 DESC92C_RATEMCS1 = 0x0d,
253 DESC92C_RATEMCS2 = 0x0e,
254 DESC92C_RATEMCS3 = 0x0f,
255 DESC92C_RATEMCS4 = 0x10,
256 DESC92C_RATEMCS5 = 0x11,
257 DESC92C_RATEMCS6 = 0x12,
258 DESC92C_RATEMCS7 = 0x13,
259 DESC92C_RATEMCS8 = 0x14,
260 DESC92C_RATEMCS9 = 0x15,
261 DESC92C_RATEMCS10 = 0x16,
262 DESC92C_RATEMCS11 = 0x17,
263 DESC92C_RATEMCS12 = 0x18,
264 DESC92C_RATEMCS13 = 0x19,
265 DESC92C_RATEMCS14 = 0x1a,
266 DESC92C_RATEMCS15 = 0x1b,
267 DESC92C_RATEMCS15_SG = 0x1c,
268 DESC92C_RATEMCS32 = 0x20,
269 };
270
271 struct phy_sts_cck_8192s_t {
272 u8 adc_pwdb_X[4];
273 u8 sq_rpt;
274 u8 cck_agc_rpt;
275 };
276
277 struct h2c_cmd_8192c {
278 u8 element_id;
279 u32 cmd_len;
280 u8 *p_cmdbuffer;
281 };
282
_rtl92c_get_chnl_group(u8 chnl)283 static inline u8 _rtl92c_get_chnl_group(u8 chnl)
284 {
285 u8 group = 0;
286
287 if (chnl < 3)
288 group = 0;
289 else if (chnl < 9)
290 group = 1;
291 else
292 group = 2;
293
294 return group;
295 }
296
297 /* NOTE: reference to rtl8192c_rates struct */
_rtl92c_rate_mapping(struct ieee80211_hw * hw,bool isHT,u8 desc_rate,bool first_ampdu)298 static inline int _rtl92c_rate_mapping(struct ieee80211_hw *hw, bool isHT,
299 u8 desc_rate, bool first_ampdu)
300 {
301 struct rtl_priv *rtlpriv = rtl_priv(hw);
302 int rate_idx = 0;
303
304 if (first_ampdu) {
305 if (false == isHT) {
306 switch (desc_rate) {
307 case DESC92C_RATE1M:
308 rate_idx = 0;
309 break;
310 case DESC92C_RATE2M:
311 rate_idx = 1;
312 break;
313 case DESC92C_RATE5_5M:
314 rate_idx = 2;
315 break;
316 case DESC92C_RATE11M:
317 rate_idx = 3;
318 break;
319 case DESC92C_RATE6M:
320 rate_idx = 4;
321 break;
322 case DESC92C_RATE9M:
323 rate_idx = 5;
324 break;
325 case DESC92C_RATE12M:
326 rate_idx = 6;
327 break;
328 case DESC92C_RATE18M:
329 rate_idx = 7;
330 break;
331 case DESC92C_RATE24M:
332 rate_idx = 8;
333 break;
334 case DESC92C_RATE36M:
335 rate_idx = 9;
336 break;
337 case DESC92C_RATE48M:
338 rate_idx = 10;
339 break;
340 case DESC92C_RATE54M:
341 rate_idx = 11;
342 break;
343 default:
344 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
345 ("Rate %d is not support, set to "
346 "1M rate.\n", desc_rate));
347 rate_idx = 0;
348 break;
349 }
350 } else {
351 rate_idx = 11;
352 }
353 return rate_idx;
354 }
355 switch (desc_rate) {
356 case DESC92C_RATE1M:
357 rate_idx = 0;
358 break;
359 case DESC92C_RATE2M:
360 rate_idx = 1;
361 break;
362 case DESC92C_RATE5_5M:
363 rate_idx = 2;
364 break;
365 case DESC92C_RATE11M:
366 rate_idx = 3;
367 break;
368 case DESC92C_RATE6M:
369 rate_idx = 4;
370 break;
371 case DESC92C_RATE9M:
372 rate_idx = 5;
373 break;
374 case DESC92C_RATE12M:
375 rate_idx = 6;
376 break;
377 case DESC92C_RATE18M:
378 rate_idx = 7;
379 break;
380 case DESC92C_RATE24M:
381 rate_idx = 8;
382 break;
383 case DESC92C_RATE36M:
384 rate_idx = 9;
385 break;
386 case DESC92C_RATE48M:
387 rate_idx = 10;
388 break;
389 case DESC92C_RATE54M:
390 rate_idx = 11;
391 break;
392 /* TODO: How to mapping MCS rate? */
393 /* NOTE: referenc to __ieee80211_rx */
394 default:
395 rate_idx = 11;
396 break;
397 }
398 return rate_idx;
399 }
400
401 #endif
402