1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #ifndef __RTL_PCI_H__
31 #define __RTL_PCI_H__
32
33 #include <linux/pci.h>
34 /*
35 1: MSDU packet queue,
36 2: Rx Command Queue
37 */
38 #define RTL_PCI_RX_MPDU_QUEUE 0
39 #define RTL_PCI_RX_CMD_QUEUE 1
40 #define RTL_PCI_MAX_RX_QUEUE 2
41
42 #define RTL_PCI_MAX_RX_COUNT 64
43 #define RTL_PCI_MAX_TX_QUEUE_COUNT 9
44
45 #define RT_TXDESC_NUM 128
46 #define RT_TXDESC_NUM_BE_QUEUE 256
47
48 #define BK_QUEUE 0
49 #define BE_QUEUE 1
50 #define VI_QUEUE 2
51 #define VO_QUEUE 3
52 #define BEACON_QUEUE 4
53 #define TXCMD_QUEUE 5
54 #define MGNT_QUEUE 6
55 #define HIGH_QUEUE 7
56 #define HCCA_QUEUE 8
57
58 #define RTL_PCI_DEVICE(vend, dev, cfg) \
59 .vendor = (vend), \
60 .device = (dev), \
61 .subvendor = PCI_ANY_ID, \
62 .subdevice = PCI_ANY_ID,\
63 .driver_data = (kernel_ulong_t)&(cfg)
64
65 #define INTEL_VENDOR_ID 0x8086
66 #define SIS_VENDOR_ID 0x1039
67 #define ATI_VENDOR_ID 0x1002
68 #define ATI_DEVICE_ID 0x7914
69 #define AMD_VENDOR_ID 0x1022
70
71 #define PCI_MAX_BRIDGE_NUMBER 255
72 #define PCI_MAX_DEVICES 32
73 #define PCI_MAX_FUNCTION 8
74
75 #define PCI_CONF_ADDRESS 0x0CF8 /*PCI Configuration Space Address */
76 #define PCI_CONF_DATA 0x0CFC /*PCI Configuration Space Data */
77
78 #define PCI_CLASS_BRIDGE_DEV 0x06
79 #define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
80 #define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10
81 #define PCI_CAP_ID_EXP 0x10
82
83 #define U1DONTCARE 0xFF
84 #define U2DONTCARE 0xFFFF
85 #define U4DONTCARE 0xFFFFFFFF
86
87 #define RTL_PCI_8192_DID 0x8192 /*8192 PCI-E */
88 #define RTL_PCI_8192SE_DID 0x8192 /*8192 SE */
89 #define RTL_PCI_8174_DID 0x8174 /*8192 SE */
90 #define RTL_PCI_8173_DID 0x8173 /*8191 SE Crab */
91 #define RTL_PCI_8172_DID 0x8172 /*8191 SE RE */
92 #define RTL_PCI_8171_DID 0x8171 /*8191 SE Unicron */
93 #define RTL_PCI_0045_DID 0x0045 /*8190 PCI for Ceraga */
94 #define RTL_PCI_0046_DID 0x0046 /*8190 Cardbus for Ceraga */
95 #define RTL_PCI_0044_DID 0x0044 /*8192e PCIE for Ceraga */
96 #define RTL_PCI_0047_DID 0x0047 /*8192e Express Card for Ceraga */
97 #define RTL_PCI_700F_DID 0x700F
98 #define RTL_PCI_701F_DID 0x701F
99 #define RTL_PCI_DLINK_DID 0x3304
100 #define RTL_PCI_8192CET_DID 0x8191 /*8192ce */
101 #define RTL_PCI_8192CE_DID 0x8178 /*8192ce */
102 #define RTL_PCI_8191CE_DID 0x8177 /*8192ce */
103 #define RTL_PCI_8188CE_DID 0x8176 /*8192ce */
104 #define RTL_PCI_8192CU_DID 0x8191 /*8192ce */
105 #define RTL_PCI_8192DE_DID 0x092D /*8192ce */
106 #define RTL_PCI_8192DU_DID 0x092D /*8192ce */
107
108 /*8192 support 16 pages of IO registers*/
109 #define RTL_MEM_MAPPED_IO_RANGE_8190PCI 0x1000
110 #define RTL_MEM_MAPPED_IO_RANGE_8192PCIE 0x4000
111 #define RTL_MEM_MAPPED_IO_RANGE_8192SE 0x4000
112 #define RTL_MEM_MAPPED_IO_RANGE_8192CE 0x4000
113 #define RTL_MEM_MAPPED_IO_RANGE_8192DE 0x4000
114
115 #define RTL_PCI_REVISION_ID_8190PCI 0x00
116 #define RTL_PCI_REVISION_ID_8192PCIE 0x01
117 #define RTL_PCI_REVISION_ID_8192SE 0x10
118 #define RTL_PCI_REVISION_ID_8192CE 0x1
119 #define RTL_PCI_REVISION_ID_8192DE 0x0
120
121 #define RTL_DEFAULT_HARDWARE_TYPE HARDWARE_TYPE_RTL8192CE
122
123 enum pci_bridge_vendor {
124 PCI_BRIDGE_VENDOR_INTEL = 0x0, /*0b'0000,0001 */
125 PCI_BRIDGE_VENDOR_ATI, /*0b'0000,0010*/
126 PCI_BRIDGE_VENDOR_AMD, /*0b'0000,0100*/
127 PCI_BRIDGE_VENDOR_SIS, /*0b'0000,1000*/
128 PCI_BRIDGE_VENDOR_UNKNOWN, /*0b'0100,0000*/
129 PCI_BRIDGE_VENDOR_MAX,
130 };
131
132 struct rtl_rx_desc {
133 u32 dword[8];
134 } __packed;
135
136 struct rtl_tx_desc {
137 u32 dword[16];
138 } __packed;
139
140 struct rtl_tx_cmd_desc {
141 u32 dword[16];
142 } __packed;
143
144 struct rtl8192_tx_ring {
145 struct rtl_tx_desc *desc;
146 dma_addr_t dma;
147 unsigned int idx;
148 unsigned int entries;
149 struct sk_buff_head queue;
150 };
151
152 struct rtl8192_rx_ring {
153 struct rtl_rx_desc *desc;
154 dma_addr_t dma;
155 unsigned int idx;
156 struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
157 };
158
159 struct rtl_pci {
160 struct pci_dev *pdev;
161
162 bool driver_is_goingto_unload;
163 bool up_first_time;
164 bool being_init_adapter;
165 bool irq_enabled;
166
167 /*Tx */
168 struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
169 int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT];
170 u32 transmit_config;
171
172 /*Rx */
173 struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE];
174 int rxringcount;
175 u16 rxbuffersize;
176 u32 receive_config;
177
178 /*irq */
179 u8 irq_alloc;
180 u32 irq_mask[2];
181
182 /*Bcn control register setting */
183 u32 reg_bcn_ctrl_val;
184
185 /*ASPM*/ u8 const_pci_aspm;
186 u8 const_amdpci_aspm;
187 u8 const_hwsw_rfoff_d3;
188 u8 const_support_pciaspm;
189 /*pci-e bridge */
190 u8 const_hostpci_aspm_setting;
191 /*pci-e device */
192 u8 const_devicepci_aspm_setting;
193 /*If it supports ASPM, Offset[560h] = 0x40,
194 otherwise Offset[560h] = 0x00. */
195 bool b_support_aspm;
196 bool b_support_backdoor;
197
198 /*QOS & EDCA */
199 enum acm_method acm_method;
200 };
201
202 struct mp_adapter {
203 u8 linkctrl_reg;
204
205 u8 busnumber;
206 u8 devnumber;
207 u8 funcnumber;
208
209 u8 pcibridge_busnum;
210 u8 pcibridge_devnum;
211 u8 pcibridge_funcnum;
212
213 u8 pcibridge_vendor;
214 u16 pcibridge_vendorid;
215 u16 pcibridge_deviceid;
216
217 u32 pcicfg_addrport;
218 u8 num4bytes;
219
220 u8 pcibridge_pciehdr_offset;
221 u8 pcibridge_linkctrlreg;
222
223 bool amd_l1_patch;
224 };
225
226 struct rtl_pci_priv {
227 struct rtl_pci dev;
228 struct mp_adapter ndis_adapter;
229 struct rtl_led_ctl ledctl;
230 };
231
232 #define rtl_pcipriv(hw) (((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
233 #define rtl_pcidev(pcipriv) (&((pcipriv)->dev))
234
235 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw);
236
237 extern struct rtl_intf_ops rtl_pci_ops;
238
239 int __devinit rtl_pci_probe(struct pci_dev *pdev,
240 const struct pci_device_id *id);
241 void rtl_pci_disconnect(struct pci_dev *pdev);
242 int rtl_pci_suspend(struct pci_dev *pdev, pm_message_t state);
243 int rtl_pci_resume(struct pci_dev *pdev);
244
pci_read8_sync(struct rtl_priv * rtlpriv,u32 addr)245 static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
246 {
247 return readb((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
248 }
249
pci_read16_sync(struct rtl_priv * rtlpriv,u32 addr)250 static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
251 {
252 return readw((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
253 }
254
pci_read32_sync(struct rtl_priv * rtlpriv,u32 addr)255 static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
256 {
257 return readl((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
258 }
259
pci_write8_async(struct rtl_priv * rtlpriv,u32 addr,u8 val)260 static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
261 {
262 writeb(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
263 }
264
pci_write16_async(struct rtl_priv * rtlpriv,u32 addr,u16 val)265 static inline void pci_write16_async(struct rtl_priv *rtlpriv,
266 u32 addr, u16 val)
267 {
268 writew(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
269 }
270
pci_write32_async(struct rtl_priv * rtlpriv,u32 addr,u32 val)271 static inline void pci_write32_async(struct rtl_priv *rtlpriv,
272 u32 addr, u32 val)
273 {
274 writel(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
275 }
276
rtl_pci_raw_write_port_ulong(u32 port,u32 val)277 static inline void rtl_pci_raw_write_port_ulong(u32 port, u32 val)
278 {
279 outl(val, port);
280 }
281
rtl_pci_raw_write_port_uchar(u32 port,u8 val)282 static inline void rtl_pci_raw_write_port_uchar(u32 port, u8 val)
283 {
284 outb(val, port);
285 }
286
rtl_pci_raw_read_port_uchar(u32 port,u8 * pval)287 static inline void rtl_pci_raw_read_port_uchar(u32 port, u8 *pval)
288 {
289 *pval = inb(port);
290 }
291
rtl_pci_raw_read_port_ushort(u32 port,u16 * pval)292 static inline void rtl_pci_raw_read_port_ushort(u32 port, u16 *pval)
293 {
294 *pval = inw(port);
295 }
296
rtl_pci_raw_read_port_ulong(u32 port,u32 * pval)297 static inline void rtl_pci_raw_read_port_ulong(u32 port, u32 *pval)
298 {
299 *pval = inl(port);
300 }
301
302 #endif
303