1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef REG_H 18 #define REG_H 19 20 #include "../reg.h" 21 22 #define AR_CR 0x0008 23 #define AR_CR_RXE (AR_SREV_9300_20_OR_LATER(ah) ? 0x0000000c : 0x00000004) 24 #define AR_CR_RXD 0x00000020 25 #define AR_CR_SWI 0x00000040 26 27 #define AR_RXDP 0x000C 28 29 #define AR_CFG 0x0014 30 #define AR_CFG_SWTD 0x00000001 31 #define AR_CFG_SWTB 0x00000002 32 #define AR_CFG_SWRD 0x00000004 33 #define AR_CFG_SWRB 0x00000008 34 #define AR_CFG_SWRG 0x00000010 35 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 36 #define AR_CFG_PHOK 0x00000100 37 #define AR_CFG_CLK_GATE_DIS 0x00000400 38 #define AR_CFG_EEBS 0x00000200 39 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 40 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 41 42 #define AR_RXBP_THRESH 0x0018 43 #define AR_RXBP_THRESH_HP 0x0000000f 44 #define AR_RXBP_THRESH_HP_S 0 45 #define AR_RXBP_THRESH_LP 0x00003f00 46 #define AR_RXBP_THRESH_LP_S 8 47 48 #define AR_MIRT 0x0020 49 #define AR_MIRT_VAL 0x0000ffff 50 #define AR_MIRT_VAL_S 16 51 52 #define AR_IER 0x0024 53 #define AR_IER_ENABLE 0x00000001 54 #define AR_IER_DISABLE 0x00000000 55 56 #define AR_TIMT 0x0028 57 #define AR_TIMT_LAST 0x0000ffff 58 #define AR_TIMT_LAST_S 0 59 #define AR_TIMT_FIRST 0xffff0000 60 #define AR_TIMT_FIRST_S 16 61 62 #define AR_RIMT 0x002C 63 #define AR_RIMT_LAST 0x0000ffff 64 #define AR_RIMT_LAST_S 0 65 #define AR_RIMT_FIRST 0xffff0000 66 #define AR_RIMT_FIRST_S 16 67 68 #define AR_DMASIZE_4B 0x00000000 69 #define AR_DMASIZE_8B 0x00000001 70 #define AR_DMASIZE_16B 0x00000002 71 #define AR_DMASIZE_32B 0x00000003 72 #define AR_DMASIZE_64B 0x00000004 73 #define AR_DMASIZE_128B 0x00000005 74 #define AR_DMASIZE_256B 0x00000006 75 #define AR_DMASIZE_512B 0x00000007 76 77 #define AR_TXCFG 0x0030 78 #define AR_TXCFG_DMASZ_MASK 0x00000007 79 #define AR_TXCFG_DMASZ_4B 0 80 #define AR_TXCFG_DMASZ_8B 1 81 #define AR_TXCFG_DMASZ_16B 2 82 #define AR_TXCFG_DMASZ_32B 3 83 #define AR_TXCFG_DMASZ_64B 4 84 #define AR_TXCFG_DMASZ_128B 5 85 #define AR_TXCFG_DMASZ_256B 6 86 #define AR_TXCFG_DMASZ_512B 7 87 #define AR_FTRIG 0x000003F0 88 #define AR_FTRIG_S 4 89 #define AR_FTRIG_IMMED 0x00000000 90 #define AR_FTRIG_64B 0x00000010 91 #define AR_FTRIG_128B 0x00000020 92 #define AR_FTRIG_192B 0x00000030 93 #define AR_FTRIG_256B 0x00000040 94 #define AR_FTRIG_512B 0x00000080 95 #define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800 96 97 #define AR_RXCFG 0x0034 98 #define AR_RXCFG_CHIRP 0x00000008 99 #define AR_RXCFG_ZLFDMA 0x00000010 100 #define AR_RXCFG_DMASZ_MASK 0x00000007 101 #define AR_RXCFG_DMASZ_4B 0 102 #define AR_RXCFG_DMASZ_8B 1 103 #define AR_RXCFG_DMASZ_16B 2 104 #define AR_RXCFG_DMASZ_32B 3 105 #define AR_RXCFG_DMASZ_64B 4 106 #define AR_RXCFG_DMASZ_128B 5 107 #define AR_RXCFG_DMASZ_256B 6 108 #define AR_RXCFG_DMASZ_512B 7 109 110 #define AR_TOPS 0x0044 111 #define AR_TOPS_MASK 0x0000FFFF 112 113 #define AR_RXNPTO 0x0048 114 #define AR_RXNPTO_MASK 0x000003FF 115 116 #define AR_TXNPTO 0x004C 117 #define AR_TXNPTO_MASK 0x000003FF 118 #define AR_TXNPTO_QCU_MASK 0x000FFC00 119 120 #define AR_RPGTO 0x0050 121 #define AR_RPGTO_MASK 0x000003FF 122 123 #define AR_RPCNT 0x0054 124 #define AR_RPCNT_MASK 0x0000001F 125 126 #define AR_MACMISC 0x0058 127 #define AR_MACMISC_PCI_EXT_FORCE 0x00000010 128 #define AR_MACMISC_DMA_OBS 0x000001E0 129 #define AR_MACMISC_DMA_OBS_S 5 130 #define AR_MACMISC_DMA_OBS_LINE_0 0 131 #define AR_MACMISC_DMA_OBS_LINE_1 1 132 #define AR_MACMISC_DMA_OBS_LINE_2 2 133 #define AR_MACMISC_DMA_OBS_LINE_3 3 134 #define AR_MACMISC_DMA_OBS_LINE_4 4 135 #define AR_MACMISC_DMA_OBS_LINE_5 5 136 #define AR_MACMISC_DMA_OBS_LINE_6 6 137 #define AR_MACMISC_DMA_OBS_LINE_7 7 138 #define AR_MACMISC_DMA_OBS_LINE_8 8 139 #define AR_MACMISC_MISC_OBS 0x00000E00 140 #define AR_MACMISC_MISC_OBS_S 9 141 #define AR_MACMISC_MISC_OBS_BUS_LSB 0x00007000 142 #define AR_MACMISC_MISC_OBS_BUS_LSB_S 12 143 #define AR_MACMISC_MISC_OBS_BUS_MSB 0x00038000 144 #define AR_MACMISC_MISC_OBS_BUS_MSB_S 15 145 #define AR_MACMISC_MISC_OBS_BUS_1 1 146 147 #define AR_DATABUF_SIZE 0x0060 148 #define AR_DATABUF_SIZE_MASK 0x00000FFF 149 150 #define AR_GTXTO 0x0064 151 #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF 152 #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 153 #define AR_GTXTO_TIMEOUT_LIMIT_S 16 154 155 #define AR_GTTM 0x0068 156 #define AR_GTTM_USEC 0x00000001 157 #define AR_GTTM_IGNORE_IDLE 0x00000002 158 #define AR_GTTM_RESET_IDLE 0x00000004 159 #define AR_GTTM_CST_USEC 0x00000008 160 161 #define AR_CST 0x006C 162 #define AR_CST_TIMEOUT_COUNTER 0x0000FFFF 163 #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 164 #define AR_CST_TIMEOUT_LIMIT_S 16 165 166 #define AR_HP_RXDP 0x0074 167 #define AR_LP_RXDP 0x0078 168 169 #define AR_ISR 0x0080 170 #define AR_ISR_RXOK 0x00000001 171 #define AR_ISR_RXDESC 0x00000002 172 #define AR_ISR_HP_RXOK 0x00000001 173 #define AR_ISR_LP_RXOK 0x00000002 174 #define AR_ISR_RXERR 0x00000004 175 #define AR_ISR_RXNOPKT 0x00000008 176 #define AR_ISR_RXEOL 0x00000010 177 #define AR_ISR_RXORN 0x00000020 178 #define AR_ISR_TXOK 0x00000040 179 #define AR_ISR_TXDESC 0x00000080 180 #define AR_ISR_TXERR 0x00000100 181 #define AR_ISR_TXNOPKT 0x00000200 182 #define AR_ISR_TXEOL 0x00000400 183 #define AR_ISR_TXURN 0x00000800 184 #define AR_ISR_MIB 0x00001000 185 #define AR_ISR_SWI 0x00002000 186 #define AR_ISR_RXPHY 0x00004000 187 #define AR_ISR_RXKCM 0x00008000 188 #define AR_ISR_SWBA 0x00010000 189 #define AR_ISR_BRSSI 0x00020000 190 #define AR_ISR_BMISS 0x00040000 191 #define AR_ISR_BNR 0x00100000 192 #define AR_ISR_RXCHIRP 0x00200000 193 #define AR_ISR_BCNMISC 0x00800000 194 #define AR_ISR_TIM 0x00800000 195 #define AR_ISR_QCBROVF 0x02000000 196 #define AR_ISR_QCBRURN 0x04000000 197 #define AR_ISR_QTRIG 0x08000000 198 #define AR_ISR_GENTMR 0x10000000 199 200 #define AR_ISR_TXMINTR 0x00080000 201 #define AR_ISR_RXMINTR 0x01000000 202 #define AR_ISR_TXINTM 0x40000000 203 #define AR_ISR_RXINTM 0x80000000 204 205 #define AR_ISR_S0 0x0084 206 #define AR_ISR_S0_QCU_TXOK 0x000003FF 207 #define AR_ISR_S0_QCU_TXOK_S 0 208 #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 209 #define AR_ISR_S0_QCU_TXDESC_S 16 210 211 #define AR_ISR_S1 0x0088 212 #define AR_ISR_S1_QCU_TXERR 0x000003FF 213 #define AR_ISR_S1_QCU_TXERR_S 0 214 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 215 #define AR_ISR_S1_QCU_TXEOL_S 16 216 217 #define AR_ISR_S2 0x008c 218 #define AR_ISR_S2_QCU_TXURN 0x000003FF 219 #define AR_ISR_S2_BB_WATCHDOG 0x00010000 220 #define AR_ISR_S2_CST 0x00400000 221 #define AR_ISR_S2_GTT 0x00800000 222 #define AR_ISR_S2_TIM 0x01000000 223 #define AR_ISR_S2_CABEND 0x02000000 224 #define AR_ISR_S2_DTIMSYNC 0x04000000 225 #define AR_ISR_S2_BCNTO 0x08000000 226 #define AR_ISR_S2_CABTO 0x10000000 227 #define AR_ISR_S2_DTIM 0x20000000 228 #define AR_ISR_S2_TSFOOR 0x40000000 229 #define AR_ISR_S2_TBTT_TIME 0x80000000 230 231 #define AR_ISR_S3 0x0090 232 #define AR_ISR_S3_QCU_QCBROVF 0x000003FF 233 #define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 234 235 #define AR_ISR_S4 0x0094 236 #define AR_ISR_S4_QCU_QTRIG 0x000003FF 237 #define AR_ISR_S4_RESV0 0xFFFFFC00 238 239 #define AR_ISR_S5 0x0098 240 #define AR_ISR_S5_TIMER_TRIG 0x000000FF 241 #define AR_ISR_S5_TIMER_THRESH 0x0007FE00 242 #define AR_ISR_S5_TIM_TIMER 0x00000010 243 #define AR_ISR_S5_DTIM_TIMER 0x00000020 244 #define AR_IMR_S5 0x00b8 245 #define AR_IMR_S5_TIM_TIMER 0x00000010 246 #define AR_IMR_S5_DTIM_TIMER 0x00000020 247 #define AR_ISR_S5_GENTIMER_TRIG 0x0000FF80 248 #define AR_ISR_S5_GENTIMER_TRIG_S 0 249 #define AR_ISR_S5_GENTIMER_THRESH 0xFF800000 250 #define AR_ISR_S5_GENTIMER_THRESH_S 16 251 #define AR_IMR_S5_GENTIMER_TRIG 0x0000FF80 252 #define AR_IMR_S5_GENTIMER_TRIG_S 0 253 #define AR_IMR_S5_GENTIMER_THRESH 0xFF800000 254 #define AR_IMR_S5_GENTIMER_THRESH_S 16 255 256 #define AR_IMR 0x00a0 257 #define AR_IMR_RXOK 0x00000001 258 #define AR_IMR_RXDESC 0x00000002 259 #define AR_IMR_RXOK_HP 0x00000001 260 #define AR_IMR_RXOK_LP 0x00000002 261 #define AR_IMR_RXERR 0x00000004 262 #define AR_IMR_RXNOPKT 0x00000008 263 #define AR_IMR_RXEOL 0x00000010 264 #define AR_IMR_RXORN 0x00000020 265 #define AR_IMR_TXOK 0x00000040 266 #define AR_IMR_TXDESC 0x00000080 267 #define AR_IMR_TXERR 0x00000100 268 #define AR_IMR_TXNOPKT 0x00000200 269 #define AR_IMR_TXEOL 0x00000400 270 #define AR_IMR_TXURN 0x00000800 271 #define AR_IMR_MIB 0x00001000 272 #define AR_IMR_SWI 0x00002000 273 #define AR_IMR_RXPHY 0x00004000 274 #define AR_IMR_RXKCM 0x00008000 275 #define AR_IMR_SWBA 0x00010000 276 #define AR_IMR_BRSSI 0x00020000 277 #define AR_IMR_BMISS 0x00040000 278 #define AR_IMR_BNR 0x00100000 279 #define AR_IMR_RXCHIRP 0x00200000 280 #define AR_IMR_BCNMISC 0x00800000 281 #define AR_IMR_TIM 0x00800000 282 #define AR_IMR_QCBROVF 0x02000000 283 #define AR_IMR_QCBRURN 0x04000000 284 #define AR_IMR_QTRIG 0x08000000 285 #define AR_IMR_GENTMR 0x10000000 286 287 #define AR_IMR_TXMINTR 0x00080000 288 #define AR_IMR_RXMINTR 0x01000000 289 #define AR_IMR_TXINTM 0x40000000 290 #define AR_IMR_RXINTM 0x80000000 291 292 #define AR_IMR_S0 0x00a4 293 #define AR_IMR_S0_QCU_TXOK 0x000003FF 294 #define AR_IMR_S0_QCU_TXOK_S 0 295 #define AR_IMR_S0_QCU_TXDESC 0x03FF0000 296 #define AR_IMR_S0_QCU_TXDESC_S 16 297 298 #define AR_IMR_S1 0x00a8 299 #define AR_IMR_S1_QCU_TXERR 0x000003FF 300 #define AR_IMR_S1_QCU_TXERR_S 0 301 #define AR_IMR_S1_QCU_TXEOL 0x03FF0000 302 #define AR_IMR_S1_QCU_TXEOL_S 16 303 304 #define AR_IMR_S2 0x00ac 305 #define AR_IMR_S2_QCU_TXURN 0x000003FF 306 #define AR_IMR_S2_QCU_TXURN_S 0 307 #define AR_IMR_S2_CST 0x00400000 308 #define AR_IMR_S2_GTT 0x00800000 309 #define AR_IMR_S2_TIM 0x01000000 310 #define AR_IMR_S2_CABEND 0x02000000 311 #define AR_IMR_S2_DTIMSYNC 0x04000000 312 #define AR_IMR_S2_BCNTO 0x08000000 313 #define AR_IMR_S2_CABTO 0x10000000 314 #define AR_IMR_S2_DTIM 0x20000000 315 #define AR_IMR_S2_TSFOOR 0x40000000 316 317 #define AR_IMR_S3 0x00b0 318 #define AR_IMR_S3_QCU_QCBROVF 0x000003FF 319 #define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 320 #define AR_IMR_S3_QCU_QCBRURN_S 16 321 322 #define AR_IMR_S4 0x00b4 323 #define AR_IMR_S4_QCU_QTRIG 0x000003FF 324 #define AR_IMR_S4_RESV0 0xFFFFFC00 325 326 #define AR_IMR_S5 0x00b8 327 #define AR_IMR_S5_TIMER_TRIG 0x000000FF 328 #define AR_IMR_S5_TIMER_THRESH 0x0000FF00 329 330 331 #define AR_ISR_RAC 0x00c0 332 #define AR_ISR_S0_S 0x00c4 333 #define AR_ISR_S0_QCU_TXOK 0x000003FF 334 #define AR_ISR_S0_QCU_TXOK_S 0 335 #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 336 #define AR_ISR_S0_QCU_TXDESC_S 16 337 338 #define AR_ISR_S1_S 0x00c8 339 #define AR_ISR_S1_QCU_TXERR 0x000003FF 340 #define AR_ISR_S1_QCU_TXERR_S 0 341 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 342 #define AR_ISR_S1_QCU_TXEOL_S 16 343 344 #define AR_ISR_S2_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d0 : 0x00cc) 345 #define AR_ISR_S3_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d4 : 0x00d0) 346 #define AR_ISR_S4_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d8 : 0x00d4) 347 #define AR_ISR_S5_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00dc : 0x00d8) 348 #define AR_DMADBG_0 0x00e0 349 #define AR_DMADBG_1 0x00e4 350 #define AR_DMADBG_2 0x00e8 351 #define AR_DMADBG_3 0x00ec 352 #define AR_DMADBG_4 0x00f0 353 #define AR_DMADBG_5 0x00f4 354 #define AR_DMADBG_6 0x00f8 355 #define AR_DMADBG_7 0x00fc 356 357 #define AR_NUM_QCU 10 358 #define AR_QCU_0 0x0001 359 #define AR_QCU_1 0x0002 360 #define AR_QCU_2 0x0004 361 #define AR_QCU_3 0x0008 362 #define AR_QCU_4 0x0010 363 #define AR_QCU_5 0x0020 364 #define AR_QCU_6 0x0040 365 #define AR_QCU_7 0x0080 366 #define AR_QCU_8 0x0100 367 #define AR_QCU_9 0x0200 368 369 #define AR_Q0_TXDP 0x0800 370 #define AR_Q1_TXDP 0x0804 371 #define AR_Q2_TXDP 0x0808 372 #define AR_Q3_TXDP 0x080c 373 #define AR_Q4_TXDP 0x0810 374 #define AR_Q5_TXDP 0x0814 375 #define AR_Q6_TXDP 0x0818 376 #define AR_Q7_TXDP 0x081c 377 #define AR_Q8_TXDP 0x0820 378 #define AR_Q9_TXDP 0x0824 379 #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2)) 380 381 #define AR_Q_STATUS_RING_START 0x830 382 #define AR_Q_STATUS_RING_END 0x834 383 384 #define AR_Q_TXE 0x0840 385 #define AR_Q_TXE_M 0x000003FF 386 387 #define AR_Q_TXD 0x0880 388 #define AR_Q_TXD_M 0x000003FF 389 390 #define AR_Q0_CBRCFG 0x08c0 391 #define AR_Q1_CBRCFG 0x08c4 392 #define AR_Q2_CBRCFG 0x08c8 393 #define AR_Q3_CBRCFG 0x08cc 394 #define AR_Q4_CBRCFG 0x08d0 395 #define AR_Q5_CBRCFG 0x08d4 396 #define AR_Q6_CBRCFG 0x08d8 397 #define AR_Q7_CBRCFG 0x08dc 398 #define AR_Q8_CBRCFG 0x08e0 399 #define AR_Q9_CBRCFG 0x08e4 400 #define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2)) 401 #define AR_Q_CBRCFG_INTERVAL 0x00FFFFFF 402 #define AR_Q_CBRCFG_INTERVAL_S 0 403 #define AR_Q_CBRCFG_OVF_THRESH 0xFF000000 404 #define AR_Q_CBRCFG_OVF_THRESH_S 24 405 406 #define AR_Q0_RDYTIMECFG 0x0900 407 #define AR_Q1_RDYTIMECFG 0x0904 408 #define AR_Q2_RDYTIMECFG 0x0908 409 #define AR_Q3_RDYTIMECFG 0x090c 410 #define AR_Q4_RDYTIMECFG 0x0910 411 #define AR_Q5_RDYTIMECFG 0x0914 412 #define AR_Q6_RDYTIMECFG 0x0918 413 #define AR_Q7_RDYTIMECFG 0x091c 414 #define AR_Q8_RDYTIMECFG 0x0920 415 #define AR_Q9_RDYTIMECFG 0x0924 416 #define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2)) 417 #define AR_Q_RDYTIMECFG_DURATION 0x00FFFFFF 418 #define AR_Q_RDYTIMECFG_DURATION_S 0 419 #define AR_Q_RDYTIMECFG_EN 0x01000000 420 421 #define AR_Q_ONESHOTARM_SC 0x0940 422 #define AR_Q_ONESHOTARM_SC_M 0x000003FF 423 #define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00 424 425 #define AR_Q_ONESHOTARM_CC 0x0980 426 #define AR_Q_ONESHOTARM_CC_M 0x000003FF 427 #define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00 428 429 #define AR_Q0_MISC 0x09c0 430 #define AR_Q1_MISC 0x09c4 431 #define AR_Q2_MISC 0x09c8 432 #define AR_Q3_MISC 0x09cc 433 #define AR_Q4_MISC 0x09d0 434 #define AR_Q5_MISC 0x09d4 435 #define AR_Q6_MISC 0x09d8 436 #define AR_Q7_MISC 0x09dc 437 #define AR_Q8_MISC 0x09e0 438 #define AR_Q9_MISC 0x09e4 439 #define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2)) 440 #define AR_Q_MISC_FSP 0x0000000F 441 #define AR_Q_MISC_FSP_ASAP 0 442 #define AR_Q_MISC_FSP_CBR 1 443 #define AR_Q_MISC_FSP_DBA_GATED 2 444 #define AR_Q_MISC_FSP_TIM_GATED 3 445 #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 446 #define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5 447 #define AR_Q_MISC_ONE_SHOT_EN 0x00000010 448 #define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 449 #define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 450 #define AR_Q_MISC_BEACON_USE 0x00000080 451 #define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100 452 #define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 453 #define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 454 #define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 455 #define AR_Q_MISC_RESV0 0xFFFFF000 456 457 #define AR_Q0_STS 0x0a00 458 #define AR_Q1_STS 0x0a04 459 #define AR_Q2_STS 0x0a08 460 #define AR_Q3_STS 0x0a0c 461 #define AR_Q4_STS 0x0a10 462 #define AR_Q5_STS 0x0a14 463 #define AR_Q6_STS 0x0a18 464 #define AR_Q7_STS 0x0a1c 465 #define AR_Q8_STS 0x0a20 466 #define AR_Q9_STS 0x0a24 467 #define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2)) 468 #define AR_Q_STS_PEND_FR_CNT 0x00000003 469 #define AR_Q_STS_RESV0 0x000000FC 470 #define AR_Q_STS_CBR_EXP_CNT 0x0000FF00 471 #define AR_Q_STS_RESV1 0xFFFF0000 472 473 #define AR_Q_RDYTIMESHDN 0x0a40 474 #define AR_Q_RDYTIMESHDN_M 0x000003FF 475 476 /* MAC Descriptor CRC check */ 477 #define AR_Q_DESC_CRCCHK 0xa44 478 /* Enable CRC check on the descriptor fetched from host */ 479 #define AR_Q_DESC_CRCCHK_EN 1 480 481 #define AR_NUM_DCU 10 482 #define AR_DCU_0 0x0001 483 #define AR_DCU_1 0x0002 484 #define AR_DCU_2 0x0004 485 #define AR_DCU_3 0x0008 486 #define AR_DCU_4 0x0010 487 #define AR_DCU_5 0x0020 488 #define AR_DCU_6 0x0040 489 #define AR_DCU_7 0x0080 490 #define AR_DCU_8 0x0100 491 #define AR_DCU_9 0x0200 492 493 #define AR_D0_QCUMASK 0x1000 494 #define AR_D1_QCUMASK 0x1004 495 #define AR_D2_QCUMASK 0x1008 496 #define AR_D3_QCUMASK 0x100c 497 #define AR_D4_QCUMASK 0x1010 498 #define AR_D5_QCUMASK 0x1014 499 #define AR_D6_QCUMASK 0x1018 500 #define AR_D7_QCUMASK 0x101c 501 #define AR_D8_QCUMASK 0x1020 502 #define AR_D9_QCUMASK 0x1024 503 #define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2)) 504 #define AR_D_QCUMASK 0x000003FF 505 #define AR_D_QCUMASK_RESV0 0xFFFFFC00 506 507 #define AR_D_TXBLK_CMD 0x1038 508 #define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i)) 509 510 #define AR_D0_LCL_IFS 0x1040 511 #define AR_D1_LCL_IFS 0x1044 512 #define AR_D2_LCL_IFS 0x1048 513 #define AR_D3_LCL_IFS 0x104c 514 #define AR_D4_LCL_IFS 0x1050 515 #define AR_D5_LCL_IFS 0x1054 516 #define AR_D6_LCL_IFS 0x1058 517 #define AR_D7_LCL_IFS 0x105c 518 #define AR_D8_LCL_IFS 0x1060 519 #define AR_D9_LCL_IFS 0x1064 520 #define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2)) 521 #define AR_D_LCL_IFS_CWMIN 0x000003FF 522 #define AR_D_LCL_IFS_CWMIN_S 0 523 #define AR_D_LCL_IFS_CWMAX 0x000FFC00 524 #define AR_D_LCL_IFS_CWMAX_S 10 525 #define AR_D_LCL_IFS_AIFS 0x0FF00000 526 #define AR_D_LCL_IFS_AIFS_S 20 527 528 #define AR_D_LCL_IFS_RESV0 0xF0000000 529 530 #define AR_D0_RETRY_LIMIT 0x1080 531 #define AR_D1_RETRY_LIMIT 0x1084 532 #define AR_D2_RETRY_LIMIT 0x1088 533 #define AR_D3_RETRY_LIMIT 0x108c 534 #define AR_D4_RETRY_LIMIT 0x1090 535 #define AR_D5_RETRY_LIMIT 0x1094 536 #define AR_D6_RETRY_LIMIT 0x1098 537 #define AR_D7_RETRY_LIMIT 0x109c 538 #define AR_D8_RETRY_LIMIT 0x10a0 539 #define AR_D9_RETRY_LIMIT 0x10a4 540 #define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2)) 541 #define AR_D_RETRY_LIMIT_FR_SH 0x0000000F 542 #define AR_D_RETRY_LIMIT_FR_SH_S 0 543 #define AR_D_RETRY_LIMIT_STA_SH 0x00003F00 544 #define AR_D_RETRY_LIMIT_STA_SH_S 8 545 #define AR_D_RETRY_LIMIT_STA_LG 0x000FC000 546 #define AR_D_RETRY_LIMIT_STA_LG_S 14 547 #define AR_D_RETRY_LIMIT_RESV0 0xFFF00000 548 549 #define AR_D0_CHNTIME 0x10c0 550 #define AR_D1_CHNTIME 0x10c4 551 #define AR_D2_CHNTIME 0x10c8 552 #define AR_D3_CHNTIME 0x10cc 553 #define AR_D4_CHNTIME 0x10d0 554 #define AR_D5_CHNTIME 0x10d4 555 #define AR_D6_CHNTIME 0x10d8 556 #define AR_D7_CHNTIME 0x10dc 557 #define AR_D8_CHNTIME 0x10e0 558 #define AR_D9_CHNTIME 0x10e4 559 #define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2)) 560 #define AR_D_CHNTIME_DUR 0x000FFFFF 561 #define AR_D_CHNTIME_DUR_S 0 562 #define AR_D_CHNTIME_EN 0x00100000 563 #define AR_D_CHNTIME_RESV0 0xFFE00000 564 565 #define AR_D0_MISC 0x1100 566 #define AR_D1_MISC 0x1104 567 #define AR_D2_MISC 0x1108 568 #define AR_D3_MISC 0x110c 569 #define AR_D4_MISC 0x1110 570 #define AR_D5_MISC 0x1114 571 #define AR_D6_MISC 0x1118 572 #define AR_D7_MISC 0x111c 573 #define AR_D8_MISC 0x1120 574 #define AR_D9_MISC 0x1124 575 #define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2)) 576 #define AR_D_MISC_BKOFF_THRESH 0x0000003F 577 #define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040 578 #define AR_D_MISC_CW_RESET_EN 0x00000080 579 #define AR_D_MISC_FRAG_WAIT_EN 0x00000100 580 #define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 581 #define AR_D_MISC_CW_BKOFF_EN 0x00001000 582 #define AR_D_MISC_VIR_COL_HANDLING 0x0000C000 583 #define AR_D_MISC_VIR_COL_HANDLING_S 14 584 #define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 585 #define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 586 #define AR_D_MISC_BEACON_USE 0x00010000 587 #define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000 588 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 589 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 590 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 591 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 592 #define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 593 #define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 594 #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 595 #define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 596 #define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000 597 #define AR_D_MISC_RESV0 0xFF000000 598 599 #define AR_D_SEQNUM 0x1140 600 601 #define AR_D_GBL_IFS_SIFS 0x1030 602 #define AR_D_GBL_IFS_SIFS_M 0x0000FFFF 603 #define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003AB 604 #define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF 605 606 #define AR_D_TXBLK_BASE 0x1038 607 #define AR_D_TXBLK_WRITE_BITMASK 0x0000FFFF 608 #define AR_D_TXBLK_WRITE_BITMASK_S 0 609 #define AR_D_TXBLK_WRITE_SLICE 0x000F0000 610 #define AR_D_TXBLK_WRITE_SLICE_S 16 611 #define AR_D_TXBLK_WRITE_DCU 0x00F00000 612 #define AR_D_TXBLK_WRITE_DCU_S 20 613 #define AR_D_TXBLK_WRITE_COMMAND 0x0F000000 614 #define AR_D_TXBLK_WRITE_COMMAND_S 24 615 616 #define AR_D_GBL_IFS_SLOT 0x1070 617 #define AR_D_GBL_IFS_SLOT_M 0x0000FFFF 618 #define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000 619 #define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR 0x00000420 620 621 #define AR_D_GBL_IFS_EIFS 0x10b0 622 #define AR_D_GBL_IFS_EIFS_M 0x0000FFFF 623 #define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000 624 #define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR 0x0000A5EB 625 626 #define AR_D_GBL_IFS_MISC 0x10f0 627 #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 628 #define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 629 #define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00 630 #define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 631 #define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 632 #define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000 633 #define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 634 #define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000 635 636 #define AR_D_FPCTL 0x1230 637 #define AR_D_FPCTL_DCU 0x0000000F 638 #define AR_D_FPCTL_DCU_S 0 639 #define AR_D_FPCTL_PREFETCH_EN 0x00000010 640 #define AR_D_FPCTL_BURST_PREFETCH 0x00007FE0 641 #define AR_D_FPCTL_BURST_PREFETCH_S 5 642 643 #define AR_D_TXPSE 0x1270 644 #define AR_D_TXPSE_CTRL 0x000003FF 645 #define AR_D_TXPSE_RESV0 0x0000FC00 646 #define AR_D_TXPSE_STATUS 0x00010000 647 #define AR_D_TXPSE_RESV1 0xFFFE0000 648 649 #define AR_D_TXSLOTMASK 0x12f0 650 #define AR_D_TXSLOTMASK_NUM 0x0000000F 651 652 #define AR_CFG_LED 0x1f04 653 #define AR_CFG_SCLK_RATE_IND 0x00000003 654 #define AR_CFG_SCLK_RATE_IND_S 0 655 #define AR_CFG_SCLK_32MHZ 0x00000000 656 #define AR_CFG_SCLK_4MHZ 0x00000001 657 #define AR_CFG_SCLK_1MHZ 0x00000002 658 #define AR_CFG_SCLK_32KHZ 0x00000003 659 #define AR_CFG_LED_BLINK_SLOW 0x00000008 660 #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 661 #define AR_CFG_LED_MODE_SEL 0x00000380 662 #define AR_CFG_LED_MODE_SEL_S 7 663 #define AR_CFG_LED_POWER 0x00000280 664 #define AR_CFG_LED_POWER_S 7 665 #define AR_CFG_LED_NETWORK 0x00000300 666 #define AR_CFG_LED_NETWORK_S 7 667 #define AR_CFG_LED_MODE_PROP 0x0 668 #define AR_CFG_LED_MODE_RPROP 0x1 669 #define AR_CFG_LED_MODE_SPLIT 0x2 670 #define AR_CFG_LED_MODE_RAND 0x3 671 #define AR_CFG_LED_MODE_POWER_OFF 0x4 672 #define AR_CFG_LED_MODE_POWER_ON 0x5 673 #define AR_CFG_LED_MODE_NETWORK_OFF 0x4 674 #define AR_CFG_LED_MODE_NETWORK_ON 0x6 675 #define AR_CFG_LED_ASSOC_CTL 0x00000c00 676 #define AR_CFG_LED_ASSOC_CTL_S 10 677 #define AR_CFG_LED_ASSOC_NONE 0x0 678 #define AR_CFG_LED_ASSOC_ACTIVE 0x1 679 #define AR_CFG_LED_ASSOC_PENDING 0x2 680 681 #define AR_CFG_LED_BLINK_SLOW 0x00000008 682 #define AR_CFG_LED_BLINK_SLOW_S 3 683 684 #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 685 #define AR_CFG_LED_BLINK_THRESH_SEL_S 4 686 687 #define AR_MAC_SLEEP 0x1f00 688 #define AR_MAC_SLEEP_MAC_AWAKE 0x00000000 689 #define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 690 691 #define AR_RC 0x4000 692 #define AR_RC_AHB 0x00000001 693 #define AR_RC_APB 0x00000002 694 #define AR_RC_HOSTIF 0x00000100 695 696 #define AR_WA 0x4004 697 #define AR_WA_BIT6 (1 << 6) 698 #define AR_WA_BIT7 (1 << 7) 699 #define AR_WA_BIT23 (1 << 23) 700 #define AR_WA_D3_L1_DISABLE (1 << 14) 701 #define AR_WA_D3_TO_L1_DISABLE_REAL (1 << 16) 702 #define AR_WA_ASPM_TIMER_BASED_DISABLE (1 << 17) 703 #define AR_WA_RESET_EN (1 << 18) /* Sw Control to enable PCI-Reset to POR (bit 15) */ 704 #define AR_WA_ANALOG_SHIFT (1 << 20) 705 #define AR_WA_POR_SHORT (1 << 21) /* PCI-E Phy reset control */ 706 #define AR_WA_BIT22 (1 << 22) 707 #define AR9285_WA_DEFAULT 0x004a050b 708 #define AR9280_WA_DEFAULT 0x0040073b 709 #define AR_WA_DEFAULT 0x0000073f 710 711 712 #define AR_PM_STATE 0x4008 713 #define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 714 715 #define AR_HOST_TIMEOUT 0x4018 716 #define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF 717 #define AR_HOST_TIMEOUT_APB_CNTR_S 0 718 #define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000 719 #define AR_HOST_TIMEOUT_LCL_CNTR_S 16 720 721 #define AR_EEPROM 0x401c 722 #define AR_EEPROM_ABSENT 0x00000100 723 #define AR_EEPROM_CORRUPT 0x00000200 724 #define AR_EEPROM_PROT_MASK 0x03FFFC00 725 #define AR_EEPROM_PROT_MASK_S 10 726 727 #define EEPROM_PROTECT_RP_0_31 0x0001 728 #define EEPROM_PROTECT_WP_0_31 0x0002 729 #define EEPROM_PROTECT_RP_32_63 0x0004 730 #define EEPROM_PROTECT_WP_32_63 0x0008 731 #define EEPROM_PROTECT_RP_64_127 0x0010 732 #define EEPROM_PROTECT_WP_64_127 0x0020 733 #define EEPROM_PROTECT_RP_128_191 0x0040 734 #define EEPROM_PROTECT_WP_128_191 0x0080 735 #define EEPROM_PROTECT_RP_192_255 0x0100 736 #define EEPROM_PROTECT_WP_192_255 0x0200 737 #define EEPROM_PROTECT_RP_256_511 0x0400 738 #define EEPROM_PROTECT_WP_256_511 0x0800 739 #define EEPROM_PROTECT_RP_512_1023 0x1000 740 #define EEPROM_PROTECT_WP_512_1023 0x2000 741 #define EEPROM_PROTECT_RP_1024_2047 0x4000 742 #define EEPROM_PROTECT_WP_1024_2047 0x8000 743 744 #define AR_SREV \ 745 ((AR_SREV_9100(ah)) ? 0x0600 : 0x4020) 746 747 #define AR_SREV_ID \ 748 ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF) 749 #define AR_SREV_VERSION 0x000000F0 750 #define AR_SREV_VERSION_S 4 751 #define AR_SREV_REVISION 0x00000007 752 753 #define AR_SREV_ID2 0xFFFFFFFF 754 #define AR_SREV_VERSION2 0xFFFC0000 755 #define AR_SREV_VERSION2_S 18 756 #define AR_SREV_TYPE2 0x0003F000 757 #define AR_SREV_TYPE2_S 12 758 #define AR_SREV_TYPE2_CHAIN 0x00001000 759 #define AR_SREV_TYPE2_HOST_MODE 0x00002000 760 #define AR_SREV_REVISION2 0x00000F00 761 #define AR_SREV_REVISION2_S 8 762 763 #define AR_SREV_VERSION_5416_PCI 0xD 764 #define AR_SREV_VERSION_5416_PCIE 0xC 765 #define AR_SREV_REVISION_5416_10 0 766 #define AR_SREV_REVISION_5416_20 1 767 #define AR_SREV_REVISION_5416_22 2 768 #define AR_SREV_VERSION_9100 0x14 769 #define AR_SREV_VERSION_9160 0x40 770 #define AR_SREV_REVISION_9160_10 0 771 #define AR_SREV_REVISION_9160_11 1 772 #define AR_SREV_VERSION_9280 0x80 773 #define AR_SREV_REVISION_9280_10 0 774 #define AR_SREV_REVISION_9280_20 1 775 #define AR_SREV_REVISION_9280_21 2 776 #define AR_SREV_VERSION_9285 0xC0 777 #define AR_SREV_REVISION_9285_10 0 778 #define AR_SREV_REVISION_9285_11 1 779 #define AR_SREV_REVISION_9285_12 2 780 #define AR_SREV_VERSION_9287 0x180 781 #define AR_SREV_REVISION_9287_10 0 782 #define AR_SREV_REVISION_9287_11 1 783 #define AR_SREV_REVISION_9287_12 2 784 #define AR_SREV_REVISION_9287_13 3 785 #define AR_SREV_VERSION_9271 0x140 786 #define AR_SREV_REVISION_9271_10 0 787 #define AR_SREV_REVISION_9271_11 1 788 #define AR_SREV_VERSION_9300 0x1c0 789 #define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */ 790 #define AR_SREV_VERSION_9485 0x240 791 #define AR_SREV_REVISION_9485_10 0 792 #define AR_SREV_REVISION_9485_11 1 793 794 #define AR_SREV_5416(_ah) \ 795 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \ 796 ((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)) 797 #define AR_SREV_5416_20_OR_LATER(_ah) \ 798 (((AR_SREV_5416(_ah)) && \ 799 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_20)) || \ 800 ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100)) 801 #define AR_SREV_5416_22_OR_LATER(_ah) \ 802 (((AR_SREV_5416(_ah)) && \ 803 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_22)) || \ 804 ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100)) 805 806 #define AR_SREV_9100(ah) \ 807 ((ah->hw_version.macVersion) == AR_SREV_VERSION_9100) 808 #define AR_SREV_9100_OR_LATER(_ah) \ 809 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100)) 810 811 #define AR_SREV_9160(_ah) \ 812 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9160)) 813 #define AR_SREV_9160_10_OR_LATER(_ah) \ 814 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9160)) 815 #define AR_SREV_9160_11(_ah) \ 816 (AR_SREV_9160(_ah) && \ 817 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9160_11)) 818 #define AR_SREV_9280(_ah) \ 819 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280)) 820 #define AR_SREV_9280_20_OR_LATER(_ah) \ 821 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9280)) 822 #define AR_SREV_9280_20(_ah) \ 823 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280)) 824 825 #define AR_SREV_9285(_ah) \ 826 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9285)) 827 #define AR_SREV_9285_12_OR_LATER(_ah) \ 828 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9285)) 829 830 #define AR_SREV_9287(_ah) \ 831 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287)) 832 #define AR_SREV_9287_11_OR_LATER(_ah) \ 833 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9287)) 834 #define AR_SREV_9287_11(_ah) \ 835 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 836 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_11)) 837 #define AR_SREV_9287_12(_ah) \ 838 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 839 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_12)) 840 #define AR_SREV_9287_12_OR_LATER(_ah) \ 841 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \ 842 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 843 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_12))) 844 #define AR_SREV_9287_13_OR_LATER(_ah) \ 845 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \ 846 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 847 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_13))) 848 849 #define AR_SREV_9271(_ah) \ 850 (((_ah))->hw_version.macVersion == AR_SREV_VERSION_9271) 851 #define AR_SREV_9271_10(_ah) \ 852 (AR_SREV_9271(_ah) && \ 853 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_10)) 854 #define AR_SREV_9271_11(_ah) \ 855 (AR_SREV_9271(_ah) && \ 856 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_11)) 857 858 #define AR_SREV_9300(_ah) \ 859 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300)) 860 #define AR_SREV_9300_20_OR_LATER(_ah) \ 861 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9300) || \ 862 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \ 863 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9300_20))) 864 865 #define AR_SREV_9485(_ah) \ 866 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9485)) 867 #define AR_SREV_9485_10(_ah) \ 868 (AR_SREV_9485(_ah) && \ 869 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_10)) 870 #define AR_SREV_9485_11(_ah) \ 871 (AR_SREV_9485(_ah) && \ 872 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_11)) 873 874 #define AR_SREV_9285E_20(_ah) \ 875 (AR_SREV_9285_12_OR_LATER(_ah) && \ 876 ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) 877 878 enum ath_usb_dev { 879 AR9280_USB = 1, /* AR7010 + AR9280, UB94 */ 880 AR9287_USB = 2, /* AR7010 + AR9287, UB95 */ 881 STORAGE_DEVICE = 3, 882 }; 883 884 #define AR_DEVID_7010(_ah) \ 885 (((_ah)->hw_version.usbdev == AR9280_USB) || \ 886 ((_ah)->hw_version.usbdev == AR9287_USB)) 887 888 #define AR_RADIO_SREV_MAJOR 0xf0 889 #define AR_RAD5133_SREV_MAJOR 0xc0 890 #define AR_RAD2133_SREV_MAJOR 0xd0 891 #define AR_RAD5122_SREV_MAJOR 0xe0 892 #define AR_RAD2122_SREV_MAJOR 0xf0 893 894 #define AR_AHB_MODE 0x4024 895 #define AR_AHB_EXACT_WR_EN 0x00000000 896 #define AR_AHB_BUF_WR_EN 0x00000001 897 #define AR_AHB_EXACT_RD_EN 0x00000000 898 #define AR_AHB_CACHELINE_RD_EN 0x00000002 899 #define AR_AHB_PREFETCH_RD_EN 0x00000004 900 #define AR_AHB_PAGE_SIZE_1K 0x00000000 901 #define AR_AHB_PAGE_SIZE_2K 0x00000008 902 #define AR_AHB_PAGE_SIZE_4K 0x00000010 903 #define AR_AHB_CUSTOM_BURST_EN 0x000000C0 904 #define AR_AHB_CUSTOM_BURST_EN_S 6 905 #define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 3 906 907 #define AR_INTR_RTC_IRQ 0x00000001 908 #define AR_INTR_MAC_IRQ 0x00000002 909 #define AR_INTR_EEP_PROT_ACCESS 0x00000004 910 #define AR_INTR_MAC_AWAKE 0x00020000 911 #define AR_INTR_MAC_ASLEEP 0x00040000 912 #define AR_INTR_SPURIOUS 0xFFFFFFFF 913 914 915 #define AR_INTR_SYNC_CAUSE_CLR 0x4028 916 917 #define AR_INTR_SYNC_CAUSE 0x4028 918 919 #define AR_INTR_SYNC_ENABLE 0x402c 920 #define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 921 #define AR_INTR_SYNC_ENABLE_GPIO_S 18 922 923 enum { 924 AR_INTR_SYNC_RTC_IRQ = 0x00000001, 925 AR_INTR_SYNC_MAC_IRQ = 0x00000002, 926 AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004, 927 AR_INTR_SYNC_APB_TIMEOUT = 0x00000008, 928 AR_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010, 929 AR_INTR_SYNC_HOST1_FATAL = 0x00000020, 930 AR_INTR_SYNC_HOST1_PERR = 0x00000040, 931 AR_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080, 932 AR_INTR_SYNC_RADM_CPL_EP = 0x00000100, 933 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200, 934 AR_INTR_SYNC_RADM_CPL_TLP_ABORT = 0x00000400, 935 AR_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800, 936 AR_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000, 937 AR_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000, 938 AR_INTR_SYNC_PM_ACCESS = 0x00004000, 939 AR_INTR_SYNC_MAC_AWAKE = 0x00008000, 940 AR_INTR_SYNC_MAC_ASLEEP = 0x00010000, 941 AR_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000, 942 AR_INTR_SYNC_ALL = 0x0003FFFF, 943 944 945 AR_INTR_SYNC_DEFAULT = (AR_INTR_SYNC_HOST1_FATAL | 946 AR_INTR_SYNC_HOST1_PERR | 947 AR_INTR_SYNC_RADM_CPL_EP | 948 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | 949 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | 950 AR_INTR_SYNC_RADM_CPL_ECRC_ERR | 951 AR_INTR_SYNC_RADM_CPL_TIMEOUT | 952 AR_INTR_SYNC_LOCAL_TIMEOUT | 953 AR_INTR_SYNC_MAC_SLEEP_ACCESS), 954 955 AR_INTR_SYNC_SPURIOUS = 0xFFFFFFFF, 956 957 }; 958 959 #define AR_INTR_ASYNC_MASK 0x4030 960 #define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 961 #define AR_INTR_ASYNC_MASK_GPIO_S 18 962 963 #define AR_INTR_SYNC_MASK 0x4034 964 #define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 965 #define AR_INTR_SYNC_MASK_GPIO_S 18 966 967 #define AR_INTR_ASYNC_CAUSE_CLR 0x4038 968 #define AR_INTR_ASYNC_CAUSE 0x4038 969 970 #define AR_INTR_ASYNC_ENABLE 0x403c 971 #define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 972 #define AR_INTR_ASYNC_ENABLE_GPIO_S 18 973 974 #define AR_PCIE_SERDES 0x4040 975 #define AR_PCIE_SERDES2 0x4044 976 #define AR_PCIE_PM_CTRL 0x4014 977 #define AR_PCIE_PM_CTRL_ENA 0x00080000 978 979 #define AR_NUM_GPIO 14 980 #define AR928X_NUM_GPIO 10 981 #define AR9285_NUM_GPIO 12 982 #define AR9287_NUM_GPIO 11 983 #define AR9271_NUM_GPIO 16 984 #define AR9300_NUM_GPIO 17 985 #define AR7010_NUM_GPIO 16 986 987 #define AR_GPIO_IN_OUT 0x4048 988 #define AR_GPIO_IN_VAL 0x0FFFC000 989 #define AR_GPIO_IN_VAL_S 14 990 #define AR928X_GPIO_IN_VAL 0x000FFC00 991 #define AR928X_GPIO_IN_VAL_S 10 992 #define AR9285_GPIO_IN_VAL 0x00FFF000 993 #define AR9285_GPIO_IN_VAL_S 12 994 #define AR9287_GPIO_IN_VAL 0x003FF800 995 #define AR9287_GPIO_IN_VAL_S 11 996 #define AR9271_GPIO_IN_VAL 0xFFFF0000 997 #define AR9271_GPIO_IN_VAL_S 16 998 #define AR7010_GPIO_IN_VAL 0x0000FFFF 999 #define AR7010_GPIO_IN_VAL_S 0 1000 1001 #define AR_GPIO_IN 0x404c 1002 #define AR9300_GPIO_IN_VAL 0x0001FFFF 1003 #define AR9300_GPIO_IN_VAL_S 0 1004 1005 #define AR_GPIO_OE_OUT (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c) 1006 #define AR_GPIO_OE_OUT_DRV 0x3 1007 #define AR_GPIO_OE_OUT_DRV_NO 0x0 1008 #define AR_GPIO_OE_OUT_DRV_LOW 0x1 1009 #define AR_GPIO_OE_OUT_DRV_HI 0x2 1010 #define AR_GPIO_OE_OUT_DRV_ALL 0x3 1011 1012 #define AR7010_GPIO_OE 0x52000 1013 #define AR7010_GPIO_OE_MASK 0x1 1014 #define AR7010_GPIO_OE_AS_OUTPUT 0x0 1015 #define AR7010_GPIO_OE_AS_INPUT 0x1 1016 #define AR7010_GPIO_IN 0x52004 1017 #define AR7010_GPIO_OUT 0x52008 1018 #define AR7010_GPIO_SET 0x5200C 1019 #define AR7010_GPIO_CLEAR 0x52010 1020 #define AR7010_GPIO_INT 0x52014 1021 #define AR7010_GPIO_INT_TYPE 0x52018 1022 #define AR7010_GPIO_INT_POLARITY 0x5201C 1023 #define AR7010_GPIO_PENDING 0x52020 1024 #define AR7010_GPIO_INT_MASK 0x52024 1025 #define AR7010_GPIO_FUNCTION 0x52028 1026 1027 #define AR_GPIO_INTR_POL (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050) 1028 #define AR_GPIO_INTR_POL_VAL 0x0001FFFF 1029 #define AR_GPIO_INTR_POL_VAL_S 0 1030 1031 #define AR_GPIO_INPUT_EN_VAL (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054) 1032 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 1033 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2 1034 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 1035 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S 3 1036 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 1037 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4 1038 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 1039 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 1040 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400 1041 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 10 1042 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 1043 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12 1044 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 1045 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 1046 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 1047 #define AR_GPIO_JTAG_DISABLE 0x00020000 1048 1049 #define AR_GPIO_INPUT_MUX1 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058) 1050 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 1051 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 1052 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00 1053 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 1054 1055 #define AR_GPIO_INPUT_MUX2 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c) 1056 #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f 1057 #define AR_GPIO_INPUT_MUX2_CLK25_S 0 1058 #define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 1059 #define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 1060 #define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 1061 #define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 1062 1063 #define AR_GPIO_OUTPUT_MUX1 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060) 1064 #define AR_GPIO_OUTPUT_MUX2 (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064) 1065 #define AR_GPIO_OUTPUT_MUX3 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068) 1066 1067 #define AR_INPUT_STATE (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c) 1068 1069 #define AR_EEPROM_STATUS_DATA (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c) 1070 #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 1071 #define AR_EEPROM_STATUS_DATA_VAL_S 0 1072 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 1073 #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 1074 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 1075 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 1076 1077 #define AR_OBS (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080) 1078 1079 #define AR_GPIO_PDPU (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088) 1080 1081 #define AR_PCIE_MSI (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094) 1082 #define AR_PCIE_MSI_ENABLE 0x00000001 1083 1084 #define AR_INTR_PRIO_SYNC_ENABLE 0x40c4 1085 #define AR_INTR_PRIO_ASYNC_MASK 0x40c8 1086 #define AR_INTR_PRIO_SYNC_MASK 0x40cc 1087 #define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4 1088 #define AR_ENT_OTP 0x40d8 1089 #define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000 1090 #define AR_ENT_OTP_MPSD 0x00800000 1091 #define AR_CH0_BB_DPLL2 0x16184 1092 #define AR_CH0_BB_DPLL3 0x16188 1093 #define AR_CH0_DDR_DPLL2 0x16244 1094 #define AR_CH0_DDR_DPLL3 0x16248 1095 #define AR_CH0_DPLL2_KD 0x03F80000 1096 #define AR_CH0_DPLL2_KD_S 19 1097 #define AR_CH0_DPLL2_KI 0x3C000000 1098 #define AR_CH0_DPLL2_KI_S 26 1099 #define AR_CH0_DPLL3_PHASE_SHIFT 0x3F800000 1100 #define AR_CH0_DPLL3_PHASE_SHIFT_S 23 1101 #define AR_PHY_CCA_NOM_VAL_2GHZ -118 1102 1103 #define AR_RTC_9300_PLL_DIV 0x000003ff 1104 #define AR_RTC_9300_PLL_DIV_S 0 1105 #define AR_RTC_9300_PLL_REFDIV 0x00003C00 1106 #define AR_RTC_9300_PLL_REFDIV_S 10 1107 #define AR_RTC_9300_PLL_CLKSEL 0x0000C000 1108 #define AR_RTC_9300_PLL_CLKSEL_S 14 1109 1110 #define AR_RTC_9160_PLL_DIV 0x000003ff 1111 #define AR_RTC_9160_PLL_DIV_S 0 1112 #define AR_RTC_9160_PLL_REFDIV 0x00003C00 1113 #define AR_RTC_9160_PLL_REFDIV_S 10 1114 #define AR_RTC_9160_PLL_CLKSEL 0x0000C000 1115 #define AR_RTC_9160_PLL_CLKSEL_S 14 1116 1117 #define AR_RTC_BASE 0x00020000 1118 #define AR_RTC_RC \ 1119 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0000) : 0x7000) 1120 #define AR_RTC_RC_M 0x00000003 1121 #define AR_RTC_RC_MAC_WARM 0x00000001 1122 #define AR_RTC_RC_MAC_COLD 0x00000002 1123 #define AR_RTC_RC_COLD_RESET 0x00000004 1124 #define AR_RTC_RC_WARM_RESET 0x00000008 1125 1126 /* Crystal Control */ 1127 #define AR_RTC_XTAL_CONTROL 0x7004 1128 1129 /* Reg Control 0 */ 1130 #define AR_RTC_REG_CONTROL0 0x7008 1131 1132 /* Reg Control 1 */ 1133 #define AR_RTC_REG_CONTROL1 0x700c 1134 #define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001 1135 1136 #define AR_RTC_PLL_CONTROL \ 1137 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014) 1138 1139 #define AR_RTC_PLL_CONTROL2 0x703c 1140 1141 #define AR_RTC_PLL_DIV 0x0000001f 1142 #define AR_RTC_PLL_DIV_S 0 1143 #define AR_RTC_PLL_DIV2 0x00000020 1144 #define AR_RTC_PLL_REFDIV_5 0x000000c0 1145 #define AR_RTC_PLL_CLKSEL 0x00000300 1146 #define AR_RTC_PLL_CLKSEL_S 8 1147 1148 #define PLL3 0x16188 1149 #define PLL3_DO_MEAS_MASK 0x40000000 1150 #define PLL4 0x1618c 1151 #define PLL4_MEAS_DONE 0x8 1152 #define SQSUM_DVC_MASK 0x007ffff8 1153 1154 #define AR_RTC_RESET \ 1155 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040) 1156 #define AR_RTC_RESET_EN (0x00000001) 1157 1158 #define AR_RTC_STATUS \ 1159 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0044) : 0x7044) 1160 1161 #define AR_RTC_STATUS_M \ 1162 ((AR_SREV_9100(ah)) ? 0x0000003f : 0x0000000f) 1163 1164 #define AR_RTC_PM_STATUS_M 0x0000000f 1165 1166 #define AR_RTC_STATUS_SHUTDOWN 0x00000001 1167 #define AR_RTC_STATUS_ON 0x00000002 1168 #define AR_RTC_STATUS_SLEEP 0x00000004 1169 #define AR_RTC_STATUS_WAKEUP 0x00000008 1170 1171 #define AR_RTC_SLEEP_CLK \ 1172 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048) 1173 #define AR_RTC_FORCE_DERIVED_CLK 0x2 1174 #define AR_RTC_FORCE_SWREG_PRD 0x00000004 1175 1176 #define AR_RTC_FORCE_WAKE \ 1177 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c) 1178 #define AR_RTC_FORCE_WAKE_EN 0x00000001 1179 #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 1180 1181 1182 #define AR_RTC_INTR_CAUSE \ 1183 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0050) : 0x7050) 1184 1185 #define AR_RTC_INTR_ENABLE \ 1186 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0054) : 0x7054) 1187 1188 #define AR_RTC_INTR_MASK \ 1189 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058) 1190 1191 /* RTC_DERIVED_* - only for AR9100 */ 1192 1193 #define AR_RTC_DERIVED_CLK (AR_RTC_BASE + 0x0038) 1194 #define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe 1195 #define AR_RTC_DERIVED_CLK_PERIOD_S 1 1196 1197 #define AR_SEQ_MASK 0x8060 1198 1199 #define AR_AN_RF2G1_CH0 0x7810 1200 #define AR_AN_RF2G1_CH0_OB 0x03800000 1201 #define AR_AN_RF2G1_CH0_OB_S 23 1202 #define AR_AN_RF2G1_CH0_DB 0x1C000000 1203 #define AR_AN_RF2G1_CH0_DB_S 26 1204 1205 #define AR_AN_RF5G1_CH0 0x7818 1206 #define AR_AN_RF5G1_CH0_OB5 0x00070000 1207 #define AR_AN_RF5G1_CH0_OB5_S 16 1208 #define AR_AN_RF5G1_CH0_DB5 0x00380000 1209 #define AR_AN_RF5G1_CH0_DB5_S 19 1210 1211 #define AR_AN_RF2G1_CH1 0x7834 1212 #define AR_AN_RF2G1_CH1_OB 0x03800000 1213 #define AR_AN_RF2G1_CH1_OB_S 23 1214 #define AR_AN_RF2G1_CH1_DB 0x1C000000 1215 #define AR_AN_RF2G1_CH1_DB_S 26 1216 1217 #define AR_AN_RF5G1_CH1 0x783C 1218 #define AR_AN_RF5G1_CH1_OB5 0x00070000 1219 #define AR_AN_RF5G1_CH1_OB5_S 16 1220 #define AR_AN_RF5G1_CH1_DB5 0x00380000 1221 #define AR_AN_RF5G1_CH1_DB5_S 19 1222 1223 #define AR_AN_TOP1 0x7890 1224 #define AR_AN_TOP1_DACIPMODE 0x00040000 1225 #define AR_AN_TOP1_DACIPMODE_S 18 1226 1227 #define AR_AN_TOP2 0x7894 1228 #define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 1229 #define AR_AN_TOP2_XPABIAS_LVL_S 30 1230 #define AR_AN_TOP2_LOCALBIAS 0x00200000 1231 #define AR_AN_TOP2_LOCALBIAS_S 21 1232 #define AR_AN_TOP2_PWDCLKIND 0x00400000 1233 #define AR_AN_TOP2_PWDCLKIND_S 22 1234 1235 #define AR_AN_SYNTH9 0x7868 1236 #define AR_AN_SYNTH9_REFDIVA 0xf8000000 1237 #define AR_AN_SYNTH9_REFDIVA_S 27 1238 1239 #define AR9285_AN_RF2G1 0x7820 1240 #define AR9285_AN_RF2G1_ENPACAL 0x00000800 1241 #define AR9285_AN_RF2G1_ENPACAL_S 11 1242 #define AR9285_AN_RF2G1_PDPADRV1 0x02000000 1243 #define AR9285_AN_RF2G1_PDPADRV1_S 25 1244 #define AR9285_AN_RF2G1_PDPADRV2 0x01000000 1245 #define AR9285_AN_RF2G1_PDPADRV2_S 24 1246 #define AR9285_AN_RF2G1_PDPAOUT 0x00800000 1247 #define AR9285_AN_RF2G1_PDPAOUT_S 23 1248 1249 1250 #define AR9285_AN_RF2G2 0x7824 1251 #define AR9285_AN_RF2G2_OFFCAL 0x00001000 1252 #define AR9285_AN_RF2G2_OFFCAL_S 12 1253 1254 #define AR9285_AN_RF2G3 0x7828 1255 #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000 1256 #define AR9285_AN_RF2G3_PDVCCOMP_S 25 1257 #define AR9285_AN_RF2G3_OB_0 0x00E00000 1258 #define AR9285_AN_RF2G3_OB_0_S 21 1259 #define AR9285_AN_RF2G3_OB_1 0x001C0000 1260 #define AR9285_AN_RF2G3_OB_1_S 18 1261 #define AR9285_AN_RF2G3_OB_2 0x00038000 1262 #define AR9285_AN_RF2G3_OB_2_S 15 1263 #define AR9285_AN_RF2G3_OB_3 0x00007000 1264 #define AR9285_AN_RF2G3_OB_3_S 12 1265 #define AR9285_AN_RF2G3_OB_4 0x00000E00 1266 #define AR9285_AN_RF2G3_OB_4_S 9 1267 1268 #define AR9285_AN_RF2G3_DB1_0 0x000001C0 1269 #define AR9285_AN_RF2G3_DB1_0_S 6 1270 #define AR9285_AN_RF2G3_DB1_1 0x00000038 1271 #define AR9285_AN_RF2G3_DB1_1_S 3 1272 #define AR9285_AN_RF2G3_DB1_2 0x00000007 1273 #define AR9285_AN_RF2G3_DB1_2_S 0 1274 #define AR9285_AN_RF2G4 0x782C 1275 #define AR9285_AN_RF2G4_DB1_3 0xE0000000 1276 #define AR9285_AN_RF2G4_DB1_3_S 29 1277 #define AR9285_AN_RF2G4_DB1_4 0x1C000000 1278 #define AR9285_AN_RF2G4_DB1_4_S 26 1279 1280 #define AR9285_AN_RF2G4_DB2_0 0x03800000 1281 #define AR9285_AN_RF2G4_DB2_0_S 23 1282 #define AR9285_AN_RF2G4_DB2_1 0x00700000 1283 #define AR9285_AN_RF2G4_DB2_1_S 20 1284 #define AR9285_AN_RF2G4_DB2_2 0x000E0000 1285 #define AR9285_AN_RF2G4_DB2_2_S 17 1286 #define AR9285_AN_RF2G4_DB2_3 0x0001C000 1287 #define AR9285_AN_RF2G4_DB2_3_S 14 1288 #define AR9285_AN_RF2G4_DB2_4 0x00003800 1289 #define AR9285_AN_RF2G4_DB2_4_S 11 1290 1291 #define AR9285_RF2G5 0x7830 1292 #define AR9285_RF2G5_IC50TX 0xfffff8ff 1293 #define AR9285_RF2G5_IC50TX_SET 0x00000400 1294 #define AR9285_RF2G5_IC50TX_XE_SET 0x00000500 1295 #define AR9285_RF2G5_IC50TX_CLEAR 0x00000700 1296 #define AR9285_RF2G5_IC50TX_CLEAR_S 8 1297 1298 /* AR9271 : 0x7828, 0x782c different setting from AR9285 */ 1299 #define AR9271_AN_RF2G3_OB_cck 0x001C0000 1300 #define AR9271_AN_RF2G3_OB_cck_S 18 1301 #define AR9271_AN_RF2G3_OB_psk 0x00038000 1302 #define AR9271_AN_RF2G3_OB_psk_S 15 1303 #define AR9271_AN_RF2G3_OB_qam 0x00007000 1304 #define AR9271_AN_RF2G3_OB_qam_S 12 1305 1306 #define AR9271_AN_RF2G3_DB_1 0x00E00000 1307 #define AR9271_AN_RF2G3_DB_1_S 21 1308 1309 #define AR9271_AN_RF2G3_CCOMP 0xFFF 1310 #define AR9271_AN_RF2G3_CCOMP_S 0 1311 1312 #define AR9271_AN_RF2G4_DB_2 0xE0000000 1313 #define AR9271_AN_RF2G4_DB_2_S 29 1314 1315 #define AR9285_AN_RF2G6 0x7834 1316 #define AR9285_AN_RF2G6_CCOMP 0x00007800 1317 #define AR9285_AN_RF2G6_CCOMP_S 11 1318 #define AR9285_AN_RF2G6_OFFS 0x03f00000 1319 #define AR9285_AN_RF2G6_OFFS_S 20 1320 1321 #define AR9271_AN_RF2G6_OFFS 0x07f00000 1322 #define AR9271_AN_RF2G6_OFFS_S 20 1323 1324 #define AR9285_AN_RF2G7 0x7838 1325 #define AR9285_AN_RF2G7_PWDDB 0x00000002 1326 #define AR9285_AN_RF2G7_PWDDB_S 1 1327 #define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000 1328 #define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29 1329 1330 #define AR9285_AN_RF2G8 0x783C 1331 #define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000 1332 #define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14 1333 1334 1335 #define AR9285_AN_RF2G9 0x7840 1336 #define AR9285_AN_RXTXBB1 0x7854 1337 #define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020 1338 #define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5 1339 #define AR9285_AN_RXTXBB1_PDV2I 0x00000080 1340 #define AR9285_AN_RXTXBB1_PDV2I_S 7 1341 #define AR9285_AN_RXTXBB1_PDDACIF 0x00000100 1342 #define AR9285_AN_RXTXBB1_PDDACIF_S 8 1343 #define AR9285_AN_RXTXBB1_SPARE9 0x00000001 1344 #define AR9285_AN_RXTXBB1_SPARE9_S 0 1345 1346 #define AR9285_AN_TOP2 0x7868 1347 1348 #define AR9285_AN_TOP3 0x786c 1349 #define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C 1350 #define AR9285_AN_TOP3_XPABIAS_LVL_S 2 1351 #define AR9285_AN_TOP3_PWDDAC 0x00800000 1352 #define AR9285_AN_TOP3_PWDDAC_S 23 1353 1354 #define AR9285_AN_TOP4 0x7870 1355 #define AR9285_AN_TOP4_DEFAULT 0x10142c00 1356 1357 #define AR9287_AN_RF2G3_CH0 0x7808 1358 #define AR9287_AN_RF2G3_CH1 0x785c 1359 #define AR9287_AN_RF2G3_DB1 0xE0000000 1360 #define AR9287_AN_RF2G3_DB1_S 29 1361 #define AR9287_AN_RF2G3_DB2 0x1C000000 1362 #define AR9287_AN_RF2G3_DB2_S 26 1363 #define AR9287_AN_RF2G3_OB_CCK 0x03800000 1364 #define AR9287_AN_RF2G3_OB_CCK_S 23 1365 #define AR9287_AN_RF2G3_OB_PSK 0x00700000 1366 #define AR9287_AN_RF2G3_OB_PSK_S 20 1367 #define AR9287_AN_RF2G3_OB_QAM 0x000E0000 1368 #define AR9287_AN_RF2G3_OB_QAM_S 17 1369 #define AR9287_AN_RF2G3_OB_PAL_OFF 0x0001C000 1370 #define AR9287_AN_RF2G3_OB_PAL_OFF_S 14 1371 1372 #define AR9287_AN_TXPC0 0x7898 1373 #define AR9287_AN_TXPC0_TXPCMODE 0x0000C000 1374 #define AR9287_AN_TXPC0_TXPCMODE_S 14 1375 #define AR9287_AN_TXPC0_TXPCMODE_NORMAL 0 1376 #define AR9287_AN_TXPC0_TXPCMODE_TEST 1 1377 #define AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE 2 1378 #define AR9287_AN_TXPC0_TXPCMODE_ATBTEST 3 1379 1380 #define AR9287_AN_TOP2 0x78b4 1381 #define AR9287_AN_TOP2_XPABIAS_LVL 0xC0000000 1382 #define AR9287_AN_TOP2_XPABIAS_LVL_S 30 1383 1384 /* AR9271 specific stuff */ 1385 #define AR9271_RESET_POWER_DOWN_CONTROL 0x50044 1386 #define AR9271_RADIO_RF_RST 0x20 1387 #define AR9271_GATE_MAC_CTL 0x4000 1388 1389 #define AR_STA_ID0 0x8000 1390 #define AR_STA_ID1 0x8004 1391 #define AR_STA_ID1_SADH_MASK 0x0000FFFF 1392 #define AR_STA_ID1_STA_AP 0x00010000 1393 #define AR_STA_ID1_ADHOC 0x00020000 1394 #define AR_STA_ID1_PWR_SAV 0x00040000 1395 #define AR_STA_ID1_KSRCHDIS 0x00080000 1396 #define AR_STA_ID1_PCF 0x00100000 1397 #define AR_STA_ID1_USE_DEFANT 0x00200000 1398 #define AR_STA_ID1_DEFANT_UPDATE 0x00400000 1399 #define AR_STA_ID1_RTS_USE_DEF 0x00800000 1400 #define AR_STA_ID1_ACKCTS_6MB 0x01000000 1401 #define AR_STA_ID1_BASE_RATE_11B 0x02000000 1402 #define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 1403 #define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 1404 #define AR_STA_ID1_KSRCH_MODE 0x10000000 1405 #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 1406 #define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 1407 #define AR_STA_ID1_MCAST_KSRCH 0x80000000 1408 1409 #define AR_BSS_ID0 0x8008 1410 #define AR_BSS_ID1 0x800C 1411 #define AR_BSS_ID1_U16 0x0000FFFF 1412 #define AR_BSS_ID1_AID 0x07FF0000 1413 #define AR_BSS_ID1_AID_S 16 1414 1415 #define AR_BCN_RSSI_AVE 0x8010 1416 #define AR_BCN_RSSI_AVE_MASK 0x00000FFF 1417 1418 #define AR_TIME_OUT 0x8014 1419 #define AR_TIME_OUT_ACK 0x00003FFF 1420 #define AR_TIME_OUT_ACK_S 0 1421 #define AR_TIME_OUT_CTS 0x3FFF0000 1422 #define AR_TIME_OUT_CTS_S 16 1423 #define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR 0x16001D56 1424 1425 #define AR_RSSI_THR 0x8018 1426 #define AR_RSSI_THR_MASK 0x000000FF 1427 #define AR_RSSI_THR_BM_THR 0x0000FF00 1428 #define AR_RSSI_THR_BM_THR_S 8 1429 #define AR_RSSI_BCN_WEIGHT 0x1F000000 1430 #define AR_RSSI_BCN_WEIGHT_S 24 1431 #define AR_RSSI_BCN_RSSI_RST 0x20000000 1432 1433 #define AR_USEC 0x801c 1434 #define AR_USEC_USEC 0x0000007F 1435 #define AR_USEC_TX_LAT 0x007FC000 1436 #define AR_USEC_TX_LAT_S 14 1437 #define AR_USEC_RX_LAT 0x1F800000 1438 #define AR_USEC_RX_LAT_S 23 1439 #define AR_USEC_ASYNC_FIFO_DUR 0x12e00074 1440 1441 #define AR_RESET_TSF 0x8020 1442 #define AR_RESET_TSF_ONCE 0x01000000 1443 1444 #define AR_MAX_CFP_DUR 0x8038 1445 #define AR_CFP_VAL 0x0000FFFF 1446 1447 #define AR_RX_FILTER 0x803C 1448 1449 #define AR_MCAST_FIL0 0x8040 1450 #define AR_MCAST_FIL1 0x8044 1451 1452 /* 1453 * AR_DIAG_SW - Register which can be used for diagnostics and testing purposes. 1454 * 1455 * The force RX abort (AR_DIAG_RX_ABORT, bit 25) can be used in conjunction with 1456 * RX block (AR_DIAG_RX_DIS, bit 5) to help fast channel change to shut down 1457 * receive. The force RX abort bit will kill any frame which is currently being 1458 * transferred between the MAC and baseband. The RX block bit (AR_DIAG_RX_DIS) 1459 * will prevent any new frames from getting started. 1460 */ 1461 #define AR_DIAG_SW 0x8048 1462 #define AR_DIAG_CACHE_ACK 0x00000001 1463 #define AR_DIAG_ACK_DIS 0x00000002 1464 #define AR_DIAG_CTS_DIS 0x00000004 1465 #define AR_DIAG_ENCRYPT_DIS 0x00000008 1466 #define AR_DIAG_DECRYPT_DIS 0x00000010 1467 #define AR_DIAG_RX_DIS 0x00000020 /* RX block */ 1468 #define AR_DIAG_LOOP_BACK 0x00000040 1469 #define AR_DIAG_CORR_FCS 0x00000080 1470 #define AR_DIAG_CHAN_INFO 0x00000100 1471 #define AR_DIAG_SCRAM_SEED 0x0001FE00 1472 #define AR_DIAG_SCRAM_SEED_S 8 1473 #define AR_DIAG_FRAME_NV0 0x00020000 1474 #define AR_DIAG_OBS_PT_SEL1 0x000C0000 1475 #define AR_DIAG_OBS_PT_SEL1_S 18 1476 #define AR_DIAG_FORCE_RX_CLEAR 0x00100000 /* force rx_clear high */ 1477 #define AR_DIAG_IGNORE_VIRT_CS 0x00200000 1478 #define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 1479 #define AR_DIAG_EIFS_CTRL_ENA 0x00800000 1480 #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 1481 #define AR_DIAG_RX_ABORT 0x02000000 /* Force RX abort */ 1482 #define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 1483 #define AR_DIAG_OBS_PT_SEL2 0x08000000 1484 #define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 1485 #define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 1486 1487 #define AR_TSF_L32 0x804c 1488 #define AR_TSF_U32 0x8050 1489 1490 #define AR_TST_ADDAC 0x8054 1491 #define AR_DEF_ANTENNA 0x8058 1492 1493 #define AR_AES_MUTE_MASK0 0x805c 1494 #define AR_AES_MUTE_MASK0_FC 0x0000FFFF 1495 #define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 1496 #define AR_AES_MUTE_MASK0_QOS_S 16 1497 1498 #define AR_AES_MUTE_MASK1 0x8060 1499 #define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF 1500 #define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000 1501 #define AR_AES_MUTE_MASK1_FC_MGMT_S 16 1502 1503 #define AR_GATED_CLKS 0x8064 1504 #define AR_GATED_CLKS_TX 0x00000002 1505 #define AR_GATED_CLKS_RX 0x00000004 1506 #define AR_GATED_CLKS_REG 0x00000008 1507 1508 #define AR_OBS_BUS_CTRL 0x8068 1509 #define AR_OBS_BUS_SEL_1 0x00040000 1510 #define AR_OBS_BUS_SEL_2 0x00080000 1511 #define AR_OBS_BUS_SEL_3 0x000C0000 1512 #define AR_OBS_BUS_SEL_4 0x08040000 1513 #define AR_OBS_BUS_SEL_5 0x08080000 1514 1515 #define AR_OBS_BUS_1 0x806c 1516 #define AR_OBS_BUS_1_PCU 0x00000001 1517 #define AR_OBS_BUS_1_RX_END 0x00000002 1518 #define AR_OBS_BUS_1_RX_WEP 0x00000004 1519 #define AR_OBS_BUS_1_RX_BEACON 0x00000008 1520 #define AR_OBS_BUS_1_RX_FILTER 0x00000010 1521 #define AR_OBS_BUS_1_TX_HCF 0x00000020 1522 #define AR_OBS_BUS_1_QUIET_TIME 0x00000040 1523 #define AR_OBS_BUS_1_CHAN_IDLE 0x00000080 1524 #define AR_OBS_BUS_1_TX_HOLD 0x00000100 1525 #define AR_OBS_BUS_1_TX_FRAME 0x00000200 1526 #define AR_OBS_BUS_1_RX_FRAME 0x00000400 1527 #define AR_OBS_BUS_1_RX_CLEAR 0x00000800 1528 #define AR_OBS_BUS_1_WEP_STATE 0x0003F000 1529 #define AR_OBS_BUS_1_WEP_STATE_S 12 1530 #define AR_OBS_BUS_1_RX_STATE 0x01F00000 1531 #define AR_OBS_BUS_1_RX_STATE_S 20 1532 #define AR_OBS_BUS_1_TX_STATE 0x7E000000 1533 #define AR_OBS_BUS_1_TX_STATE_S 25 1534 1535 #define AR_LAST_TSTP 0x8080 1536 #define AR_NAV 0x8084 1537 #define AR_RTS_OK 0x8088 1538 #define AR_RTS_FAIL 0x808c 1539 #define AR_ACK_FAIL 0x8090 1540 #define AR_FCS_FAIL 0x8094 1541 #define AR_BEACON_CNT 0x8098 1542 1543 #define AR_SLEEP1 0x80d4 1544 #define AR_SLEEP1_ASSUME_DTIM 0x00080000 1545 #define AR_SLEEP1_CAB_TIMEOUT 0xFFE00000 1546 #define AR_SLEEP1_CAB_TIMEOUT_S 21 1547 1548 #define AR_SLEEP2 0x80d8 1549 #define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000 1550 #define AR_SLEEP2_BEACON_TIMEOUT_S 21 1551 1552 #define AR_TPC 0x80e8 1553 #define AR_TPC_ACK 0x0000003f 1554 #define AR_TPC_ACK_S 0x00 1555 #define AR_TPC_CTS 0x00003f00 1556 #define AR_TPC_CTS_S 0x08 1557 #define AR_TPC_CHIRP 0x003f0000 1558 #define AR_TPC_CHIRP_S 0x16 1559 1560 #define AR_QUIET1 0x80fc 1561 #define AR_QUIET1_NEXT_QUIET_S 0 1562 #define AR_QUIET1_NEXT_QUIET_M 0x0000ffff 1563 #define AR_QUIET1_QUIET_ENABLE 0x00010000 1564 #define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 1565 #define AR_QUIET1_QUIET_ACK_CTS_ENABLE_S 17 1566 #define AR_QUIET2 0x8100 1567 #define AR_QUIET2_QUIET_PERIOD_S 0 1568 #define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff 1569 #define AR_QUIET2_QUIET_DUR_S 16 1570 #define AR_QUIET2_QUIET_DUR 0xffff0000 1571 1572 #define AR_TSF_PARM 0x8104 1573 #define AR_TSF_INCREMENT_M 0x000000ff 1574 #define AR_TSF_INCREMENT_S 0x00 1575 1576 #define AR_QOS_NO_ACK 0x8108 1577 #define AR_QOS_NO_ACK_TWO_BIT 0x0000000f 1578 #define AR_QOS_NO_ACK_TWO_BIT_S 0 1579 #define AR_QOS_NO_ACK_BIT_OFF 0x00000070 1580 #define AR_QOS_NO_ACK_BIT_OFF_S 4 1581 #define AR_QOS_NO_ACK_BYTE_OFF 0x00000180 1582 #define AR_QOS_NO_ACK_BYTE_OFF_S 7 1583 1584 #define AR_PHY_ERR 0x810c 1585 1586 #define AR_PHY_ERR_DCHIRP 0x00000008 1587 #define AR_PHY_ERR_RADAR 0x00000020 1588 #define AR_PHY_ERR_OFDM_TIMING 0x00020000 1589 #define AR_PHY_ERR_CCK_TIMING 0x02000000 1590 1591 #define AR_RXFIFO_CFG 0x8114 1592 1593 1594 #define AR_MIC_QOS_CONTROL 0x8118 1595 #define AR_MIC_QOS_SELECT 0x811c 1596 1597 #define AR_PCU_MISC 0x8120 1598 #define AR_PCU_FORCE_BSSID_MATCH 0x00000001 1599 #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 1600 #define AR_PCU_TX_ADD_TSF 0x00000008 1601 #define AR_PCU_CCK_SIFS_MODE 0x00000010 1602 #define AR_PCU_RX_ANT_UPDT 0x00000800 1603 #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 1604 #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 1605 #define AR_PCU_BUG_12306_FIX_ENA 0x00020000 1606 #define AR_PCU_FORCE_QUIET_COLL 0x00040000 1607 #define AR_PCU_TBTT_PROTECT 0x00200000 1608 #define AR_PCU_CLEAR_VMF 0x01000000 1609 #define AR_PCU_CLEAR_BA_VALID 0x04000000 1610 #define AR_PCU_ALWAYS_PERFORM_KEYSEARCH 0x10000000 1611 1612 #define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 1613 #define AR_PCU_BT_ANT_PREVENT_RX_S 20 1614 1615 #define AR_FILT_OFDM 0x8124 1616 #define AR_FILT_OFDM_COUNT 0x00FFFFFF 1617 1618 #define AR_FILT_CCK 0x8128 1619 #define AR_FILT_CCK_COUNT 0x00FFFFFF 1620 1621 #define AR_PHY_ERR_1 0x812c 1622 #define AR_PHY_ERR_1_COUNT 0x00FFFFFF 1623 #define AR_PHY_ERR_MASK_1 0x8130 1624 1625 #define AR_PHY_ERR_2 0x8134 1626 #define AR_PHY_ERR_2_COUNT 0x00FFFFFF 1627 #define AR_PHY_ERR_MASK_2 0x8138 1628 1629 #define AR_PHY_COUNTMAX (3 << 22) 1630 #define AR_MIBCNT_INTRMASK (3 << 22) 1631 1632 #define AR_TSFOOR_THRESHOLD 0x813c 1633 #define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF 1634 1635 #define AR_PHY_ERR_EIFS_MASK 0x8144 1636 1637 #define AR_PHY_ERR_3 0x8168 1638 #define AR_PHY_ERR_3_COUNT 0x00FFFFFF 1639 #define AR_PHY_ERR_MASK_3 0x816c 1640 1641 #define AR_BT_COEX_MODE 0x8170 1642 #define AR_BT_TIME_EXTEND 0x000000ff 1643 #define AR_BT_TIME_EXTEND_S 0 1644 #define AR_BT_TXSTATE_EXTEND 0x00000100 1645 #define AR_BT_TXSTATE_EXTEND_S 8 1646 #define AR_BT_TX_FRAME_EXTEND 0x00000200 1647 #define AR_BT_TX_FRAME_EXTEND_S 9 1648 #define AR_BT_MODE 0x00000c00 1649 #define AR_BT_MODE_S 10 1650 #define AR_BT_QUIET 0x00001000 1651 #define AR_BT_QUIET_S 12 1652 #define AR_BT_QCU_THRESH 0x0001e000 1653 #define AR_BT_QCU_THRESH_S 13 1654 #define AR_BT_RX_CLEAR_POLARITY 0x00020000 1655 #define AR_BT_RX_CLEAR_POLARITY_S 17 1656 #define AR_BT_PRIORITY_TIME 0x00fc0000 1657 #define AR_BT_PRIORITY_TIME_S 18 1658 #define AR_BT_FIRST_SLOT_TIME 0xff000000 1659 #define AR_BT_FIRST_SLOT_TIME_S 24 1660 1661 #define AR_BT_COEX_WEIGHT 0x8174 1662 #define AR_BT_COEX_WGHT 0xff55 1663 #define AR_STOMP_ALL_WLAN_WGHT 0xfcfc 1664 #define AR_STOMP_LOW_WLAN_WGHT 0xa8a8 1665 #define AR_STOMP_NONE_WLAN_WGHT 0x0000 1666 #define AR_BTCOEX_BT_WGHT 0x0000ffff 1667 #define AR_BTCOEX_BT_WGHT_S 0 1668 #define AR_BTCOEX_WL_WGHT 0xffff0000 1669 #define AR_BTCOEX_WL_WGHT_S 16 1670 1671 #define AR_BT_COEX_MODE2 0x817c 1672 #define AR_BT_BCN_MISS_THRESH 0x000000ff 1673 #define AR_BT_BCN_MISS_THRESH_S 0 1674 #define AR_BT_BCN_MISS_CNT 0x0000ff00 1675 #define AR_BT_BCN_MISS_CNT_S 8 1676 #define AR_BT_HOLD_RX_CLEAR 0x00010000 1677 #define AR_BT_HOLD_RX_CLEAR_S 16 1678 #define AR_BT_DISABLE_BT_ANT 0x00100000 1679 #define AR_BT_DISABLE_BT_ANT_S 20 1680 1681 #define AR_TXSIFS 0x81d0 1682 #define AR_TXSIFS_TIME 0x000000FF 1683 #define AR_TXSIFS_TX_LATENCY 0x00000F00 1684 #define AR_TXSIFS_TX_LATENCY_S 8 1685 #define AR_TXSIFS_ACK_SHIFT 0x00007000 1686 #define AR_TXSIFS_ACK_SHIFT_S 12 1687 1688 #define AR_TXOP_X 0x81ec 1689 #define AR_TXOP_X_VAL 0x000000FF 1690 1691 1692 #define AR_TXOP_0_3 0x81f0 1693 #define AR_TXOP_4_7 0x81f4 1694 #define AR_TXOP_8_11 0x81f8 1695 #define AR_TXOP_12_15 0x81fc 1696 1697 #define AR_NEXT_NDP2_TIMER 0x8180 1698 #define AR_FIRST_NDP_TIMER 7 1699 #define AR_NDP2_PERIOD 0x81a0 1700 #define AR_NDP2_TIMER_MODE 0x81c0 1701 1702 #define AR_GEN_TIMERS(_i) (0x8200 + ((_i) << 2)) 1703 #define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0) 1704 #define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMERS(1) 1705 #define AR_NEXT_SWBA AR_GEN_TIMERS(2) 1706 #define AR_NEXT_CFP AR_GEN_TIMERS(2) 1707 #define AR_NEXT_HCF AR_GEN_TIMERS(3) 1708 #define AR_NEXT_TIM AR_GEN_TIMERS(4) 1709 #define AR_NEXT_DTIM AR_GEN_TIMERS(5) 1710 #define AR_NEXT_QUIET_TIMER AR_GEN_TIMERS(6) 1711 #define AR_NEXT_NDP_TIMER AR_GEN_TIMERS(7) 1712 1713 #define AR_BEACON_PERIOD AR_GEN_TIMERS(8) 1714 #define AR_DMA_BEACON_PERIOD AR_GEN_TIMERS(9) 1715 #define AR_SWBA_PERIOD AR_GEN_TIMERS(10) 1716 #define AR_HCF_PERIOD AR_GEN_TIMERS(11) 1717 #define AR_TIM_PERIOD AR_GEN_TIMERS(12) 1718 #define AR_DTIM_PERIOD AR_GEN_TIMERS(13) 1719 #define AR_QUIET_PERIOD AR_GEN_TIMERS(14) 1720 #define AR_NDP_PERIOD AR_GEN_TIMERS(15) 1721 1722 #define AR_TIMER_MODE 0x8240 1723 #define AR_TBTT_TIMER_EN 0x00000001 1724 #define AR_DBA_TIMER_EN 0x00000002 1725 #define AR_SWBA_TIMER_EN 0x00000004 1726 #define AR_HCF_TIMER_EN 0x00000008 1727 #define AR_TIM_TIMER_EN 0x00000010 1728 #define AR_DTIM_TIMER_EN 0x00000020 1729 #define AR_QUIET_TIMER_EN 0x00000040 1730 #define AR_NDP_TIMER_EN 0x00000080 1731 #define AR_TIMER_OVERFLOW_INDEX 0x00000700 1732 #define AR_TIMER_OVERFLOW_INDEX_S 8 1733 #define AR_TIMER_THRESH 0xFFFFF000 1734 #define AR_TIMER_THRESH_S 12 1735 1736 #define AR_SLP32_MODE 0x8244 1737 #define AR_SLP32_HALF_CLK_LATENCY 0x000FFFFF 1738 #define AR_SLP32_ENA 0x00100000 1739 #define AR_SLP32_TSF_WRITE_STATUS 0x00200000 1740 1741 #define AR_SLP32_WAKE 0x8248 1742 #define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF 1743 1744 #define AR_SLP32_INC 0x824c 1745 #define AR_SLP32_TST_INC 0x000FFFFF 1746 1747 #define AR_SLP_CNT 0x8250 1748 #define AR_SLP_CYCLE_CNT 0x8254 1749 1750 #define AR_SLP_MIB_CTRL 0x8258 1751 #define AR_SLP_MIB_CLEAR 0x00000001 1752 #define AR_SLP_MIB_PENDING 0x00000002 1753 1754 #define AR_MAC_PCU_LOGIC_ANALYZER 0x8264 1755 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 1756 1757 1758 #define AR_2040_MODE 0x8318 1759 #define AR_2040_JOINED_RX_CLEAR 0x00000001 1760 1761 1762 #define AR_EXTRCCNT 0x8328 1763 1764 #define AR_SELFGEN_MASK 0x832c 1765 1766 #define AR_PCU_TXBUF_CTRL 0x8340 1767 #define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF 1768 #define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 1769 #define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380 1770 1771 #define AR_PCU_MISC_MODE2 0x8344 1772 #define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 1773 #define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 1774 1775 #define AR_PCU_MISC_MODE2_RESERVED 0x00000038 1776 #define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040 1777 #define AR_PCU_MISC_MODE2_CFP_IGNORE 0x00000080 1778 #define AR_PCU_MISC_MODE2_MGMT_QOS 0x0000FF00 1779 #define AR_PCU_MISC_MODE2_MGMT_QOS_S 8 1780 #define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION 0x00010000 1781 #define AR_PCU_MISC_MODE2_ENABLE_AGGWEP 0x00020000 1782 #define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 1783 #define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 1784 #define AR_PCU_MISC_MODE2_RESERVED2 0xFFFE0000 1785 1786 #define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358 1787 #define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400 1788 #define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000 1789 1790 1791 #define AR_AES_MUTE_MASK0 0x805c 1792 #define AR_AES_MUTE_MASK0_FC 0x0000FFFF 1793 #define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 1794 #define AR_AES_MUTE_MASK0_QOS_S 16 1795 1796 #define AR_AES_MUTE_MASK1 0x8060 1797 #define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF 1798 #define AR_AES_MUTE_MASK1_SEQ_S 0 1799 #define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000 1800 #define AR_AES_MUTE_MASK1_FC_MGMT_S 16 1801 1802 #define AR_RATE_DURATION_0 0x8700 1803 #define AR_RATE_DURATION_31 0x87CC 1804 #define AR_RATE_DURATION_32 0x8780 1805 #define AR_RATE_DURATION(_n) (AR_RATE_DURATION_0 + ((_n)<<2)) 1806 1807 1808 #define AR_KEYTABLE_0 0x8800 1809 #define AR_KEYTABLE(_n) (AR_KEYTABLE_0 + ((_n)*32)) 1810 #define AR_KEY_CACHE_SIZE 128 1811 #define AR_RSVD_KEYTABLE_ENTRIES 4 1812 #define AR_KEY_TYPE 0x00000007 1813 #define AR_KEYTABLE_TYPE_40 0x00000000 1814 #define AR_KEYTABLE_TYPE_104 0x00000001 1815 #define AR_KEYTABLE_TYPE_128 0x00000003 1816 #define AR_KEYTABLE_TYPE_TKIP 0x00000004 1817 #define AR_KEYTABLE_TYPE_AES 0x00000005 1818 #define AR_KEYTABLE_TYPE_CCM 0x00000006 1819 #define AR_KEYTABLE_TYPE_CLR 0x00000007 1820 #define AR_KEYTABLE_ANT 0x00000008 1821 #define AR_KEYTABLE_VALID 0x00008000 1822 #define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0) 1823 #define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4) 1824 #define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8) 1825 #define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12) 1826 #define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16) 1827 #define AR_KEYTABLE_TYPE(_n) (AR_KEYTABLE(_n) + 20) 1828 #define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) 1829 #define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) 1830 1831 #define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */ 1832 #define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */ 1833 1834 #define AR_AGG_WEP_ENABLE_FIX 0x00000008 /* This allows the use of AR_AGG_WEP_ENABLE */ 1835 #define AR_ADHOC_MCAST_KEYID_ENABLE 0x00000040 /* This bit enables the Multicast search 1836 * based on both MAC Address and Key ID. 1837 * If bit is 0, then Multicast search is 1838 * based on MAC address only. 1839 * For Merlin and above only. 1840 */ 1841 #define AR_AGG_WEP_ENABLE 0x00020000 /* This field enables AGG_WEP feature, 1842 * when it is enable, AGG_WEP would takes 1843 * charge of the encryption interface of 1844 * pcu_txsm. 1845 */ 1846 1847 #define AR9300_SM_BASE 0xa200 1848 #define AR9002_PHY_AGC_CONTROL 0x9860 1849 #define AR9003_PHY_AGC_CONTROL AR9300_SM_BASE + 0xc4 1850 #define AR_PHY_AGC_CONTROL (AR_SREV_9300_20_OR_LATER(ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AGC_CONTROL) 1851 #define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */ 1852 #define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calibration */ 1853 #define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800 /* allow offset calibration */ 1854 #define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* enable noise floor calibration to happen */ 1855 #define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 /* allow tx filter calibration */ 1856 #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */ 1857 #define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */ 1858 #define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */ 1859 #define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0 1860 #define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6 1861 1862 #endif 1863