1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef HW_H
18 #define HW_H
19
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23
24 #include "mac.h"
25 #include "ani.h"
26 #include "eeprom.h"
27 #include "calib.h"
28 #include "reg.h"
29 #include "phy.h"
30 #include "btcoex.h"
31
32 #include "../regd.h"
33
34 #define ATHEROS_VENDOR_ID 0x168c
35
36 #define AR5416_DEVID_PCI 0x0023
37 #define AR5416_DEVID_PCIE 0x0024
38 #define AR9160_DEVID_PCI 0x0027
39 #define AR9280_DEVID_PCI 0x0029
40 #define AR9280_DEVID_PCIE 0x002a
41 #define AR9285_DEVID_PCIE 0x002b
42 #define AR2427_DEVID_PCIE 0x002c
43 #define AR9287_DEVID_PCI 0x002d
44 #define AR9287_DEVID_PCIE 0x002e
45 #define AR9300_DEVID_PCIE 0x0030
46 #define AR9300_DEVID_AR9485_PCIE 0x0032
47
48 #define AR5416_AR9100_DEVID 0x000b
49
50 #define AR_SUBVENDOR_ID_NOG 0x0e11
51 #define AR_SUBVENDOR_ID_NEW_A 0x7065
52 #define AR5416_MAGIC 0x19641014
53
54 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
55 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
56 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
57
58 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
59
60 #define ATH_DEFAULT_NOISE_FLOOR -95
61
62 #define ATH9K_RSSI_BAD -128
63
64 #define ATH9K_NUM_CHANNELS 38
65
66 /* Register read/write primitives */
67 #define REG_WRITE(_ah, _reg, _val) \
68 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
69
70 #define REG_READ(_ah, _reg) \
71 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
72
73 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
74 ath9k_hw_common(_ah)->ops->multi_read((_ah), (_addr), (_val), (_cnt))
75
76 #define ENABLE_REGWRITE_BUFFER(_ah) \
77 do { \
78 if (ath9k_hw_common(_ah)->ops->enable_write_buffer) \
79 ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
80 } while (0)
81
82 #define REGWRITE_BUFFER_FLUSH(_ah) \
83 do { \
84 if (ath9k_hw_common(_ah)->ops->write_flush) \
85 ath9k_hw_common(_ah)->ops->write_flush((_ah)); \
86 } while (0)
87
88 #define SM(_v, _f) (((_v) << _f##_S) & _f)
89 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
90 #define REG_RMW(_a, _r, _set, _clr) \
91 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
92 #define REG_RMW_FIELD(_a, _r, _f, _v) \
93 REG_WRITE(_a, _r, \
94 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
95 #define REG_READ_FIELD(_a, _r, _f) \
96 (((REG_READ(_a, _r) & _f) >> _f##_S))
97 #define REG_SET_BIT(_a, _r, _f) \
98 REG_WRITE(_a, _r, REG_READ(_a, _r) | (_f))
99 #define REG_CLR_BIT(_a, _r, _f) \
100 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~(_f))
101
102 #define DO_DELAY(x) do { \
103 if ((++(x) % 64) == 0) \
104 udelay(1); \
105 } while (0)
106
107 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
108 int r; \
109 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
110 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
111 INI_RA((iniarray), r, (column))); \
112 DO_DELAY(regWr); \
113 } \
114 } while (0)
115
116 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
117 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
118 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
119 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
120 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
121 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
122 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
123
124 #define AR_GPIOD_MASK 0x00001FFF
125 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
126
127 #define BASE_ACTIVATE_DELAY 100
128 #define RTC_PLL_SETTLE_DELAY 100
129 #define COEF_SCALE_S 24
130 #define HT40_CHANNEL_CENTER_SHIFT 10
131
132 #define ATH9K_ANTENNA0_CHAINMASK 0x1
133 #define ATH9K_ANTENNA1_CHAINMASK 0x2
134
135 #define ATH9K_NUM_DMA_DEBUG_REGS 8
136 #define ATH9K_NUM_QUEUES 10
137
138 #define MAX_RATE_POWER 63
139 #define AH_WAIT_TIMEOUT 100000 /* (us) */
140 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
141 #define AH_TIME_QUANTUM 10
142 #define AR_KEYTABLE_SIZE 128
143 #define POWER_UP_TIME 10000
144 #define SPUR_RSSI_THRESH 40
145
146 #define CAB_TIMEOUT_VAL 10
147 #define BEACON_TIMEOUT_VAL 10
148 #define MIN_BEACON_TIMEOUT_VAL 1
149 #define SLEEP_SLOP 3
150
151 #define INIT_CONFIG_STATUS 0x00000000
152 #define INIT_RSSI_THR 0x00000700
153 #define INIT_BCON_CNTRL_REG 0x00000000
154
155 #define TU_TO_USEC(_tu) ((_tu) << 10)
156
157 #define ATH9K_HW_RX_HP_QDEPTH 16
158 #define ATH9K_HW_RX_LP_QDEPTH 128
159
160 #define PAPRD_GAIN_TABLE_ENTRIES 32
161 #define PAPRD_TABLE_SZ 24
162
163 enum ath_hw_txq_subtype {
164 ATH_TXQ_AC_BE = 0,
165 ATH_TXQ_AC_BK = 1,
166 ATH_TXQ_AC_VI = 2,
167 ATH_TXQ_AC_VO = 3,
168 };
169
170 enum ath_ini_subsys {
171 ATH_INI_PRE = 0,
172 ATH_INI_CORE,
173 ATH_INI_POST,
174 ATH_INI_NUM_SPLIT,
175 };
176
177 enum ath9k_hw_caps {
178 ATH9K_HW_CAP_HT = BIT(0),
179 ATH9K_HW_CAP_RFSILENT = BIT(1),
180 ATH9K_HW_CAP_CST = BIT(2),
181 ATH9K_HW_CAP_ENHANCEDPM = BIT(3),
182 ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
183 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
184 ATH9K_HW_CAP_EDMA = BIT(6),
185 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7),
186 ATH9K_HW_CAP_LDPC = BIT(8),
187 ATH9K_HW_CAP_FASTCLOCK = BIT(9),
188 ATH9K_HW_CAP_SGI_20 = BIT(10),
189 ATH9K_HW_CAP_PAPRD = BIT(11),
190 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
191 ATH9K_HW_CAP_2GHZ = BIT(13),
192 ATH9K_HW_CAP_5GHZ = BIT(14),
193 ATH9K_HW_CAP_APM = BIT(15),
194 };
195
196 struct ath9k_hw_capabilities {
197 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
198 u16 total_queues;
199 u16 keycache_size;
200 u16 low_5ghz_chan, high_5ghz_chan;
201 u16 low_2ghz_chan, high_2ghz_chan;
202 u16 rts_aggr_limit;
203 u8 tx_chainmask;
204 u8 rx_chainmask;
205 u8 max_txchains;
206 u8 max_rxchains;
207 u16 tx_triglevel_max;
208 u16 reg_cap;
209 u8 num_gpio_pins;
210 u8 rx_hp_qdepth;
211 u8 rx_lp_qdepth;
212 u8 rx_status_len;
213 u8 tx_desc_len;
214 u8 txs_len;
215 u16 pcie_lcr_offset;
216 bool pcie_lcr_extsync_en;
217 };
218
219 struct ath9k_ops_config {
220 int dma_beacon_response_time;
221 int sw_beacon_response_time;
222 int additional_swba_backoff;
223 int ack_6mb;
224 u32 cwm_ignore_extcca;
225 u8 pcie_powersave_enable;
226 bool pcieSerDesWrite;
227 u8 pcie_clock_req;
228 u32 pcie_waen;
229 u8 analog_shiftreg;
230 u8 ht_enable;
231 u8 paprd_disable;
232 u32 ofdm_trig_low;
233 u32 ofdm_trig_high;
234 u32 cck_trig_high;
235 u32 cck_trig_low;
236 u32 enable_ani;
237 int serialize_regmode;
238 bool rx_intr_mitigation;
239 bool tx_intr_mitigation;
240 #define SPUR_DISABLE 0
241 #define SPUR_ENABLE_IOCTL 1
242 #define SPUR_ENABLE_EEPROM 2
243 #define AR_SPUR_5413_1 1640
244 #define AR_SPUR_5413_2 1200
245 #define AR_NO_SPUR 0x8000
246 #define AR_BASE_FREQ_2GHZ 2300
247 #define AR_BASE_FREQ_5GHZ 4900
248 #define AR_SPUR_FEEQ_BOUND_HT40 19
249 #define AR_SPUR_FEEQ_BOUND_HT20 10
250 int spurmode;
251 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
252 u8 max_txtrig_level;
253 u16 ani_poll_interval; /* ANI poll interval in ms */
254 };
255
256 enum ath9k_int {
257 ATH9K_INT_RX = 0x00000001,
258 ATH9K_INT_RXDESC = 0x00000002,
259 ATH9K_INT_RXHP = 0x00000001,
260 ATH9K_INT_RXLP = 0x00000002,
261 ATH9K_INT_RXNOFRM = 0x00000008,
262 ATH9K_INT_RXEOL = 0x00000010,
263 ATH9K_INT_RXORN = 0x00000020,
264 ATH9K_INT_TX = 0x00000040,
265 ATH9K_INT_TXDESC = 0x00000080,
266 ATH9K_INT_TIM_TIMER = 0x00000100,
267 ATH9K_INT_BB_WATCHDOG = 0x00000400,
268 ATH9K_INT_TXURN = 0x00000800,
269 ATH9K_INT_MIB = 0x00001000,
270 ATH9K_INT_RXPHY = 0x00004000,
271 ATH9K_INT_RXKCM = 0x00008000,
272 ATH9K_INT_SWBA = 0x00010000,
273 ATH9K_INT_BMISS = 0x00040000,
274 ATH9K_INT_BNR = 0x00100000,
275 ATH9K_INT_TIM = 0x00200000,
276 ATH9K_INT_DTIM = 0x00400000,
277 ATH9K_INT_DTIMSYNC = 0x00800000,
278 ATH9K_INT_GPIO = 0x01000000,
279 ATH9K_INT_CABEND = 0x02000000,
280 ATH9K_INT_TSFOOR = 0x04000000,
281 ATH9K_INT_GENTIMER = 0x08000000,
282 ATH9K_INT_CST = 0x10000000,
283 ATH9K_INT_GTT = 0x20000000,
284 ATH9K_INT_FATAL = 0x40000000,
285 ATH9K_INT_GLOBAL = 0x80000000,
286 ATH9K_INT_BMISC = ATH9K_INT_TIM |
287 ATH9K_INT_DTIM |
288 ATH9K_INT_DTIMSYNC |
289 ATH9K_INT_TSFOOR |
290 ATH9K_INT_CABEND,
291 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
292 ATH9K_INT_RXDESC |
293 ATH9K_INT_RXEOL |
294 ATH9K_INT_RXORN |
295 ATH9K_INT_TXURN |
296 ATH9K_INT_TXDESC |
297 ATH9K_INT_MIB |
298 ATH9K_INT_RXPHY |
299 ATH9K_INT_RXKCM |
300 ATH9K_INT_SWBA |
301 ATH9K_INT_BMISS |
302 ATH9K_INT_GPIO,
303 ATH9K_INT_NOCARD = 0xffffffff
304 };
305
306 #define CHANNEL_CW_INT 0x00002
307 #define CHANNEL_CCK 0x00020
308 #define CHANNEL_OFDM 0x00040
309 #define CHANNEL_2GHZ 0x00080
310 #define CHANNEL_5GHZ 0x00100
311 #define CHANNEL_PASSIVE 0x00200
312 #define CHANNEL_DYN 0x00400
313 #define CHANNEL_HALF 0x04000
314 #define CHANNEL_QUARTER 0x08000
315 #define CHANNEL_HT20 0x10000
316 #define CHANNEL_HT40PLUS 0x20000
317 #define CHANNEL_HT40MINUS 0x40000
318
319 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
320 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
321 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
322 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
323 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
324 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
325 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
326 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
327 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
328 #define CHANNEL_ALL \
329 (CHANNEL_OFDM| \
330 CHANNEL_CCK| \
331 CHANNEL_2GHZ | \
332 CHANNEL_5GHZ | \
333 CHANNEL_HT20 | \
334 CHANNEL_HT40PLUS | \
335 CHANNEL_HT40MINUS)
336
337 struct ath9k_hw_cal_data {
338 u16 channel;
339 u32 channelFlags;
340 int32_t CalValid;
341 int8_t iCoff;
342 int8_t qCoff;
343 bool paprd_done;
344 bool nfcal_pending;
345 bool nfcal_interference;
346 u16 small_signal_gain[AR9300_MAX_CHAINS];
347 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
348 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
349 };
350
351 struct ath9k_channel {
352 struct ieee80211_channel *chan;
353 struct ar5416AniState ani;
354 u16 channel;
355 u32 channelFlags;
356 u32 chanmode;
357 s16 noisefloor;
358 };
359
360 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
361 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
362 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
363 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
364 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
365 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
366 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
367 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
368 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
369 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
370 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
371 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
372
373 /* These macros check chanmode and not channelFlags */
374 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
375 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
376 ((_c)->chanmode == CHANNEL_G_HT20))
377 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
378 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
379 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
380 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
381 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
382
383 enum ath9k_power_mode {
384 ATH9K_PM_AWAKE = 0,
385 ATH9K_PM_FULL_SLEEP,
386 ATH9K_PM_NETWORK_SLEEP,
387 ATH9K_PM_UNDEFINED
388 };
389
390 enum ath9k_tp_scale {
391 ATH9K_TP_SCALE_MAX = 0,
392 ATH9K_TP_SCALE_50,
393 ATH9K_TP_SCALE_25,
394 ATH9K_TP_SCALE_12,
395 ATH9K_TP_SCALE_MIN
396 };
397
398 enum ser_reg_mode {
399 SER_REG_MODE_OFF = 0,
400 SER_REG_MODE_ON = 1,
401 SER_REG_MODE_AUTO = 2,
402 };
403
404 enum ath9k_rx_qtype {
405 ATH9K_RX_QUEUE_HP,
406 ATH9K_RX_QUEUE_LP,
407 ATH9K_RX_QUEUE_MAX,
408 };
409
410 struct ath9k_beacon_state {
411 u32 bs_nexttbtt;
412 u32 bs_nextdtim;
413 u32 bs_intval;
414 #define ATH9K_BEACON_PERIOD 0x0000ffff
415 #define ATH9K_BEACON_ENA 0x00800000
416 #define ATH9K_BEACON_RESET_TSF 0x01000000
417 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
418 u32 bs_dtimperiod;
419 u16 bs_cfpperiod;
420 u16 bs_cfpmaxduration;
421 u32 bs_cfpnext;
422 u16 bs_timoffset;
423 u16 bs_bmissthreshold;
424 u32 bs_sleepduration;
425 u32 bs_tsfoor_threshold;
426 };
427
428 struct chan_centers {
429 u16 synth_center;
430 u16 ctl_center;
431 u16 ext_center;
432 };
433
434 enum {
435 ATH9K_RESET_POWER_ON,
436 ATH9K_RESET_WARM,
437 ATH9K_RESET_COLD,
438 };
439
440 struct ath9k_hw_version {
441 u32 magic;
442 u16 devid;
443 u16 subvendorid;
444 u32 macVersion;
445 u16 macRev;
446 u16 phyRev;
447 u16 analog5GhzRev;
448 u16 analog2GhzRev;
449 u16 subsysid;
450 enum ath_usb_dev usbdev;
451 };
452
453 /* Generic TSF timer definitions */
454
455 #define ATH_MAX_GEN_TIMER 16
456
457 #define AR_GENTMR_BIT(_index) (1 << (_index))
458
459 /*
460 * Using de Bruijin sequence to look up 1's index in a 32 bit number
461 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
462 */
463 #define debruijn32 0x077CB531U
464
465 struct ath_gen_timer_configuration {
466 u32 next_addr;
467 u32 period_addr;
468 u32 mode_addr;
469 u32 mode_mask;
470 };
471
472 struct ath_gen_timer {
473 void (*trigger)(void *arg);
474 void (*overflow)(void *arg);
475 void *arg;
476 u8 index;
477 };
478
479 struct ath_gen_timer_table {
480 u32 gen_timer_index[32];
481 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
482 union {
483 unsigned long timer_bits;
484 u16 val;
485 } timer_mask;
486 };
487
488 struct ath_hw_antcomb_conf {
489 u8 main_lna_conf;
490 u8 alt_lna_conf;
491 u8 fast_div_bias;
492 };
493
494 /**
495 * struct ath_hw_radar_conf - radar detection initialization parameters
496 *
497 * @pulse_inband: threshold for checking the ratio of in-band power
498 * to total power for short radar pulses (half dB steps)
499 * @pulse_inband_step: threshold for checking an in-band power to total
500 * power ratio increase for short radar pulses (half dB steps)
501 * @pulse_height: threshold for detecting the beginning of a short
502 * radar pulse (dB step)
503 * @pulse_rssi: threshold for detecting if a short radar pulse is
504 * gone (dB step)
505 * @pulse_maxlen: maximum pulse length (0.8 us steps)
506 *
507 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
508 * @radar_inband: threshold for checking the ratio of in-band power
509 * to total power for long radar pulses (half dB steps)
510 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
511 *
512 * @ext_channel: enable extension channel radar detection
513 */
514 struct ath_hw_radar_conf {
515 unsigned int pulse_inband;
516 unsigned int pulse_inband_step;
517 unsigned int pulse_height;
518 unsigned int pulse_rssi;
519 unsigned int pulse_maxlen;
520
521 unsigned int radar_rssi;
522 unsigned int radar_inband;
523 int fir_power;
524
525 bool ext_channel;
526 };
527
528 /**
529 * struct ath_hw_private_ops - callbacks used internally by hardware code
530 *
531 * This structure contains private callbacks designed to only be used internally
532 * by the hardware core.
533 *
534 * @init_cal_settings: setup types of calibrations supported
535 * @init_cal: starts actual calibration
536 *
537 * @init_mode_regs: Initializes mode registers
538 * @init_mode_gain_regs: Initialize TX/RX gain registers
539 *
540 * @rf_set_freq: change frequency
541 * @spur_mitigate_freq: spur mitigation
542 * @rf_alloc_ext_banks:
543 * @rf_free_ext_banks:
544 * @set_rf_regs:
545 * @compute_pll_control: compute the PLL control value to use for
546 * AR_RTC_PLL_CONTROL for a given channel
547 * @setup_calibration: set up calibration
548 * @iscal_supported: used to query if a type of calibration is supported
549 *
550 * @ani_cache_ini_regs: cache the values for ANI from the initial
551 * register settings through the register initialization.
552 */
553 struct ath_hw_private_ops {
554 /* Calibration ops */
555 void (*init_cal_settings)(struct ath_hw *ah);
556 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
557
558 void (*init_mode_regs)(struct ath_hw *ah);
559 void (*init_mode_gain_regs)(struct ath_hw *ah);
560 void (*setup_calibration)(struct ath_hw *ah,
561 struct ath9k_cal_list *currCal);
562
563 /* PHY ops */
564 int (*rf_set_freq)(struct ath_hw *ah,
565 struct ath9k_channel *chan);
566 void (*spur_mitigate_freq)(struct ath_hw *ah,
567 struct ath9k_channel *chan);
568 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
569 void (*rf_free_ext_banks)(struct ath_hw *ah);
570 bool (*set_rf_regs)(struct ath_hw *ah,
571 struct ath9k_channel *chan,
572 u16 modesIndex);
573 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
574 void (*init_bb)(struct ath_hw *ah,
575 struct ath9k_channel *chan);
576 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
577 void (*olc_init)(struct ath_hw *ah);
578 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
579 void (*mark_phy_inactive)(struct ath_hw *ah);
580 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
581 bool (*rfbus_req)(struct ath_hw *ah);
582 void (*rfbus_done)(struct ath_hw *ah);
583 void (*restore_chainmask)(struct ath_hw *ah);
584 void (*set_diversity)(struct ath_hw *ah, bool value);
585 u32 (*compute_pll_control)(struct ath_hw *ah,
586 struct ath9k_channel *chan);
587 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
588 int param);
589 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
590 void (*set_radar_params)(struct ath_hw *ah,
591 struct ath_hw_radar_conf *conf);
592
593 /* ANI */
594 void (*ani_cache_ini_regs)(struct ath_hw *ah);
595 };
596
597 /**
598 * struct ath_hw_ops - callbacks used by hardware code and driver code
599 *
600 * This structure contains callbacks designed to to be used internally by
601 * hardware code and also by the lower level driver.
602 *
603 * @config_pci_powersave:
604 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
605 */
606 struct ath_hw_ops {
607 void (*config_pci_powersave)(struct ath_hw *ah,
608 int restore,
609 int power_off);
610 void (*rx_enable)(struct ath_hw *ah);
611 void (*set_desc_link)(void *ds, u32 link);
612 void (*get_desc_link)(void *ds, u32 **link);
613 bool (*calibrate)(struct ath_hw *ah,
614 struct ath9k_channel *chan,
615 u8 rxchainmask,
616 bool longcal);
617 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
618 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
619 bool is_firstseg, bool is_is_lastseg,
620 const void *ds0, dma_addr_t buf_addr,
621 unsigned int qcu);
622 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
623 struct ath_tx_status *ts);
624 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
625 u32 pktLen, enum ath9k_pkt_type type,
626 u32 txPower, u32 keyIx,
627 enum ath9k_key_type keyType,
628 u32 flags);
629 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
630 void *lastds,
631 u32 durUpdateEn, u32 rtsctsRate,
632 u32 rtsctsDuration,
633 struct ath9k_11n_rate_series series[],
634 u32 nseries, u32 flags);
635 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
636 u32 aggrLen);
637 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
638 u32 numDelims);
639 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
640 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
641 void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
642 u32 burstDuration);
643 void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
644 u32 vmf);
645 };
646
647 struct ath_nf_limits {
648 s16 max;
649 s16 min;
650 s16 nominal;
651 };
652
653 /* ah_flags */
654 #define AH_USE_EEPROM 0x1
655 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
656
657 struct ath_hw {
658 struct ieee80211_hw *hw;
659 struct ath_common common;
660 struct ath9k_hw_version hw_version;
661 struct ath9k_ops_config config;
662 struct ath9k_hw_capabilities caps;
663 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
664 struct ath9k_channel *curchan;
665
666 union {
667 struct ar5416_eeprom_def def;
668 struct ar5416_eeprom_4k map4k;
669 struct ar9287_eeprom map9287;
670 struct ar9300_eeprom ar9300_eep;
671 } eeprom;
672 const struct eeprom_ops *eep_ops;
673
674 bool sw_mgmt_crypto;
675 bool is_pciexpress;
676 bool is_monitoring;
677 bool need_an_top2_fixup;
678 u16 tx_trig_level;
679
680 u32 nf_regs[6];
681 struct ath_nf_limits nf_2g;
682 struct ath_nf_limits nf_5g;
683 u16 rfsilent;
684 u32 rfkill_gpio;
685 u32 rfkill_polarity;
686 u32 ah_flags;
687
688 bool htc_reset_init;
689
690 enum nl80211_iftype opmode;
691 enum ath9k_power_mode power_mode;
692
693 struct ath9k_hw_cal_data *caldata;
694 struct ath9k_pacal_info pacal_info;
695 struct ar5416Stats stats;
696 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
697
698 int16_t curchan_rad_index;
699 enum ath9k_int imask;
700 u32 imrs2_reg;
701 u32 txok_interrupt_mask;
702 u32 txerr_interrupt_mask;
703 u32 txdesc_interrupt_mask;
704 u32 txeol_interrupt_mask;
705 u32 txurn_interrupt_mask;
706 bool chip_fullsleep;
707 u32 atim_window;
708
709 /* Calibration */
710 u32 supp_cals;
711 struct ath9k_cal_list iq_caldata;
712 struct ath9k_cal_list adcgain_caldata;
713 struct ath9k_cal_list adcdc_caldata;
714 struct ath9k_cal_list tempCompCalData;
715 struct ath9k_cal_list *cal_list;
716 struct ath9k_cal_list *cal_list_last;
717 struct ath9k_cal_list *cal_list_curr;
718 #define totalPowerMeasI meas0.unsign
719 #define totalPowerMeasQ meas1.unsign
720 #define totalIqCorrMeas meas2.sign
721 #define totalAdcIOddPhase meas0.unsign
722 #define totalAdcIEvenPhase meas1.unsign
723 #define totalAdcQOddPhase meas2.unsign
724 #define totalAdcQEvenPhase meas3.unsign
725 #define totalAdcDcOffsetIOddPhase meas0.sign
726 #define totalAdcDcOffsetIEvenPhase meas1.sign
727 #define totalAdcDcOffsetQOddPhase meas2.sign
728 #define totalAdcDcOffsetQEvenPhase meas3.sign
729 union {
730 u32 unsign[AR5416_MAX_CHAINS];
731 int32_t sign[AR5416_MAX_CHAINS];
732 } meas0;
733 union {
734 u32 unsign[AR5416_MAX_CHAINS];
735 int32_t sign[AR5416_MAX_CHAINS];
736 } meas1;
737 union {
738 u32 unsign[AR5416_MAX_CHAINS];
739 int32_t sign[AR5416_MAX_CHAINS];
740 } meas2;
741 union {
742 u32 unsign[AR5416_MAX_CHAINS];
743 int32_t sign[AR5416_MAX_CHAINS];
744 } meas3;
745 u16 cal_samples;
746
747 u32 sta_id1_defaults;
748 u32 misc_mode;
749 enum {
750 AUTO_32KHZ,
751 USE_32KHZ,
752 DONT_USE_32KHZ,
753 } enable_32kHz_clock;
754
755 /* Private to hardware code */
756 struct ath_hw_private_ops private_ops;
757 /* Accessed by the lower level driver */
758 struct ath_hw_ops ops;
759
760 /* Used to program the radio on non single-chip devices */
761 u32 *analogBank0Data;
762 u32 *analogBank1Data;
763 u32 *analogBank2Data;
764 u32 *analogBank3Data;
765 u32 *analogBank6Data;
766 u32 *analogBank6TPCData;
767 u32 *analogBank7Data;
768 u32 *addac5416_21;
769 u32 *bank6Temp;
770
771 u8 txpower_limit;
772 int coverage_class;
773 u32 slottime;
774 u32 globaltxtimeout;
775
776 /* ANI */
777 u32 proc_phyerr;
778 u32 aniperiod;
779 int totalSizeDesired[5];
780 int coarse_high[5];
781 int coarse_low[5];
782 int firpwr[5];
783 enum ath9k_ani_cmd ani_function;
784
785 /* Bluetooth coexistance */
786 struct ath_btcoex_hw btcoex_hw;
787
788 u32 intr_txqs;
789 u8 txchainmask;
790 u8 rxchainmask;
791
792 struct ath_hw_radar_conf radar_conf;
793
794 u32 originalGain[22];
795 int initPDADC;
796 int PDADCdelta;
797 u8 led_pin;
798
799 struct ar5416IniArray iniModes;
800 struct ar5416IniArray iniCommon;
801 struct ar5416IniArray iniBank0;
802 struct ar5416IniArray iniBB_RfGain;
803 struct ar5416IniArray iniBank1;
804 struct ar5416IniArray iniBank2;
805 struct ar5416IniArray iniBank3;
806 struct ar5416IniArray iniBank6;
807 struct ar5416IniArray iniBank6TPC;
808 struct ar5416IniArray iniBank7;
809 struct ar5416IniArray iniAddac;
810 struct ar5416IniArray iniPcieSerdes;
811 struct ar5416IniArray iniPcieSerdesLowPower;
812 struct ar5416IniArray iniModesAdditional;
813 struct ar5416IniArray iniModesRxGain;
814 struct ar5416IniArray iniModesTxGain;
815 struct ar5416IniArray iniModes_9271_1_0_only;
816 struct ar5416IniArray iniCckfirNormal;
817 struct ar5416IniArray iniCckfirJapan2484;
818 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
819 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
820 struct ar5416IniArray iniModes_9271_ANI_reg;
821 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
822 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
823
824 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
825 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
826 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
827 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
828
829 u32 intr_gen_timer_trigger;
830 u32 intr_gen_timer_thresh;
831 struct ath_gen_timer_table hw_gen_timers;
832
833 struct ar9003_txs *ts_ring;
834 void *ts_start;
835 u32 ts_paddr_start;
836 u32 ts_paddr_end;
837 u16 ts_tail;
838 u8 ts_size;
839
840 u32 bb_watchdog_last_status;
841 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
842
843 unsigned int paprd_target_power;
844 unsigned int paprd_training_power;
845 unsigned int paprd_ratemask;
846 unsigned int paprd_ratemask_ht40;
847 bool paprd_table_write_done;
848 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
849 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
850 /*
851 * Store the permanent value of Reg 0x4004in WARegVal
852 * so we dont have to R/M/W. We should not be reading
853 * this register when in sleep states.
854 */
855 u32 WARegVal;
856
857 /* Enterprise mode cap */
858 u32 ent_mode;
859 };
860
ath9k_hw_common(struct ath_hw * ah)861 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
862 {
863 return &ah->common;
864 }
865
ath9k_hw_regulatory(struct ath_hw * ah)866 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
867 {
868 return &(ath9k_hw_common(ah)->regulatory);
869 }
870
ath9k_hw_private_ops(struct ath_hw * ah)871 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
872 {
873 return &ah->private_ops;
874 }
875
ath9k_hw_ops(struct ath_hw * ah)876 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
877 {
878 return &ah->ops;
879 }
880
get_streams(int mask)881 static inline u8 get_streams(int mask)
882 {
883 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
884 }
885
886 /* Initialization, Detach, Reset */
887 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
888 void ath9k_hw_deinit(struct ath_hw *ah);
889 int ath9k_hw_init(struct ath_hw *ah);
890 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
891 struct ath9k_hw_cal_data *caldata, bool bChannelChange);
892 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
893 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
894
895 /* GPIO / RFKILL / Antennae */
896 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
897 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
898 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
899 u32 ah_signal_type);
900 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
901 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
902 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
903 void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
904 struct ath_hw_antcomb_conf *antconf);
905 void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
906 struct ath_hw_antcomb_conf *antconf);
907
908 /* General Operation */
909 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
910 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
911 bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
912 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
913 u8 phy, int kbps,
914 u32 frameLen, u16 rateix, bool shortPreamble);
915 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
916 struct ath9k_channel *chan,
917 struct chan_centers *centers);
918 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
919 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
920 bool ath9k_hw_phy_disable(struct ath_hw *ah);
921 bool ath9k_hw_disable(struct ath_hw *ah);
922 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
923 void ath9k_hw_setopmode(struct ath_hw *ah);
924 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
925 void ath9k_hw_setbssidmask(struct ath_hw *ah);
926 void ath9k_hw_write_associd(struct ath_hw *ah);
927 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
928 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
929 void ath9k_hw_reset_tsf(struct ath_hw *ah);
930 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
931 void ath9k_hw_init_global_settings(struct ath_hw *ah);
932 unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
933 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
934 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
935 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
936 const struct ath9k_beacon_state *bs);
937 bool ath9k_hw_check_alive(struct ath_hw *ah);
938
939 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
940
941 /* Generic hw timer primitives */
942 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
943 void (*trigger)(void *),
944 void (*overflow)(void *),
945 void *arg,
946 u8 timer_index);
947 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
948 struct ath_gen_timer *timer,
949 u32 timer_next,
950 u32 timer_period);
951 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
952
953 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
954 void ath_gen_timer_isr(struct ath_hw *hw);
955
956 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
957
958 /* HTC */
959 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
960
961 /* PHY */
962 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
963 u32 *coef_mantissa, u32 *coef_exponent);
964
965 /*
966 * Code Specific to AR5008, AR9001 or AR9002,
967 * we stuff these here to avoid callbacks for AR9003.
968 */
969 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
970 int ar9002_hw_rf_claim(struct ath_hw *ah);
971 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
972 void ar9002_hw_update_async_fifo(struct ath_hw *ah);
973 void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
974
975 /*
976 * Code specific to AR9003, we stuff these here to avoid callbacks
977 * for older families
978 */
979 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
980 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
981 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
982 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
983 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
984 struct ath9k_hw_cal_data *caldata,
985 int chain);
986 int ar9003_paprd_create_curve(struct ath_hw *ah,
987 struct ath9k_hw_cal_data *caldata, int chain);
988 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
989 int ar9003_paprd_init_table(struct ath_hw *ah);
990 bool ar9003_paprd_is_done(struct ath_hw *ah);
991 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
992
993 /* Hardware family op attach helpers */
994 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
995 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
996 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
997
998 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
999 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1000
1001 void ar9002_hw_attach_ops(struct ath_hw *ah);
1002 void ar9003_hw_attach_ops(struct ath_hw *ah);
1003
1004 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1005 /*
1006 * ANI work can be shared between all families but a next
1007 * generation implementation of ANI will be used only for AR9003 only
1008 * for now as the other families still need to be tested with the same
1009 * next generation ANI. Feel free to start testing it though for the
1010 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
1011 */
1012 extern int modparam_force_new_ani;
1013 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1014 void ath9k_hw_proc_mib_event(struct ath_hw *ah);
1015 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1016
1017 #define ATH_PCIE_CAP_LINK_CTRL 0x70
1018 #define ATH_PCIE_CAP_LINK_L0S 1
1019 #define ATH_PCIE_CAP_LINK_L1 2
1020
1021 #define ATH9K_CLOCK_RATE_CCK 22
1022 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1023 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1024 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1025
1026 #endif
1027