1 /*
2 * Copyright (c) 2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "hw.h"
18
19 enum ath_bt_mode {
20 ATH_BT_COEX_MODE_LEGACY, /* legacy rx_clear mode */
21 ATH_BT_COEX_MODE_UNSLOTTED, /* untimed/unslotted mode */
22 ATH_BT_COEX_MODE_SLOTTED, /* slotted mode */
23 ATH_BT_COEX_MODE_DISALBED, /* coexistence disabled */
24 };
25
26 struct ath_btcoex_config {
27 u8 bt_time_extend;
28 bool bt_txstate_extend;
29 bool bt_txframe_extend;
30 enum ath_bt_mode bt_mode; /* coexistence mode */
31 bool bt_quiet_collision;
32 bool bt_rxclear_polarity; /* invert rx_clear as WLAN_ACTIVE*/
33 u8 bt_priority_time;
34 u8 bt_first_slot_time;
35 bool bt_hold_rx_clear;
36 };
37
38
ath9k_hw_init_btcoex_hw(struct ath_hw * ah,int qnum)39 void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
40 {
41 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
42 const struct ath_btcoex_config ath_bt_config = {
43 .bt_time_extend = 0,
44 .bt_txstate_extend = true,
45 .bt_txframe_extend = true,
46 .bt_mode = ATH_BT_COEX_MODE_SLOTTED,
47 .bt_quiet_collision = true,
48 .bt_rxclear_polarity = true,
49 .bt_priority_time = 2,
50 .bt_first_slot_time = 5,
51 .bt_hold_rx_clear = true,
52 };
53 u32 i;
54
55 btcoex_hw->bt_coex_mode =
56 (btcoex_hw->bt_coex_mode & AR_BT_QCU_THRESH) |
57 SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) |
58 SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
59 SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
60 SM(ath_bt_config.bt_mode, AR_BT_MODE) |
61 SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) |
62 SM(ath_bt_config.bt_rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) |
63 SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) |
64 SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) |
65 SM(qnum, AR_BT_QCU_THRESH);
66
67 btcoex_hw->bt_coex_mode2 =
68 SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) |
69 SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
70 AR_BT_DISABLE_BT_ANT;
71
72 for (i = 0; i < 32; i++)
73 ah->hw_gen_timers.gen_timer_index[(debruijn32 << i) >> 27] = i;
74 }
75 EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);
76
ath9k_hw_btcoex_init_2wire(struct ath_hw * ah)77 void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
78 {
79 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
80
81 /* connect bt_active to baseband */
82 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
83 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
84 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
85
86 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
87 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
88
89 /* Set input mux for bt_active to gpio pin */
90 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
91 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
92 btcoex_hw->btactive_gpio);
93
94 /* Configure the desired gpio port for input */
95 ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
96 }
97 EXPORT_SYMBOL(ath9k_hw_btcoex_init_2wire);
98
ath9k_hw_btcoex_init_3wire(struct ath_hw * ah)99 void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
100 {
101 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
102
103 /* btcoex 3-wire */
104 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
105 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
106 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
107
108 /* Set input mux for bt_prority_async and
109 * bt_active_async to GPIO pins */
110 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
111 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
112 btcoex_hw->btactive_gpio);
113
114 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
115 AR_GPIO_INPUT_MUX1_BT_PRIORITY,
116 btcoex_hw->btpriority_gpio);
117
118 /* Configure the desired GPIO ports for input */
119
120 ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
121 ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btpriority_gpio);
122 }
123 EXPORT_SYMBOL(ath9k_hw_btcoex_init_3wire);
124
ath9k_hw_btcoex_enable_2wire(struct ath_hw * ah)125 static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah)
126 {
127 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
128
129 /* Configure the desired GPIO port for TX_FRAME output */
130 ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
131 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
132 }
133
ath9k_hw_btcoex_set_weight(struct ath_hw * ah,u32 bt_weight,u32 wlan_weight)134 void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
135 u32 bt_weight,
136 u32 wlan_weight)
137 {
138 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
139
140 btcoex_hw->bt_coex_weights = SM(bt_weight, AR_BTCOEX_BT_WGHT) |
141 SM(wlan_weight, AR_BTCOEX_WL_WGHT);
142 }
143 EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);
144
ath9k_hw_btcoex_enable_3wire(struct ath_hw * ah)145 static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
146 {
147 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
148 u32 val;
149
150 /*
151 * Program coex mode and weight registers to
152 * enable coex 3-wire
153 */
154 REG_WRITE(ah, AR_BT_COEX_MODE, btcoex_hw->bt_coex_mode);
155 REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_hw->bt_coex_weights);
156 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_hw->bt_coex_mode2);
157
158 if (AR_SREV_9271(ah)) {
159 val = REG_READ(ah, 0x50040);
160 val &= 0xFFFFFEFF;
161 REG_WRITE(ah, 0x50040, val);
162 }
163
164 REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
165 REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
166
167 ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
168 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
169 }
170
ath9k_hw_btcoex_enable(struct ath_hw * ah)171 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
172 {
173 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
174
175 switch (btcoex_hw->scheme) {
176 case ATH_BTCOEX_CFG_NONE:
177 break;
178 case ATH_BTCOEX_CFG_2WIRE:
179 ath9k_hw_btcoex_enable_2wire(ah);
180 break;
181 case ATH_BTCOEX_CFG_3WIRE:
182 ath9k_hw_btcoex_enable_3wire(ah);
183 break;
184 }
185
186 REG_RMW(ah, AR_GPIO_PDPU,
187 (0x2 << (btcoex_hw->btactive_gpio * 2)),
188 (0x3 << (btcoex_hw->btactive_gpio * 2)));
189
190 ah->btcoex_hw.enabled = true;
191 }
192 EXPORT_SYMBOL(ath9k_hw_btcoex_enable);
193
ath9k_hw_btcoex_disable(struct ath_hw * ah)194 void ath9k_hw_btcoex_disable(struct ath_hw *ah)
195 {
196 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
197
198 ath9k_hw_set_gpio(ah, btcoex_hw->wlanactive_gpio, 0);
199
200 ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
201 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
202
203 if (btcoex_hw->scheme == ATH_BTCOEX_CFG_3WIRE) {
204 REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
205 REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
206 REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
207 }
208
209 ah->btcoex_hw.enabled = false;
210 }
211 EXPORT_SYMBOL(ath9k_hw_btcoex_disable);
212