1 /* 2 * falc.h Description of the Siemens FALC T1/E1 framer. 3 * 4 * Author: Ivan Passos <ivan@cyclades.com> 5 * 6 * Copyright: (c) 2000-2001 Cyclades Corp. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 * 13 * $Log: falc-lh.h,v $ 14 * Revision 3.1 2001/06/15 12:41:10 regina 15 * upping major version number 16 * 17 * Revision 1.1.1.1 2001/06/13 20:24:47 daniela 18 * PC300 initial CVS version (3.4.0-pre1) 19 * 20 * Revision 1.1 2000/05/15 ivan 21 * Included DJA bits for the LIM2 register. 22 * 23 * Revision 1.0 2000/02/22 ivan 24 * Initial version. 25 * 26 */ 27 28 #ifndef _FALC_LH_H 29 #define _FALC_LH_H 30 31 #define NUM_OF_T1_CHANNELS 24 32 #define NUM_OF_E1_CHANNELS 32 33 34 /*>>>>>>>>>>>>>>>>> FALC Register Bits (Transmit Mode) <<<<<<<<<<<<<<<<<<< */ 35 36 /* CMDR (Command Register) 37 ---------------- E1 & T1 ------------------------------ */ 38 #define CMDR_RMC 0x80 39 #define CMDR_RRES 0x40 40 #define CMDR_XREP 0x20 41 #define CMDR_XRES 0x10 42 #define CMDR_XHF 0x08 43 #define CMDR_XTF 0x04 44 #define CMDR_XME 0x02 45 #define CMDR_SRES 0x01 46 47 /* MODE (Mode Register) 48 ----------------- E1 & T1 ----------------------------- */ 49 #define MODE_MDS2 0x80 50 #define MODE_MDS1 0x40 51 #define MODE_MDS0 0x20 52 #define MODE_BRAC 0x10 53 #define MODE_HRAC 0x08 54 55 /* IPC (Interrupt Port Configuration) 56 ----------------- E1 & T1 ----------------------------- */ 57 #define IPC_VIS 0x80 58 #define IPC_SCI 0x04 59 #define IPC_IC1 0x02 60 #define IPC_IC0 0x01 61 62 /* CCR1 (Common Configuration Register 1) 63 ----------------- E1 & T1 ----------------------------- */ 64 #define CCR1_SFLG 0x80 65 #define CCR1_XTS16RA 0x40 66 #define CCR1_BRM 0x40 67 #define CCR1_CASSYM 0x20 68 #define CCR1_EDLX 0x20 69 #define CCR1_EITS 0x10 70 #define CCR1_ITF 0x08 71 #define CCR1_RFT1 0x02 72 #define CCR1_RFT0 0x01 73 74 /* CCR3 (Common Configuration Register 3) 75 ---------------- E1 & T1 ------------------------------ */ 76 77 #define CCR3_PRE1 0x80 78 #define CCR3_PRE0 0x40 79 #define CCR3_EPT 0x20 80 #define CCR3_RADD 0x10 81 #define CCR3_RCRC 0x04 82 #define CCR3_XCRC 0x02 83 84 85 /* RTR1-4 (Receive Timeslot Register 1-4) 86 ---------------- E1 & T1 ------------------------------ */ 87 88 #define RTR1_TS0 0x80 89 #define RTR1_TS1 0x40 90 #define RTR1_TS2 0x20 91 #define RTR1_TS3 0x10 92 #define RTR1_TS4 0x08 93 #define RTR1_TS5 0x04 94 #define RTR1_TS6 0x02 95 #define RTR1_TS7 0x01 96 97 #define RTR2_TS8 0x80 98 #define RTR2_TS9 0x40 99 #define RTR2_TS10 0x20 100 #define RTR2_TS11 0x10 101 #define RTR2_TS12 0x08 102 #define RTR2_TS13 0x04 103 #define RTR2_TS14 0x02 104 #define RTR2_TS15 0x01 105 106 #define RTR3_TS16 0x80 107 #define RTR3_TS17 0x40 108 #define RTR3_TS18 0x20 109 #define RTR3_TS19 0x10 110 #define RTR3_TS20 0x08 111 #define RTR3_TS21 0x04 112 #define RTR3_TS22 0x02 113 #define RTR3_TS23 0x01 114 115 #define RTR4_TS24 0x80 116 #define RTR4_TS25 0x40 117 #define RTR4_TS26 0x20 118 #define RTR4_TS27 0x10 119 #define RTR4_TS28 0x08 120 #define RTR4_TS29 0x04 121 #define RTR4_TS30 0x02 122 #define RTR4_TS31 0x01 123 124 125 /* TTR1-4 (Transmit Timeslot Register 1-4) 126 ---------------- E1 & T1 ------------------------------ */ 127 128 #define TTR1_TS0 0x80 129 #define TTR1_TS1 0x40 130 #define TTR1_TS2 0x20 131 #define TTR1_TS3 0x10 132 #define TTR1_TS4 0x08 133 #define TTR1_TS5 0x04 134 #define TTR1_TS6 0x02 135 #define TTR1_TS7 0x01 136 137 #define TTR2_TS8 0x80 138 #define TTR2_TS9 0x40 139 #define TTR2_TS10 0x20 140 #define TTR2_TS11 0x10 141 #define TTR2_TS12 0x08 142 #define TTR2_TS13 0x04 143 #define TTR2_TS14 0x02 144 #define TTR2_TS15 0x01 145 146 #define TTR3_TS16 0x80 147 #define TTR3_TS17 0x40 148 #define TTR3_TS18 0x20 149 #define TTR3_TS19 0x10 150 #define TTR3_TS20 0x08 151 #define TTR3_TS21 0x04 152 #define TTR3_TS22 0x02 153 #define TTR3_TS23 0x01 154 155 #define TTR4_TS24 0x80 156 #define TTR4_TS25 0x40 157 #define TTR4_TS26 0x20 158 #define TTR4_TS27 0x10 159 #define TTR4_TS28 0x08 160 #define TTR4_TS29 0x04 161 #define TTR4_TS30 0x02 162 #define TTR4_TS31 0x01 163 164 165 166 /* IMR0-4 (Interrupt Mask Register 0-4) 167 168 ----------------- E1 & T1 ----------------------------- */ 169 170 #define IMR0_RME 0x80 171 #define IMR0_RFS 0x40 172 #define IMR0_T8MS 0x20 173 #define IMR0_ISF 0x20 174 #define IMR0_RMB 0x10 175 #define IMR0_CASC 0x08 176 #define IMR0_RSC 0x08 177 #define IMR0_CRC6 0x04 178 #define IMR0_CRC4 0x04 179 #define IMR0_PDEN 0x02 180 #define IMR0_RPF 0x01 181 182 #define IMR1_CASE 0x80 183 #define IMR1_RDO 0x40 184 #define IMR1_ALLS 0x20 185 #define IMR1_XDU 0x10 186 #define IMR1_XMB 0x08 187 #define IMR1_XLSC 0x02 188 #define IMR1_XPR 0x01 189 #define IMR1_LLBSC 0x80 190 191 #define IMR2_FAR 0x80 192 #define IMR2_LFA 0x40 193 #define IMR2_MFAR 0x20 194 #define IMR2_T400MS 0x10 195 #define IMR2_LMFA 0x10 196 #define IMR2_AIS 0x08 197 #define IMR2_LOS 0x04 198 #define IMR2_RAR 0x02 199 #define IMR2_RA 0x01 200 201 #define IMR3_ES 0x80 202 #define IMR3_SEC 0x40 203 #define IMR3_LMFA16 0x20 204 #define IMR3_AIS16 0x10 205 #define IMR3_RA16 0x08 206 #define IMR3_API 0x04 207 #define IMR3_XSLP 0x20 208 #define IMR3_XSLN 0x10 209 #define IMR3_LLBSC 0x08 210 #define IMR3_XRS 0x04 211 #define IMR3_SLN 0x02 212 #define IMR3_SLP 0x01 213 214 #define IMR4_LFA 0x80 215 #define IMR4_FER 0x40 216 #define IMR4_CER 0x20 217 #define IMR4_AIS 0x10 218 #define IMR4_LOS 0x08 219 #define IMR4_CVE 0x04 220 #define IMR4_SLIP 0x02 221 #define IMR4_EBE 0x01 222 223 /* FMR0-5 for E1 and T1 (Framer Mode Register ) */ 224 225 #define FMR0_XC1 0x80 226 #define FMR0_XC0 0x40 227 #define FMR0_RC1 0x20 228 #define FMR0_RC0 0x10 229 #define FMR0_EXTD 0x08 230 #define FMR0_ALM 0x04 231 #define E1_FMR0_FRS 0x02 232 #define T1_FMR0_FRS 0x08 233 #define FMR0_SRAF 0x04 234 #define FMR0_EXLS 0x02 235 #define FMR0_SIM 0x01 236 237 #define FMR1_MFCS 0x80 238 #define FMR1_AFR 0x40 239 #define FMR1_ENSA 0x20 240 #define FMR1_CTM 0x80 241 #define FMR1_SIGM 0x40 242 #define FMR1_EDL 0x20 243 #define FMR1_PMOD 0x10 244 #define FMR1_XFS 0x08 245 #define FMR1_CRC 0x08 246 #define FMR1_ECM 0x04 247 #define FMR1_IMOD 0x02 248 #define FMR1_XAIS 0x01 249 250 #define FMR2_RFS1 0x80 251 #define FMR2_RFS0 0x40 252 #define FMR2_MCSP 0x40 253 #define FMR2_RTM 0x20 254 #define FMR2_SSP 0x20 255 #define FMR2_DAIS 0x10 256 #define FMR2_SAIS 0x08 257 #define FMR2_PLB 0x04 258 #define FMR2_AXRA 0x02 259 #define FMR2_ALMF 0x01 260 #define FMR2_EXZE 0x01 261 262 #define LOOP_RTM 0x40 263 #define LOOP_SFM 0x40 264 #define LOOP_ECLB 0x20 265 #define LOOP_CLA 0x1f 266 267 /*--------------------- E1 ----------------------------*/ 268 #define FMR3_XLD 0x20 269 #define FMR3_XLU 0x10 270 271 /*--------------------- T1 ----------------------------*/ 272 #define FMR4_AIS3 0x80 273 #define FMR4_TM 0x40 274 #define FMR4_XRA 0x20 275 #define FMR4_SSC1 0x10 276 #define FMR4_SSC0 0x08 277 #define FMR4_AUTO 0x04 278 #define FMR4_FM1 0x02 279 #define FMR4_FM0 0x01 280 281 #define FMR5_SRS 0x80 282 #define FMR5_EIBR 0x40 283 #define FMR5_XLD 0x20 284 #define FMR5_XLU 0x10 285 286 287 /* LOOP (Channel Loop Back) 288 289 ------------------ E1 & T1 ---------------------------- */ 290 291 #define LOOP_SFM 0x40 292 #define LOOP_ECLB 0x20 293 #define LOOP_CLA4 0x10 294 #define LOOP_CLA3 0x08 295 #define LOOP_CLA2 0x04 296 #define LOOP_CLA1 0x02 297 #define LOOP_CLA0 0x01 298 299 300 301 /* XSW (Transmit Service Word Pulseframe) 302 303 ------------------- E1 --------------------------- */ 304 305 #define XSW_XSIS 0x80 306 #define XSW_XTM 0x40 307 #define XSW_XRA 0x20 308 #define XSW_XY0 0x10 309 #define XSW_XY1 0x08 310 #define XSW_XY2 0x04 311 #define XSW_XY3 0x02 312 #define XSW_XY4 0x01 313 314 315 /* XSP (Transmit Spare Bits) 316 317 ------------------- E1 --------------------------- */ 318 319 #define XSP_XAP 0x80 320 #define XSP_CASEN 0x40 321 #define XSP_TT0 0x20 322 #define XSP_EBP 0x10 323 #define XSP_AXS 0x08 324 #define XSP_XSIF 0x04 325 #define XSP_XS13 0x02 326 #define XSP_XS15 0x01 327 328 329 /* XC0/1 (Transmit Control 0/1) 330 ------------------ E1 & T1 ---------------------------- */ 331 332 #define XC0_SA8E 0x80 333 #define XC0_SA7E 0x40 334 #define XC0_SA6E 0x20 335 #define XC0_SA5E 0x10 336 #define XC0_SA4E 0x08 337 #define XC0_BRM 0x80 338 #define XC0_MFBS 0x40 339 #define XC0_SFRZ 0x10 340 #define XC0_XCO2 0x04 341 #define XC0_XCO1 0x02 342 #define XC0_XCO0 0x01 343 344 #define XC1_XTO5 0x20 345 #define XC1_XTO4 0x10 346 #define XC1_XTO3 0x08 347 #define XC1_XTO2 0x04 348 #define XC1_XTO1 0x02 349 #define XC1_XTO0 0x01 350 351 352 /* RC0/1 (Receive Control 0/1) 353 ------------------ E1 & T1 ---------------------------- */ 354 355 #define RC0_SICS 0x40 356 #define RC0_CRCI 0x20 357 #define RC0_XCRCI 0x10 358 #define RC0_RDIS 0x08 359 #define RC0_RCO2 0x04 360 #define RC0_RCO1 0x02 361 #define RC0_RCO0 0x01 362 363 #define RC1_SWD 0x80 364 #define RC1_ASY4 0x40 365 #define RC1_RRAM 0x40 366 #define RC1_RTO5 0x20 367 #define RC1_RTO4 0x10 368 #define RC1_RTO3 0x08 369 #define RC1_RTO2 0x04 370 #define RC1_RTO1 0x02 371 #define RC1_RTO0 0x01 372 373 374 375 /* XPM0-2 (Transmit Pulse Mask 0-2) 376 --------------------- E1 & T1 ------------------------- */ 377 378 #define XPM0_XP12 0x80 379 #define XPM0_XP11 0x40 380 #define XPM0_XP10 0x20 381 #define XPM0_XP04 0x10 382 #define XPM0_XP03 0x08 383 #define XPM0_XP02 0x04 384 #define XPM0_XP01 0x02 385 #define XPM0_XP00 0x01 386 387 #define XPM1_XP30 0x80 388 #define XPM1_XP24 0x40 389 #define XPM1_XP23 0x20 390 #define XPM1_XP22 0x10 391 #define XPM1_XP21 0x08 392 #define XPM1_XP20 0x04 393 #define XPM1_XP14 0x02 394 #define XPM1_XP13 0x01 395 396 #define XPM2_XLHP 0x80 397 #define XPM2_XLT 0x40 398 #define XPM2_DAXLT 0x20 399 #define XPM2_XP34 0x08 400 #define XPM2_XP33 0x04 401 #define XPM2_XP32 0x02 402 #define XPM2_XP31 0x01 403 404 405 /* TSWM (Transparent Service Word Mask) 406 ------------------ E1 ---------------------------- */ 407 408 #define TSWM_TSIS 0x80 409 #define TSWM_TSIF 0x40 410 #define TSWM_TRA 0x20 411 #define TSWM_TSA4 0x10 412 #define TSWM_TSA5 0x08 413 #define TSWM_TSA6 0x04 414 #define TSWM_TSA7 0x02 415 #define TSWM_TSA8 0x01 416 417 /* IDLE <Idle Channel Code Register> 418 419 ------------------ E1 & T1 ----------------------- */ 420 421 #define IDLE_IDL7 0x80 422 #define IDLE_IDL6 0x40 423 #define IDLE_IDL5 0x20 424 #define IDLE_IDL4 0x10 425 #define IDLE_IDL3 0x08 426 #define IDLE_IDL2 0x04 427 #define IDLE_IDL1 0x02 428 #define IDLE_IDL0 0x01 429 430 431 /* XSA4-8 <Transmit SA4-8 Register(Read/Write) > 432 -------------------E1 ----------------------------- */ 433 434 #define XSA4_XS47 0x80 435 #define XSA4_XS46 0x40 436 #define XSA4_XS45 0x20 437 #define XSA4_XS44 0x10 438 #define XSA4_XS43 0x08 439 #define XSA4_XS42 0x04 440 #define XSA4_XS41 0x02 441 #define XSA4_XS40 0x01 442 443 #define XSA5_XS57 0x80 444 #define XSA5_XS56 0x40 445 #define XSA5_XS55 0x20 446 #define XSA5_XS54 0x10 447 #define XSA5_XS53 0x08 448 #define XSA5_XS52 0x04 449 #define XSA5_XS51 0x02 450 #define XSA5_XS50 0x01 451 452 #define XSA6_XS67 0x80 453 #define XSA6_XS66 0x40 454 #define XSA6_XS65 0x20 455 #define XSA6_XS64 0x10 456 #define XSA6_XS63 0x08 457 #define XSA6_XS62 0x04 458 #define XSA6_XS61 0x02 459 #define XSA6_XS60 0x01 460 461 #define XSA7_XS77 0x80 462 #define XSA7_XS76 0x40 463 #define XSA7_XS75 0x20 464 #define XSA7_XS74 0x10 465 #define XSA7_XS73 0x08 466 #define XSA7_XS72 0x04 467 #define XSA7_XS71 0x02 468 #define XSA7_XS70 0x01 469 470 #define XSA8_XS87 0x80 471 #define XSA8_XS86 0x40 472 #define XSA8_XS85 0x20 473 #define XSA8_XS84 0x10 474 #define XSA8_XS83 0x08 475 #define XSA8_XS82 0x04 476 #define XSA8_XS81 0x02 477 #define XSA8_XS80 0x01 478 479 480 /* XDL1-3 (Transmit DL-Bit Register1-3 (read/write)) 481 ----------------------- T1 --------------------- */ 482 483 #define XDL1_XDL17 0x80 484 #define XDL1_XDL16 0x40 485 #define XDL1_XDL15 0x20 486 #define XDL1_XDL14 0x10 487 #define XDL1_XDL13 0x08 488 #define XDL1_XDL12 0x04 489 #define XDL1_XDL11 0x02 490 #define XDL1_XDL10 0x01 491 492 #define XDL2_XDL27 0x80 493 #define XDL2_XDL26 0x40 494 #define XDL2_XDL25 0x20 495 #define XDL2_XDL24 0x10 496 #define XDL2_XDL23 0x08 497 #define XDL2_XDL22 0x04 498 #define XDL2_XDL21 0x02 499 #define XDL2_XDL20 0x01 500 501 #define XDL3_XDL37 0x80 502 #define XDL3_XDL36 0x40 503 #define XDL3_XDL35 0x20 504 #define XDL3_XDL34 0x10 505 #define XDL3_XDL33 0x08 506 #define XDL3_XDL32 0x04 507 #define XDL3_XDL31 0x02 508 #define XDL3_XDL30 0x01 509 510 511 /* ICB1-4 (Idle Channel Register 1-4) 512 ------------------ E1 ---------------------------- */ 513 514 #define E1_ICB1_IC0 0x80 515 #define E1_ICB1_IC1 0x40 516 #define E1_ICB1_IC2 0x20 517 #define E1_ICB1_IC3 0x10 518 #define E1_ICB1_IC4 0x08 519 #define E1_ICB1_IC5 0x04 520 #define E1_ICB1_IC6 0x02 521 #define E1_ICB1_IC7 0x01 522 523 #define E1_ICB2_IC8 0x80 524 #define E1_ICB2_IC9 0x40 525 #define E1_ICB2_IC10 0x20 526 #define E1_ICB2_IC11 0x10 527 #define E1_ICB2_IC12 0x08 528 #define E1_ICB2_IC13 0x04 529 #define E1_ICB2_IC14 0x02 530 #define E1_ICB2_IC15 0x01 531 532 #define E1_ICB3_IC16 0x80 533 #define E1_ICB3_IC17 0x40 534 #define E1_ICB3_IC18 0x20 535 #define E1_ICB3_IC19 0x10 536 #define E1_ICB3_IC20 0x08 537 #define E1_ICB3_IC21 0x04 538 #define E1_ICB3_IC22 0x02 539 #define E1_ICB3_IC23 0x01 540 541 #define E1_ICB4_IC24 0x80 542 #define E1_ICB4_IC25 0x40 543 #define E1_ICB4_IC26 0x20 544 #define E1_ICB4_IC27 0x10 545 #define E1_ICB4_IC28 0x08 546 #define E1_ICB4_IC29 0x04 547 #define E1_ICB4_IC30 0x02 548 #define E1_ICB4_IC31 0x01 549 550 /* ICB1-4 (Idle Channel Register 1-4) 551 ------------------ T1 ---------------------------- */ 552 553 #define T1_ICB1_IC1 0x80 554 #define T1_ICB1_IC2 0x40 555 #define T1_ICB1_IC3 0x20 556 #define T1_ICB1_IC4 0x10 557 #define T1_ICB1_IC5 0x08 558 #define T1_ICB1_IC6 0x04 559 #define T1_ICB1_IC7 0x02 560 #define T1_ICB1_IC8 0x01 561 562 #define T1_ICB2_IC9 0x80 563 #define T1_ICB2_IC10 0x40 564 #define T1_ICB2_IC11 0x20 565 #define T1_ICB2_IC12 0x10 566 #define T1_ICB2_IC13 0x08 567 #define T1_ICB2_IC14 0x04 568 #define T1_ICB2_IC15 0x02 569 #define T1_ICB2_IC16 0x01 570 571 #define T1_ICB3_IC17 0x80 572 #define T1_ICB3_IC18 0x40 573 #define T1_ICB3_IC19 0x20 574 #define T1_ICB3_IC20 0x10 575 #define T1_ICB3_IC21 0x08 576 #define T1_ICB3_IC22 0x04 577 #define T1_ICB3_IC23 0x02 578 #define T1_ICB3_IC24 0x01 579 580 /* FMR3 (Framer Mode Register 3) 581 --------------------E1------------------------ */ 582 583 #define FMR3_CMI 0x08 584 #define FMR3_SYNSA 0x04 585 #define FMR3_CFRZ 0x02 586 #define FMR3_EXTIW 0x01 587 588 589 590 /* CCB1-3 (Clear Channel Register) 591 ------------------- T1 ----------------------- */ 592 593 #define CCB1_CH1 0x80 594 #define CCB1_CH2 0x40 595 #define CCB1_CH3 0x20 596 #define CCB1_CH4 0x10 597 #define CCB1_CH5 0x08 598 #define CCB1_CH6 0x04 599 #define CCB1_CH7 0x02 600 #define CCB1_CH8 0x01 601 602 #define CCB2_CH9 0x80 603 #define CCB2_CH10 0x40 604 #define CCB2_CH11 0x20 605 #define CCB2_CH12 0x10 606 #define CCB2_CH13 0x08 607 #define CCB2_CH14 0x04 608 #define CCB2_CH15 0x02 609 #define CCB2_CH16 0x01 610 611 #define CCB3_CH17 0x80 612 #define CCB3_CH18 0x40 613 #define CCB3_CH19 0x20 614 #define CCB3_CH20 0x10 615 #define CCB3_CH21 0x08 616 #define CCB3_CH22 0x04 617 #define CCB3_CH23 0x02 618 #define CCB3_CH24 0x01 619 620 621 /* LIM0/1 (Line Interface Mode 0/1) 622 ------------------- E1 & T1 --------------------------- */ 623 624 #define LIM0_XFB 0x80 625 #define LIM0_XDOS 0x40 626 #define LIM0_SCL1 0x20 627 #define LIM0_SCL0 0x10 628 #define LIM0_EQON 0x08 629 #define LIM0_ELOS 0x04 630 #define LIM0_LL 0x02 631 #define LIM0_MAS 0x01 632 633 #define LIM1_EFSC 0x80 634 #define LIM1_RIL2 0x40 635 #define LIM1_RIL1 0x20 636 #define LIM1_RIL0 0x10 637 #define LIM1_DCOC 0x08 638 #define LIM1_JATT 0x04 639 #define LIM1_RL 0x02 640 #define LIM1_DRS 0x01 641 642 643 /* PCDR (Pulse Count Detection Register(Read/Write)) 644 ------------------ E1 & T1 ------------------------- */ 645 646 #define PCDR_PCD7 0x80 647 #define PCDR_PCD6 0x40 648 #define PCDR_PCD5 0x20 649 #define PCDR_PCD4 0x10 650 #define PCDR_PCD3 0x08 651 #define PCDR_PCD2 0x04 652 #define PCDR_PCD1 0x02 653 #define PCDR_PCD0 0x01 654 655 #define PCRR_PCR7 0x80 656 #define PCRR_PCR6 0x40 657 #define PCRR_PCR5 0x20 658 #define PCRR_PCR4 0x10 659 #define PCRR_PCR3 0x08 660 #define PCRR_PCR2 0x04 661 #define PCRR_PCR1 0x02 662 #define PCRR_PCR0 0x01 663 664 665 /* LIM2 (Line Interface Mode 2) 666 667 ------------------ E1 & T1 ---------------------------- */ 668 669 #define LIM2_DJA2 0x20 670 #define LIM2_DJA1 0x10 671 #define LIM2_LOS2 0x02 672 #define LIM2_LOS1 0x01 673 674 /* LCR1 (Loop Code Register 1) */ 675 676 #define LCR1_EPRM 0x80 677 #define LCR1_XPRBS 0x40 678 679 /* SIC1 (System Interface Control 1) */ 680 #define SIC1_SRSC 0x80 681 #define SIC1_RBS1 0x20 682 #define SIC1_RBS0 0x10 683 #define SIC1_SXSC 0x08 684 #define SIC1_XBS1 0x02 685 #define SIC1_XBS0 0x01 686 687 /* DEC (Disable Error Counter) 688 ------------------ E1 & T1 ---------------------------- */ 689 690 #define DEC_DCEC3 0x20 691 #define DEC_DBEC 0x10 692 #define DEC_DCEC1 0x08 693 #define DEC_DCEC 0x08 694 #define DEC_DEBC 0x04 695 #define DEC_DCVC 0x02 696 #define DEC_DFEC 0x01 697 698 699 /* FALC Register Bits (Receive Mode) 700 ---------------------------------------------------------------------------- */ 701 702 703 /* FRS0/1 (Framer Receive Status Register 0/1) 704 ----------------- E1 & T1 ---------------------------------- */ 705 706 #define FRS0_LOS 0x80 707 #define FRS0_AIS 0x40 708 #define FRS0_LFA 0x20 709 #define FRS0_RRA 0x10 710 #define FRS0_API 0x08 711 #define FRS0_NMF 0x04 712 #define FRS0_LMFA 0x02 713 #define FRS0_FSRF 0x01 714 715 #define FRS1_TS16RA 0x40 716 #define FRS1_TS16LOS 0x20 717 #define FRS1_TS16AIS 0x10 718 #define FRS1_TS16LFA 0x08 719 #define FRS1_EXZD 0x80 720 #define FRS1_LLBDD 0x10 721 #define FRS1_LLBAD 0x08 722 #define FRS1_XLS 0x02 723 #define FRS1_XLO 0x01 724 #define FRS1_PDEN 0x40 725 726 /* FRS2/3 (Framer Receive Status Register 2/3) 727 ----------------- T1 ---------------------------------- */ 728 729 #define FRS2_ESC2 0x80 730 #define FRS2_ESC1 0x40 731 #define FRS2_ESC0 0x20 732 733 #define FRS3_FEH5 0x20 734 #define FRS3_FEH4 0x10 735 #define FRS3_FEH3 0x08 736 #define FRS3_FEH2 0x04 737 #define FRS3_FEH1 0x02 738 #define FRS3_FEH0 0x01 739 740 741 /* RSW (Receive Service Word Pulseframe) 742 ----------------- E1 ------------------------------ */ 743 744 #define RSW_RSI 0x80 745 #define RSW_RRA 0x20 746 #define RSW_RYO 0x10 747 #define RSW_RY1 0x08 748 #define RSW_RY2 0x04 749 #define RSW_RY3 0x02 750 #define RSW_RY4 0x01 751 752 753 /* RSP (Receive Spare Bits / Additional Status) 754 ---------------- E1 ------------------------------- */ 755 756 #define RSP_SI1 0x80 757 #define RSP_SI2 0x40 758 #define RSP_LLBDD 0x10 759 #define RSP_LLBAD 0x08 760 #define RSP_RSIF 0x04 761 #define RSP_RS13 0x02 762 #define RSP_RS15 0x01 763 764 765 /* FECL (Framing Error Counter) 766 ---------------- E1 & T1 -------------------------- */ 767 768 #define FECL_FE7 0x80 769 #define FECL_FE6 0x40 770 #define FECL_FE5 0x20 771 #define FECL_FE4 0x10 772 #define FECL_FE3 0x08 773 #define FECL_FE2 0x04 774 #define FECL_FE1 0x02 775 #define FECL_FE0 0x01 776 777 #define FECH_FE15 0x80 778 #define FECH_FE14 0x40 779 #define FECH_FE13 0x20 780 #define FECH_FE12 0x10 781 #define FECH_FE11 0x08 782 #define FECH_FE10 0x04 783 #define FECH_FE9 0x02 784 #define FECH_FE8 0x01 785 786 787 /* CVCl (Code Violation Counter) 788 ----------------- E1 ------------------------- */ 789 790 #define CVCL_CV7 0x80 791 #define CVCL_CV6 0x40 792 #define CVCL_CV5 0x20 793 #define CVCL_CV4 0x10 794 #define CVCL_CV3 0x08 795 #define CVCL_CV2 0x04 796 #define CVCL_CV1 0x02 797 #define CVCL_CV0 0x01 798 799 #define CVCH_CV15 0x80 800 #define CVCH_CV14 0x40 801 #define CVCH_CV13 0x20 802 #define CVCH_CV12 0x10 803 #define CVCH_CV11 0x08 804 #define CVCH_CV10 0x04 805 #define CVCH_CV9 0x02 806 #define CVCH_CV8 0x01 807 808 809 /* CEC1-3L (CRC Error Counter) 810 ------------------ E1 ----------------------------- */ 811 812 #define CEC1L_CR7 0x80 813 #define CEC1L_CR6 0x40 814 #define CEC1L_CR5 0x20 815 #define CEC1L_CR4 0x10 816 #define CEC1L_CR3 0x08 817 #define CEC1L_CR2 0x04 818 #define CEC1L_CR1 0x02 819 #define CEC1L_CR0 0x01 820 821 #define CEC1H_CR15 0x80 822 #define CEC1H_CR14 0x40 823 #define CEC1H_CR13 0x20 824 #define CEC1H_CR12 0x10 825 #define CEC1H_CR11 0x08 826 #define CEC1H_CR10 0x04 827 #define CEC1H_CR9 0x02 828 #define CEC1H_CR8 0x01 829 830 #define CEC2L_CR7 0x80 831 #define CEC2L_CR6 0x40 832 #define CEC2L_CR5 0x20 833 #define CEC2L_CR4 0x10 834 #define CEC2L_CR3 0x08 835 #define CEC2L_CR2 0x04 836 #define CEC2L_CR1 0x02 837 #define CEC2L_CR0 0x01 838 839 #define CEC2H_CR15 0x80 840 #define CEC2H_CR14 0x40 841 #define CEC2H_CR13 0x20 842 #define CEC2H_CR12 0x10 843 #define CEC2H_CR11 0x08 844 #define CEC2H_CR10 0x04 845 #define CEC2H_CR9 0x02 846 #define CEC2H_CR8 0x01 847 848 #define CEC3L_CR7 0x80 849 #define CEC3L_CR6 0x40 850 #define CEC3L_CR5 0x20 851 #define CEC3L_CR4 0x10 852 #define CEC3L_CR3 0x08 853 #define CEC3L_CR2 0x04 854 #define CEC3L_CR1 0x02 855 #define CEC3L_CR0 0x01 856 857 #define CEC3H_CR15 0x80 858 #define CEC3H_CR14 0x40 859 #define CEC3H_CR13 0x20 860 #define CEC3H_CR12 0x10 861 #define CEC3H_CR11 0x08 862 #define CEC3H_CR10 0x04 863 #define CEC3H_CR9 0x02 864 #define CEC3H_CR8 0x01 865 866 867 /* CECL (CRC Error Counter) 868 869 ------------------ T1 ----------------------------- */ 870 871 #define CECL_CR7 0x80 872 #define CECL_CR6 0x40 873 #define CECL_CR5 0x20 874 #define CECL_CR4 0x10 875 #define CECL_CR3 0x08 876 #define CECL_CR2 0x04 877 #define CECL_CR1 0x02 878 #define CECL_CR0 0x01 879 880 #define CECH_CR15 0x80 881 #define CECH_CR14 0x40 882 #define CECH_CR13 0x20 883 #define CECH_CR12 0x10 884 #define CECH_CR11 0x08 885 #define CECH_CR10 0x04 886 #define CECH_CR9 0x02 887 #define CECH_CR8 0x01 888 889 /* EBCL (E Bit Error Counter) 890 ------------------- E1 & T1 ------------------------- */ 891 892 #define EBCL_EB7 0x80 893 #define EBCL_EB6 0x40 894 #define EBCL_EB5 0x20 895 #define EBCL_EB4 0x10 896 #define EBCL_EB3 0x08 897 #define EBCL_EB2 0x04 898 #define EBCL_EB1 0x02 899 #define EBCL_EB0 0x01 900 901 #define EBCH_EB15 0x80 902 #define EBCH_EB14 0x40 903 #define EBCH_EB13 0x20 904 #define EBCH_EB12 0x10 905 #define EBCH_EB11 0x08 906 #define EBCH_EB10 0x04 907 #define EBCH_EB9 0x02 908 #define EBCH_EB8 0x01 909 910 911 /* RSA4-8 (Receive Sa4-8-Bit Register) 912 -------------------- E1 --------------------------- */ 913 914 #define RSA4_RS47 0x80 915 #define RSA4_RS46 0x40 916 #define RSA4_RS45 0x20 917 #define RSA4_RS44 0x10 918 #define RSA4_RS43 0x08 919 #define RSA4_RS42 0x04 920 #define RSA4_RS41 0x02 921 #define RSA4_RS40 0x01 922 923 #define RSA5_RS57 0x80 924 #define RSA5_RS56 0x40 925 #define RSA5_RS55 0x20 926 #define RSA5_RS54 0x10 927 #define RSA5_RS53 0x08 928 #define RSA5_RS52 0x04 929 #define RSA5_RS51 0x02 930 #define RSA5_RS50 0x01 931 932 #define RSA6_RS67 0x80 933 #define RSA6_RS66 0x40 934 #define RSA6_RS65 0x20 935 #define RSA6_RS64 0x10 936 #define RSA6_RS63 0x08 937 #define RSA6_RS62 0x04 938 #define RSA6_RS61 0x02 939 #define RSA6_RS60 0x01 940 941 #define RSA7_RS77 0x80 942 #define RSA7_RS76 0x40 943 #define RSA7_RS75 0x20 944 #define RSA7_RS74 0x10 945 #define RSA7_RS73 0x08 946 #define RSA7_RS72 0x04 947 #define RSA7_RS71 0x02 948 #define RSA7_RS70 0x01 949 950 #define RSA8_RS87 0x80 951 #define RSA8_RS86 0x40 952 #define RSA8_RS85 0x20 953 #define RSA8_RS84 0x10 954 #define RSA8_RS83 0x08 955 #define RSA8_RS82 0x04 956 #define RSA8_RS81 0x02 957 #define RSA8_RS80 0x01 958 959 /* RSA6S (Receive Sa6 Bit Status Register) 960 ------------------------ T1 ------------------------- */ 961 962 #define RSA6S_SX 0x20 963 #define RSA6S_SF 0x10 964 #define RSA6S_SE 0x08 965 #define RSA6S_SC 0x04 966 #define RSA6S_SA 0x02 967 #define RSA6S_S8 0x01 968 969 970 /* RDL1-3 Receive DL-Bit Register1-3) 971 ------------------------ T1 ------------------------- */ 972 973 #define RDL1_RDL17 0x80 974 #define RDL1_RDL16 0x40 975 #define RDL1_RDL15 0x20 976 #define RDL1_RDL14 0x10 977 #define RDL1_RDL13 0x08 978 #define RDL1_RDL12 0x04 979 #define RDL1_RDL11 0x02 980 #define RDL1_RDL10 0x01 981 982 #define RDL2_RDL27 0x80 983 #define RDL2_RDL26 0x40 984 #define RDL2_RDL25 0x20 985 #define RDL2_RDL24 0x10 986 #define RDL2_RDL23 0x08 987 #define RDL2_RDL22 0x04 988 #define RDL2_RDL21 0x02 989 #define RDL2_RDL20 0x01 990 991 #define RDL3_RDL37 0x80 992 #define RDL3_RDL36 0x40 993 #define RDL3_RDL35 0x20 994 #define RDL3_RDL34 0x10 995 #define RDL3_RDL33 0x08 996 #define RDL3_RDL32 0x04 997 #define RDL3_RDL31 0x02 998 #define RDL3_RDL30 0x01 999 1000 1001 /* SIS (Signaling Status Register) 1002 1003 -------------------- E1 & T1 -------------------------- */ 1004 1005 #define SIS_XDOV 0x80 1006 #define SIS_XFW 0x40 1007 #define SIS_XREP 0x20 1008 #define SIS_RLI 0x08 1009 #define SIS_CEC 0x04 1010 #define SIS_BOM 0x01 1011 1012 1013 /* RSIS (Receive Signaling Status Register) 1014 1015 -------------------- E1 & T1 --------------------------- */ 1016 1017 #define RSIS_VFR 0x80 1018 #define RSIS_RDO 0x40 1019 #define RSIS_CRC16 0x20 1020 #define RSIS_RAB 0x10 1021 #define RSIS_HA1 0x08 1022 #define RSIS_HA0 0x04 1023 #define RSIS_HFR 0x02 1024 #define RSIS_LA 0x01 1025 1026 1027 /* RBCL/H (Receive Byte Count Low/High) 1028 1029 ------------------- E1 & T1 ----------------------- */ 1030 1031 #define RBCL_RBC7 0x80 1032 #define RBCL_RBC6 0x40 1033 #define RBCL_RBC5 0x20 1034 #define RBCL_RBC4 0x10 1035 #define RBCL_RBC3 0x08 1036 #define RBCL_RBC2 0x04 1037 #define RBCL_RBC1 0x02 1038 #define RBCL_RBC0 0x01 1039 1040 #define RBCH_OV 0x10 1041 #define RBCH_RBC11 0x08 1042 #define RBCH_RBC10 0x04 1043 #define RBCH_RBC9 0x02 1044 #define RBCH_RBC8 0x01 1045 1046 1047 /* ISR1-3 (Interrupt Status Register 1-3) 1048 1049 ------------------ E1 & T1 ------------------------------ */ 1050 1051 #define FISR0_RME 0x80 1052 #define FISR0_RFS 0x40 1053 #define FISR0_T8MS 0x20 1054 #define FISR0_ISF 0x20 1055 #define FISR0_RMB 0x10 1056 #define FISR0_CASC 0x08 1057 #define FISR0_RSC 0x08 1058 #define FISR0_CRC6 0x04 1059 #define FISR0_CRC4 0x04 1060 #define FISR0_PDEN 0x02 1061 #define FISR0_RPF 0x01 1062 1063 #define FISR1_CASE 0x80 1064 #define FISR1_LLBSC 0x80 1065 #define FISR1_RDO 0x40 1066 #define FISR1_ALLS 0x20 1067 #define FISR1_XDU 0x10 1068 #define FISR1_XMB 0x08 1069 #define FISR1_XLSC 0x02 1070 #define FISR1_XPR 0x01 1071 1072 #define FISR2_FAR 0x80 1073 #define FISR2_LFA 0x40 1074 #define FISR2_MFAR 0x20 1075 #define FISR2_T400MS 0x10 1076 #define FISR2_LMFA 0x10 1077 #define FISR2_AIS 0x08 1078 #define FISR2_LOS 0x04 1079 #define FISR2_RAR 0x02 1080 #define FISR2_RA 0x01 1081 1082 #define FISR3_ES 0x80 1083 #define FISR3_SEC 0x40 1084 #define FISR3_LMFA16 0x20 1085 #define FISR3_AIS16 0x10 1086 #define FISR3_RA16 0x08 1087 #define FISR3_API 0x04 1088 #define FISR3_XSLP 0x20 1089 #define FISR3_XSLN 0x10 1090 #define FISR3_LLBSC 0x08 1091 #define FISR3_XRS 0x04 1092 #define FISR3_SLN 0x02 1093 #define FISR3_SLP 0x01 1094 1095 1096 /* GIS (Global Interrupt Status Register) 1097 1098 --------------------- E1 & T1 --------------------- */ 1099 1100 #define GIS_ISR3 0x08 1101 #define GIS_ISR2 0x04 1102 #define GIS_ISR1 0x02 1103 #define GIS_ISR0 0x01 1104 1105 1106 /* VSTR (Version Status Register) 1107 1108 --------------------- E1 & T1 --------------------- */ 1109 1110 #define VSTR_VN3 0x08 1111 #define VSTR_VN2 0x04 1112 #define VSTR_VN1 0x02 1113 #define VSTR_VN0 0x01 1114 1115 1116 /*>>>>>>>>>>>>>>>>>>>>> Local Control Structures <<<<<<<<<<<<<<<<<<<<<<<<< */ 1117 1118 /* Write-only Registers (E1/T1 control mode write registers) */ 1119 #define XFIFOH 0x00 /* Tx FIFO High Byte */ 1120 #define XFIFOL 0x01 /* Tx FIFO Low Byte */ 1121 #define CMDR 0x02 /* Command Reg */ 1122 #define DEC 0x60 /* Disable Error Counter */ 1123 #define TEST2 0x62 /* Manuf. Test Reg 2 */ 1124 #define XS(nbr) (0x70 + (nbr)) /* Tx CAS Reg (0 to 15) */ 1125 1126 /* Read-write Registers (E1/T1 status mode read registers) */ 1127 #define MODE 0x03 /* Mode Reg */ 1128 #define RAH1 0x04 /* Receive Address High 1 */ 1129 #define RAH2 0x05 /* Receive Address High 2 */ 1130 #define RAL1 0x06 /* Receive Address Low 1 */ 1131 #define RAL2 0x07 /* Receive Address Low 2 */ 1132 #define IPC 0x08 /* Interrupt Port Configuration */ 1133 #define CCR1 0x09 /* Common Configuration Reg 1 */ 1134 #define CCR3 0x0A /* Common Configuration Reg 3 */ 1135 #define PRE 0x0B /* Preamble Reg */ 1136 #define RTR1 0x0C /* Receive Timeslot Reg 1 */ 1137 #define RTR2 0x0D /* Receive Timeslot Reg 2 */ 1138 #define RTR3 0x0E /* Receive Timeslot Reg 3 */ 1139 #define RTR4 0x0F /* Receive Timeslot Reg 4 */ 1140 #define TTR1 0x10 /* Transmit Timeslot Reg 1 */ 1141 #define TTR2 0x11 /* Transmit Timeslot Reg 2 */ 1142 #define TTR3 0x12 /* Transmit Timeslot Reg 3 */ 1143 #define TTR4 0x13 /* Transmit Timeslot Reg 4 */ 1144 #define IMR0 0x14 /* Interrupt Mask Reg 0 */ 1145 #define IMR1 0x15 /* Interrupt Mask Reg 1 */ 1146 #define IMR2 0x16 /* Interrupt Mask Reg 2 */ 1147 #define IMR3 0x17 /* Interrupt Mask Reg 3 */ 1148 #define IMR4 0x18 /* Interrupt Mask Reg 4 */ 1149 #define IMR5 0x19 /* Interrupt Mask Reg 5 */ 1150 #define FMR0 0x1A /* Framer Mode Reigster 0 */ 1151 #define FMR1 0x1B /* Framer Mode Reigster 1 */ 1152 #define FMR2 0x1C /* Framer Mode Reigster 2 */ 1153 #define LOOP 0x1D /* Channel Loop Back */ 1154 #define XSW 0x1E /* Transmit Service Word */ 1155 #define FMR4 0x1E /* Framer Mode Reg 4 */ 1156 #define XSP 0x1F /* Transmit Spare Bits */ 1157 #define FMR5 0x1F /* Framer Mode Reg 5 */ 1158 #define XC0 0x20 /* Transmit Control 0 */ 1159 #define XC1 0x21 /* Transmit Control 1 */ 1160 #define RC0 0x22 /* Receive Control 0 */ 1161 #define RC1 0x23 /* Receive Control 1 */ 1162 #define XPM0 0x24 /* Transmit Pulse Mask 0 */ 1163 #define XPM1 0x25 /* Transmit Pulse Mask 1 */ 1164 #define XPM2 0x26 /* Transmit Pulse Mask 2 */ 1165 #define TSWM 0x27 /* Transparent Service Word Mask */ 1166 #define TEST1 0x28 /* Manuf. Test Reg 1 */ 1167 #define IDLE 0x29 /* Idle Channel Code */ 1168 #define XSA4 0x2A /* Transmit SA4 Bit Reg */ 1169 #define XDL1 0x2A /* Transmit DL-Bit Reg 2 */ 1170 #define XSA5 0x2B /* Transmit SA4 Bit Reg */ 1171 #define XDL2 0x2B /* Transmit DL-Bit Reg 2 */ 1172 #define XSA6 0x2C /* Transmit SA4 Bit Reg */ 1173 #define XDL3 0x2C /* Transmit DL-Bit Reg 2 */ 1174 #define XSA7 0x2D /* Transmit SA4 Bit Reg */ 1175 #define CCB1 0x2D /* Clear Channel Reg 1 */ 1176 #define XSA8 0x2E /* Transmit SA4 Bit Reg */ 1177 #define CCB2 0x2E /* Clear Channel Reg 2 */ 1178 #define FMR3 0x2F /* Framer Mode Reg. 3 */ 1179 #define CCB3 0x2F /* Clear Channel Reg 3 */ 1180 #define ICB1 0x30 /* Idle Channel Reg 1 */ 1181 #define ICB2 0x31 /* Idle Channel Reg 2 */ 1182 #define ICB3 0x32 /* Idle Channel Reg 3 */ 1183 #define ICB4 0x33 /* Idle Channel Reg 4 */ 1184 #define LIM0 0x34 /* Line Interface Mode 0 */ 1185 #define LIM1 0x35 /* Line Interface Mode 1 */ 1186 #define PCDR 0x36 /* Pulse Count Detection */ 1187 #define PCRR 0x37 /* Pulse Count Recovery */ 1188 #define LIM2 0x38 /* Line Interface Mode Reg 2 */ 1189 #define LCR1 0x39 /* Loop Code Reg 1 */ 1190 #define LCR2 0x3A /* Loop Code Reg 2 */ 1191 #define LCR3 0x3B /* Loop Code Reg 3 */ 1192 #define SIC1 0x3C /* System Interface Control 1 */ 1193 1194 /* Read-only Registers (E1/T1 control mode read registers) */ 1195 #define RFIFOH 0x00 /* Receive FIFO */ 1196 #define RFIFOL 0x01 /* Receive FIFO */ 1197 #define FRS0 0x4C /* Framer Receive Status 0 */ 1198 #define FRS1 0x4D /* Framer Receive Status 1 */ 1199 #define RSW 0x4E /* Receive Service Word */ 1200 #define FRS2 0x4E /* Framer Receive Status 2 */ 1201 #define RSP 0x4F /* Receive Spare Bits */ 1202 #define FRS3 0x4F /* Framer Receive Status 3 */ 1203 #define FECL 0x50 /* Framing Error Counter */ 1204 #define FECH 0x51 /* Framing Error Counter */ 1205 #define CVCL 0x52 /* Code Violation Counter */ 1206 #define CVCH 0x53 /* Code Violation Counter */ 1207 #define CECL 0x54 /* CRC Error Counter 1 */ 1208 #define CECH 0x55 /* CRC Error Counter 1 */ 1209 #define EBCL 0x56 /* E-Bit Error Counter */ 1210 #define EBCH 0x57 /* E-Bit Error Counter */ 1211 #define BECL 0x58 /* Bit Error Counter Low */ 1212 #define BECH 0x59 /* Bit Error Counter Low */ 1213 #define CEC3 0x5A /* CRC Error Counter 3 (16-bit) */ 1214 #define RSA4 0x5C /* Receive SA4 Bit Reg */ 1215 #define RDL1 0x5C /* Receive DL-Bit Reg 1 */ 1216 #define RSA5 0x5D /* Receive SA5 Bit Reg */ 1217 #define RDL2 0x5D /* Receive DL-Bit Reg 2 */ 1218 #define RSA6 0x5E /* Receive SA6 Bit Reg */ 1219 #define RDL3 0x5E /* Receive DL-Bit Reg 3 */ 1220 #define RSA7 0x5F /* Receive SA7 Bit Reg */ 1221 #define RSA8 0x60 /* Receive SA8 Bit Reg */ 1222 #define RSA6S 0x61 /* Receive SA6 Bit Status Reg */ 1223 #define TSR0 0x62 /* Manuf. Test Reg 0 */ 1224 #define TSR1 0x63 /* Manuf. Test Reg 1 */ 1225 #define SIS 0x64 /* Signaling Status Reg */ 1226 #define RSIS 0x65 /* Receive Signaling Status Reg */ 1227 #define RBCL 0x66 /* Receive Byte Control */ 1228 #define RBCH 0x67 /* Receive Byte Control */ 1229 #define FISR0 0x68 /* Interrupt Status Reg 0 */ 1230 #define FISR1 0x69 /* Interrupt Status Reg 1 */ 1231 #define FISR2 0x6A /* Interrupt Status Reg 2 */ 1232 #define FISR3 0x6B /* Interrupt Status Reg 3 */ 1233 #define GIS 0x6E /* Global Interrupt Status */ 1234 #define VSTR 0x6F /* Version Status */ 1235 #define RS(nbr) (0x70 + (nbr)) /* Rx CAS Reg (0 to 15) */ 1236 1237 #endif /* _FALC_LH_H */ 1238 1239