1 /*******************************************************************************
2   Header File to describe the DMA descriptors.
3   Enhanced descriptors have been in case of DWMAC1000 Cores.
4 
5   This program is free software; you can redistribute it and/or modify it
6   under the terms and conditions of the GNU General Public License,
7   version 2, as published by the Free Software Foundation.
8 
9   This program is distributed in the hope it will be useful, but WITHOUT
10   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12   more details.
13 
14   You should have received a copy of the GNU General Public License along with
15   this program; if not, write to the Free Software Foundation, Inc.,
16   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 
18   The full GNU General Public License is included in this distribution in
19   the file called "COPYING".
20 
21   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
22 *******************************************************************************/
23 struct dma_desc {
24 	/* Receive descriptor */
25 	union {
26 		struct {
27 			/* RDES0 */
28 			u32 reserved1:1;
29 			u32 crc_error:1;
30 			u32 dribbling:1;
31 			u32 mii_error:1;
32 			u32 receive_watchdog:1;
33 			u32 frame_type:1;
34 			u32 collision:1;
35 			u32 frame_too_long:1;
36 			u32 last_descriptor:1;
37 			u32 first_descriptor:1;
38 			u32 multicast_frame:1;
39 			u32 run_frame:1;
40 			u32 length_error:1;
41 			u32 partial_frame_error:1;
42 			u32 descriptor_error:1;
43 			u32 error_summary:1;
44 			u32 frame_length:14;
45 			u32 filtering_fail:1;
46 			u32 own:1;
47 			/* RDES1 */
48 			u32 buffer1_size:11;
49 			u32 buffer2_size:11;
50 			u32 reserved2:2;
51 			u32 second_address_chained:1;
52 			u32 end_ring:1;
53 			u32 reserved3:5;
54 			u32 disable_ic:1;
55 		} rx;
56 		struct {
57 			/* RDES0 */
58 			u32 payload_csum_error:1;
59 			u32 crc_error:1;
60 			u32 dribbling:1;
61 			u32 error_gmii:1;
62 			u32 receive_watchdog:1;
63 			u32 frame_type:1;
64 			u32 late_collision:1;
65 			u32 ipc_csum_error:1;
66 			u32 last_descriptor:1;
67 			u32 first_descriptor:1;
68 			u32 vlan_tag:1;
69 			u32 overflow_error:1;
70 			u32 length_error:1;
71 			u32 sa_filter_fail:1;
72 			u32 descriptor_error:1;
73 			u32 error_summary:1;
74 			u32 frame_length:14;
75 			u32 da_filter_fail:1;
76 			u32 own:1;
77 			/* RDES1 */
78 			u32 buffer1_size:13;
79 			u32 reserved1:1;
80 			u32 second_address_chained:1;
81 			u32 end_ring:1;
82 			u32 buffer2_size:13;
83 			u32 reserved2:2;
84 			u32 disable_ic:1;
85 		} erx;		/* -- enhanced -- */
86 
87 		/* Transmit descriptor */
88 		struct {
89 			/* TDES0 */
90 			u32 deferred:1;
91 			u32 underflow_error:1;
92 			u32 excessive_deferral:1;
93 			u32 collision_count:4;
94 			u32 heartbeat_fail:1;
95 			u32 excessive_collisions:1;
96 			u32 late_collision:1;
97 			u32 no_carrier:1;
98 			u32 loss_carrier:1;
99 			u32 reserved1:3;
100 			u32 error_summary:1;
101 			u32 reserved2:15;
102 			u32 own:1;
103 			/* TDES1 */
104 			u32 buffer1_size:11;
105 			u32 buffer2_size:11;
106 			u32 reserved3:1;
107 			u32 disable_padding:1;
108 			u32 second_address_chained:1;
109 			u32 end_ring:1;
110 			u32 crc_disable:1;
111 			u32 reserved4:2;
112 			u32 first_segment:1;
113 			u32 last_segment:1;
114 			u32 interrupt:1;
115 		} tx;
116 		struct {
117 			/* TDES0 */
118 			u32 deferred:1;
119 			u32 underflow_error:1;
120 			u32 excessive_deferral:1;
121 			u32 collision_count:4;
122 			u32 vlan_frame:1;
123 			u32 excessive_collisions:1;
124 			u32 late_collision:1;
125 			u32 no_carrier:1;
126 			u32 loss_carrier:1;
127 			u32 payload_error:1;
128 			u32 frame_flushed:1;
129 			u32 jabber_timeout:1;
130 			u32 error_summary:1;
131 			u32 ip_header_error:1;
132 			u32 time_stamp_status:1;
133 			u32 reserved1:2;
134 			u32 second_address_chained:1;
135 			u32 end_ring:1;
136 			u32 checksum_insertion:2;
137 			u32 reserved2:1;
138 			u32 time_stamp_enable:1;
139 			u32 disable_padding:1;
140 			u32 crc_disable:1;
141 			u32 first_segment:1;
142 			u32 last_segment:1;
143 			u32 interrupt:1;
144 			u32 own:1;
145 			/* TDES1 */
146 			u32 buffer1_size:13;
147 			u32 reserved3:3;
148 			u32 buffer2_size:13;
149 			u32 reserved4:3;
150 		} etx;		/* -- enhanced -- */
151 	} des01;
152 	unsigned int des2;
153 	unsigned int des3;
154 };
155 
156 /* Transmit checksum insertion control */
157 enum tdes_csum_insertion {
158 	cic_disabled = 0,	/* Checksum Insertion Control */
159 	cic_only_ip = 1,	/* Only IP header */
160 	cic_no_pseudoheader = 2,	/* IP header but pseudoheader
161 					 * is not calculated */
162 	cic_full = 3,		/* IP header and pseudoheader */
163 };
164