1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28
29 /* Linux PRO/1000 Ethernet Driver main header file */
30
31 #ifndef _IGB_H_
32 #define _IGB_H_
33
34 #include "e1000_mac.h"
35 #include "e1000_82575.h"
36
37 #include <linux/clocksource.h>
38 #include <linux/timecompare.h>
39 #include <linux/net_tstamp.h>
40
41 struct igb_adapter;
42
43 /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
44 #define IGB_START_ITR 648
45
46 /* TX/RX descriptor defines */
47 #define IGB_DEFAULT_TXD 256
48 #define IGB_MIN_TXD 80
49 #define IGB_MAX_TXD 4096
50
51 #define IGB_DEFAULT_RXD 256
52 #define IGB_MIN_RXD 80
53 #define IGB_MAX_RXD 4096
54
55 #define IGB_DEFAULT_ITR 3 /* dynamic */
56 #define IGB_MAX_ITR_USECS 10000
57 #define IGB_MIN_ITR_USECS 10
58 #define NON_Q_VECTORS 1
59 #define MAX_Q_VECTORS 8
60
61 /* Transmit and receive queues */
62 #define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \
63 (hw->mac.type > e1000_82575 ? 8 : 4))
64 #define IGB_ABS_MAX_TX_QUEUES 8
65 #define IGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES
66
67 #define IGB_MAX_VF_MC_ENTRIES 30
68 #define IGB_MAX_VF_FUNCTIONS 8
69 #define IGB_MAX_VFTA_ENTRIES 128
70
71 struct vf_data_storage {
72 unsigned char vf_mac_addresses[ETH_ALEN];
73 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
74 u16 num_vf_mc_hashes;
75 u16 vlans_enabled;
76 u32 flags;
77 unsigned long last_nack;
78 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
79 u16 pf_qos;
80 u16 tx_rate;
81 };
82
83 #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
84 #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
85 #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
86 #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
87
88 /* RX descriptor control thresholds.
89 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
90 * descriptors available in its onboard memory.
91 * Setting this to 0 disables RX descriptor prefetch.
92 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
93 * available in host memory.
94 * If PTHRESH is 0, this should also be 0.
95 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
96 * descriptors until either it has this many to write back, or the
97 * ITR timer expires.
98 */
99 #define IGB_RX_PTHRESH 8
100 #define IGB_RX_HTHRESH 8
101 #define IGB_RX_WTHRESH 1
102 #define IGB_TX_PTHRESH 8
103 #define IGB_TX_HTHRESH 1
104 #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
105 adapter->msix_entries) ? 1 : 16)
106
107 /* this is the size past which hardware will drop packets when setting LPE=0 */
108 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
109
110 /* Supported Rx Buffer Sizes */
111 #define IGB_RXBUFFER_64 64 /* Used for packet split */
112 #define IGB_RXBUFFER_128 128 /* Used for packet split */
113 #define IGB_RXBUFFER_1024 1024
114 #define IGB_RXBUFFER_2048 2048
115 #define IGB_RXBUFFER_16384 16384
116
117 #define MAX_STD_JUMBO_FRAME_SIZE 9234
118
119 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
120 #define IGB_TX_QUEUE_WAKE 16
121 /* How many Rx Buffers do we bundle into one write to the hardware ? */
122 #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
123
124 #define AUTO_ALL_MODES 0
125 #define IGB_EEPROM_APME 0x0400
126
127 #ifndef IGB_MASTER_SLAVE
128 /* Switch to override PHY master/slave setting */
129 #define IGB_MASTER_SLAVE e1000_ms_hw_default
130 #endif
131
132 #define IGB_MNG_VLAN_NONE -1
133
134 /* wrapper around a pointer to a socket buffer,
135 * so a DMA handle can be stored along with the buffer */
136 struct igb_buffer {
137 struct sk_buff *skb;
138 dma_addr_t dma;
139 union {
140 /* TX */
141 struct {
142 unsigned long time_stamp;
143 u16 length;
144 u16 next_to_watch;
145 unsigned int bytecount;
146 u16 gso_segs;
147 u8 tx_flags;
148 u8 mapped_as_page;
149 };
150 /* RX */
151 struct {
152 struct page *page;
153 dma_addr_t page_dma;
154 u16 page_offset;
155 };
156 };
157 };
158
159 struct igb_tx_queue_stats {
160 u64 packets;
161 u64 bytes;
162 u64 restart_queue;
163 u64 restart_queue2;
164 };
165
166 struct igb_rx_queue_stats {
167 u64 packets;
168 u64 bytes;
169 u64 drops;
170 u64 csum_err;
171 u64 alloc_failed;
172 };
173
174 struct igb_q_vector {
175 struct igb_adapter *adapter; /* backlink */
176 struct igb_ring *rx_ring;
177 struct igb_ring *tx_ring;
178 struct napi_struct napi;
179
180 u32 eims_value;
181 u16 cpu;
182
183 u16 itr_val;
184 u8 set_itr;
185 void __iomem *itr_register;
186
187 char name[IFNAMSIZ + 9];
188 };
189
190 struct igb_ring {
191 struct igb_q_vector *q_vector; /* backlink to q_vector */
192 struct net_device *netdev; /* back pointer to net_device */
193 struct device *dev; /* device pointer for dma mapping */
194 dma_addr_t dma; /* phys address of the ring */
195 void *desc; /* descriptor ring memory */
196 unsigned int size; /* length of desc. ring in bytes */
197 u16 count; /* number of desc. in the ring */
198 u16 next_to_use;
199 u16 next_to_clean;
200 u8 queue_index;
201 u8 reg_idx;
202 void __iomem *head;
203 void __iomem *tail;
204 struct igb_buffer *buffer_info; /* array of buffer info structs */
205
206 unsigned int total_bytes;
207 unsigned int total_packets;
208
209 u32 flags;
210
211 union {
212 /* TX */
213 struct {
214 struct igb_tx_queue_stats tx_stats;
215 struct u64_stats_sync tx_syncp;
216 struct u64_stats_sync tx_syncp2;
217 bool detect_tx_hung;
218 };
219 /* RX */
220 struct {
221 struct igb_rx_queue_stats rx_stats;
222 struct u64_stats_sync rx_syncp;
223 u32 rx_buffer_len;
224 };
225 };
226 };
227
228 #define IGB_RING_FLAG_RX_CSUM 0x00000001 /* RX CSUM enabled */
229 #define IGB_RING_FLAG_RX_SCTP_CSUM 0x00000002 /* SCTP CSUM offload enabled */
230
231 #define IGB_RING_FLAG_TX_CTX_IDX 0x00000001 /* HW requires context index */
232
233 #define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS)
234
235 #define E1000_RX_DESC_ADV(R, i) \
236 (&(((union e1000_adv_rx_desc *)((R).desc))[i]))
237 #define E1000_TX_DESC_ADV(R, i) \
238 (&(((union e1000_adv_tx_desc *)((R).desc))[i]))
239 #define E1000_TX_CTXTDESC_ADV(R, i) \
240 (&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
241
242 /* igb_desc_unused - calculate if we have unused descriptors */
igb_desc_unused(struct igb_ring * ring)243 static inline int igb_desc_unused(struct igb_ring *ring)
244 {
245 if (ring->next_to_clean > ring->next_to_use)
246 return ring->next_to_clean - ring->next_to_use - 1;
247
248 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
249 }
250
251 /* board specific private data structure */
252 struct igb_adapter {
253 struct timer_list watchdog_timer;
254 struct timer_list phy_info_timer;
255 struct vlan_group *vlgrp;
256 u16 mng_vlan_id;
257 u32 bd_number;
258 u32 wol;
259 u32 en_mng_pt;
260 u16 link_speed;
261 u16 link_duplex;
262
263 /* Interrupt Throttle Rate */
264 u32 rx_itr_setting;
265 u32 tx_itr_setting;
266 u16 tx_itr;
267 u16 rx_itr;
268
269 struct work_struct reset_task;
270 struct work_struct watchdog_task;
271 bool fc_autoneg;
272 u8 tx_timeout_factor;
273 struct timer_list blink_timer;
274 unsigned long led_status;
275
276 /* TX */
277 struct igb_ring *tx_ring[16];
278 u32 tx_timeout_count;
279
280 /* RX */
281 struct igb_ring *rx_ring[16];
282 int num_tx_queues;
283 int num_rx_queues;
284
285 u32 max_frame_size;
286 u32 min_frame_size;
287
288 /* OS defined structs */
289 struct net_device *netdev;
290 struct pci_dev *pdev;
291 struct cyclecounter cycles;
292 struct timecounter clock;
293 struct timecompare compare;
294 struct hwtstamp_config hwtstamp_config;
295
296 spinlock_t stats64_lock;
297 struct rtnl_link_stats64 stats64;
298
299 /* structs defined in e1000_hw.h */
300 struct e1000_hw hw;
301 struct e1000_hw_stats stats;
302 struct e1000_phy_info phy_info;
303 struct e1000_phy_stats phy_stats;
304
305 u32 test_icr;
306 struct igb_ring test_tx_ring;
307 struct igb_ring test_rx_ring;
308
309 int msg_enable;
310
311 unsigned int num_q_vectors;
312 struct igb_q_vector *q_vector[MAX_Q_VECTORS];
313 struct msix_entry *msix_entries;
314 u32 eims_enable_mask;
315 u32 eims_other;
316
317 /* to not mess up cache alignment, always add to the bottom */
318 unsigned long state;
319 unsigned int flags;
320 u32 eeprom_wol;
321
322 struct igb_ring *multi_tx_table[IGB_ABS_MAX_TX_QUEUES];
323 u16 tx_ring_count;
324 u16 rx_ring_count;
325 unsigned int vfs_allocated_count;
326 struct vf_data_storage *vf_data;
327 int vf_rate_link_speed;
328 u32 rss_queues;
329 u32 wvbr;
330 };
331
332 #define IGB_FLAG_HAS_MSI (1 << 0)
333 #define IGB_FLAG_DCA_ENABLED (1 << 1)
334 #define IGB_FLAG_QUAD_PORT_A (1 << 2)
335 #define IGB_FLAG_QUEUE_PAIRS (1 << 3)
336 #define IGB_FLAG_DMAC (1 << 4)
337
338 /* DMA Coalescing defines */
339 #define IGB_MIN_TXPBSIZE 20408
340 #define IGB_TX_BUF_4096 4096
341 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
342
343 #define IGB_82576_TSYNC_SHIFT 19
344 #define IGB_82580_TSYNC_SHIFT 24
345 #define IGB_TS_HDR_LEN 16
346 enum e1000_state_t {
347 __IGB_TESTING,
348 __IGB_RESETTING,
349 __IGB_DOWN
350 };
351
352 enum igb_boards {
353 board_82575,
354 };
355
356 extern char igb_driver_name[];
357 extern char igb_driver_version[];
358
359 extern int igb_up(struct igb_adapter *);
360 extern void igb_down(struct igb_adapter *);
361 extern void igb_reinit_locked(struct igb_adapter *);
362 extern void igb_reset(struct igb_adapter *);
363 extern int igb_set_spd_dplx(struct igb_adapter *, u16);
364 extern int igb_setup_tx_resources(struct igb_ring *);
365 extern int igb_setup_rx_resources(struct igb_ring *);
366 extern void igb_free_tx_resources(struct igb_ring *);
367 extern void igb_free_rx_resources(struct igb_ring *);
368 extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
369 extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
370 extern void igb_setup_tctl(struct igb_adapter *);
371 extern void igb_setup_rctl(struct igb_adapter *);
372 extern netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *, struct igb_ring *);
373 extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
374 struct igb_buffer *);
375 extern void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
376 extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
377 extern bool igb_has_link(struct igb_adapter *adapter);
378 extern void igb_set_ethtool_ops(struct net_device *);
379 extern void igb_power_up_link(struct igb_adapter *);
380
igb_reset_phy(struct e1000_hw * hw)381 static inline s32 igb_reset_phy(struct e1000_hw *hw)
382 {
383 if (hw->phy.ops.reset)
384 return hw->phy.ops.reset(hw);
385
386 return 0;
387 }
388
igb_read_phy_reg(struct e1000_hw * hw,u32 offset,u16 * data)389 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
390 {
391 if (hw->phy.ops.read_reg)
392 return hw->phy.ops.read_reg(hw, offset, data);
393
394 return 0;
395 }
396
igb_write_phy_reg(struct e1000_hw * hw,u32 offset,u16 data)397 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
398 {
399 if (hw->phy.ops.write_reg)
400 return hw->phy.ops.write_reg(hw, offset, data);
401
402 return 0;
403 }
404
igb_get_phy_info(struct e1000_hw * hw)405 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
406 {
407 if (hw->phy.ops.get_phy_info)
408 return hw->phy.ops.get_phy_info(hw);
409
410 return 0;
411 }
412
413 #endif /* _IGB_H_ */
414