1 /*
2 * Copyright (c) 2010 Samsung Electronics
3 *
4 * Sylwester Nawrocki, <s.nawrocki@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #ifndef FIMC_CORE_H_
12 #define FIMC_CORE_H_
13
14 /*#define DEBUG*/
15
16 #include <linux/sched.h>
17 #include <linux/spinlock.h>
18 #include <linux/types.h>
19 #include <linux/videodev2.h>
20 #include <linux/io.h>
21 #include <media/videobuf2-core.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-mem2mem.h>
24 #include <media/v4l2-mediabus.h>
25 #include <media/s5p_fimc.h>
26
27 #include "regs-fimc.h"
28
29 #define err(fmt, args...) \
30 printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
31
32 #define dbg(fmt, args...) \
33 pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
34
35 /* Time to wait for next frame VSYNC interrupt while stopping operation. */
36 #define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
37 #define MAX_FIMC_CLOCKS 3
38 #define MODULE_NAME "s5p-fimc"
39 #define FIMC_MAX_DEVS 4
40 #define FIMC_MAX_OUT_BUFS 4
41 #define SCALER_MAX_HRATIO 64
42 #define SCALER_MAX_VRATIO 64
43 #define DMA_MIN_SIZE 8
44
45 /* indices to the clocks array */
46 enum {
47 CLK_BUS,
48 CLK_GATE,
49 CLK_CAM,
50 };
51
52 enum fimc_dev_flags {
53 /* for m2m node */
54 ST_IDLE,
55 ST_OUTDMA_RUN,
56 ST_M2M_PEND,
57 /* for capture node */
58 ST_CAPT_PEND,
59 ST_CAPT_RUN,
60 ST_CAPT_STREAM,
61 ST_CAPT_SHUT,
62 };
63
64 #define fimc_m2m_active(dev) test_bit(ST_OUTDMA_RUN, &(dev)->state)
65 #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
66
67 #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
68 #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
69
70 enum fimc_datapath {
71 FIMC_CAMERA,
72 FIMC_DMA,
73 FIMC_LCDFIFO,
74 FIMC_WRITEBACK
75 };
76
77 enum fimc_color_fmt {
78 S5P_FIMC_RGB565 = 0x10,
79 S5P_FIMC_RGB666,
80 S5P_FIMC_RGB888,
81 S5P_FIMC_RGB30_LOCAL,
82 S5P_FIMC_YCBCR420 = 0x20,
83 S5P_FIMC_YCBYCR422,
84 S5P_FIMC_YCRYCB422,
85 S5P_FIMC_CBYCRY422,
86 S5P_FIMC_CRYCBY422,
87 S5P_FIMC_YCBCR444_LOCAL,
88 };
89
90 #define fimc_fmt_is_rgb(x) ((x) & 0x10)
91
92 /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
93 #define S5P_FIMC_LSB_CRCB S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
94
95 /* The embedded image effect selection */
96 #define S5P_FIMC_EFFECT_ORIGINAL S5P_CIIMGEFF_FIN_BYPASS
97 #define S5P_FIMC_EFFECT_ARBITRARY S5P_CIIMGEFF_FIN_ARBITRARY
98 #define S5P_FIMC_EFFECT_NEGATIVE S5P_CIIMGEFF_FIN_NEGATIVE
99 #define S5P_FIMC_EFFECT_ARTFREEZE S5P_CIIMGEFF_FIN_ARTFREEZE
100 #define S5P_FIMC_EFFECT_EMBOSSING S5P_CIIMGEFF_FIN_EMBOSSING
101 #define S5P_FIMC_EFFECT_SIKHOUETTE S5P_CIIMGEFF_FIN_SILHOUETTE
102
103 /* The hardware context state. */
104 #define FIMC_PARAMS (1 << 0)
105 #define FIMC_SRC_ADDR (1 << 1)
106 #define FIMC_DST_ADDR (1 << 2)
107 #define FIMC_SRC_FMT (1 << 3)
108 #define FIMC_DST_FMT (1 << 4)
109 #define FIMC_CTX_M2M (1 << 5)
110 #define FIMC_CTX_CAP (1 << 6)
111 #define FIMC_CTX_SHUT (1 << 7)
112
113 /* Image conversion flags */
114 #define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
115 #define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
116 #define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
117 #define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
118 #define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
119 #define FIMC_SCAN_MODE_INTERLACED (1 << 2)
120 /*
121 * YCbCr data dynamic range for RGB-YUV color conversion.
122 * Y/Cb/Cr: (0 ~ 255) */
123 #define FIMC_COLOR_RANGE_WIDE (0 << 3)
124 /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
125 #define FIMC_COLOR_RANGE_NARROW (1 << 3)
126
127 #define FLIP_NONE 0
128 #define FLIP_X_AXIS 1
129 #define FLIP_Y_AXIS 2
130 #define FLIP_XY_AXIS (FLIP_X_AXIS | FLIP_Y_AXIS)
131
132 /**
133 * struct fimc_fmt - the driver's internal color format data
134 * @mbus_code: Media Bus pixel code, -1 if not applicable
135 * @name: format description
136 * @fourcc: the fourcc code for this format, 0 if not applicable
137 * @color: the corresponding fimc_color_fmt
138 * @depth: per plane driver's private 'number of bits per pixel'
139 * @memplanes: number of physically non-contiguous data planes
140 * @colplanes: number of physically contiguous data planes
141 */
142 struct fimc_fmt {
143 enum v4l2_mbus_pixelcode mbus_code;
144 char *name;
145 u32 fourcc;
146 u32 color;
147 u16 memplanes;
148 u16 colplanes;
149 u8 depth[VIDEO_MAX_PLANES];
150 u16 flags;
151 #define FMT_FLAGS_CAM (1 << 0)
152 #define FMT_FLAGS_M2M (1 << 1)
153 };
154
155 /**
156 * struct fimc_dma_offset - pixel offset information for DMA
157 * @y_h: y value horizontal offset
158 * @y_v: y value vertical offset
159 * @cb_h: cb value horizontal offset
160 * @cb_v: cb value vertical offset
161 * @cr_h: cr value horizontal offset
162 * @cr_v: cr value vertical offset
163 */
164 struct fimc_dma_offset {
165 int y_h;
166 int y_v;
167 int cb_h;
168 int cb_v;
169 int cr_h;
170 int cr_v;
171 };
172
173 /**
174 * struct fimc_effect - the configuration data for the "Arbitrary" image effect
175 * @type: effect type
176 * @pat_cb: cr value when type is "arbitrary"
177 * @pat_cr: cr value when type is "arbitrary"
178 */
179 struct fimc_effect {
180 u32 type;
181 u8 pat_cb;
182 u8 pat_cr;
183 };
184
185 /**
186 * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
187 *
188 * @scaleup_h: flag indicating scaling up horizontally
189 * @scaleup_v: flag indicating scaling up vertically
190 * @copy_mode: flag indicating transparent DMA transfer (no scaling
191 * and color format conversion)
192 * @enabled: flag indicating if the scaler is used
193 * @hfactor: horizontal shift factor
194 * @vfactor: vertical shift factor
195 * @pre_hratio: horizontal ratio of the prescaler
196 * @pre_vratio: vertical ratio of the prescaler
197 * @pre_dst_width: the prescaler's destination width
198 * @pre_dst_height: the prescaler's destination height
199 * @main_hratio: the main scaler's horizontal ratio
200 * @main_vratio: the main scaler's vertical ratio
201 * @real_width: source pixel (width - offset)
202 * @real_height: source pixel (height - offset)
203 */
204 struct fimc_scaler {
205 unsigned int scaleup_h:1;
206 unsigned int scaleup_v:1;
207 unsigned int copy_mode:1;
208 unsigned int enabled:1;
209 u32 hfactor;
210 u32 vfactor;
211 u32 pre_hratio;
212 u32 pre_vratio;
213 u32 pre_dst_width;
214 u32 pre_dst_height;
215 u32 main_hratio;
216 u32 main_vratio;
217 u32 real_width;
218 u32 real_height;
219 };
220
221 /**
222 * struct fimc_addr - the FIMC physical address set for DMA
223 *
224 * @y: luminance plane physical address
225 * @cb: Cb plane physical address
226 * @cr: Cr plane physical address
227 */
228 struct fimc_addr {
229 u32 y;
230 u32 cb;
231 u32 cr;
232 };
233
234 /**
235 * struct fimc_vid_buffer - the driver's video buffer
236 * @vb: v4l videobuf buffer
237 * @paddr: precalculated physical address set
238 * @index: buffer index for the output DMA engine
239 */
240 struct fimc_vid_buffer {
241 struct vb2_buffer vb;
242 struct list_head list;
243 struct fimc_addr paddr;
244 int index;
245 };
246
247 /**
248 * struct fimc_frame - source/target frame properties
249 * @f_width: image full width (virtual screen size)
250 * @f_height: image full height (virtual screen size)
251 * @o_width: original image width as set by S_FMT
252 * @o_height: original image height as set by S_FMT
253 * @offs_h: image horizontal pixel offset
254 * @offs_v: image vertical pixel offset
255 * @width: image pixel width
256 * @height: image pixel weight
257 * @paddr: image frame buffer physical addresses
258 * @buf_cnt: number of buffers depending on a color format
259 * @payload: image size in bytes (w x h x bpp)
260 * @color: color format
261 * @dma_offset: DMA offset in bytes
262 */
263 struct fimc_frame {
264 u32 f_width;
265 u32 f_height;
266 u32 o_width;
267 u32 o_height;
268 u32 offs_h;
269 u32 offs_v;
270 u32 width;
271 u32 height;
272 unsigned long payload[VIDEO_MAX_PLANES];
273 struct fimc_addr paddr;
274 struct fimc_dma_offset dma_offset;
275 struct fimc_fmt *fmt;
276 };
277
278 /**
279 * struct fimc_m2m_device - v4l2 memory-to-memory device data
280 * @vfd: the video device node for v4l2 m2m mode
281 * @v4l2_dev: v4l2 device for m2m mode
282 * @m2m_dev: v4l2 memory-to-memory device data
283 * @ctx: hardware context data
284 * @refcnt: the reference counter
285 */
286 struct fimc_m2m_device {
287 struct video_device *vfd;
288 struct v4l2_device v4l2_dev;
289 struct v4l2_m2m_dev *m2m_dev;
290 struct fimc_ctx *ctx;
291 int refcnt;
292 };
293
294 /**
295 * struct fimc_vid_cap - camera capture device information
296 * @ctx: hardware context data
297 * @vfd: video device node for camera capture mode
298 * @v4l2_dev: v4l2_device struct to manage subdevs
299 * @sd: pointer to camera sensor subdevice currently in use
300 * @fmt: Media Bus format configured at selected image sensor
301 * @pending_buf_q: the pending buffer queue head
302 * @active_buf_q: the queue head of buffers scheduled in hardware
303 * @vbq: the capture am video buffer queue
304 * @active_buf_cnt: number of video buffers scheduled in hardware
305 * @buf_index: index for managing the output DMA buffers
306 * @frame_count: the frame counter for statistics
307 * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
308 * @input_index: input (camera sensor) index
309 * @refcnt: driver's private reference counter
310 */
311 struct fimc_vid_cap {
312 struct fimc_ctx *ctx;
313 struct vb2_alloc_ctx *alloc_ctx;
314 struct video_device *vfd;
315 struct v4l2_device v4l2_dev;
316 struct v4l2_subdev *sd;;
317 struct v4l2_mbus_framefmt fmt;
318 struct list_head pending_buf_q;
319 struct list_head active_buf_q;
320 struct vb2_queue vbq;
321 int active_buf_cnt;
322 int buf_index;
323 unsigned int frame_count;
324 unsigned int reqbufs_count;
325 int input_index;
326 int refcnt;
327 };
328
329 /**
330 * struct fimc_pix_limit - image pixel size limits in various IP configurations
331 *
332 * @scaler_en_w: max input pixel width when the scaler is enabled
333 * @scaler_dis_w: max input pixel width when the scaler is disabled
334 * @in_rot_en_h: max input width with the input rotator is on
335 * @in_rot_dis_w: max input width with the input rotator is off
336 * @out_rot_en_w: max output width with the output rotator on
337 * @out_rot_dis_w: max output width with the output rotator off
338 */
339 struct fimc_pix_limit {
340 u16 scaler_en_w;
341 u16 scaler_dis_w;
342 u16 in_rot_en_h;
343 u16 in_rot_dis_w;
344 u16 out_rot_en_w;
345 u16 out_rot_dis_w;
346 };
347
348 /**
349 * struct samsung_fimc_variant - camera interface variant information
350 *
351 * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
352 * @has_inp_rot: set if has input rotator
353 * @has_out_rot: set if has output rotator
354 * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision
355 * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register
356 * are present in this IP revision
357 * @pix_limit: pixel size constraints for the scaler
358 * @min_inp_pixsize: minimum input pixel size
359 * @min_out_pixsize: minimum output pixel size
360 * @hor_offs_align: horizontal pixel offset aligment
361 * @out_buf_count: the number of buffers in output DMA sequence
362 */
363 struct samsung_fimc_variant {
364 unsigned int pix_hoff:1;
365 unsigned int has_inp_rot:1;
366 unsigned int has_out_rot:1;
367 unsigned int has_cistatus2:1;
368 unsigned int has_mainscaler_ext:1;
369 struct fimc_pix_limit *pix_limit;
370 u16 min_inp_pixsize;
371 u16 min_out_pixsize;
372 u16 hor_offs_align;
373 u16 out_buf_count;
374 };
375
376 /**
377 * struct samsung_fimc_driverdata - per device type driver data for init time.
378 *
379 * @variant: the variant information for this driver.
380 * @dev_cnt: number of fimc sub-devices available in SoC
381 * @lclk_frequency: fimc bus clock frequency
382 */
383 struct samsung_fimc_driverdata {
384 struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
385 unsigned long lclk_frequency;
386 int num_entities;
387 };
388
389 struct fimc_ctx;
390
391 /**
392 * struct fimc_dev - abstraction for FIMC entity
393 *
394 * @slock: the spinlock protecting this data structure
395 * @lock: the mutex protecting this data structure
396 * @pdev: pointer to the FIMC platform device
397 * @pdata: pointer to the device platform data
398 * @id: FIMC device index (0..FIMC_MAX_DEVS)
399 * @num_clocks: the number of clocks managed by this device instance
400 * @clock[]: the clocks required for FIMC operation
401 * @regs: the mapped hardware registers
402 * @regs_res: the resource claimed for IO registers
403 * @irq: interrupt number of the FIMC subdevice
404 * @irq_queue:
405 * @m2m: memory-to-memory V4L2 device information
406 * @vid_cap: camera capture device information
407 * @state: flags used to synchronize m2m and capture mode operation
408 */
409 struct fimc_dev {
410 spinlock_t slock;
411 struct mutex lock;
412 struct platform_device *pdev;
413 struct s5p_platform_fimc *pdata;
414 struct samsung_fimc_variant *variant;
415 u16 id;
416 u16 num_clocks;
417 struct clk *clock[MAX_FIMC_CLOCKS];
418 void __iomem *regs;
419 struct resource *regs_res;
420 int irq;
421 wait_queue_head_t irq_queue;
422 struct fimc_m2m_device m2m;
423 struct fimc_vid_cap vid_cap;
424 unsigned long state;
425 struct vb2_alloc_ctx *alloc_ctx;
426 };
427
428 /**
429 * fimc_ctx - the device context data
430 *
431 * @lock: mutex protecting this data structure
432 * @s_frame: source frame properties
433 * @d_frame: destination frame properties
434 * @out_order_1p: output 1-plane YCBCR order
435 * @out_order_2p: output 2-plane YCBCR order
436 * @in_order_1p input 1-plane YCBCR order
437 * @in_order_2p: input 2-plane YCBCR order
438 * @in_path: input mode (DMA or camera)
439 * @out_path: output mode (DMA or FIFO)
440 * @scaler: image scaler properties
441 * @effect: image effect
442 * @rotation: image clockwise rotation in degrees
443 * @flip: image flip mode
444 * @flags: additional flags for image conversion
445 * @state: flags to keep track of user configuration
446 * @fimc_dev: the FIMC device this context applies to
447 * @m2m_ctx: memory-to-memory device context
448 */
449 struct fimc_ctx {
450 spinlock_t slock;
451 struct fimc_frame s_frame;
452 struct fimc_frame d_frame;
453 u32 out_order_1p;
454 u32 out_order_2p;
455 u32 in_order_1p;
456 u32 in_order_2p;
457 enum fimc_datapath in_path;
458 enum fimc_datapath out_path;
459 struct fimc_scaler scaler;
460 struct fimc_effect effect;
461 int rotation;
462 u32 flip;
463 u32 flags;
464 u32 state;
465 struct fimc_dev *fimc_dev;
466 struct v4l2_m2m_ctx *m2m_ctx;
467 };
468
fimc_capture_active(struct fimc_dev * fimc)469 static inline bool fimc_capture_active(struct fimc_dev *fimc)
470 {
471 unsigned long flags;
472 bool ret;
473
474 spin_lock_irqsave(&fimc->slock, flags);
475 ret = !!(fimc->state & (1 << ST_CAPT_RUN) ||
476 fimc->state & (1 << ST_CAPT_PEND));
477 spin_unlock_irqrestore(&fimc->slock, flags);
478 return ret;
479 }
480
fimc_ctx_state_lock_set(u32 state,struct fimc_ctx * ctx)481 static inline void fimc_ctx_state_lock_set(u32 state, struct fimc_ctx *ctx)
482 {
483 unsigned long flags;
484
485 spin_lock_irqsave(&ctx->slock, flags);
486 ctx->state |= state;
487 spin_unlock_irqrestore(&ctx->slock, flags);
488 }
489
fimc_ctx_state_is_set(u32 mask,struct fimc_ctx * ctx)490 static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)
491 {
492 unsigned long flags;
493 bool ret;
494
495 spin_lock_irqsave(&ctx->slock, flags);
496 ret = (ctx->state & mask) == mask;
497 spin_unlock_irqrestore(&ctx->slock, flags);
498 return ret;
499 }
500
tiled_fmt(struct fimc_fmt * fmt)501 static inline int tiled_fmt(struct fimc_fmt *fmt)
502 {
503 return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
504 }
505
fimc_hw_clear_irq(struct fimc_dev * dev)506 static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
507 {
508 u32 cfg = readl(dev->regs + S5P_CIGCTRL);
509 cfg |= S5P_CIGCTRL_IRQ_CLR;
510 writel(cfg, dev->regs + S5P_CIGCTRL);
511 }
512
fimc_hw_enable_scaler(struct fimc_dev * dev,bool on)513 static inline void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
514 {
515 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
516 if (on)
517 cfg |= S5P_CISCCTRL_SCALERSTART;
518 else
519 cfg &= ~S5P_CISCCTRL_SCALERSTART;
520 writel(cfg, dev->regs + S5P_CISCCTRL);
521 }
522
fimc_hw_activate_input_dma(struct fimc_dev * dev,bool on)523 static inline void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
524 {
525 u32 cfg = readl(dev->regs + S5P_MSCTRL);
526 if (on)
527 cfg |= S5P_MSCTRL_ENVID;
528 else
529 cfg &= ~S5P_MSCTRL_ENVID;
530 writel(cfg, dev->regs + S5P_MSCTRL);
531 }
532
fimc_hw_dis_capture(struct fimc_dev * dev)533 static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
534 {
535 u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
536 cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
537 writel(cfg, dev->regs + S5P_CIIMGCPT);
538 }
539
540 /**
541 * fimc_hw_set_dma_seq - configure output DMA buffer sequence
542 * @mask: each bit corresponds to one of 32 output buffer registers set
543 * 1 to include buffer in the sequence, 0 to disable
544 *
545 * This function mask output DMA ring buffers, i.e. it allows to configure
546 * which of the output buffer address registers will be used by the DMA
547 * engine.
548 */
fimc_hw_set_dma_seq(struct fimc_dev * dev,u32 mask)549 static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask)
550 {
551 writel(mask, dev->regs + S5P_CIFCNTSEQ);
552 }
553
ctx_get_frame(struct fimc_ctx * ctx,enum v4l2_buf_type type)554 static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
555 enum v4l2_buf_type type)
556 {
557 struct fimc_frame *frame;
558
559 if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
560 if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx))
561 frame = &ctx->s_frame;
562 else
563 return ERR_PTR(-EINVAL);
564 } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
565 frame = &ctx->d_frame;
566 } else {
567 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
568 "Wrong buffer/video queue type (%d)\n", type);
569 return ERR_PTR(-EINVAL);
570 }
571
572 return frame;
573 }
574
575 /* Return an index to the buffer actually being written. */
fimc_hw_get_frame_index(struct fimc_dev * dev)576 static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
577 {
578 u32 reg;
579
580 if (dev->variant->has_cistatus2) {
581 reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F;
582 return reg > 0 ? --reg : reg;
583 } else {
584 reg = readl(dev->regs + S5P_CISTATUS);
585 return (reg & S5P_CISTATUS_FRAMECNT_MASK) >>
586 S5P_CISTATUS_FRAMECNT_SHIFT;
587 }
588 }
589
590 /* -----------------------------------------------------*/
591 /* fimc-reg.c */
592 void fimc_hw_reset(struct fimc_dev *fimc);
593 void fimc_hw_set_rotation(struct fimc_ctx *ctx);
594 void fimc_hw_set_target_format(struct fimc_ctx *ctx);
595 void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
596 void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable);
597 void fimc_hw_en_irq(struct fimc_dev *fimc, int enable);
598 void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
599 void fimc_hw_set_mainscaler(struct fimc_ctx *ctx);
600 void fimc_hw_en_capture(struct fimc_ctx *ctx);
601 void fimc_hw_set_effect(struct fimc_ctx *ctx);
602 void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
603 void fimc_hw_set_input_path(struct fimc_ctx *ctx);
604 void fimc_hw_set_output_path(struct fimc_ctx *ctx);
605 void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr);
606 void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr,
607 int index);
608 int fimc_hw_set_camera_source(struct fimc_dev *fimc,
609 struct s5p_fimc_isp_info *cam);
610 int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f);
611 int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
612 struct s5p_fimc_isp_info *cam);
613 int fimc_hw_set_camera_type(struct fimc_dev *fimc,
614 struct s5p_fimc_isp_info *cam);
615
616 /* -----------------------------------------------------*/
617 /* fimc-core.c */
618 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
619 struct v4l2_fmtdesc *f);
620 int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv,
621 struct v4l2_format *f);
622 int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
623 struct v4l2_format *f);
624 int fimc_vidioc_queryctrl(struct file *file, void *priv,
625 struct v4l2_queryctrl *qc);
626 int fimc_vidioc_g_ctrl(struct file *file, void *priv,
627 struct v4l2_control *ctrl);
628
629 int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr);
630 int check_ctrl_val(struct fimc_ctx *ctx, struct v4l2_control *ctrl);
631 int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl);
632
633 struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask);
634 struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
635 unsigned int mask);
636
637 int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot);
638 int fimc_set_scaler_info(struct fimc_ctx *ctx);
639 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
640 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
641 struct fimc_frame *frame, struct fimc_addr *paddr);
642
643 /* -----------------------------------------------------*/
644 /* fimc-capture.c */
645 int fimc_register_capture_device(struct fimc_dev *fimc);
646 void fimc_unregister_capture_device(struct fimc_dev *fimc);
647 int fimc_sensor_sd_init(struct fimc_dev *fimc, int index);
648 int fimc_vid_cap_buf_queue(struct fimc_dev *fimc,
649 struct fimc_vid_buffer *fimc_vb);
650
651 /* Locking: the caller holds fimc->slock */
fimc_activate_capture(struct fimc_ctx * ctx)652 static inline void fimc_activate_capture(struct fimc_ctx *ctx)
653 {
654 fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
655 fimc_hw_en_capture(ctx);
656 }
657
fimc_deactivate_capture(struct fimc_dev * fimc)658 static inline void fimc_deactivate_capture(struct fimc_dev *fimc)
659 {
660 fimc_hw_en_lastirq(fimc, true);
661 fimc_hw_dis_capture(fimc);
662 fimc_hw_enable_scaler(fimc, false);
663 fimc_hw_en_lastirq(fimc, false);
664 }
665
666 /*
667 * Add buf to the capture active buffers queue.
668 * Locking: Need to be called with fimc_dev::slock held.
669 */
active_queue_add(struct fimc_vid_cap * vid_cap,struct fimc_vid_buffer * buf)670 static inline void active_queue_add(struct fimc_vid_cap *vid_cap,
671 struct fimc_vid_buffer *buf)
672 {
673 list_add_tail(&buf->list, &vid_cap->active_buf_q);
674 vid_cap->active_buf_cnt++;
675 }
676
677 /*
678 * Pop a video buffer from the capture active buffers queue
679 * Locking: Need to be called with fimc_dev::slock held.
680 */
681 static inline struct fimc_vid_buffer *
active_queue_pop(struct fimc_vid_cap * vid_cap)682 active_queue_pop(struct fimc_vid_cap *vid_cap)
683 {
684 struct fimc_vid_buffer *buf;
685 buf = list_entry(vid_cap->active_buf_q.next,
686 struct fimc_vid_buffer, list);
687 list_del(&buf->list);
688 vid_cap->active_buf_cnt--;
689 return buf;
690 }
691
692 /* Add video buffer to the capture pending buffers queue */
fimc_pending_queue_add(struct fimc_vid_cap * vid_cap,struct fimc_vid_buffer * buf)693 static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
694 struct fimc_vid_buffer *buf)
695 {
696 list_add_tail(&buf->list, &vid_cap->pending_buf_q);
697 }
698
699 /* Add video buffer to the capture pending buffers queue */
700 static inline struct fimc_vid_buffer *
pending_queue_pop(struct fimc_vid_cap * vid_cap)701 pending_queue_pop(struct fimc_vid_cap *vid_cap)
702 {
703 struct fimc_vid_buffer *buf;
704 buf = list_entry(vid_cap->pending_buf_q.next,
705 struct fimc_vid_buffer, list);
706 list_del(&buf->list);
707 return buf;
708 }
709
710 #endif /* FIMC_CORE_H_ */
711