1 /* 2 * Copyright 2006-2007 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 24 /****************************************************************************/ 25 /*Portion I: Definitions shared between VBIOS and Driver */ 26 /****************************************************************************/ 27 28 29 #ifndef _ATOMBIOS_H 30 #define _ATOMBIOS_H 31 32 #define ATOM_VERSION_MAJOR 0x00020000 33 #define ATOM_VERSION_MINOR 0x00000002 34 35 #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) 36 37 /* Endianness should be specified before inclusion, 38 * default to little endian 39 */ 40 #ifndef ATOM_BIG_ENDIAN 41 #error Endian not specified 42 #endif 43 44 #ifdef _H2INC 45 #ifndef ULONG 46 typedef unsigned long ULONG; 47 #endif 48 49 #ifndef UCHAR 50 typedef unsigned char UCHAR; 51 #endif 52 53 #ifndef USHORT 54 typedef unsigned short USHORT; 55 #endif 56 #endif 57 58 #define ATOM_DAC_A 0 59 #define ATOM_DAC_B 1 60 #define ATOM_EXT_DAC 2 61 62 #define ATOM_CRTC1 0 63 #define ATOM_CRTC2 1 64 #define ATOM_CRTC3 2 65 #define ATOM_CRTC4 3 66 #define ATOM_CRTC5 4 67 #define ATOM_CRTC6 5 68 #define ATOM_CRTC_INVALID 0xFF 69 70 #define ATOM_DIGA 0 71 #define ATOM_DIGB 1 72 73 #define ATOM_PPLL1 0 74 #define ATOM_PPLL2 1 75 #define ATOM_DCPLL 2 76 #define ATOM_PPLL0 2 77 #define ATOM_EXT_PLL1 8 78 #define ATOM_EXT_PLL2 9 79 #define ATOM_EXT_CLOCK 10 80 #define ATOM_PPLL_INVALID 0xFF 81 82 #define ENCODER_REFCLK_SRC_P1PLL 0 83 #define ENCODER_REFCLK_SRC_P2PLL 1 84 #define ENCODER_REFCLK_SRC_DCPLL 2 85 #define ENCODER_REFCLK_SRC_EXTCLK 3 86 #define ENCODER_REFCLK_SRC_INVALID 0xFF 87 88 #define ATOM_SCALER1 0 89 #define ATOM_SCALER2 1 90 91 #define ATOM_SCALER_DISABLE 0 92 #define ATOM_SCALER_CENTER 1 93 #define ATOM_SCALER_EXPANSION 2 94 #define ATOM_SCALER_MULTI_EX 3 95 96 #define ATOM_DISABLE 0 97 #define ATOM_ENABLE 1 98 #define ATOM_LCD_BLOFF (ATOM_DISABLE+2) 99 #define ATOM_LCD_BLON (ATOM_ENABLE+2) 100 #define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) 101 #define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) 102 #define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) 103 #define ATOM_ENCODER_INIT (ATOM_DISABLE+7) 104 #define ATOM_GET_STATUS (ATOM_DISABLE+8) 105 106 #define ATOM_BLANKING 1 107 #define ATOM_BLANKING_OFF 0 108 109 #define ATOM_CURSOR1 0 110 #define ATOM_CURSOR2 1 111 112 #define ATOM_ICON1 0 113 #define ATOM_ICON2 1 114 115 #define ATOM_CRT1 0 116 #define ATOM_CRT2 1 117 118 #define ATOM_TV_NTSC 1 119 #define ATOM_TV_NTSCJ 2 120 #define ATOM_TV_PAL 3 121 #define ATOM_TV_PALM 4 122 #define ATOM_TV_PALCN 5 123 #define ATOM_TV_PALN 6 124 #define ATOM_TV_PAL60 7 125 #define ATOM_TV_SECAM 8 126 #define ATOM_TV_CV 16 127 128 #define ATOM_DAC1_PS2 1 129 #define ATOM_DAC1_CV 2 130 #define ATOM_DAC1_NTSC 3 131 #define ATOM_DAC1_PAL 4 132 133 #define ATOM_DAC2_PS2 ATOM_DAC1_PS2 134 #define ATOM_DAC2_CV ATOM_DAC1_CV 135 #define ATOM_DAC2_NTSC ATOM_DAC1_NTSC 136 #define ATOM_DAC2_PAL ATOM_DAC1_PAL 137 138 #define ATOM_PM_ON 0 139 #define ATOM_PM_STANDBY 1 140 #define ATOM_PM_SUSPEND 2 141 #define ATOM_PM_OFF 3 142 143 /* Bit0:{=0:single, =1:dual}, 144 Bit1 {=0:666RGB, =1:888RGB}, 145 Bit2:3:{Grey level} 146 Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/ 147 148 #define ATOM_PANEL_MISC_DUAL 0x00000001 149 #define ATOM_PANEL_MISC_888RGB 0x00000002 150 #define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C 151 #define ATOM_PANEL_MISC_FPDI 0x00000010 152 #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 153 #define ATOM_PANEL_MISC_SPATIAL 0x00000020 154 #define ATOM_PANEL_MISC_TEMPORAL 0x00000040 155 #define ATOM_PANEL_MISC_API_ENABLED 0x00000080 156 157 158 #define MEMTYPE_DDR1 "DDR1" 159 #define MEMTYPE_DDR2 "DDR2" 160 #define MEMTYPE_DDR3 "DDR3" 161 #define MEMTYPE_DDR4 "DDR4" 162 163 #define ASIC_BUS_TYPE_PCI "PCI" 164 #define ASIC_BUS_TYPE_AGP "AGP" 165 #define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" 166 167 /* Maximum size of that FireGL flag string */ 168 169 #define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support 170 #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) 171 172 #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop 173 #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 174 175 #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support 176 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) 177 178 #define HW_ASSISTED_I2C_STATUS_FAILURE 2 179 #define HW_ASSISTED_I2C_STATUS_SUCCESS 1 180 181 #pragma pack(1) /* BIOS data must use byte aligment */ 182 183 /* Define offset to location of ROM header. */ 184 185 #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L 186 #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L 187 188 #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 189 #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ 190 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f 191 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e 192 193 /* Common header for all ROM Data tables. 194 Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. 195 And the pointer actually points to this header. */ 196 197 typedef struct _ATOM_COMMON_TABLE_HEADER 198 { 199 USHORT usStructureSize; 200 UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ 201 UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ 202 /*Image can't be updated, while Driver needs to carry the new table! */ 203 }ATOM_COMMON_TABLE_HEADER; 204 205 /****************************************************************************/ 206 // Structure stores the ROM header. 207 /****************************************************************************/ 208 typedef struct _ATOM_ROM_HEADER 209 { 210 ATOM_COMMON_TABLE_HEADER sHeader; 211 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, 212 atombios should init it as "ATOM", don't change the position */ 213 USHORT usBiosRuntimeSegmentAddress; 214 USHORT usProtectedModeInfoOffset; 215 USHORT usConfigFilenameOffset; 216 USHORT usCRC_BlockOffset; 217 USHORT usBIOS_BootupMessageOffset; 218 USHORT usInt10Offset; 219 USHORT usPciBusDevInitCode; 220 USHORT usIoBaseAddress; 221 USHORT usSubsystemVendorID; 222 USHORT usSubsystemID; 223 USHORT usPCI_InfoOffset; 224 USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ 225 USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ 226 UCHAR ucExtendedFunctionCode; 227 UCHAR ucReserved; 228 }ATOM_ROM_HEADER; 229 230 /*==============================Command Table Portion==================================== */ 231 232 #ifdef UEFI_BUILD 233 #define UTEMP USHORT 234 #define USHORT void* 235 #endif 236 237 /****************************************************************************/ 238 // Structures used in Command.mtb 239 /****************************************************************************/ 240 typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ 241 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 242 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON 243 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 244 USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios 245 USHORT DIGxEncoderControl; //Only used by Bios 246 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 247 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 248 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed 249 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 250 USHORT GPIOPinControl; //Atomic Table, only used by Bios 251 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 252 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 253 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 254 USHORT DynamicClockGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 255 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 256 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 257 USHORT MemoryPLLInit; 258 USHORT AdjustDisplayPll; //only used by Bios 259 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 260 USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios 261 USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios 262 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 263 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 264 USHORT LCD1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 265 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 266 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 267 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 268 USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead 269 USHORT GetConditionalGoldenSetting; //only used by Bios 270 USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1 271 USHORT TMDSAEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3 272 USHORT LVDSEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3 273 USHORT TV1OutputControl; //Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead 274 USHORT EnableScaler; //Atomic Table, used only by Bios 275 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 276 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 277 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 278 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 279 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios 280 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 281 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 282 USHORT SetCRTC_Replication; //Atomic Table, used only by Bios 283 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 284 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios 285 USHORT UpdateCRTC_DoubleBufferRegisters; 286 USHORT LUT_AutoFill; //Atomic Table, only used by Bios 287 USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios 288 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 289 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 290 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 291 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 292 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 293 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios 294 USHORT MemoryCleanUp; //Atomic Table, only used by Bios 295 USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios 296 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components 297 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components 298 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init 299 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 300 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 301 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock 302 USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock 303 USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios 304 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 305 USHORT MemoryTraining; //Atomic Table, used only by Bios 306 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 307 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 308 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 309 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 310 USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 311 USHORT SetupHWAssistedI2CStatus; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" 312 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 313 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 314 USHORT EnableYUV; //Atomic Table, indirectly used by various SW components,called from EnableVGARender 315 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 316 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 317 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 318 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 319 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios 320 USHORT DPEncoderService; //Function Table,only used by Bios 321 }ATOM_MASTER_LIST_OF_COMMAND_TABLES; 322 323 // For backward compatible 324 #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction 325 #define UNIPHYTransmitterControl DIG1TransmitterControl 326 #define LVTMATransmitterControl DIG2TransmitterControl 327 #define SetCRTC_DPM_State GetConditionalGoldenSetting 328 #define SetUniphyInstance ASIC_StaticPwrMgtStatusChange 329 #define HPDInterruptService ReadHWAssistedI2CStatus 330 #define EnableVGA_Access GetSCLKOverMCLKRatio 331 #define GetDispObjectInfo EnableYUV 332 333 typedef struct _ATOM_MASTER_COMMAND_TABLE 334 { 335 ATOM_COMMON_TABLE_HEADER sHeader; 336 ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; 337 }ATOM_MASTER_COMMAND_TABLE; 338 339 /****************************************************************************/ 340 // Structures used in every command table 341 /****************************************************************************/ 342 typedef struct _ATOM_TABLE_ATTRIBUTE 343 { 344 #if ATOM_BIG_ENDIAN 345 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 346 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 347 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 348 #else 349 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 350 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 351 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 352 #endif 353 }ATOM_TABLE_ATTRIBUTE; 354 355 typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS 356 { 357 ATOM_TABLE_ATTRIBUTE sbfAccess; 358 USHORT susAccess; 359 }ATOM_TABLE_ATTRIBUTE_ACCESS; 360 361 /****************************************************************************/ 362 // Common header for all command tables. 363 // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 364 // And the pointer actually points to this header. 365 /****************************************************************************/ 366 typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER 367 { 368 ATOM_COMMON_TABLE_HEADER CommonHeader; 369 ATOM_TABLE_ATTRIBUTE TableAttribute; 370 }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; 371 372 /****************************************************************************/ 373 // Structures used by ComputeMemoryEnginePLLTable 374 /****************************************************************************/ 375 #define COMPUTE_MEMORY_PLL_PARAM 1 376 #define COMPUTE_ENGINE_PLL_PARAM 2 377 #define ADJUST_MC_SETTING_PARAM 3 378 379 /****************************************************************************/ 380 // Structures used by AdjustMemoryControllerTable 381 /****************************************************************************/ 382 typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ 383 { 384 #if ATOM_BIG_ENDIAN 385 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 386 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 387 ULONG ulClockFreq:24; 388 #else 389 ULONG ulClockFreq:24; 390 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 391 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 392 #endif 393 }ATOM_ADJUST_MEMORY_CLOCK_FREQ; 394 #define POINTER_RETURN_FLAG 0x80 395 396 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 397 { 398 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div 399 UCHAR ucAction; //0:reserved //1:Memory //2:Engine 400 UCHAR ucReserved; //may expand to return larger Fbdiv later 401 UCHAR ucFbDiv; //return value 402 UCHAR ucPostDiv; //return value 403 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; 404 405 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 406 { 407 ULONG ulClock; //When return, [23:0] return real clock 408 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register 409 USHORT usFbDiv; //return Feedback value to be written to register 410 UCHAR ucPostDiv; //return post div to be written to register 411 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; 412 #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 413 414 415 #define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value 416 #define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 417 #define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 418 #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 419 #define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 420 #define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 421 #define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK 422 423 #define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 424 #define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 425 #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 426 #define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 427 #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 428 429 typedef struct _ATOM_COMPUTE_CLOCK_FREQ 430 { 431 #if ATOM_BIG_ENDIAN 432 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 433 ULONG ulClockFreq:24; // in unit of 10kHz 434 #else 435 ULONG ulClockFreq:24; // in unit of 10kHz 436 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 437 #endif 438 }ATOM_COMPUTE_CLOCK_FREQ; 439 440 typedef struct _ATOM_S_MPLL_FB_DIVIDER 441 { 442 USHORT usFbDivFrac; 443 USHORT usFbDiv; 444 }ATOM_S_MPLL_FB_DIVIDER; 445 446 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 447 { 448 union 449 { 450 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 451 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 452 }; 453 UCHAR ucRefDiv; //Output Parameter 454 UCHAR ucPostDiv; //Output Parameter 455 UCHAR ucCntlFlag; //Output Parameter 456 UCHAR ucReserved; 457 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; 458 459 // ucCntlFlag 460 #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 461 #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 462 #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 463 #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 464 465 466 // V4 are only used for APU which PLL outside GPU 467 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 468 { 469 #if ATOM_BIG_ENDIAN 470 ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly 471 ULONG ulClock:24; //Input= target clock, output = actual clock 472 #else 473 ULONG ulClock:24; //Input= target clock, output = actual clock 474 ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly 475 #endif 476 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; 477 478 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 479 { 480 union 481 { 482 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 483 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 484 }; 485 UCHAR ucRefDiv; //Output Parameter 486 UCHAR ucPostDiv; //Output Parameter 487 union 488 { 489 UCHAR ucCntlFlag; //Output Flags 490 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode 491 }; 492 UCHAR ucReserved; 493 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; 494 495 // ucInputFlag 496 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode 497 498 typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER 499 { 500 ATOM_COMPUTE_CLOCK_FREQ ulClock; 501 ULONG ulReserved[2]; 502 }DYNAMICE_MEMORY_SETTINGS_PARAMETER; 503 504 typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER 505 { 506 ATOM_COMPUTE_CLOCK_FREQ ulClock; 507 ULONG ulMemoryClock; 508 ULONG ulReserved; 509 }DYNAMICE_ENGINE_SETTINGS_PARAMETER; 510 511 /****************************************************************************/ 512 // Structures used by SetEngineClockTable 513 /****************************************************************************/ 514 typedef struct _SET_ENGINE_CLOCK_PARAMETERS 515 { 516 ULONG ulTargetEngineClock; //In 10Khz unit 517 }SET_ENGINE_CLOCK_PARAMETERS; 518 519 typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION 520 { 521 ULONG ulTargetEngineClock; //In 10Khz unit 522 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 523 }SET_ENGINE_CLOCK_PS_ALLOCATION; 524 525 /****************************************************************************/ 526 // Structures used by SetMemoryClockTable 527 /****************************************************************************/ 528 typedef struct _SET_MEMORY_CLOCK_PARAMETERS 529 { 530 ULONG ulTargetMemoryClock; //In 10Khz unit 531 }SET_MEMORY_CLOCK_PARAMETERS; 532 533 typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION 534 { 535 ULONG ulTargetMemoryClock; //In 10Khz unit 536 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 537 }SET_MEMORY_CLOCK_PS_ALLOCATION; 538 539 /****************************************************************************/ 540 // Structures used by ASIC_Init.ctb 541 /****************************************************************************/ 542 typedef struct _ASIC_INIT_PARAMETERS 543 { 544 ULONG ulDefaultEngineClock; //In 10Khz unit 545 ULONG ulDefaultMemoryClock; //In 10Khz unit 546 }ASIC_INIT_PARAMETERS; 547 548 typedef struct _ASIC_INIT_PS_ALLOCATION 549 { 550 ASIC_INIT_PARAMETERS sASICInitClocks; 551 SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure 552 }ASIC_INIT_PS_ALLOCATION; 553 554 /****************************************************************************/ 555 // Structure used by DynamicClockGatingTable.ctb 556 /****************************************************************************/ 557 typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS 558 { 559 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 560 UCHAR ucPadding[3]; 561 }DYNAMIC_CLOCK_GATING_PARAMETERS; 562 #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS 563 564 /****************************************************************************/ 565 // Structure used by EnableASIC_StaticPwrMgtTable.ctb 566 /****************************************************************************/ 567 typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 568 { 569 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 570 UCHAR ucPadding[3]; 571 }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; 572 #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 573 574 /****************************************************************************/ 575 // Structures used by DAC_LoadDetectionTable.ctb 576 /****************************************************************************/ 577 typedef struct _DAC_LOAD_DETECTION_PARAMETERS 578 { 579 USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} 580 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} 581 UCHAR ucMisc; //Valid only when table revision =1.3 and above 582 }DAC_LOAD_DETECTION_PARAMETERS; 583 584 // DAC_LOAD_DETECTION_PARAMETERS.ucMisc 585 #define DAC_LOAD_MISC_YPrPb 0x01 586 587 typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION 588 { 589 DAC_LOAD_DETECTION_PARAMETERS sDacload; 590 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC 591 }DAC_LOAD_DETECTION_PS_ALLOCATION; 592 593 /****************************************************************************/ 594 // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb 595 /****************************************************************************/ 596 typedef struct _DAC_ENCODER_CONTROL_PARAMETERS 597 { 598 USHORT usPixelClock; // in 10KHz; for bios convenient 599 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) 600 UCHAR ucAction; // 0: turn off encoder 601 // 1: setup and turn on encoder 602 // 7: ATOM_ENCODER_INIT Initialize DAC 603 }DAC_ENCODER_CONTROL_PARAMETERS; 604 605 #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS 606 607 /****************************************************************************/ 608 // Structures used by DIG1EncoderControlTable 609 // DIG2EncoderControlTable 610 // ExternalEncoderControlTable 611 /****************************************************************************/ 612 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS 613 { 614 USHORT usPixelClock; // in 10KHz; for bios convenient 615 UCHAR ucConfig; 616 // [2] Link Select: 617 // =0: PHY linkA if bfLane<3 618 // =1: PHY linkB if bfLanes<3 619 // =0: PHY linkA+B if bfLanes=3 620 // [3] Transmitter Sel 621 // =0: UNIPHY or PCIEPHY 622 // =1: LVTMA 623 UCHAR ucAction; // =0: turn off encoder 624 // =1: turn on encoder 625 UCHAR ucEncoderMode; 626 // =0: DP encoder 627 // =1: LVDS encoder 628 // =2: DVI encoder 629 // =3: HDMI encoder 630 // =4: SDVO encoder 631 UCHAR ucLaneNum; // how many lanes to enable 632 UCHAR ucReserved[2]; 633 }DIG_ENCODER_CONTROL_PARAMETERS; 634 #define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS 635 #define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS 636 637 //ucConfig 638 #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 639 #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 640 #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 641 #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02 642 #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 643 #define ATOM_ENCODER_CONFIG_LINKA 0x00 644 #define ATOM_ENCODER_CONFIG_LINKB 0x04 645 #define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA 646 #define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB 647 #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 648 #define ATOM_ENCODER_CONFIG_UNIPHY 0x00 649 #define ATOM_ENCODER_CONFIG_LVTMA 0x08 650 #define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 651 #define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 652 #define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 653 // ucAction 654 // ATOM_ENABLE: Enable Encoder 655 // ATOM_DISABLE: Disable Encoder 656 657 //ucEncoderMode 658 #define ATOM_ENCODER_MODE_DP 0 659 #define ATOM_ENCODER_MODE_LVDS 1 660 #define ATOM_ENCODER_MODE_DVI 2 661 #define ATOM_ENCODER_MODE_HDMI 3 662 #define ATOM_ENCODER_MODE_SDVO 4 663 #define ATOM_ENCODER_MODE_DP_AUDIO 5 664 #define ATOM_ENCODER_MODE_TV 13 665 #define ATOM_ENCODER_MODE_CV 14 666 #define ATOM_ENCODER_MODE_CRT 15 667 #define ATOM_ENCODER_MODE_DVO 16 668 #define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2 669 #define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2 670 671 typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 672 { 673 #if ATOM_BIG_ENDIAN 674 UCHAR ucReserved1:2; 675 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 676 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 677 UCHAR ucReserved:1; 678 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 679 #else 680 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 681 UCHAR ucReserved:1; 682 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 683 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 684 UCHAR ucReserved1:2; 685 #endif 686 }ATOM_DIG_ENCODER_CONFIG_V2; 687 688 689 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 690 { 691 USHORT usPixelClock; // in 10KHz; for bios convenient 692 ATOM_DIG_ENCODER_CONFIG_V2 acConfig; 693 UCHAR ucAction; 694 UCHAR ucEncoderMode; 695 // =0: DP encoder 696 // =1: LVDS encoder 697 // =2: DVI encoder 698 // =3: HDMI encoder 699 // =4: SDVO encoder 700 UCHAR ucLaneNum; // how many lanes to enable 701 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 702 UCHAR ucReserved; 703 }DIG_ENCODER_CONTROL_PARAMETERS_V2; 704 705 //ucConfig 706 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 707 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 708 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 709 #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 710 #define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 711 #define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 712 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 713 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 714 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 715 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 716 717 // ucAction: 718 // ATOM_DISABLE 719 // ATOM_ENABLE 720 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 721 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 722 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a 723 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13 724 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b 725 #define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c 726 #define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d 727 #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e 728 #define ATOM_ENCODER_CMD_SETUP 0x0f 729 730 // ucStatus 731 #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 732 #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 733 734 //ucTableFormatRevision=1 735 //ucTableContentRevision=3 736 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 737 typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 738 { 739 #if ATOM_BIG_ENDIAN 740 UCHAR ucReserved1:1; 741 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 742 UCHAR ucReserved:3; 743 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 744 #else 745 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 746 UCHAR ucReserved:3; 747 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 748 UCHAR ucReserved1:1; 749 #endif 750 }ATOM_DIG_ENCODER_CONFIG_V3; 751 752 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 753 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 754 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 755 #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 756 #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00 757 #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10 758 #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20 759 #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30 760 #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40 761 #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50 762 763 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 764 { 765 USHORT usPixelClock; // in 10KHz; for bios convenient 766 ATOM_DIG_ENCODER_CONFIG_V3 acConfig; 767 UCHAR ucAction; 768 UCHAR ucEncoderMode; 769 // =0: DP encoder 770 // =1: LVDS encoder 771 // =2: DVI encoder 772 // =3: HDMI encoder 773 // =4: SDVO encoder 774 // =5: DP audio 775 UCHAR ucLaneNum; // how many lanes to enable 776 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 777 UCHAR ucReserved; 778 }DIG_ENCODER_CONTROL_PARAMETERS_V3; 779 780 //ucTableFormatRevision=1 781 //ucTableContentRevision=4 782 // start from NI 783 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 784 typedef struct _ATOM_DIG_ENCODER_CONFIG_V4 785 { 786 #if ATOM_BIG_ENDIAN 787 UCHAR ucReserved1:1; 788 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 789 UCHAR ucReserved:2; 790 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 791 #else 792 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 793 UCHAR ucReserved:2; 794 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 795 UCHAR ucReserved1:1; 796 #endif 797 }ATOM_DIG_ENCODER_CONFIG_V4; 798 799 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03 800 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00 801 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01 802 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02 803 #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70 804 #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00 805 #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10 806 #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20 807 #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30 808 #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40 809 #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50 810 811 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 812 { 813 USHORT usPixelClock; // in 10KHz; for bios convenient 814 union{ 815 ATOM_DIG_ENCODER_CONFIG_V4 acConfig; 816 UCHAR ucConfig; 817 }; 818 UCHAR ucAction; 819 UCHAR ucEncoderMode; 820 // =0: DP encoder 821 // =1: LVDS encoder 822 // =2: DVI encoder 823 // =3: HDMI encoder 824 // =4: SDVO encoder 825 // =5: DP audio 826 UCHAR ucLaneNum; // how many lanes to enable 827 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 828 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version 829 }DIG_ENCODER_CONTROL_PARAMETERS_V4; 830 831 // define ucBitPerColor: 832 #define PANEL_BPC_UNDEFINE 0x00 833 #define PANEL_6BIT_PER_COLOR 0x01 834 #define PANEL_8BIT_PER_COLOR 0x02 835 #define PANEL_10BIT_PER_COLOR 0x03 836 #define PANEL_12BIT_PER_COLOR 0x04 837 #define PANEL_16BIT_PER_COLOR 0x05 838 839 /****************************************************************************/ 840 // Structures used by UNIPHYTransmitterControlTable 841 // LVTMATransmitterControlTable 842 // DVOOutputControlTable 843 /****************************************************************************/ 844 typedef struct _ATOM_DP_VS_MODE 845 { 846 UCHAR ucLaneSel; 847 UCHAR ucLaneSet; 848 }ATOM_DP_VS_MODE; 849 850 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS 851 { 852 union 853 { 854 USHORT usPixelClock; // in 10KHz; for bios convenient 855 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 856 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 857 }; 858 UCHAR ucConfig; 859 // [0]=0: 4 lane Link, 860 // =1: 8 lane Link ( Dual Links TMDS ) 861 // [1]=0: InCoherent mode 862 // =1: Coherent Mode 863 // [2] Link Select: 864 // =0: PHY linkA if bfLane<3 865 // =1: PHY linkB if bfLanes<3 866 // =0: PHY linkA+B if bfLanes=3 867 // [5:4]PCIE lane Sel 868 // =0: lane 0~3 or 0~7 869 // =1: lane 4~7 870 // =2: lane 8~11 or 8~15 871 // =3: lane 12~15 872 UCHAR ucAction; // =0: turn off encoder 873 // =1: turn on encoder 874 UCHAR ucReserved[4]; 875 }DIG_TRANSMITTER_CONTROL_PARAMETERS; 876 877 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS 878 879 //ucInitInfo 880 #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff 881 882 //ucConfig 883 #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 884 #define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 885 #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 886 #define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 887 #define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 888 #define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 889 #define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 890 891 #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 892 #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 893 #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 894 895 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 896 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 897 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 898 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 899 #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 900 #define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 901 #define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 902 #define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 903 #define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 904 #define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 905 #define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 906 907 //ucAction 908 #define ATOM_TRANSMITTER_ACTION_DISABLE 0 909 #define ATOM_TRANSMITTER_ACTION_ENABLE 1 910 #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 911 #define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 912 #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 913 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 914 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 915 #define ATOM_TRANSMITTER_ACTION_INIT 7 916 #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 917 #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 918 #define ATOM_TRANSMITTER_ACTION_SETUP 10 919 #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 920 #define ATOM_TRANSMITTER_ACTION_POWER_ON 12 921 #define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 922 923 // Following are used for DigTransmitterControlTable ver1.2 924 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 925 { 926 #if ATOM_BIG_ENDIAN 927 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 928 // =1 Dig Transmitter 2 ( Uniphy CD ) 929 // =2 Dig Transmitter 3 ( Uniphy EF ) 930 UCHAR ucReserved:1; 931 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 932 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 933 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 934 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 935 936 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 937 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 938 #else 939 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 940 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 941 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 942 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 943 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 944 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 945 UCHAR ucReserved:1; 946 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 947 // =1 Dig Transmitter 2 ( Uniphy CD ) 948 // =2 Dig Transmitter 3 ( Uniphy EF ) 949 #endif 950 }ATOM_DIG_TRANSMITTER_CONFIG_V2; 951 952 //ucConfig 953 //Bit0 954 #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 955 956 //Bit1 957 #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 958 959 //Bit2 960 #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 961 #define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 962 #define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 963 964 // Bit3 965 #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 966 #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 967 #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 968 969 // Bit4 970 #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 971 972 // Bit7:6 973 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 974 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB 975 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD 976 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF 977 978 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 979 { 980 union 981 { 982 USHORT usPixelClock; // in 10KHz; for bios convenient 983 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 984 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 985 }; 986 ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; 987 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 988 UCHAR ucReserved[4]; 989 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; 990 991 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 992 { 993 #if ATOM_BIG_ENDIAN 994 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 995 // =1 Dig Transmitter 2 ( Uniphy CD ) 996 // =2 Dig Transmitter 3 ( Uniphy EF ) 997 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 998 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 999 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1000 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1001 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1002 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1003 #else 1004 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1005 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1006 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1007 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1008 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1009 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1010 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1011 // =1 Dig Transmitter 2 ( Uniphy CD ) 1012 // =2 Dig Transmitter 3 ( Uniphy EF ) 1013 #endif 1014 }ATOM_DIG_TRANSMITTER_CONFIG_V3; 1015 1016 1017 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 1018 { 1019 union 1020 { 1021 USHORT usPixelClock; // in 10KHz; for bios convenient 1022 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1023 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1024 }; 1025 ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; 1026 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1027 UCHAR ucLaneNum; 1028 UCHAR ucReserved[3]; 1029 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; 1030 1031 //ucConfig 1032 //Bit0 1033 #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 1034 1035 //Bit1 1036 #define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 1037 1038 //Bit2 1039 #define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 1040 #define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 1041 #define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 1042 1043 // Bit3 1044 #define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 1045 #define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 1046 #define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 1047 1048 // Bit5:4 1049 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 1050 #define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 1051 #define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 1052 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 1053 1054 // Bit7:6 1055 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 1056 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB 1057 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD 1058 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF 1059 1060 1061 /****************************************************************************/ 1062 // Structures used by UNIPHYTransmitterControlTable V1.4 1063 // ASIC Families: NI 1064 // ucTableFormatRevision=1 1065 // ucTableContentRevision=4 1066 /****************************************************************************/ 1067 typedef struct _ATOM_DP_VS_MODE_V4 1068 { 1069 UCHAR ucLaneSel; 1070 union 1071 { 1072 UCHAR ucLaneSet; 1073 struct { 1074 #if ATOM_BIG_ENDIAN 1075 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1076 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1077 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1078 #else 1079 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1080 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1081 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1082 #endif 1083 }; 1084 }; 1085 }ATOM_DP_VS_MODE_V4; 1086 1087 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 1088 { 1089 #if ATOM_BIG_ENDIAN 1090 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1091 // =1 Dig Transmitter 2 ( Uniphy CD ) 1092 // =2 Dig Transmitter 3 ( Uniphy EF ) 1093 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1094 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1095 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1096 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1097 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1098 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1099 #else 1100 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1101 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1102 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1103 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1104 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1105 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1106 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1107 // =1 Dig Transmitter 2 ( Uniphy CD ) 1108 // =2 Dig Transmitter 3 ( Uniphy EF ) 1109 #endif 1110 }ATOM_DIG_TRANSMITTER_CONFIG_V4; 1111 1112 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 1113 { 1114 union 1115 { 1116 USHORT usPixelClock; // in 10KHz; for bios convenient 1117 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1118 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version 1119 }; 1120 union 1121 { 1122 ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; 1123 UCHAR ucConfig; 1124 }; 1125 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1126 UCHAR ucLaneNum; 1127 UCHAR ucReserved[3]; 1128 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; 1129 1130 //ucConfig 1131 //Bit0 1132 #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 1133 //Bit1 1134 #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 1135 //Bit2 1136 #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 1137 #define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 1138 #define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 1139 // Bit3 1140 #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 1141 #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 1142 #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 1143 // Bit5:4 1144 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 1145 #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 1146 #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10 1147 #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4 1148 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3 1149 // Bit7:6 1150 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0 1151 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB 1152 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD 1153 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF 1154 1155 1156 /****************************************************************************/ 1157 // Structures used by ExternalEncoderControlTable V1.3 1158 // ASIC Families: Evergreen, Llano, NI 1159 // ucTableFormatRevision=1 1160 // ucTableContentRevision=3 1161 /****************************************************************************/ 1162 1163 typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 1164 { 1165 union{ 1166 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 1167 USHORT usConnectorId; // connector id, valid when ucAction = INIT 1168 }; 1169 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 1170 UCHAR ucAction; // 1171 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 1172 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 1173 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 1174 UCHAR ucReserved; 1175 }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; 1176 1177 // ucAction 1178 #define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00 1179 #define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01 1180 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07 1181 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f 1182 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 1183 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 1184 #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 1185 1186 // ucConfig 1187 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 1188 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 1189 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 1190 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02 1191 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK 0x70 1192 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00 1193 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10 1194 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20 1195 1196 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 1197 { 1198 EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder; 1199 ULONG ulReserved[2]; 1200 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; 1201 1202 1203 /****************************************************************************/ 1204 // Structures used by DAC1OuputControlTable 1205 // DAC2OuputControlTable 1206 // LVTMAOutputControlTable (Before DEC30) 1207 // TMDSAOutputControlTable (Before DEC30) 1208 /****************************************************************************/ 1209 typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1210 { 1211 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE 1212 // When the display is LCD, in addition to above: 1213 // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| 1214 // ATOM_LCD_SELFTEST_STOP 1215 1216 UCHAR aucPadding[3]; // padding to DWORD aligned 1217 }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; 1218 1219 #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1220 1221 1222 #define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1223 #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1224 1225 #define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1226 #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1227 1228 #define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1229 #define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1230 1231 #define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1232 #define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1233 1234 #define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1235 #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1236 1237 #define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1238 #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1239 1240 #define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1241 #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1242 1243 #define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1244 #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION 1245 #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS 1246 1247 /****************************************************************************/ 1248 // Structures used by BlankCRTCTable 1249 /****************************************************************************/ 1250 typedef struct _BLANK_CRTC_PARAMETERS 1251 { 1252 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1253 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF 1254 USHORT usBlackColorRCr; 1255 USHORT usBlackColorGY; 1256 USHORT usBlackColorBCb; 1257 }BLANK_CRTC_PARAMETERS; 1258 #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS 1259 1260 /****************************************************************************/ 1261 // Structures used by EnableCRTCTable 1262 // EnableCRTCMemReqTable 1263 // UpdateCRTC_DoubleBufferRegistersTable 1264 /****************************************************************************/ 1265 typedef struct _ENABLE_CRTC_PARAMETERS 1266 { 1267 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1268 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1269 UCHAR ucPadding[2]; 1270 }ENABLE_CRTC_PARAMETERS; 1271 #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS 1272 1273 /****************************************************************************/ 1274 // Structures used by SetCRTC_OverScanTable 1275 /****************************************************************************/ 1276 typedef struct _SET_CRTC_OVERSCAN_PARAMETERS 1277 { 1278 USHORT usOverscanRight; // right 1279 USHORT usOverscanLeft; // left 1280 USHORT usOverscanBottom; // bottom 1281 USHORT usOverscanTop; // top 1282 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1283 UCHAR ucPadding[3]; 1284 }SET_CRTC_OVERSCAN_PARAMETERS; 1285 #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS 1286 1287 /****************************************************************************/ 1288 // Structures used by SetCRTC_ReplicationTable 1289 /****************************************************************************/ 1290 typedef struct _SET_CRTC_REPLICATION_PARAMETERS 1291 { 1292 UCHAR ucH_Replication; // horizontal replication 1293 UCHAR ucV_Replication; // vertical replication 1294 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1295 UCHAR ucPadding; 1296 }SET_CRTC_REPLICATION_PARAMETERS; 1297 #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS 1298 1299 /****************************************************************************/ 1300 // Structures used by SelectCRTC_SourceTable 1301 /****************************************************************************/ 1302 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS 1303 { 1304 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1305 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... 1306 UCHAR ucPadding[2]; 1307 }SELECT_CRTC_SOURCE_PARAMETERS; 1308 #define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS 1309 1310 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 1311 { 1312 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1313 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1314 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1315 UCHAR ucPadding; 1316 }SELECT_CRTC_SOURCE_PARAMETERS_V2; 1317 1318 //ucEncoderID 1319 //#define ASIC_INT_DAC1_ENCODER_ID 0x00 1320 //#define ASIC_INT_TV_ENCODER_ID 0x02 1321 //#define ASIC_INT_DIG1_ENCODER_ID 0x03 1322 //#define ASIC_INT_DAC2_ENCODER_ID 0x04 1323 //#define ASIC_EXT_TV_ENCODER_ID 0x06 1324 //#define ASIC_INT_DVO_ENCODER_ID 0x07 1325 //#define ASIC_INT_DIG2_ENCODER_ID 0x09 1326 //#define ASIC_EXT_DIG_ENCODER_ID 0x05 1327 1328 //ucEncodeMode 1329 //#define ATOM_ENCODER_MODE_DP 0 1330 //#define ATOM_ENCODER_MODE_LVDS 1 1331 //#define ATOM_ENCODER_MODE_DVI 2 1332 //#define ATOM_ENCODER_MODE_HDMI 3 1333 //#define ATOM_ENCODER_MODE_SDVO 4 1334 //#define ATOM_ENCODER_MODE_TV 13 1335 //#define ATOM_ENCODER_MODE_CV 14 1336 //#define ATOM_ENCODER_MODE_CRT 15 1337 1338 /****************************************************************************/ 1339 // Structures used by SetPixelClockTable 1340 // GetPixelClockTable 1341 /****************************************************************************/ 1342 //Major revision=1., Minor revision=1 1343 typedef struct _PIXEL_CLOCK_PARAMETERS 1344 { 1345 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1346 // 0 means disable PPLL 1347 USHORT usRefDiv; // Reference divider 1348 USHORT usFbDiv; // feedback divider 1349 UCHAR ucPostDiv; // post divider 1350 UCHAR ucFracFbDiv; // fractional feedback divider 1351 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1352 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1353 UCHAR ucCRTC; // Which CRTC uses this Ppll 1354 UCHAR ucPadding; 1355 }PIXEL_CLOCK_PARAMETERS; 1356 1357 //Major revision=1., Minor revision=2, add ucMiscIfno 1358 //ucMiscInfo: 1359 #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 1360 #define MISC_DEVICE_INDEX_MASK 0xF0 1361 #define MISC_DEVICE_INDEX_SHIFT 4 1362 1363 typedef struct _PIXEL_CLOCK_PARAMETERS_V2 1364 { 1365 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1366 // 0 means disable PPLL 1367 USHORT usRefDiv; // Reference divider 1368 USHORT usFbDiv; // feedback divider 1369 UCHAR ucPostDiv; // post divider 1370 UCHAR ucFracFbDiv; // fractional feedback divider 1371 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1372 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1373 UCHAR ucCRTC; // Which CRTC uses this Ppll 1374 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog 1375 }PIXEL_CLOCK_PARAMETERS_V2; 1376 1377 //Major revision=1., Minor revision=3, structure/definition change 1378 //ucEncoderMode: 1379 //ATOM_ENCODER_MODE_DP 1380 //ATOM_ENOCDER_MODE_LVDS 1381 //ATOM_ENOCDER_MODE_DVI 1382 //ATOM_ENOCDER_MODE_HDMI 1383 //ATOM_ENOCDER_MODE_SDVO 1384 //ATOM_ENCODER_MODE_TV 13 1385 //ATOM_ENCODER_MODE_CV 14 1386 //ATOM_ENCODER_MODE_CRT 15 1387 1388 //ucDVOConfig 1389 //#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 1390 //#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 1391 //#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 1392 //#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 1393 //#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 1394 //#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 1395 //#define DVO_ENCODER_CONFIG_24BIT 0x08 1396 1397 //ucMiscInfo: also changed, see below 1398 #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 1399 #define PIXEL_CLOCK_MISC_VGA_MODE 0x02 1400 #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 1401 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 1402 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 1403 #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 1404 #define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 1405 // V1.4 for RoadRunner 1406 #define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 1407 #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 1408 1409 1410 typedef struct _PIXEL_CLOCK_PARAMETERS_V3 1411 { 1412 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1413 // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. 1414 USHORT usRefDiv; // Reference divider 1415 USHORT usFbDiv; // feedback divider 1416 UCHAR ucPostDiv; // post divider 1417 UCHAR ucFracFbDiv; // fractional feedback divider 1418 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1419 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h 1420 union 1421 { 1422 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ 1423 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit 1424 }; 1425 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel 1426 // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source 1427 // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider 1428 }PIXEL_CLOCK_PARAMETERS_V3; 1429 1430 #define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 1431 #define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST 1432 1433 typedef struct _PIXEL_CLOCK_PARAMETERS_V5 1434 { 1435 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to 1436 // drive the pixel clock. not used for DCPLL case. 1437 union{ 1438 UCHAR ucReserved; 1439 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. 1440 }; 1441 USHORT usPixelClock; // target the pixel clock to drive the CRTC timing 1442 // 0 means disable PPLL/DCPLL. 1443 USHORT usFbDiv; // feedback divider integer part. 1444 UCHAR ucPostDiv; // post divider. 1445 UCHAR ucRefDiv; // Reference divider 1446 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1447 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1448 // indicate which graphic encoder will be used. 1449 UCHAR ucEncoderMode; // Encoder mode: 1450 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1451 // bit[1]= when VGA timing is used. 1452 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1453 // bit[4]= RefClock source for PPLL. 1454 // =0: XTLAIN( default mode ) 1455 // =1: other external clock source, which is pre-defined 1456 // by VBIOS depend on the feature required. 1457 // bit[7:5]: reserved. 1458 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1459 1460 }PIXEL_CLOCK_PARAMETERS_V5; 1461 1462 #define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 1463 #define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 1464 #define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c 1465 #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 1466 #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 1467 #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 1468 #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 1469 1470 typedef struct _CRTC_PIXEL_CLOCK_FREQ 1471 { 1472 #if ATOM_BIG_ENDIAN 1473 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1474 // drive the pixel clock. not used for DCPLL case. 1475 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1476 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1477 #else 1478 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1479 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1480 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1481 // drive the pixel clock. not used for DCPLL case. 1482 #endif 1483 }CRTC_PIXEL_CLOCK_FREQ; 1484 1485 typedef struct _PIXEL_CLOCK_PARAMETERS_V6 1486 { 1487 union{ 1488 CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency 1489 ULONG ulDispEngClkFreq; // dispclk frequency 1490 }; 1491 USHORT usFbDiv; // feedback divider integer part. 1492 UCHAR ucPostDiv; // post divider. 1493 UCHAR ucRefDiv; // Reference divider 1494 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1495 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1496 // indicate which graphic encoder will be used. 1497 UCHAR ucEncoderMode; // Encoder mode: 1498 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1499 // bit[1]= when VGA timing is used. 1500 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1501 // bit[4]= RefClock source for PPLL. 1502 // =0: XTLAIN( default mode ) 1503 // =1: other external clock source, which is pre-defined 1504 // by VBIOS depend on the feature required. 1505 // bit[7:5]: reserved. 1506 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1507 1508 }PIXEL_CLOCK_PARAMETERS_V6; 1509 1510 #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01 1511 #define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02 1512 #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c 1513 #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 1514 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 1515 #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 1516 #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c 1517 #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 1518 1519 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 1520 { 1521 PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; 1522 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; 1523 1524 typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 1525 { 1526 UCHAR ucStatus; 1527 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock 1528 UCHAR ucReserved[2]; 1529 }GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; 1530 1531 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 1532 { 1533 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; 1534 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; 1535 1536 /****************************************************************************/ 1537 // Structures used by AdjustDisplayPllTable 1538 /****************************************************************************/ 1539 typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS 1540 { 1541 USHORT usPixelClock; 1542 UCHAR ucTransmitterID; 1543 UCHAR ucEncodeMode; 1544 union 1545 { 1546 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit 1547 UCHAR ucConfig; //if none DVO, not defined yet 1548 }; 1549 UCHAR ucReserved[3]; 1550 }ADJUST_DISPLAY_PLL_PARAMETERS; 1551 1552 #define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 1553 #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS 1554 1555 typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 1556 { 1557 USHORT usPixelClock; // target pixel clock 1558 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h 1559 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI 1560 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX 1561 UCHAR ucExtTransmitterID; // external encoder id. 1562 UCHAR ucReserved[2]; 1563 }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; 1564 1565 // usDispPllConfig v1.2 for RoadRunner 1566 #define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO 1567 #define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO 1568 #define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO 1569 #define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO 1570 #define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO 1571 #define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO 1572 #define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO 1573 #define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS 1574 #define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI 1575 #define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS 1576 1577 1578 typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 1579 { 1580 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc 1581 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) 1582 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider 1583 UCHAR ucReserved[2]; 1584 }ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; 1585 1586 typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 1587 { 1588 union 1589 { 1590 ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; 1591 ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; 1592 }; 1593 } ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; 1594 1595 /****************************************************************************/ 1596 // Structures used by EnableYUVTable 1597 /****************************************************************************/ 1598 typedef struct _ENABLE_YUV_PARAMETERS 1599 { 1600 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) 1601 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format 1602 UCHAR ucPadding[2]; 1603 }ENABLE_YUV_PARAMETERS; 1604 #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS 1605 1606 /****************************************************************************/ 1607 // Structures used by GetMemoryClockTable 1608 /****************************************************************************/ 1609 typedef struct _GET_MEMORY_CLOCK_PARAMETERS 1610 { 1611 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit 1612 } GET_MEMORY_CLOCK_PARAMETERS; 1613 #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS 1614 1615 /****************************************************************************/ 1616 // Structures used by GetEngineClockTable 1617 /****************************************************************************/ 1618 typedef struct _GET_ENGINE_CLOCK_PARAMETERS 1619 { 1620 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit 1621 } GET_ENGINE_CLOCK_PARAMETERS; 1622 #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS 1623 1624 /****************************************************************************/ 1625 // Following Structures and constant may be obsolete 1626 /****************************************************************************/ 1627 //Maxium 8 bytes,the data read in will be placed in the parameter space. 1628 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed 1629 typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1630 { 1631 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1632 USHORT usVRAMAddress; //Address in Frame Buffer where to pace raw EDID 1633 USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status 1634 //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte 1635 UCHAR ucSlaveAddr; //Read from which slave 1636 UCHAR ucLineNumber; //Read from which HW assisted line 1637 }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; 1638 #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1639 1640 1641 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 1642 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 1643 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 1644 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 1645 #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 1646 1647 typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1648 { 1649 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1650 USHORT usByteOffset; //Write to which byte 1651 //Upper portion of usByteOffset is Format of data 1652 //1bytePS+offsetPS 1653 //2bytesPS+offsetPS 1654 //blockID+offsetPS 1655 //blockID+offsetID 1656 //blockID+counterID+offsetID 1657 UCHAR ucData; //PS data1 1658 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 1659 UCHAR ucSlaveAddr; //Write to which slave 1660 UCHAR ucLineNumber; //Write from which HW assisted line 1661 }WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; 1662 1663 #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1664 1665 typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS 1666 { 1667 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1668 UCHAR ucSlaveAddr; //Write to which slave 1669 UCHAR ucLineNumber; //Write from which HW assisted line 1670 }SET_UP_HW_I2C_DATA_PARAMETERS; 1671 1672 1673 /**************************************************************************/ 1674 #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1675 1676 1677 /****************************************************************************/ 1678 // Structures used by PowerConnectorDetectionTable 1679 /****************************************************************************/ 1680 typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS 1681 { 1682 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1683 UCHAR ucPwrBehaviorId; 1684 USHORT usPwrBudget; //how much power currently boot to in unit of watt 1685 }POWER_CONNECTOR_DETECTION_PARAMETERS; 1686 1687 typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION 1688 { 1689 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1690 UCHAR ucReserved; 1691 USHORT usPwrBudget; //how much power currently boot to in unit of watt 1692 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 1693 }POWER_CONNECTOR_DETECTION_PS_ALLOCATION; 1694 1695 /****************************LVDS SS Command Table Definitions**********************/ 1696 1697 /****************************************************************************/ 1698 // Structures used by EnableSpreadSpectrumOnPPLLTable 1699 /****************************************************************************/ 1700 typedef struct _ENABLE_LVDS_SS_PARAMETERS 1701 { 1702 USHORT usSpreadSpectrumPercentage; 1703 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1704 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY 1705 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1706 UCHAR ucPadding[3]; 1707 }ENABLE_LVDS_SS_PARAMETERS; 1708 1709 //ucTableFormatRevision=1,ucTableContentRevision=2 1710 typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 1711 { 1712 USHORT usSpreadSpectrumPercentage; 1713 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1714 UCHAR ucSpreadSpectrumStep; // 1715 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1716 UCHAR ucSpreadSpectrumDelay; 1717 UCHAR ucSpreadSpectrumRange; 1718 UCHAR ucPadding; 1719 }ENABLE_LVDS_SS_PARAMETERS_V2; 1720 1721 //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. 1722 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL 1723 { 1724 USHORT usSpreadSpectrumPercentage; 1725 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1726 UCHAR ucSpreadSpectrumStep; // 1727 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1728 UCHAR ucSpreadSpectrumDelay; 1729 UCHAR ucSpreadSpectrumRange; 1730 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 1731 }ENABLE_SPREAD_SPECTRUM_ON_PPLL; 1732 1733 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 1734 { 1735 USHORT usSpreadSpectrumPercentage; 1736 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 1737 // Bit[1]: 1-Ext. 0-Int. 1738 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 1739 // Bits[7:4] reserved 1740 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1741 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 1742 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 1743 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; 1744 1745 #define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 1746 #define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 1747 #define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 1748 #define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c 1749 #define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 1750 #define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 1751 #define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 1752 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF 1753 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 1754 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 1755 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 1756 1757 // Used by DCE5.0 1758 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 1759 { 1760 USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 1761 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 1762 // Bit[1]: 1-Ext. 0-Int. 1763 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 1764 // Bits[7:4] reserved 1765 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1766 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 1767 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 1768 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; 1769 1770 #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 1771 #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 1772 #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 1773 #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c 1774 #define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00 1775 #define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04 1776 #define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08 1777 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF 1778 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0 1779 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00 1780 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8 1781 1782 #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL 1783 1784 /**************************************************************************/ 1785 1786 typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION 1787 { 1788 PIXEL_CLOCK_PARAMETERS sPCLKInput; 1789 ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion 1790 }SET_PIXEL_CLOCK_PS_ALLOCATION; 1791 1792 #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION 1793 1794 /****************************************************************************/ 1795 // Structures used by ### 1796 /****************************************************************************/ 1797 typedef struct _MEMORY_TRAINING_PARAMETERS 1798 { 1799 ULONG ulTargetMemoryClock; //In 10Khz unit 1800 }MEMORY_TRAINING_PARAMETERS; 1801 #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS 1802 1803 1804 /****************************LVDS and other encoder command table definitions **********************/ 1805 1806 1807 /****************************************************************************/ 1808 // Structures used by LVDSEncoderControlTable (Before DCE30) 1809 // LVTMAEncoderControlTable (Before DCE30) 1810 // TMDSAEncoderControlTable (Before DCE30) 1811 /****************************************************************************/ 1812 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS 1813 { 1814 USHORT usPixelClock; // in 10KHz; for bios convenient 1815 UCHAR ucMisc; // bit0=0: Enable single link 1816 // =1: Enable dual link 1817 // Bit1=0: 666RGB 1818 // =1: 888RGB 1819 UCHAR ucAction; // 0: turn off encoder 1820 // 1: setup and turn on encoder 1821 }LVDS_ENCODER_CONTROL_PARAMETERS; 1822 1823 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS 1824 1825 #define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS 1826 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS 1827 1828 #define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS 1829 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS 1830 1831 1832 //ucTableFormatRevision=1,ucTableContentRevision=2 1833 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 1834 { 1835 USHORT usPixelClock; // in 10KHz; for bios convenient 1836 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below 1837 UCHAR ucAction; // 0: turn off encoder 1838 // 1: setup and turn on encoder 1839 UCHAR ucTruncate; // bit0=0: Disable truncate 1840 // =1: Enable truncate 1841 // bit4=0: 666RGB 1842 // =1: 888RGB 1843 UCHAR ucSpatial; // bit0=0: Disable spatial dithering 1844 // =1: Enable spatial dithering 1845 // bit4=0: 666RGB 1846 // =1: 888RGB 1847 UCHAR ucTemporal; // bit0=0: Disable temporal dithering 1848 // =1: Enable temporal dithering 1849 // bit4=0: 666RGB 1850 // =1: 888RGB 1851 // bit5=0: Gray level 2 1852 // =1: Gray level 4 1853 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E 1854 // =1: 25FRC_SEL pattern F 1855 // bit6:5=0: 50FRC_SEL pattern A 1856 // =1: 50FRC_SEL pattern B 1857 // =2: 50FRC_SEL pattern C 1858 // =3: 50FRC_SEL pattern D 1859 // bit7=0: 75FRC_SEL pattern E 1860 // =1: 75FRC_SEL pattern F 1861 }LVDS_ENCODER_CONTROL_PARAMETERS_V2; 1862 1863 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 1864 1865 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 1866 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 1867 1868 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 1869 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 1870 1871 #define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 1872 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 1873 1874 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 1875 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 1876 1877 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 1878 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 1879 1880 /****************************************************************************/ 1881 // Structures used by ### 1882 /****************************************************************************/ 1883 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS 1884 { 1885 UCHAR ucEnable; // Enable or Disable External TMDS encoder 1886 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} 1887 UCHAR ucPadding[2]; 1888 }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; 1889 1890 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION 1891 { 1892 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; 1893 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 1894 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; 1895 1896 #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 1897 1898 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 1899 { 1900 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; 1901 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 1902 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; 1903 1904 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION 1905 { 1906 DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; 1907 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 1908 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; 1909 1910 /****************************************************************************/ 1911 // Structures used by DVOEncoderControlTable 1912 /****************************************************************************/ 1913 //ucTableFormatRevision=1,ucTableContentRevision=3 1914 1915 //ucDVOConfig: 1916 #define DVO_ENCODER_CONFIG_RATE_SEL 0x01 1917 #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 1918 #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 1919 #define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 1920 #define DVO_ENCODER_CONFIG_LOW12BIT 0x00 1921 #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 1922 #define DVO_ENCODER_CONFIG_24BIT 0x08 1923 1924 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 1925 { 1926 USHORT usPixelClock; 1927 UCHAR ucDVOConfig; 1928 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 1929 UCHAR ucReseved[4]; 1930 }DVO_ENCODER_CONTROL_PARAMETERS_V3; 1931 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 1932 1933 //ucTableFormatRevision=1 1934 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for 1935 // bit1=0: non-coherent mode 1936 // =1: coherent mode 1937 1938 //========================================================================================== 1939 //Only change is here next time when changing encoder parameter definitions again! 1940 #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 1941 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST 1942 1943 #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 1944 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST 1945 1946 #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 1947 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST 1948 1949 #define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS 1950 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION 1951 1952 //========================================================================================== 1953 #define PANEL_ENCODER_MISC_DUAL 0x01 1954 #define PANEL_ENCODER_MISC_COHERENT 0x02 1955 #define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 1956 #define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 1957 1958 #define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE 1959 #define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE 1960 #define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) 1961 1962 #define PANEL_ENCODER_TRUNCATE_EN 0x01 1963 #define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 1964 #define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 1965 #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 1966 #define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 1967 #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 1968 #define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 1969 #define PANEL_ENCODER_25FRC_MASK 0x10 1970 #define PANEL_ENCODER_25FRC_E 0x00 1971 #define PANEL_ENCODER_25FRC_F 0x10 1972 #define PANEL_ENCODER_50FRC_MASK 0x60 1973 #define PANEL_ENCODER_50FRC_A 0x00 1974 #define PANEL_ENCODER_50FRC_B 0x20 1975 #define PANEL_ENCODER_50FRC_C 0x40 1976 #define PANEL_ENCODER_50FRC_D 0x60 1977 #define PANEL_ENCODER_75FRC_MASK 0x80 1978 #define PANEL_ENCODER_75FRC_E 0x00 1979 #define PANEL_ENCODER_75FRC_F 0x80 1980 1981 /****************************************************************************/ 1982 // Structures used by SetVoltageTable 1983 /****************************************************************************/ 1984 #define SET_VOLTAGE_TYPE_ASIC_VDDC 1 1985 #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 1986 #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 1987 #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 1988 #define SET_VOLTAGE_INIT_MODE 5 1989 #define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic 1990 1991 #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 1992 #define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 1993 #define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 1994 1995 #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 1996 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 1997 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 1998 1999 typedef struct _SET_VOLTAGE_PARAMETERS 2000 { 2001 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2002 UCHAR ucVoltageMode; // To set all, to set source A or source B or ... 2003 UCHAR ucVoltageIndex; // An index to tell which voltage level 2004 UCHAR ucReserved; 2005 }SET_VOLTAGE_PARAMETERS; 2006 2007 typedef struct _SET_VOLTAGE_PARAMETERS_V2 2008 { 2009 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2010 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode 2011 USHORT usVoltageLevel; // real voltage level 2012 }SET_VOLTAGE_PARAMETERS_V2; 2013 2014 typedef struct _SET_VOLTAGE_PS_ALLOCATION 2015 { 2016 SET_VOLTAGE_PARAMETERS sASICSetVoltage; 2017 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2018 }SET_VOLTAGE_PS_ALLOCATION; 2019 2020 /****************************************************************************/ 2021 // Structures used by TVEncoderControlTable 2022 /****************************************************************************/ 2023 typedef struct _TV_ENCODER_CONTROL_PARAMETERS 2024 { 2025 USHORT usPixelClock; // in 10KHz; for bios convenient 2026 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." 2027 UCHAR ucAction; // 0: turn off encoder 2028 // 1: setup and turn on encoder 2029 }TV_ENCODER_CONTROL_PARAMETERS; 2030 2031 typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION 2032 { 2033 TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; 2034 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one 2035 }TV_ENCODER_CONTROL_PS_ALLOCATION; 2036 2037 //==============================Data Table Portion==================================== 2038 2039 /****************************************************************************/ 2040 // Structure used in Data.mtb 2041 /****************************************************************************/ 2042 typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES 2043 { 2044 USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! 2045 USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios 2046 USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios 2047 USHORT StandardVESA_Timing; // Only used by Bios 2048 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 2049 USHORT DAC_Info; // Will be obsolete from R600 2050 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info 2051 USHORT TMDS_Info; // Will be obsolete from R600 2052 USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 2053 USHORT SupportedDevicesInfo; // Will be obsolete from R600 2054 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 2055 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 2056 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 2057 USHORT VESA_ToInternalModeLUT; // Only used by Bios 2058 USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 2059 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 2060 USHORT CompassionateData; // Will be obsolete from R600 2061 USHORT SaveRestoreInfo; // Only used by Bios 2062 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info 2063 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon 2064 USHORT XTMDS_Info; // Will be obsolete from R600 2065 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used 2066 USHORT Object_Header; // Shared by various SW components,latest version 1.1 2067 USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! 2068 USHORT MC_InitParameter; // Only used by command table 2069 USHORT ASIC_VDDC_Info; // Will be obsolete from R600 2070 USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" 2071 USHORT TV_VideoMode; // Only used by command table 2072 USHORT VRAM_Info; // Only used by command table, latest version 1.3 2073 USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 2074 USHORT IntegratedSystemInfo; // Shared by various SW components 2075 USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 2076 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 2077 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 2078 }ATOM_MASTER_LIST_OF_DATA_TABLES; 2079 2080 // For backward compatible 2081 #define LVDS_Info LCD_Info 2082 2083 typedef struct _ATOM_MASTER_DATA_TABLE 2084 { 2085 ATOM_COMMON_TABLE_HEADER sHeader; 2086 ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; 2087 }ATOM_MASTER_DATA_TABLE; 2088 2089 2090 /****************************************************************************/ 2091 // Structure used in MultimediaCapabilityInfoTable 2092 /****************************************************************************/ 2093 typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO 2094 { 2095 ATOM_COMMON_TABLE_HEADER sHeader; 2096 ULONG ulSignature; // HW info table signature string "$ATI" 2097 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) 2098 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) 2099 UCHAR ucVideoPortInfo; // Provides the video port capabilities 2100 UCHAR ucHostPortInfo; // Provides host port configuration information 2101 }ATOM_MULTIMEDIA_CAPABILITY_INFO; 2102 2103 /****************************************************************************/ 2104 // Structure used in MultimediaConfigInfoTable 2105 /****************************************************************************/ 2106 typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO 2107 { 2108 ATOM_COMMON_TABLE_HEADER sHeader; 2109 ULONG ulSignature; // MM info table signature sting "$MMT" 2110 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) 2111 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) 2112 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting 2113 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) 2114 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) 2115 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) 2116 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) 2117 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2118 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2119 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2120 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2121 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2122 }ATOM_MULTIMEDIA_CONFIG_INFO; 2123 2124 2125 /****************************************************************************/ 2126 // Structures used in FirmwareInfoTable 2127 /****************************************************************************/ 2128 2129 // usBIOSCapability Definition: 2130 // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; 2131 // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; 2132 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; 2133 // Others: Reserved 2134 #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 2135 #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 2136 #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 2137 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. 2138 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. 2139 #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 2140 #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 2141 #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 2142 #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 2143 #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 2144 #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 2145 #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 2146 #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip 2147 #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip 2148 2149 #ifndef _H2INC 2150 2151 //Please don't add or expand this bitfield structure below, this one will retire soon.! 2152 typedef struct _ATOM_FIRMWARE_CAPABILITY 2153 { 2154 #if ATOM_BIG_ENDIAN 2155 USHORT Reserved:3; 2156 USHORT HyperMemory_Size:4; 2157 USHORT HyperMemory_Support:1; 2158 USHORT PPMode_Assigned:1; 2159 USHORT WMI_SUPPORT:1; 2160 USHORT GPUControlsBL:1; 2161 USHORT EngineClockSS_Support:1; 2162 USHORT MemoryClockSS_Support:1; 2163 USHORT ExtendedDesktopSupport:1; 2164 USHORT DualCRTC_Support:1; 2165 USHORT FirmwarePosted:1; 2166 #else 2167 USHORT FirmwarePosted:1; 2168 USHORT DualCRTC_Support:1; 2169 USHORT ExtendedDesktopSupport:1; 2170 USHORT MemoryClockSS_Support:1; 2171 USHORT EngineClockSS_Support:1; 2172 USHORT GPUControlsBL:1; 2173 USHORT WMI_SUPPORT:1; 2174 USHORT PPMode_Assigned:1; 2175 USHORT HyperMemory_Support:1; 2176 USHORT HyperMemory_Size:4; 2177 USHORT Reserved:3; 2178 #endif 2179 }ATOM_FIRMWARE_CAPABILITY; 2180 2181 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2182 { 2183 ATOM_FIRMWARE_CAPABILITY sbfAccess; 2184 USHORT susAccess; 2185 }ATOM_FIRMWARE_CAPABILITY_ACCESS; 2186 2187 #else 2188 2189 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2190 { 2191 USHORT susAccess; 2192 }ATOM_FIRMWARE_CAPABILITY_ACCESS; 2193 2194 #endif 2195 2196 typedef struct _ATOM_FIRMWARE_INFO 2197 { 2198 ATOM_COMMON_TABLE_HEADER sHeader; 2199 ULONG ulFirmwareRevision; 2200 ULONG ulDefaultEngineClock; //In 10Khz unit 2201 ULONG ulDefaultMemoryClock; //In 10Khz unit 2202 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2203 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2204 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2205 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2206 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2207 ULONG ulASICMaxEngineClock; //In 10Khz unit 2208 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2209 UCHAR ucASICMaxTemperature; 2210 UCHAR ucPadding[3]; //Don't use them 2211 ULONG aulReservedForBIOS[3]; //Don't use them 2212 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2213 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2214 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2215 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2216 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2217 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2218 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2219 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2220 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2221 USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! 2222 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2223 USHORT usReferenceClock; //In 10Khz unit 2224 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2225 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2226 UCHAR ucDesign_ID; //Indicate what is the board design 2227 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2228 }ATOM_FIRMWARE_INFO; 2229 2230 typedef struct _ATOM_FIRMWARE_INFO_V1_2 2231 { 2232 ATOM_COMMON_TABLE_HEADER sHeader; 2233 ULONG ulFirmwareRevision; 2234 ULONG ulDefaultEngineClock; //In 10Khz unit 2235 ULONG ulDefaultMemoryClock; //In 10Khz unit 2236 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2237 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2238 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2239 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2240 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2241 ULONG ulASICMaxEngineClock; //In 10Khz unit 2242 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2243 UCHAR ucASICMaxTemperature; 2244 UCHAR ucMinAllowedBL_Level; 2245 UCHAR ucPadding[2]; //Don't use them 2246 ULONG aulReservedForBIOS[2]; //Don't use them 2247 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2248 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2249 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2250 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2251 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2252 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2253 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2254 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2255 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2256 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2257 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2258 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2259 USHORT usReferenceClock; //In 10Khz unit 2260 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2261 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2262 UCHAR ucDesign_ID; //Indicate what is the board design 2263 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2264 }ATOM_FIRMWARE_INFO_V1_2; 2265 2266 typedef struct _ATOM_FIRMWARE_INFO_V1_3 2267 { 2268 ATOM_COMMON_TABLE_HEADER sHeader; 2269 ULONG ulFirmwareRevision; 2270 ULONG ulDefaultEngineClock; //In 10Khz unit 2271 ULONG ulDefaultMemoryClock; //In 10Khz unit 2272 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2273 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2274 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2275 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2276 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2277 ULONG ulASICMaxEngineClock; //In 10Khz unit 2278 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2279 UCHAR ucASICMaxTemperature; 2280 UCHAR ucMinAllowedBL_Level; 2281 UCHAR ucPadding[2]; //Don't use them 2282 ULONG aulReservedForBIOS; //Don't use them 2283 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 2284 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2285 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2286 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2287 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2288 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2289 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2290 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2291 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2292 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2293 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2294 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2295 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2296 USHORT usReferenceClock; //In 10Khz unit 2297 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2298 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2299 UCHAR ucDesign_ID; //Indicate what is the board design 2300 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2301 }ATOM_FIRMWARE_INFO_V1_3; 2302 2303 typedef struct _ATOM_FIRMWARE_INFO_V1_4 2304 { 2305 ATOM_COMMON_TABLE_HEADER sHeader; 2306 ULONG ulFirmwareRevision; 2307 ULONG ulDefaultEngineClock; //In 10Khz unit 2308 ULONG ulDefaultMemoryClock; //In 10Khz unit 2309 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2310 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2311 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2312 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2313 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2314 ULONG ulASICMaxEngineClock; //In 10Khz unit 2315 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2316 UCHAR ucASICMaxTemperature; 2317 UCHAR ucMinAllowedBL_Level; 2318 USHORT usBootUpVDDCVoltage; //In MV unit 2319 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2320 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2321 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 2322 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2323 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2324 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2325 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2326 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2327 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2328 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2329 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2330 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2331 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2332 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2333 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2334 USHORT usReferenceClock; //In 10Khz unit 2335 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2336 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2337 UCHAR ucDesign_ID; //Indicate what is the board design 2338 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2339 }ATOM_FIRMWARE_INFO_V1_4; 2340 2341 //the structure below to be used from Cypress 2342 typedef struct _ATOM_FIRMWARE_INFO_V2_1 2343 { 2344 ATOM_COMMON_TABLE_HEADER sHeader; 2345 ULONG ulFirmwareRevision; 2346 ULONG ulDefaultEngineClock; //In 10Khz unit 2347 ULONG ulDefaultMemoryClock; //In 10Khz unit 2348 ULONG ulReserved1; 2349 ULONG ulReserved2; 2350 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2351 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2352 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2353 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock 2354 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit 2355 UCHAR ucReserved1; //Was ucASICMaxTemperature; 2356 UCHAR ucMinAllowedBL_Level; 2357 USHORT usBootUpVDDCVoltage; //In MV unit 2358 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2359 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2360 ULONG ulReserved4; //Was ulAsicMaximumVoltage 2361 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2362 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2363 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2364 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2365 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2366 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2367 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2368 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2369 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2370 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2371 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2372 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2373 USHORT usCoreReferenceClock; //In 10Khz unit 2374 USHORT usMemoryReferenceClock; //In 10Khz unit 2375 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 2376 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2377 UCHAR ucReserved4[3]; 2378 }ATOM_FIRMWARE_INFO_V2_1; 2379 2380 //the structure below to be used from NI 2381 //ucTableFormatRevision=2 2382 //ucTableContentRevision=2 2383 typedef struct _ATOM_FIRMWARE_INFO_V2_2 2384 { 2385 ATOM_COMMON_TABLE_HEADER sHeader; 2386 ULONG ulFirmwareRevision; 2387 ULONG ulDefaultEngineClock; //In 10Khz unit 2388 ULONG ulDefaultMemoryClock; //In 10Khz unit 2389 ULONG ulReserved[2]; 2390 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* 2391 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* 2392 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2393 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? 2394 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. 2395 UCHAR ucReserved3; //Was ucASICMaxTemperature; 2396 UCHAR ucMinAllowedBL_Level; 2397 USHORT usBootUpVDDCVoltage; //In MV unit 2398 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2399 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2400 ULONG ulReserved4; //Was ulAsicMaximumVoltage 2401 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2402 ULONG ulReserved5; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input 2403 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input 2404 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output 2405 USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC 2406 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2407 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2408 USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 2409 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2410 USHORT usCoreReferenceClock; //In 10Khz unit 2411 USHORT usMemoryReferenceClock; //In 10Khz unit 2412 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 2413 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2414 UCHAR ucReserved9[3]; 2415 USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 2416 USHORT usReserved12; 2417 ULONG ulReserved10[3]; // New added comparing to previous version 2418 }ATOM_FIRMWARE_INFO_V2_2; 2419 2420 #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2 2421 2422 /****************************************************************************/ 2423 // Structures used in IntegratedSystemInfoTable 2424 /****************************************************************************/ 2425 #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 2426 #define IGP_CAP_FLAG_AC_CARD 0x4 2427 #define IGP_CAP_FLAG_SDVO_CARD 0x8 2428 #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 2429 2430 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO 2431 { 2432 ATOM_COMMON_TABLE_HEADER sHeader; 2433 ULONG ulBootUpEngineClock; //in 10kHz unit 2434 ULONG ulBootUpMemoryClock; //in 10kHz unit 2435 ULONG ulMaxSystemMemoryClock; //in 10kHz unit 2436 ULONG ulMinSystemMemoryClock; //in 10kHz unit 2437 UCHAR ucNumberOfCyclesInPeriodHi; 2438 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. 2439 USHORT usReserved1; 2440 USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage 2441 USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage 2442 ULONG ulReserved[2]; 2443 2444 USHORT usFSBClock; //In MHz unit 2445 USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable 2446 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card 2447 //Bit[4]==1: P/2 mode, ==0: P/1 mode 2448 USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal 2449 USHORT usK8MemoryClock; //in MHz unit 2450 USHORT usK8SyncStartDelay; //in 0.01 us unit 2451 USHORT usK8DataReturnTime; //in 0.01 us unit 2452 UCHAR ucMaxNBVoltage; 2453 UCHAR ucMinNBVoltage; 2454 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved 2455 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod 2456 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime 2457 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit 2458 UCHAR ucMaxNBVoltageHigh; 2459 UCHAR ucMinNBVoltageHigh; 2460 }ATOM_INTEGRATED_SYSTEM_INFO; 2461 2462 /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO 2463 ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock 2464 For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock 2465 ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2466 For AMD IGP,for now this can be 0 2467 ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2468 For AMD IGP,for now this can be 0 2469 2470 usFSBClock: For Intel IGP,it's FSB Freq 2471 For AMD IGP,it's HT Link Speed 2472 2473 usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 2474 usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2475 usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2476 2477 VC:Voltage Control 2478 ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2479 ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2480 2481 ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. 2482 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 2483 2484 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2485 ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2486 2487 2488 usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. 2489 usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. 2490 */ 2491 2492 2493 /* 2494 The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; 2495 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. 2496 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. 2497 2498 SW components can access the IGP system infor structure in the same way as before 2499 */ 2500 2501 2502 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 2503 { 2504 ATOM_COMMON_TABLE_HEADER sHeader; 2505 ULONG ulBootUpEngineClock; //in 10kHz unit 2506 ULONG ulReserved1[2]; //must be 0x0 for the reserved 2507 ULONG ulBootUpUMAClock; //in 10kHz unit 2508 ULONG ulBootUpSidePortClock; //in 10kHz unit 2509 ULONG ulMinSidePortClock; //in 10kHz unit 2510 ULONG ulReserved2[6]; //must be 0x0 for the reserved 2511 ULONG ulSystemConfig; //see explanation below 2512 ULONG ulBootUpReqDisplayVector; 2513 ULONG ulOtherDisplayMisc; 2514 ULONG ulDDISlot1Config; 2515 ULONG ulDDISlot2Config; 2516 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 2517 UCHAR ucUMAChannelNumber; 2518 UCHAR ucDockingPinBit; 2519 UCHAR ucDockingPinPolarity; 2520 ULONG ulDockingPinCFGInfo; 2521 ULONG ulCPUCapInfo; 2522 USHORT usNumberOfCyclesInPeriod; 2523 USHORT usMaxNBVoltage; 2524 USHORT usMinNBVoltage; 2525 USHORT usBootUpNBVoltage; 2526 ULONG ulHTLinkFreq; //in 10Khz 2527 USHORT usMinHTLinkWidth; 2528 USHORT usMaxHTLinkWidth; 2529 USHORT usUMASyncStartDelay; 2530 USHORT usUMADataReturnTime; 2531 USHORT usLinkStatusZeroTime; 2532 USHORT usDACEfuse; //for storing badgap value (for RS880 only) 2533 ULONG ulHighVoltageHTLinkFreq; // in 10Khz 2534 ULONG ulLowVoltageHTLinkFreq; // in 10Khz 2535 USHORT usMaxUpStreamHTLinkWidth; 2536 USHORT usMaxDownStreamHTLinkWidth; 2537 USHORT usMinUpStreamHTLinkWidth; 2538 USHORT usMinDownStreamHTLinkWidth; 2539 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. 2540 USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. 2541 ULONG ulReserved3[96]; //must be 0x0 2542 }ATOM_INTEGRATED_SYSTEM_INFO_V2; 2543 2544 /* 2545 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; 2546 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present 2547 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock 2548 2549 ulSystemConfig: 2550 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; 2551 Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state 2552 =0: system boots up at driver control state. Power state depends on PowerPlay table. 2553 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. 2554 Bit[3]=1: Only one power state(Performance) will be supported. 2555 =0: Multiple power states supported from PowerPlay table. 2556 Bit[4]=1: CLMC is supported and enabled on current system. 2557 =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. 2558 Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. 2559 =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. 2560 Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. 2561 =0: Voltage settings is determined by powerplay table. 2562 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. 2563 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. 2564 Bit[8]=1: CDLF is supported and enabled on current system. 2565 =0: CDLF is not supported or enabled on current system. 2566 Bit[9]=1: DLL Shut Down feature is enabled on current system. 2567 =0: DLL Shut Down feature is not enabled or supported on current system. 2568 2569 ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. 2570 2571 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; 2572 [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition; 2573 2574 ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). 2575 [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) 2576 [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) 2577 When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. 2578 in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: 2579 one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. 2580 2581 [15:8] - Lane configuration attribute; 2582 [23:16]- Connector type, possible value: 2583 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 2584 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 2585 CONNECTOR_OBJECT_ID_HDMI_TYPE_A 2586 CONNECTOR_OBJECT_ID_DISPLAYPORT 2587 CONNECTOR_OBJECT_ID_eDP 2588 [31:24]- Reserved 2589 2590 ulDDISlot2Config: Same as Slot1. 2591 ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. 2592 For IGP, Hypermemory is the only memory type showed in CCC. 2593 2594 ucUMAChannelNumber: how many channels for the UMA; 2595 2596 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin 2597 ucDockingPinBit: which bit in this register to read the pin status; 2598 ucDockingPinPolarity:Polarity of the pin when docked; 2599 2600 ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0 2601 2602 usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. 2603 2604 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. 2605 usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. 2606 GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 2607 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 2608 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 2609 2610 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. 2611 2612 ulHTLinkFreq: Bootup HT link Frequency in 10Khz. 2613 usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. 2614 If CDLW enabled, both upstream and downstream width should be the same during bootup. 2615 usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. 2616 If CDLW enabled, both upstream and downstream width should be the same during bootup. 2617 2618 usUMASyncStartDelay: Memory access latency, required for watermark calculation 2619 usUMADataReturnTime: Memory access latency, required for watermark calculation 2620 usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us 2621 for Griffin or Greyhound. SBIOS needs to convert to actual time by: 2622 if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) 2623 if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) 2624 if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) 2625 if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) 2626 2627 ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. 2628 This must be less than or equal to ulHTLinkFreq(bootup frequency). 2629 ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. 2630 This must be less than or equal to ulHighVoltageHTLinkFreq. 2631 2632 usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. 2633 usMaxDownStreamHTLinkWidth: same as above. 2634 usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. 2635 usMinDownStreamHTLinkWidth: same as above. 2636 */ 2637 2638 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition 2639 #define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 2640 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 2641 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 2642 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3 2643 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4 2644 2645 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH // this deff reflects max defined CPU code 2646 2647 #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 2648 #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 2649 #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 2650 #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 2651 #define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 2652 #define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 2653 #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 2654 #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 2655 #define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 2656 #define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 2657 2658 #define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF 2659 2660 #define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F 2661 #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 2662 #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 2663 #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 2664 #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 2665 #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 2666 2667 #define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 2668 #define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 2669 #define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 2670 2671 #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 2672 2673 // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR 2674 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 2675 { 2676 ATOM_COMMON_TABLE_HEADER sHeader; 2677 ULONG ulBootUpEngineClock; //in 10kHz unit 2678 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. 2679 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge 2680 ULONG ulBootUpUMAClock; //in 10kHz unit 2681 ULONG ulReserved1[8]; //must be 0x0 for the reserved 2682 ULONG ulBootUpReqDisplayVector; 2683 ULONG ulOtherDisplayMisc; 2684 ULONG ulReserved2[4]; //must be 0x0 for the reserved 2685 ULONG ulSystemConfig; //TBD 2686 ULONG ulCPUCapInfo; //TBD 2687 USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 2688 USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 2689 USHORT usBootUpNBVoltage; //boot up NB voltage 2690 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD 2691 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD 2692 ULONG ulReserved3[4]; //must be 0x0 for the reserved 2693 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition 2694 ULONG ulDDISlot2Config; 2695 ULONG ulDDISlot3Config; 2696 ULONG ulDDISlot4Config; 2697 ULONG ulReserved4[4]; //must be 0x0 for the reserved 2698 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 2699 UCHAR ucUMAChannelNumber; 2700 USHORT usReserved; 2701 ULONG ulReserved5[4]; //must be 0x0 for the reserved 2702 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default 2703 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback 2704 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications 2705 ULONG ulReserved6[61]; //must be 0x0 2706 }ATOM_INTEGRATED_SYSTEM_INFO_V5; 2707 2708 #define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 2709 #define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 2710 #define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 2711 #define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 2712 #define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 2713 #define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 2714 #define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 2715 #define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 2716 #define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 2717 #define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 2718 #define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A 2719 #define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B 2720 #define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C 2721 #define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D 2722 2723 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable 2724 #define ASIC_INT_DAC1_ENCODER_ID 0x00 2725 #define ASIC_INT_TV_ENCODER_ID 0x02 2726 #define ASIC_INT_DIG1_ENCODER_ID 0x03 2727 #define ASIC_INT_DAC2_ENCODER_ID 0x04 2728 #define ASIC_EXT_TV_ENCODER_ID 0x06 2729 #define ASIC_INT_DVO_ENCODER_ID 0x07 2730 #define ASIC_INT_DIG2_ENCODER_ID 0x09 2731 #define ASIC_EXT_DIG_ENCODER_ID 0x05 2732 #define ASIC_EXT_DIG2_ENCODER_ID 0x08 2733 #define ASIC_INT_DIG3_ENCODER_ID 0x0a 2734 #define ASIC_INT_DIG4_ENCODER_ID 0x0b 2735 #define ASIC_INT_DIG5_ENCODER_ID 0x0c 2736 #define ASIC_INT_DIG6_ENCODER_ID 0x0d 2737 2738 //define Encoder attribute 2739 #define ATOM_ANALOG_ENCODER 0 2740 #define ATOM_DIGITAL_ENCODER 1 2741 #define ATOM_DP_ENCODER 2 2742 2743 #define ATOM_ENCODER_ENUM_MASK 0x70 2744 #define ATOM_ENCODER_ENUM_ID1 0x00 2745 #define ATOM_ENCODER_ENUM_ID2 0x10 2746 #define ATOM_ENCODER_ENUM_ID3 0x20 2747 #define ATOM_ENCODER_ENUM_ID4 0x30 2748 #define ATOM_ENCODER_ENUM_ID5 0x40 2749 #define ATOM_ENCODER_ENUM_ID6 0x50 2750 2751 #define ATOM_DEVICE_CRT1_INDEX 0x00000000 2752 #define ATOM_DEVICE_LCD1_INDEX 0x00000001 2753 #define ATOM_DEVICE_TV1_INDEX 0x00000002 2754 #define ATOM_DEVICE_DFP1_INDEX 0x00000003 2755 #define ATOM_DEVICE_CRT2_INDEX 0x00000004 2756 #define ATOM_DEVICE_LCD2_INDEX 0x00000005 2757 #define ATOM_DEVICE_DFP6_INDEX 0x00000006 2758 #define ATOM_DEVICE_DFP2_INDEX 0x00000007 2759 #define ATOM_DEVICE_CV_INDEX 0x00000008 2760 #define ATOM_DEVICE_DFP3_INDEX 0x00000009 2761 #define ATOM_DEVICE_DFP4_INDEX 0x0000000A 2762 #define ATOM_DEVICE_DFP5_INDEX 0x0000000B 2763 2764 #define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C 2765 #define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D 2766 #define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E 2767 #define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F 2768 #define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) 2769 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO 2770 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) 2771 2772 #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) 2773 2774 #define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) 2775 #define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) 2776 #define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) 2777 #define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) 2778 #define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) 2779 #define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) 2780 #define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) 2781 #define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) 2782 #define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) 2783 #define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) 2784 #define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) 2785 #define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) 2786 2787 #define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) 2788 #define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) 2789 #define ATOM_DEVICE_TV_SUPPORT (ATOM_DEVICE_TV1_SUPPORT) 2790 #define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) 2791 2792 #define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 2793 #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 2794 #define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 2795 #define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 2796 #define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 2797 #define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 2798 #define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 2799 #define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 2800 #define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 2801 #define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 2802 #define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 2803 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A 2804 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B 2805 #define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E 2806 #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F 2807 2808 2809 #define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F 2810 #define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 2811 #define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 2812 #define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 2813 #define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 2814 #define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 2815 2816 #define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 2817 2818 #define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F 2819 #define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 2820 2821 #define ATOM_DEVICE_I2C_ID_MASK 0x00000070 2822 #define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 2823 #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 2824 #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 2825 #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 2826 #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 2827 2828 #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 2829 #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 2830 #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 2831 #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 2832 2833 // usDeviceSupport: 2834 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported 2835 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported 2836 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported 2837 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported 2838 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported 2839 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported 2840 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported 2841 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported 2842 // Bit 8 = 0 - no CV support= 1- CV is supported 2843 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported 2844 // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported 2845 // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported 2846 // 2847 // 2848 2849 /****************************************************************************/ 2850 /* Structure used in MclkSS_InfoTable */ 2851 /****************************************************************************/ 2852 // ucI2C_ConfigID 2853 // [7:0] - I2C LINE Associate ID 2854 // = 0 - no I2C 2855 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) 2856 // = 0, [6:0]=SW assisted I2C ID 2857 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use 2858 // = 2, HW engine for Multimedia use 2859 // = 3-7 Reserved for future I2C engines 2860 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C 2861 2862 typedef struct _ATOM_I2C_ID_CONFIG 2863 { 2864 #if ATOM_BIG_ENDIAN 2865 UCHAR bfHW_Capable:1; 2866 UCHAR bfHW_EngineID:3; 2867 UCHAR bfI2C_LineMux:4; 2868 #else 2869 UCHAR bfI2C_LineMux:4; 2870 UCHAR bfHW_EngineID:3; 2871 UCHAR bfHW_Capable:1; 2872 #endif 2873 }ATOM_I2C_ID_CONFIG; 2874 2875 typedef union _ATOM_I2C_ID_CONFIG_ACCESS 2876 { 2877 ATOM_I2C_ID_CONFIG sbfAccess; 2878 UCHAR ucAccess; 2879 }ATOM_I2C_ID_CONFIG_ACCESS; 2880 2881 2882 /****************************************************************************/ 2883 // Structure used in GPIO_I2C_InfoTable 2884 /****************************************************************************/ 2885 typedef struct _ATOM_GPIO_I2C_ASSIGMENT 2886 { 2887 USHORT usClkMaskRegisterIndex; 2888 USHORT usClkEnRegisterIndex; 2889 USHORT usClkY_RegisterIndex; 2890 USHORT usClkA_RegisterIndex; 2891 USHORT usDataMaskRegisterIndex; 2892 USHORT usDataEnRegisterIndex; 2893 USHORT usDataY_RegisterIndex; 2894 USHORT usDataA_RegisterIndex; 2895 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 2896 UCHAR ucClkMaskShift; 2897 UCHAR ucClkEnShift; 2898 UCHAR ucClkY_Shift; 2899 UCHAR ucClkA_Shift; 2900 UCHAR ucDataMaskShift; 2901 UCHAR ucDataEnShift; 2902 UCHAR ucDataY_Shift; 2903 UCHAR ucDataA_Shift; 2904 UCHAR ucReserved1; 2905 UCHAR ucReserved2; 2906 }ATOM_GPIO_I2C_ASSIGMENT; 2907 2908 typedef struct _ATOM_GPIO_I2C_INFO 2909 { 2910 ATOM_COMMON_TABLE_HEADER sHeader; 2911 ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; 2912 }ATOM_GPIO_I2C_INFO; 2913 2914 /****************************************************************************/ 2915 // Common Structure used in other structures 2916 /****************************************************************************/ 2917 2918 #ifndef _H2INC 2919 2920 //Please don't add or expand this bitfield structure below, this one will retire soon.! 2921 typedef struct _ATOM_MODE_MISC_INFO 2922 { 2923 #if ATOM_BIG_ENDIAN 2924 USHORT Reserved:6; 2925 USHORT RGB888:1; 2926 USHORT DoubleClock:1; 2927 USHORT Interlace:1; 2928 USHORT CompositeSync:1; 2929 USHORT V_ReplicationBy2:1; 2930 USHORT H_ReplicationBy2:1; 2931 USHORT VerticalCutOff:1; 2932 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 2933 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 2934 USHORT HorizontalCutOff:1; 2935 #else 2936 USHORT HorizontalCutOff:1; 2937 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 2938 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 2939 USHORT VerticalCutOff:1; 2940 USHORT H_ReplicationBy2:1; 2941 USHORT V_ReplicationBy2:1; 2942 USHORT CompositeSync:1; 2943 USHORT Interlace:1; 2944 USHORT DoubleClock:1; 2945 USHORT RGB888:1; 2946 USHORT Reserved:6; 2947 #endif 2948 }ATOM_MODE_MISC_INFO; 2949 2950 typedef union _ATOM_MODE_MISC_INFO_ACCESS 2951 { 2952 ATOM_MODE_MISC_INFO sbfAccess; 2953 USHORT usAccess; 2954 }ATOM_MODE_MISC_INFO_ACCESS; 2955 2956 #else 2957 2958 typedef union _ATOM_MODE_MISC_INFO_ACCESS 2959 { 2960 USHORT usAccess; 2961 }ATOM_MODE_MISC_INFO_ACCESS; 2962 2963 #endif 2964 2965 // usModeMiscInfo- 2966 #define ATOM_H_CUTOFF 0x01 2967 #define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low 2968 #define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low 2969 #define ATOM_V_CUTOFF 0x08 2970 #define ATOM_H_REPLICATIONBY2 0x10 2971 #define ATOM_V_REPLICATIONBY2 0x20 2972 #define ATOM_COMPOSITESYNC 0x40 2973 #define ATOM_INTERLACE 0x80 2974 #define ATOM_DOUBLE_CLOCK_MODE 0x100 2975 #define ATOM_RGB888_MODE 0x200 2976 2977 //usRefreshRate- 2978 #define ATOM_REFRESH_43 43 2979 #define ATOM_REFRESH_47 47 2980 #define ATOM_REFRESH_56 56 2981 #define ATOM_REFRESH_60 60 2982 #define ATOM_REFRESH_65 65 2983 #define ATOM_REFRESH_70 70 2984 #define ATOM_REFRESH_72 72 2985 #define ATOM_REFRESH_75 75 2986 #define ATOM_REFRESH_85 85 2987 2988 // ATOM_MODE_TIMING data are exactly the same as VESA timing data. 2989 // Translation from EDID to ATOM_MODE_TIMING, use the following formula. 2990 // 2991 // VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK 2992 // = EDID_HA + EDID_HBL 2993 // VESA_HDISP = VESA_ACTIVE = EDID_HA 2994 // VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH 2995 // = EDID_HA + EDID_HSO 2996 // VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW 2997 // VESA_BORDER = EDID_BORDER 2998 2999 /****************************************************************************/ 3000 // Structure used in SetCRTC_UsingDTDTimingTable 3001 /****************************************************************************/ 3002 typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS 3003 { 3004 USHORT usH_Size; 3005 USHORT usH_Blanking_Time; 3006 USHORT usV_Size; 3007 USHORT usV_Blanking_Time; 3008 USHORT usH_SyncOffset; 3009 USHORT usH_SyncWidth; 3010 USHORT usV_SyncOffset; 3011 USHORT usV_SyncWidth; 3012 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3013 UCHAR ucH_Border; // From DFP EDID 3014 UCHAR ucV_Border; 3015 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3016 UCHAR ucPadding[3]; 3017 }SET_CRTC_USING_DTD_TIMING_PARAMETERS; 3018 3019 /****************************************************************************/ 3020 // Structure used in SetCRTC_TimingTable 3021 /****************************************************************************/ 3022 typedef struct _SET_CRTC_TIMING_PARAMETERS 3023 { 3024 USHORT usH_Total; // horizontal total 3025 USHORT usH_Disp; // horizontal display 3026 USHORT usH_SyncStart; // horozontal Sync start 3027 USHORT usH_SyncWidth; // horizontal Sync width 3028 USHORT usV_Total; // vertical total 3029 USHORT usV_Disp; // vertical display 3030 USHORT usV_SyncStart; // vertical Sync start 3031 USHORT usV_SyncWidth; // vertical Sync width 3032 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3033 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3034 UCHAR ucOverscanRight; // right 3035 UCHAR ucOverscanLeft; // left 3036 UCHAR ucOverscanBottom; // bottom 3037 UCHAR ucOverscanTop; // top 3038 UCHAR ucReserved; 3039 }SET_CRTC_TIMING_PARAMETERS; 3040 #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS 3041 3042 /****************************************************************************/ 3043 // Structure used in StandardVESA_TimingTable 3044 // AnalogTV_InfoTable 3045 // ComponentVideoInfoTable 3046 /****************************************************************************/ 3047 typedef struct _ATOM_MODE_TIMING 3048 { 3049 USHORT usCRTC_H_Total; 3050 USHORT usCRTC_H_Disp; 3051 USHORT usCRTC_H_SyncStart; 3052 USHORT usCRTC_H_SyncWidth; 3053 USHORT usCRTC_V_Total; 3054 USHORT usCRTC_V_Disp; 3055 USHORT usCRTC_V_SyncStart; 3056 USHORT usCRTC_V_SyncWidth; 3057 USHORT usPixelClock; //in 10Khz unit 3058 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3059 USHORT usCRTC_OverscanRight; 3060 USHORT usCRTC_OverscanLeft; 3061 USHORT usCRTC_OverscanBottom; 3062 USHORT usCRTC_OverscanTop; 3063 USHORT usReserve; 3064 UCHAR ucInternalModeNumber; 3065 UCHAR ucRefreshRate; 3066 }ATOM_MODE_TIMING; 3067 3068 typedef struct _ATOM_DTD_FORMAT 3069 { 3070 USHORT usPixClk; 3071 USHORT usHActive; 3072 USHORT usHBlanking_Time; 3073 USHORT usVActive; 3074 USHORT usVBlanking_Time; 3075 USHORT usHSyncOffset; 3076 USHORT usHSyncWidth; 3077 USHORT usVSyncOffset; 3078 USHORT usVSyncWidth; 3079 USHORT usImageHSize; 3080 USHORT usImageVSize; 3081 UCHAR ucHBorder; 3082 UCHAR ucVBorder; 3083 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3084 UCHAR ucInternalModeNumber; 3085 UCHAR ucRefreshRate; 3086 }ATOM_DTD_FORMAT; 3087 3088 /****************************************************************************/ 3089 // Structure used in LVDS_InfoTable 3090 // * Need a document to describe this table 3091 /****************************************************************************/ 3092 #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 3093 #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 3094 #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 3095 #define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 3096 3097 //ucTableFormatRevision=1 3098 //ucTableContentRevision=1 3099 typedef struct _ATOM_LVDS_INFO 3100 { 3101 ATOM_COMMON_TABLE_HEADER sHeader; 3102 ATOM_DTD_FORMAT sLCDTiming; 3103 USHORT usModePatchTableOffset; 3104 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3105 USHORT usOffDelayInMs; 3106 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3107 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3108 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3109 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3110 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3111 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3112 UCHAR ucPanelDefaultRefreshRate; 3113 UCHAR ucPanelIdentification; 3114 UCHAR ucSS_Id; 3115 }ATOM_LVDS_INFO; 3116 3117 //ucTableFormatRevision=1 3118 //ucTableContentRevision=2 3119 typedef struct _ATOM_LVDS_INFO_V12 3120 { 3121 ATOM_COMMON_TABLE_HEADER sHeader; 3122 ATOM_DTD_FORMAT sLCDTiming; 3123 USHORT usExtInfoTableOffset; 3124 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3125 USHORT usOffDelayInMs; 3126 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3127 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3128 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3129 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3130 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3131 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3132 UCHAR ucPanelDefaultRefreshRate; 3133 UCHAR ucPanelIdentification; 3134 UCHAR ucSS_Id; 3135 USHORT usLCDVenderID; 3136 USHORT usLCDProductID; 3137 UCHAR ucLCDPanel_SpecialHandlingCap; 3138 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3139 UCHAR ucReserved[2]; 3140 }ATOM_LVDS_INFO_V12; 3141 3142 //Definitions for ucLCDPanel_SpecialHandlingCap: 3143 3144 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3145 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3146 #define LCDPANEL_CAP_READ_EDID 0x1 3147 3148 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3149 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3150 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3151 #define LCDPANEL_CAP_DRR_SUPPORTED 0x2 3152 3153 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3154 #define LCDPANEL_CAP_eDP 0x4 3155 3156 3157 //Color Bit Depth definition in EDID V1.4 @BYTE 14h 3158 //Bit 6 5 4 3159 // 0 0 0 - Color bit depth is undefined 3160 // 0 0 1 - 6 Bits per Primary Color 3161 // 0 1 0 - 8 Bits per Primary Color 3162 // 0 1 1 - 10 Bits per Primary Color 3163 // 1 0 0 - 12 Bits per Primary Color 3164 // 1 0 1 - 14 Bits per Primary Color 3165 // 1 1 0 - 16 Bits per Primary Color 3166 // 1 1 1 - Reserved 3167 3168 #define PANEL_COLOR_BIT_DEPTH_MASK 0x70 3169 3170 // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} 3171 #define PANEL_RANDOM_DITHER 0x80 3172 #define PANEL_RANDOM_DITHER_MASK 0x80 3173 3174 #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this 3175 3176 /****************************************************************************/ 3177 // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 3178 // ASIC Families: NI 3179 // ucTableFormatRevision=1 3180 // ucTableContentRevision=3 3181 /****************************************************************************/ 3182 typedef struct _ATOM_LCD_INFO_V13 3183 { 3184 ATOM_COMMON_TABLE_HEADER sHeader; 3185 ATOM_DTD_FORMAT sLCDTiming; 3186 USHORT usExtInfoTableOffset; 3187 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3188 ULONG ulReserved0; 3189 UCHAR ucLCD_Misc; // Reorganized in V13 3190 // Bit0: {=0:single, =1:dual}, 3191 // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, 3192 // Bit3:2: {Grey level} 3193 // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) 3194 // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? 3195 UCHAR ucPanelDefaultRefreshRate; 3196 UCHAR ucPanelIdentification; 3197 UCHAR ucSS_Id; 3198 USHORT usLCDVenderID; 3199 USHORT usLCDProductID; 3200 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 3201 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own 3202 // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED 3203 // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) 3204 // Bit7-3: Reserved 3205 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3206 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 3207 3208 UCHAR ucPowerSequenceDIGONtoDE_in4Ms; 3209 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms; 3210 UCHAR ucPowerSequenceDEtoDIGON_in4Ms; 3211 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms; 3212 3213 UCHAR ucOffDelay_in4Ms; 3214 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms; 3215 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms; 3216 UCHAR ucReserved1; 3217 3218 ULONG ulReserved[4]; 3219 }ATOM_LCD_INFO_V13; 3220 3221 #define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 3222 3223 //Definitions for ucLCD_Misc 3224 #define ATOM_PANEL_MISC_V13_DUAL 0x00000001 3225 #define ATOM_PANEL_MISC_V13_FPDI 0x00000002 3226 #define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C 3227 #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2 3228 #define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70 3229 #define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10 3230 #define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20 3231 3232 //Color Bit Depth definition in EDID V1.4 @BYTE 14h 3233 //Bit 6 5 4 3234 // 0 0 0 - Color bit depth is undefined 3235 // 0 0 1 - 6 Bits per Primary Color 3236 // 0 1 0 - 8 Bits per Primary Color 3237 // 0 1 1 - 10 Bits per Primary Color 3238 // 1 0 0 - 12 Bits per Primary Color 3239 // 1 0 1 - 14 Bits per Primary Color 3240 // 1 1 0 - 16 Bits per Primary Color 3241 // 1 1 1 - Reserved 3242 3243 //Definitions for ucLCDPanel_SpecialHandlingCap: 3244 3245 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3246 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3247 #define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version 3248 3249 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3250 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3251 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3252 #define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version 3253 3254 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3255 #define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version 3256 3257 typedef struct _ATOM_PATCH_RECORD_MODE 3258 { 3259 UCHAR ucRecordType; 3260 USHORT usHDisp; 3261 USHORT usVDisp; 3262 }ATOM_PATCH_RECORD_MODE; 3263 3264 typedef struct _ATOM_LCD_RTS_RECORD 3265 { 3266 UCHAR ucRecordType; 3267 UCHAR ucRTSValue; 3268 }ATOM_LCD_RTS_RECORD; 3269 3270 //!! If the record below exits, it shoud always be the first record for easy use in command table!!! 3271 // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. 3272 typedef struct _ATOM_LCD_MODE_CONTROL_CAP 3273 { 3274 UCHAR ucRecordType; 3275 USHORT usLCDCap; 3276 }ATOM_LCD_MODE_CONTROL_CAP; 3277 3278 #define LCD_MODE_CAP_BL_OFF 1 3279 #define LCD_MODE_CAP_CRTC_OFF 2 3280 #define LCD_MODE_CAP_PANEL_OFF 4 3281 3282 typedef struct _ATOM_FAKE_EDID_PATCH_RECORD 3283 { 3284 UCHAR ucRecordType; 3285 UCHAR ucFakeEDIDLength; 3286 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. 3287 } ATOM_FAKE_EDID_PATCH_RECORD; 3288 3289 typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD 3290 { 3291 UCHAR ucRecordType; 3292 USHORT usHSize; 3293 USHORT usVSize; 3294 }ATOM_PANEL_RESOLUTION_PATCH_RECORD; 3295 3296 #define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 3297 #define LCD_RTS_RECORD_TYPE 2 3298 #define LCD_CAP_RECORD_TYPE 3 3299 #define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 3300 #define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 3301 #define ATOM_RECORD_END_TYPE 0xFF 3302 3303 /****************************Spread Spectrum Info Table Definitions **********************/ 3304 3305 //ucTableFormatRevision=1 3306 //ucTableContentRevision=2 3307 typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT 3308 { 3309 USHORT usSpreadSpectrumPercentage; 3310 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD 3311 UCHAR ucSS_Step; 3312 UCHAR ucSS_Delay; 3313 UCHAR ucSS_Id; 3314 UCHAR ucRecommendedRef_Div; 3315 UCHAR ucSS_Range; //it was reserved for V11 3316 }ATOM_SPREAD_SPECTRUM_ASSIGNMENT; 3317 3318 #define ATOM_MAX_SS_ENTRY 16 3319 #define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. 3320 #define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. 3321 #define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz 3322 #define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz 3323 3324 3325 #define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 3326 #define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 3327 #define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 3328 #define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 3329 #define ATOM_INTERNAL_SS_MASK 0x00000000 3330 #define ATOM_EXTERNAL_SS_MASK 0x00000002 3331 #define EXEC_SS_STEP_SIZE_SHIFT 2 3332 #define EXEC_SS_DELAY_SHIFT 4 3333 #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 3334 3335 typedef struct _ATOM_SPREAD_SPECTRUM_INFO 3336 { 3337 ATOM_COMMON_TABLE_HEADER sHeader; 3338 ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; 3339 }ATOM_SPREAD_SPECTRUM_INFO; 3340 3341 /****************************************************************************/ 3342 // Structure used in AnalogTV_InfoTable (Top level) 3343 /****************************************************************************/ 3344 //ucTVBootUpDefaultStd definition: 3345 3346 //ATOM_TV_NTSC 1 3347 //ATOM_TV_NTSCJ 2 3348 //ATOM_TV_PAL 3 3349 //ATOM_TV_PALM 4 3350 //ATOM_TV_PALCN 5 3351 //ATOM_TV_PALN 6 3352 //ATOM_TV_PAL60 7 3353 //ATOM_TV_SECAM 8 3354 3355 //ucTVSupportedStd definition: 3356 #define NTSC_SUPPORT 0x1 3357 #define NTSCJ_SUPPORT 0x2 3358 3359 #define PAL_SUPPORT 0x4 3360 #define PALM_SUPPORT 0x8 3361 #define PALCN_SUPPORT 0x10 3362 #define PALN_SUPPORT 0x20 3363 #define PAL60_SUPPORT 0x40 3364 #define SECAM_SUPPORT 0x80 3365 3366 #define MAX_SUPPORTED_TV_TIMING 2 3367 3368 typedef struct _ATOM_ANALOG_TV_INFO 3369 { 3370 ATOM_COMMON_TABLE_HEADER sHeader; 3371 UCHAR ucTV_SupportedStandard; 3372 UCHAR ucTV_BootUpDefaultStandard; 3373 UCHAR ucExt_TV_ASIC_ID; 3374 UCHAR ucExt_TV_ASIC_SlaveAddr; 3375 /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/ 3376 ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; 3377 }ATOM_ANALOG_TV_INFO; 3378 3379 #define MAX_SUPPORTED_TV_TIMING_V1_2 3 3380 3381 typedef struct _ATOM_ANALOG_TV_INFO_V1_2 3382 { 3383 ATOM_COMMON_TABLE_HEADER sHeader; 3384 UCHAR ucTV_SupportedStandard; 3385 UCHAR ucTV_BootUpDefaultStandard; 3386 UCHAR ucExt_TV_ASIC_ID; 3387 UCHAR ucExt_TV_ASIC_SlaveAddr; 3388 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2]; 3389 }ATOM_ANALOG_TV_INFO_V1_2; 3390 3391 typedef struct _ATOM_DPCD_INFO 3392 { 3393 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 3394 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane 3395 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP 3396 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) 3397 }ATOM_DPCD_INFO; 3398 3399 #define ATOM_DPCD_MAX_LANE_MASK 0x1F 3400 3401 /**************************************************************************/ 3402 // VRAM usage and their defintions 3403 3404 // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. 3405 // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. 3406 // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! 3407 // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR 3408 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX 3409 3410 #ifndef VESA_MEMORY_IN_64K_BLOCK 3411 #define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) 3412 #endif 3413 3414 #define ATOM_EDID_RAW_DATASIZE 256 //In Bytes 3415 #define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes 3416 #define ATOM_HWICON_INFOTABLE_SIZE 32 3417 #define MAX_DTD_MODE_IN_VRAM 6 3418 #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) 3419 #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) 3420 //20 bytes for Encoder Type and DPCD in STD EDID area 3421 #define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) 3422 #define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) 3423 3424 #define ATOM_HWICON1_SURFACE_ADDR 0 3425 #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 3426 #define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 3427 #define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) 3428 #define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3429 #define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3430 3431 #define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3432 #define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3433 #define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3434 3435 #define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3436 3437 #define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3438 #define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3439 #define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3440 3441 #define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3442 #define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3443 #define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3444 3445 #define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3446 #define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3447 #define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3448 3449 #define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3450 #define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3451 #define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3452 3453 #define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3454 #define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3455 #define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3456 3457 #define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3458 #define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3459 #define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3460 3461 #define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3462 #define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3463 #define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3464 3465 #define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3466 #define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3467 #define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3468 3469 #define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3470 #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3471 #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3472 3473 #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3474 3475 #define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) 3476 #define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 3477 3478 //The size below is in Kb! 3479 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) 3480 3481 #define ATOM_VRAM_RESERVE_V2_SIZE 32 3482 3483 #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L 3484 #define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 3485 #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 3486 #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 3487 3488 /***********************************************************************************/ 3489 // Structure used in VRAM_UsageByFirmwareTable 3490 // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm 3491 // at running time. 3492 // note2: From RV770, the memory is more than 32bit addressable, so we will change 3493 // ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains 3494 // exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware 3495 // (in offset to start of memory address) is KB aligned instead of byte aligend. 3496 /***********************************************************************************/ 3497 // Note3: 3498 /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter, 3499 for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: 3500 3501 If (ulStartAddrUsedByFirmware!=0) 3502 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; 3503 Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose 3504 else //Non VGA case 3505 if (FB_Size<=2Gb) 3506 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; 3507 else 3508 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB 3509 3510 CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ 3511 3512 #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 3513 3514 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO 3515 { 3516 ULONG ulStartAddrUsedByFirmware; 3517 USHORT usFirmwareUseInKb; 3518 USHORT usReserved; 3519 }ATOM_FIRMWARE_VRAM_RESERVE_INFO; 3520 3521 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE 3522 { 3523 ATOM_COMMON_TABLE_HEADER sHeader; 3524 ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 3525 }ATOM_VRAM_USAGE_BY_FIRMWARE; 3526 3527 // change verion to 1.5, when allow driver to allocate the vram area for command table access. 3528 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 3529 { 3530 ULONG ulStartAddrUsedByFirmware; 3531 USHORT usFirmwareUseInKb; 3532 USHORT usFBUsedByDrvInKb; 3533 }ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; 3534 3535 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 3536 { 3537 ATOM_COMMON_TABLE_HEADER sHeader; 3538 ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 3539 }ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; 3540 3541 /****************************************************************************/ 3542 // Structure used in GPIO_Pin_LUTTable 3543 /****************************************************************************/ 3544 typedef struct _ATOM_GPIO_PIN_ASSIGNMENT 3545 { 3546 USHORT usGpioPin_AIndex; 3547 UCHAR ucGpioPinBitShift; 3548 UCHAR ucGPIO_ID; 3549 }ATOM_GPIO_PIN_ASSIGNMENT; 3550 3551 typedef struct _ATOM_GPIO_PIN_LUT 3552 { 3553 ATOM_COMMON_TABLE_HEADER sHeader; 3554 ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; 3555 }ATOM_GPIO_PIN_LUT; 3556 3557 /****************************************************************************/ 3558 // Structure used in ComponentVideoInfoTable 3559 /****************************************************************************/ 3560 #define GPIO_PIN_ACTIVE_HIGH 0x1 3561 3562 #define MAX_SUPPORTED_CV_STANDARDS 5 3563 3564 // definitions for ATOM_D_INFO.ucSettings 3565 #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] 3566 #define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out 3567 #define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] 3568 3569 typedef struct _ATOM_GPIO_INFO 3570 { 3571 USHORT usAOffset; 3572 UCHAR ucSettings; 3573 UCHAR ucReserved; 3574 }ATOM_GPIO_INFO; 3575 3576 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) 3577 #define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 3578 3579 // definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i 3580 #define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; 3581 #define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] 3582 3583 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode 3584 //Line 3 out put 5V. 3585 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 3586 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 3587 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 3588 3589 //Line 3 out put 2.2V 3590 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box 3591 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box 3592 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 3593 3594 //Line 3 out put 0V 3595 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 3596 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 3597 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 3598 3599 #define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] 3600 3601 #define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 3602 3603 //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. 3604 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 3605 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 3606 3607 3608 typedef struct _ATOM_COMPONENT_VIDEO_INFO 3609 { 3610 ATOM_COMMON_TABLE_HEADER sHeader; 3611 USHORT usMask_PinRegisterIndex; 3612 USHORT usEN_PinRegisterIndex; 3613 USHORT usY_PinRegisterIndex; 3614 USHORT usA_PinRegisterIndex; 3615 UCHAR ucBitShift; 3616 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low 3617 ATOM_DTD_FORMAT sReserved; // must be zeroed out 3618 UCHAR ucMiscInfo; 3619 UCHAR uc480i; 3620 UCHAR uc480p; 3621 UCHAR uc720p; 3622 UCHAR uc1080i; 3623 UCHAR ucLetterBoxMode; 3624 UCHAR ucReserved[3]; 3625 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 3626 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 3627 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 3628 }ATOM_COMPONENT_VIDEO_INFO; 3629 3630 //ucTableFormatRevision=2 3631 //ucTableContentRevision=1 3632 typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 3633 { 3634 ATOM_COMMON_TABLE_HEADER sHeader; 3635 UCHAR ucMiscInfo; 3636 UCHAR uc480i; 3637 UCHAR uc480p; 3638 UCHAR uc720p; 3639 UCHAR uc1080i; 3640 UCHAR ucReserved; 3641 UCHAR ucLetterBoxMode; 3642 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 3643 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 3644 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 3645 }ATOM_COMPONENT_VIDEO_INFO_V21; 3646 3647 #define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 3648 3649 /****************************************************************************/ 3650 // Structure used in object_InfoTable 3651 /****************************************************************************/ 3652 typedef struct _ATOM_OBJECT_HEADER 3653 { 3654 ATOM_COMMON_TABLE_HEADER sHeader; 3655 USHORT usDeviceSupport; 3656 USHORT usConnectorObjectTableOffset; 3657 USHORT usRouterObjectTableOffset; 3658 USHORT usEncoderObjectTableOffset; 3659 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 3660 USHORT usDisplayPathTableOffset; 3661 }ATOM_OBJECT_HEADER; 3662 3663 typedef struct _ATOM_OBJECT_HEADER_V3 3664 { 3665 ATOM_COMMON_TABLE_HEADER sHeader; 3666 USHORT usDeviceSupport; 3667 USHORT usConnectorObjectTableOffset; 3668 USHORT usRouterObjectTableOffset; 3669 USHORT usEncoderObjectTableOffset; 3670 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 3671 USHORT usDisplayPathTableOffset; 3672 USHORT usMiscObjectTableOffset; 3673 }ATOM_OBJECT_HEADER_V3; 3674 3675 typedef struct _ATOM_DISPLAY_OBJECT_PATH 3676 { 3677 USHORT usDeviceTag; //supported device 3678 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 3679 USHORT usConnObjectId; //Connector Object ID 3680 USHORT usGPUObjectId; //GPU ID 3681 USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. 3682 }ATOM_DISPLAY_OBJECT_PATH; 3683 3684 typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH 3685 { 3686 USHORT usDeviceTag; //supported device 3687 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 3688 USHORT usConnObjectId; //Connector Object ID 3689 USHORT usGPUObjectId; //GPU ID 3690 USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder 3691 }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; 3692 3693 typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE 3694 { 3695 UCHAR ucNumOfDispPath; 3696 UCHAR ucVersion; 3697 UCHAR ucPadding[2]; 3698 ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; 3699 }ATOM_DISPLAY_OBJECT_PATH_TABLE; 3700 3701 3702 typedef struct _ATOM_OBJECT //each object has this structure 3703 { 3704 USHORT usObjectID; 3705 USHORT usSrcDstTableOffset; 3706 USHORT usRecordOffset; //this pointing to a bunch of records defined below 3707 USHORT usReserved; 3708 }ATOM_OBJECT; 3709 3710 typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure 3711 { 3712 UCHAR ucNumberOfObjects; 3713 UCHAR ucPadding[3]; 3714 ATOM_OBJECT asObjects[1]; 3715 }ATOM_OBJECT_TABLE; 3716 3717 typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure 3718 { 3719 UCHAR ucNumberOfSrc; 3720 USHORT usSrcObjectID[1]; 3721 UCHAR ucNumberOfDst; 3722 USHORT usDstObjectID[1]; 3723 }ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; 3724 3725 3726 //Two definitions below are for OPM on MXM module designs 3727 3728 #define EXT_HPDPIN_LUTINDEX_0 0 3729 #define EXT_HPDPIN_LUTINDEX_1 1 3730 #define EXT_HPDPIN_LUTINDEX_2 2 3731 #define EXT_HPDPIN_LUTINDEX_3 3 3732 #define EXT_HPDPIN_LUTINDEX_4 4 3733 #define EXT_HPDPIN_LUTINDEX_5 5 3734 #define EXT_HPDPIN_LUTINDEX_6 6 3735 #define EXT_HPDPIN_LUTINDEX_7 7 3736 #define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) 3737 3738 #define EXT_AUXDDC_LUTINDEX_0 0 3739 #define EXT_AUXDDC_LUTINDEX_1 1 3740 #define EXT_AUXDDC_LUTINDEX_2 2 3741 #define EXT_AUXDDC_LUTINDEX_3 3 3742 #define EXT_AUXDDC_LUTINDEX_4 4 3743 #define EXT_AUXDDC_LUTINDEX_5 5 3744 #define EXT_AUXDDC_LUTINDEX_6 6 3745 #define EXT_AUXDDC_LUTINDEX_7 7 3746 #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) 3747 3748 //ucChannelMapping are defined as following 3749 //for DP connector, eDP, DP to VGA/LVDS 3750 //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 3751 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 3752 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 3753 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 3754 typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING 3755 { 3756 #if ATOM_BIG_ENDIAN 3757 UCHAR ucDP_Lane3_Source:2; 3758 UCHAR ucDP_Lane2_Source:2; 3759 UCHAR ucDP_Lane1_Source:2; 3760 UCHAR ucDP_Lane0_Source:2; 3761 #else 3762 UCHAR ucDP_Lane0_Source:2; 3763 UCHAR ucDP_Lane1_Source:2; 3764 UCHAR ucDP_Lane2_Source:2; 3765 UCHAR ucDP_Lane3_Source:2; 3766 #endif 3767 }ATOM_DP_CONN_CHANNEL_MAPPING; 3768 3769 //for DVI/HDMI, in dual link case, both links have to have same mapping. 3770 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 3771 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 3772 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 3773 //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 3774 typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING 3775 { 3776 #if ATOM_BIG_ENDIAN 3777 UCHAR ucDVI_CLK_Source:2; 3778 UCHAR ucDVI_DATA0_Source:2; 3779 UCHAR ucDVI_DATA1_Source:2; 3780 UCHAR ucDVI_DATA2_Source:2; 3781 #else 3782 UCHAR ucDVI_DATA2_Source:2; 3783 UCHAR ucDVI_DATA1_Source:2; 3784 UCHAR ucDVI_DATA0_Source:2; 3785 UCHAR ucDVI_CLK_Source:2; 3786 #endif 3787 }ATOM_DVI_CONN_CHANNEL_MAPPING; 3788 3789 typedef struct _EXT_DISPLAY_PATH 3790 { 3791 USHORT usDeviceTag; //A bit vector to show what devices are supported 3792 USHORT usDeviceACPIEnum; //16bit device ACPI id. 3793 USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions 3794 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT 3795 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT 3796 USHORT usExtEncoderObjId; //external encoder object id 3797 union{ 3798 UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping 3799 ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; 3800 ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; 3801 }; 3802 UCHAR ucReserved; 3803 USHORT usReserved[2]; 3804 }EXT_DISPLAY_PATH; 3805 3806 #define NUMBER_OF_UCHAR_FOR_GUID 16 3807 #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 3808 3809 typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO 3810 { 3811 ATOM_COMMON_TABLE_HEADER sHeader; 3812 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string 3813 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. 3814 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. 3815 UCHAR uc3DStereoPinId; // use for eDP panel 3816 UCHAR Reserved [6]; // for potential expansion 3817 }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; 3818 3819 //Related definitions, all records are different but they have a commond header 3820 typedef struct _ATOM_COMMON_RECORD_HEADER 3821 { 3822 UCHAR ucRecordType; //An emun to indicate the record type 3823 UCHAR ucRecordSize; //The size of the whole record in byte 3824 }ATOM_COMMON_RECORD_HEADER; 3825 3826 3827 #define ATOM_I2C_RECORD_TYPE 1 3828 #define ATOM_HPD_INT_RECORD_TYPE 2 3829 #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 3830 #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 3831 #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 3832 #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 3833 #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 3834 #define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 3835 #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 3836 #define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 3837 #define ATOM_CONNECTOR_CF_RECORD_TYPE 11 3838 #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 3839 #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 3840 #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 3841 #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 3842 #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table 3843 #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table 3844 #define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record 3845 #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 3846 #define ATOM_ENCODER_CAP_RECORD_TYPE 20 3847 3848 3849 //Must be updated when new record type is added,equal to that record definition! 3850 #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE 3851 3852 typedef struct _ATOM_I2C_RECORD 3853 { 3854 ATOM_COMMON_RECORD_HEADER sheader; 3855 ATOM_I2C_ID_CONFIG sucI2cId; 3856 UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC 3857 }ATOM_I2C_RECORD; 3858 3859 typedef struct _ATOM_HPD_INT_RECORD 3860 { 3861 ATOM_COMMON_RECORD_HEADER sheader; 3862 UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 3863 UCHAR ucPlugged_PinState; 3864 }ATOM_HPD_INT_RECORD; 3865 3866 3867 typedef struct _ATOM_OUTPUT_PROTECTION_RECORD 3868 { 3869 ATOM_COMMON_RECORD_HEADER sheader; 3870 UCHAR ucProtectionFlag; 3871 UCHAR ucReserved; 3872 }ATOM_OUTPUT_PROTECTION_RECORD; 3873 3874 typedef struct _ATOM_CONNECTOR_DEVICE_TAG 3875 { 3876 ULONG ulACPIDeviceEnum; //Reserved for now 3877 USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" 3878 USHORT usPadding; 3879 }ATOM_CONNECTOR_DEVICE_TAG; 3880 3881 typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD 3882 { 3883 ATOM_COMMON_RECORD_HEADER sheader; 3884 UCHAR ucNumberOfDevice; 3885 UCHAR ucReserved; 3886 ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation 3887 }ATOM_CONNECTOR_DEVICE_TAG_RECORD; 3888 3889 3890 typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD 3891 { 3892 ATOM_COMMON_RECORD_HEADER sheader; 3893 UCHAR ucConfigGPIOID; 3894 UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in 3895 UCHAR ucFlowinGPIPID; 3896 UCHAR ucExtInGPIPID; 3897 }ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; 3898 3899 typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD 3900 { 3901 ATOM_COMMON_RECORD_HEADER sheader; 3902 UCHAR ucCTL1GPIO_ID; 3903 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high 3904 UCHAR ucCTL2GPIO_ID; 3905 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high 3906 UCHAR ucCTL3GPIO_ID; 3907 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high 3908 UCHAR ucCTLFPGA_IN_ID; 3909 UCHAR ucPadding[3]; 3910 }ATOM_ENCODER_FPGA_CONTROL_RECORD; 3911 3912 typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD 3913 { 3914 ATOM_COMMON_RECORD_HEADER sheader; 3915 UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 3916 UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected 3917 }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; 3918 3919 typedef struct _ATOM_JTAG_RECORD 3920 { 3921 ATOM_COMMON_RECORD_HEADER sheader; 3922 UCHAR ucTMSGPIO_ID; 3923 UCHAR ucTMSGPIOState; //Set to 1 when it's active high 3924 UCHAR ucTCKGPIO_ID; 3925 UCHAR ucTCKGPIOState; //Set to 1 when it's active high 3926 UCHAR ucTDOGPIO_ID; 3927 UCHAR ucTDOGPIOState; //Set to 1 when it's active high 3928 UCHAR ucTDIGPIO_ID; 3929 UCHAR ucTDIGPIOState; //Set to 1 when it's active high 3930 UCHAR ucPadding[2]; 3931 }ATOM_JTAG_RECORD; 3932 3933 3934 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 3935 typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR 3936 { 3937 UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table 3938 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin 3939 }ATOM_GPIO_PIN_CONTROL_PAIR; 3940 3941 typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD 3942 { 3943 ATOM_COMMON_RECORD_HEADER sheader; 3944 UCHAR ucFlags; // Future expnadibility 3945 UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object 3946 ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 3947 }ATOM_OBJECT_GPIO_CNTL_RECORD; 3948 3949 //Definitions for GPIO pin state 3950 #define GPIO_PIN_TYPE_INPUT 0x00 3951 #define GPIO_PIN_TYPE_OUTPUT 0x10 3952 #define GPIO_PIN_TYPE_HW_CONTROL 0x20 3953 3954 //For GPIO_PIN_TYPE_OUTPUT the following is defined 3955 #define GPIO_PIN_OUTPUT_STATE_MASK 0x01 3956 #define GPIO_PIN_OUTPUT_STATE_SHIFT 0 3957 #define GPIO_PIN_STATE_ACTIVE_LOW 0x0 3958 #define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 3959 3960 // Indexes to GPIO array in GLSync record 3961 #define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 3962 #define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 3963 #define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 3964 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 3965 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 3966 #define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 3967 #define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 3968 #define ATOM_GPIO_INDEX_GLSYNC_MAX 7 3969 3970 typedef struct _ATOM_ENCODER_DVO_CF_RECORD 3971 { 3972 ATOM_COMMON_RECORD_HEADER sheader; 3973 ULONG ulStrengthControl; // DVOA strength control for CF 3974 UCHAR ucPadding[2]; 3975 }ATOM_ENCODER_DVO_CF_RECORD; 3976 3977 // Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap 3978 #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by this path 3979 3980 typedef struct _ATOM_ENCODER_CAP_RECORD 3981 { 3982 ATOM_COMMON_RECORD_HEADER sheader; 3983 union { 3984 USHORT usEncoderCap; 3985 struct { 3986 #if ATOM_BIG_ENDIAN 3987 USHORT usReserved:15; // Bit1-15 may be defined for other capability in future 3988 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 3989 #else 3990 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 3991 USHORT usReserved:15; // Bit1-15 may be defined for other capability in future 3992 #endif 3993 }; 3994 }; 3995 }ATOM_ENCODER_CAP_RECORD; 3996 3997 // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle 3998 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 3999 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 4000 4001 typedef struct _ATOM_CONNECTOR_CF_RECORD 4002 { 4003 ATOM_COMMON_RECORD_HEADER sheader; 4004 USHORT usMaxPixClk; 4005 UCHAR ucFlowCntlGpioId; 4006 UCHAR ucSwapCntlGpioId; 4007 UCHAR ucConnectedDvoBundle; 4008 UCHAR ucPadding; 4009 }ATOM_CONNECTOR_CF_RECORD; 4010 4011 typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD 4012 { 4013 ATOM_COMMON_RECORD_HEADER sheader; 4014 ATOM_DTD_FORMAT asTiming; 4015 }ATOM_CONNECTOR_HARDCODE_DTD_RECORD; 4016 4017 typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD 4018 { 4019 ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 4020 UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A 4021 UCHAR ucReserved; 4022 }ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; 4023 4024 4025 typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD 4026 { 4027 ATOM_COMMON_RECORD_HEADER sheader; 4028 UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state 4029 UCHAR ucMuxControlPin; 4030 UCHAR ucMuxState[2]; //for alligment purpose 4031 }ATOM_ROUTER_DDC_PATH_SELECT_RECORD; 4032 4033 typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD 4034 { 4035 ATOM_COMMON_RECORD_HEADER sheader; 4036 UCHAR ucMuxType; 4037 UCHAR ucMuxControlPin; 4038 UCHAR ucMuxState[2]; //for alligment purpose 4039 }ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; 4040 4041 // define ucMuxType 4042 #define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f 4043 #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 4044 4045 typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 4046 { 4047 ATOM_COMMON_RECORD_HEADER sheader; 4048 UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table 4049 }ATOM_CONNECTOR_HPDPIN_LUT_RECORD; 4050 4051 typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 4052 { 4053 ATOM_COMMON_RECORD_HEADER sheader; 4054 ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID 4055 }ATOM_CONNECTOR_AUXDDC_LUT_RECORD; 4056 4057 typedef struct _ATOM_OBJECT_LINK_RECORD 4058 { 4059 ATOM_COMMON_RECORD_HEADER sheader; 4060 USHORT usObjectID; //could be connector, encorder or other object in object.h 4061 }ATOM_OBJECT_LINK_RECORD; 4062 4063 typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD 4064 { 4065 ATOM_COMMON_RECORD_HEADER sheader; 4066 USHORT usReserved; 4067 }ATOM_CONNECTOR_REMOTE_CAP_RECORD; 4068 4069 /****************************************************************************/ 4070 // ASIC voltage data table 4071 /****************************************************************************/ 4072 typedef struct _ATOM_VOLTAGE_INFO_HEADER 4073 { 4074 USHORT usVDDCBaseLevel; //In number of 50mv unit 4075 USHORT usReserved; //For possible extension table offset 4076 UCHAR ucNumOfVoltageEntries; 4077 UCHAR ucBytesPerVoltageEntry; 4078 UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit 4079 UCHAR ucDefaultVoltageEntry; 4080 UCHAR ucVoltageControlI2cLine; 4081 UCHAR ucVoltageControlAddress; 4082 UCHAR ucVoltageControlOffset; 4083 }ATOM_VOLTAGE_INFO_HEADER; 4084 4085 typedef struct _ATOM_VOLTAGE_INFO 4086 { 4087 ATOM_COMMON_TABLE_HEADER sHeader; 4088 ATOM_VOLTAGE_INFO_HEADER viHeader; 4089 UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry 4090 }ATOM_VOLTAGE_INFO; 4091 4092 4093 typedef struct _ATOM_VOLTAGE_FORMULA 4094 { 4095 USHORT usVoltageBaseLevel; // In number of 1mv unit 4096 USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit 4097 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 4098 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv 4099 UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep 4100 UCHAR ucReserved; 4101 UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries 4102 }ATOM_VOLTAGE_FORMULA; 4103 4104 typedef struct _VOLTAGE_LUT_ENTRY 4105 { 4106 USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code 4107 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 4108 }VOLTAGE_LUT_ENTRY; 4109 4110 typedef struct _ATOM_VOLTAGE_FORMULA_V2 4111 { 4112 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 4113 UCHAR ucReserved[3]; 4114 VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries 4115 }ATOM_VOLTAGE_FORMULA_V2; 4116 4117 typedef struct _ATOM_VOLTAGE_CONTROL 4118 { 4119 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine 4120 UCHAR ucVoltageControlI2cLine; 4121 UCHAR ucVoltageControlAddress; 4122 UCHAR ucVoltageControlOffset; 4123 USHORT usGpioPin_AIndex; //GPIO_PAD register index 4124 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff 4125 UCHAR ucReserved; 4126 }ATOM_VOLTAGE_CONTROL; 4127 4128 // Define ucVoltageControlId 4129 #define VOLTAGE_CONTROLLED_BY_HW 0x00 4130 #define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F 4131 #define VOLTAGE_CONTROLLED_BY_GPIO 0x80 4132 #define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage 4133 #define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI 4134 #define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage 4135 #define VOLTAGE_CONTROL_ID_DS4402 0x04 4136 #define VOLTAGE_CONTROL_ID_UP6266 0x05 4137 #define VOLTAGE_CONTROL_ID_SCORPIO 0x06 4138 #define VOLTAGE_CONTROL_ID_VT1556M 0x07 4139 #define VOLTAGE_CONTROL_ID_CHL822x 0x08 4140 #define VOLTAGE_CONTROL_ID_VT1586M 0x09 4141 4142 typedef struct _ATOM_VOLTAGE_OBJECT 4143 { 4144 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4145 UCHAR ucSize; //Size of Object 4146 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 4147 ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID 4148 }ATOM_VOLTAGE_OBJECT; 4149 4150 typedef struct _ATOM_VOLTAGE_OBJECT_V2 4151 { 4152 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4153 UCHAR ucSize; //Size of Object 4154 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 4155 ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID 4156 }ATOM_VOLTAGE_OBJECT_V2; 4157 4158 typedef struct _ATOM_VOLTAGE_OBJECT_INFO 4159 { 4160 ATOM_COMMON_TABLE_HEADER sHeader; 4161 ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control 4162 }ATOM_VOLTAGE_OBJECT_INFO; 4163 4164 typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 4165 { 4166 ATOM_COMMON_TABLE_HEADER sHeader; 4167 ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control 4168 }ATOM_VOLTAGE_OBJECT_INFO_V2; 4169 4170 typedef struct _ATOM_LEAKID_VOLTAGE 4171 { 4172 UCHAR ucLeakageId; 4173 UCHAR ucReserved; 4174 USHORT usVoltage; 4175 }ATOM_LEAKID_VOLTAGE; 4176 4177 typedef struct _ATOM_ASIC_PROFILE_VOLTAGE 4178 { 4179 UCHAR ucProfileId; 4180 UCHAR ucReserved; 4181 USHORT usSize; 4182 USHORT usEfuseSpareStartAddr; 4183 USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, 4184 ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage 4185 }ATOM_ASIC_PROFILE_VOLTAGE; 4186 4187 //ucProfileId 4188 #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 4189 #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 4190 #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 4191 4192 typedef struct _ATOM_ASIC_PROFILING_INFO 4193 { 4194 ATOM_COMMON_TABLE_HEADER asHeader; 4195 ATOM_ASIC_PROFILE_VOLTAGE asVoltage; 4196 }ATOM_ASIC_PROFILING_INFO; 4197 4198 typedef struct _ATOM_POWER_SOURCE_OBJECT 4199 { 4200 UCHAR ucPwrSrcId; // Power source 4201 UCHAR ucPwrSensorType; // GPIO, I2C or none 4202 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id 4203 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect 4204 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect 4205 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect 4206 UCHAR ucPwrSensActiveState; // high active or low active 4207 UCHAR ucReserve[3]; // reserve 4208 USHORT usSensPwr; // in unit of watt 4209 }ATOM_POWER_SOURCE_OBJECT; 4210 4211 typedef struct _ATOM_POWER_SOURCE_INFO 4212 { 4213 ATOM_COMMON_TABLE_HEADER asHeader; 4214 UCHAR asPwrbehave[16]; 4215 ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; 4216 }ATOM_POWER_SOURCE_INFO; 4217 4218 4219 //Define ucPwrSrcId 4220 #define POWERSOURCE_PCIE_ID1 0x00 4221 #define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 4222 #define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 4223 #define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 4224 #define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 4225 4226 //define ucPwrSensorId 4227 #define POWER_SENSOR_ALWAYS 0x00 4228 #define POWER_SENSOR_GPIO 0x01 4229 #define POWER_SENSOR_I2C 0x02 4230 4231 typedef struct _ATOM_CLK_VOLT_CAPABILITY 4232 { 4233 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table 4234 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 4235 }ATOM_CLK_VOLT_CAPABILITY; 4236 4237 typedef struct _ATOM_AVAILABLE_SCLK_LIST 4238 { 4239 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 4240 USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK 4241 USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK 4242 }ATOM_AVAILABLE_SCLK_LIST; 4243 4244 // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition 4245 #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0] 4246 4247 // this IntegrateSystemInfoTable is used for Liano/Ontario APU 4248 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 4249 { 4250 ATOM_COMMON_TABLE_HEADER sHeader; 4251 ULONG ulBootUpEngineClock; 4252 ULONG ulDentistVCOFreq; 4253 ULONG ulBootUpUMAClock; 4254 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 4255 ULONG ulBootUpReqDisplayVector; 4256 ULONG ulOtherDisplayMisc; 4257 ULONG ulGPUCapInfo; 4258 ULONG ulSB_MMIO_Base_Addr; 4259 USHORT usRequestedPWMFreqInHz; 4260 UCHAR ucHtcTmpLmt; 4261 UCHAR ucHtcHystLmt; 4262 ULONG ulMinEngineClock; 4263 ULONG ulSystemConfig; 4264 ULONG ulCPUCapInfo; 4265 USHORT usNBP0Voltage; 4266 USHORT usNBP1Voltage; 4267 USHORT usBootUpNBVoltage; 4268 USHORT usExtDispConnInfoOffset; 4269 USHORT usPanelRefreshRateRange; 4270 UCHAR ucMemoryType; 4271 UCHAR ucUMAChannelNumber; 4272 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; 4273 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; 4274 ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; 4275 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 4276 ULONG ulGMCRestoreResetTime; 4277 ULONG ulMinimumNClk; 4278 ULONG ulIdleNClk; 4279 ULONG ulDDR_DLL_PowerUpTime; 4280 ULONG ulDDR_PLL_PowerUpTime; 4281 USHORT usPCIEClkSSPercentage; 4282 USHORT usPCIEClkSSType; 4283 USHORT usLvdsSSPercentage; 4284 USHORT usLvdsSSpreadRateIn10Hz; 4285 USHORT usHDMISSPercentage; 4286 USHORT usHDMISSpreadRateIn10Hz; 4287 USHORT usDVISSPercentage; 4288 USHORT usDVISSpreadRateIn10Hz; 4289 ULONG ulReserved3[21]; 4290 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 4291 }ATOM_INTEGRATED_SYSTEM_INFO_V6; 4292 4293 // ulGPUCapInfo 4294 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 4295 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 4296 4297 // ulOtherDisplayMisc 4298 #define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01 4299 4300 4301 /********************************************************************************************************************** 4302 ATOM_INTEGRATED_SYSTEM_INFO_V6 Description 4303 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 4304 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 4305 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 4306 sDISPCLK_Voltage: Report Display clock voltage requirement. 4307 4308 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: 4309 ATOM_DEVICE_CRT1_SUPPORT 0x0001 4310 ATOM_DEVICE_CRT2_SUPPORT 0x0010 4311 ATOM_DEVICE_DFP1_SUPPORT 0x0008 4312 ATOM_DEVICE_DFP6_SUPPORT 0x0040 4313 ATOM_DEVICE_DFP2_SUPPORT 0x0080 4314 ATOM_DEVICE_DFP3_SUPPORT 0x0200 4315 ATOM_DEVICE_DFP4_SUPPORT 0x0400 4316 ATOM_DEVICE_DFP5_SUPPORT 0x0800 4317 ATOM_DEVICE_LCD1_SUPPORT 0x0002 4318 ulOtherDisplayMisc: Other display related flags, not defined yet. 4319 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 4320 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 4321 bit[3]=0: Enable HW AUX mode detection logic 4322 =1: Disable HW AUX mode dettion logic 4323 ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 4324 4325 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 4326 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 4327 4328 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 4329 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 4330 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 4331 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 4332 and enabling VariBri under the driver environment from PP table is optional. 4333 4334 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 4335 that BL control from GPU is expected. 4336 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 4337 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 4338 it's per platform 4339 and enabling VariBri under the driver environment from PP table is optional. 4340 4341 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 4342 Threshold on value to enter HTC_active state. 4343 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 4344 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 4345 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 4346 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 4347 =1: PCIE Power Gating Enabled 4348 Bit[1]=0: DDR-DLL shut-down feature disabled. 4349 1: DDR-DLL shut-down feature enabled. 4350 Bit[2]=0: DDR-PLL Power down feature disabled. 4351 1: DDR-PLL Power down feature enabled. 4352 ulCPUCapInfo: TBD 4353 usNBP0Voltage: VID for voltage on NB P0 State 4354 usNBP1Voltage: VID for voltage on NB P1 State 4355 usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 4356 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 4357 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 4358 to indicate a range. 4359 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 4360 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 4361 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 4362 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 4363 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 4364 ucUMAChannelNumber: System memory channel numbers. 4365 ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 4366 ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 4367 ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 4368 sAvail_SCLK[5]: Arrays to provide available list of SLCK and corresponding voltage, order from low to high 4369 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 4370 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 4371 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 4372 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 4373 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 4374 usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 4375 usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 4376 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 4377 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4378 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4379 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4380 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4381 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4382 **********************************************************************************************************************/ 4383 4384 /**************************************************************************/ 4385 // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design 4386 //Memory SS Info Table 4387 //Define Memory Clock SS chip ID 4388 #define ICS91719 1 4389 #define ICS91720 2 4390 4391 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol 4392 typedef struct _ATOM_I2C_DATA_RECORD 4393 { 4394 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" 4395 UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually 4396 }ATOM_I2C_DATA_RECORD; 4397 4398 4399 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information 4400 typedef struct _ATOM_I2C_DEVICE_SETUP_INFO 4401 { 4402 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. 4403 UCHAR ucSSChipID; //SS chip being used 4404 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip 4405 UCHAR ucNumOfI2CDataRecords; //number of data block 4406 ATOM_I2C_DATA_RECORD asI2CData[1]; 4407 }ATOM_I2C_DEVICE_SETUP_INFO; 4408 4409 //========================================================================================== 4410 typedef struct _ATOM_ASIC_MVDD_INFO 4411 { 4412 ATOM_COMMON_TABLE_HEADER sHeader; 4413 ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; 4414 }ATOM_ASIC_MVDD_INFO; 4415 4416 //========================================================================================== 4417 #define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO 4418 4419 //========================================================================================== 4420 /**************************************************************************/ 4421 4422 typedef struct _ATOM_ASIC_SS_ASSIGNMENT 4423 { 4424 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz 4425 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 4426 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq 4427 UCHAR ucClockIndication; //Indicate which clock source needs SS 4428 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. 4429 UCHAR ucReserved[2]; 4430 }ATOM_ASIC_SS_ASSIGNMENT; 4431 4432 //Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type. 4433 //SS is not required or enabled if a match is not found. 4434 #define ASIC_INTERNAL_MEMORY_SS 1 4435 #define ASIC_INTERNAL_ENGINE_SS 2 4436 #define ASIC_INTERNAL_UVD_SS 3 4437 #define ASIC_INTERNAL_SS_ON_TMDS 4 4438 #define ASIC_INTERNAL_SS_ON_HDMI 5 4439 #define ASIC_INTERNAL_SS_ON_LVDS 6 4440 #define ASIC_INTERNAL_SS_ON_DP 7 4441 #define ASIC_INTERNAL_SS_ON_DCPLL 8 4442 #define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 4443 4444 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 4445 { 4446 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 4447 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 4448 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 4449 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 4450 UCHAR ucClockIndication; //Indicate which clock source needs SS 4451 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 4452 UCHAR ucReserved[2]; 4453 }ATOM_ASIC_SS_ASSIGNMENT_V2; 4454 4455 //ucSpreadSpectrumMode 4456 //#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 4457 //#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 4458 //#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 4459 //#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 4460 //#define ATOM_INTERNAL_SS_MASK 0x00000000 4461 //#define ATOM_EXTERNAL_SS_MASK 0x00000002 4462 4463 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO 4464 { 4465 ATOM_COMMON_TABLE_HEADER sHeader; 4466 ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; 4467 }ATOM_ASIC_INTERNAL_SS_INFO; 4468 4469 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 4470 { 4471 ATOM_COMMON_TABLE_HEADER sHeader; 4472 ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. 4473 }ATOM_ASIC_INTERNAL_SS_INFO_V2; 4474 4475 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 4476 { 4477 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 4478 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 4479 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 4480 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 4481 UCHAR ucClockIndication; //Indicate which clock source needs SS 4482 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 4483 UCHAR ucReserved[2]; 4484 }ATOM_ASIC_SS_ASSIGNMENT_V3; 4485 4486 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 4487 { 4488 ATOM_COMMON_TABLE_HEADER sHeader; 4489 ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. 4490 }ATOM_ASIC_INTERNAL_SS_INFO_V3; 4491 4492 4493 //==============================Scratch Pad Definition Portion=============================== 4494 #define ATOM_DEVICE_CONNECT_INFO_DEF 0 4495 #define ATOM_ROM_LOCATION_DEF 1 4496 #define ATOM_TV_STANDARD_DEF 2 4497 #define ATOM_ACTIVE_INFO_DEF 3 4498 #define ATOM_LCD_INFO_DEF 4 4499 #define ATOM_DOS_REQ_INFO_DEF 5 4500 #define ATOM_ACC_CHANGE_INFO_DEF 6 4501 #define ATOM_DOS_MODE_INFO_DEF 7 4502 #define ATOM_I2C_CHANNEL_STATUS_DEF 8 4503 #define ATOM_I2C_CHANNEL_STATUS1_DEF 9 4504 4505 4506 // BIOS_0_SCRATCH Definition 4507 #define ATOM_S0_CRT1_MONO 0x00000001L 4508 #define ATOM_S0_CRT1_COLOR 0x00000002L 4509 #define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) 4510 4511 #define ATOM_S0_TV1_COMPOSITE_A 0x00000004L 4512 #define ATOM_S0_TV1_SVIDEO_A 0x00000008L 4513 #define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) 4514 4515 #define ATOM_S0_CV_A 0x00000010L 4516 #define ATOM_S0_CV_DIN_A 0x00000020L 4517 #define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) 4518 4519 4520 #define ATOM_S0_CRT2_MONO 0x00000100L 4521 #define ATOM_S0_CRT2_COLOR 0x00000200L 4522 #define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) 4523 4524 #define ATOM_S0_TV1_COMPOSITE 0x00000400L 4525 #define ATOM_S0_TV1_SVIDEO 0x00000800L 4526 #define ATOM_S0_TV1_SCART 0x00004000L 4527 #define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) 4528 4529 #define ATOM_S0_CV 0x00001000L 4530 #define ATOM_S0_CV_DIN 0x00002000L 4531 #define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) 4532 4533 #define ATOM_S0_DFP1 0x00010000L 4534 #define ATOM_S0_DFP2 0x00020000L 4535 #define ATOM_S0_LCD1 0x00040000L 4536 #define ATOM_S0_LCD2 0x00080000L 4537 #define ATOM_S0_DFP6 0x00100000L 4538 #define ATOM_S0_DFP3 0x00200000L 4539 #define ATOM_S0_DFP4 0x00400000L 4540 #define ATOM_S0_DFP5 0x00800000L 4541 4542 #define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 4543 4544 #define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with 4545 // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx 4546 4547 #define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L 4548 #define ATOM_S0_THERMAL_STATE_SHIFT 26 4549 4550 #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L 4551 #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 4552 4553 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 4554 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 4555 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 4556 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 4557 4558 //Byte aligned definition for BIOS usage 4559 #define ATOM_S0_CRT1_MONOb0 0x01 4560 #define ATOM_S0_CRT1_COLORb0 0x02 4561 #define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) 4562 4563 #define ATOM_S0_TV1_COMPOSITEb0 0x04 4564 #define ATOM_S0_TV1_SVIDEOb0 0x08 4565 #define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) 4566 4567 #define ATOM_S0_CVb0 0x10 4568 #define ATOM_S0_CV_DINb0 0x20 4569 #define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) 4570 4571 #define ATOM_S0_CRT2_MONOb1 0x01 4572 #define ATOM_S0_CRT2_COLORb1 0x02 4573 #define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) 4574 4575 #define ATOM_S0_TV1_COMPOSITEb1 0x04 4576 #define ATOM_S0_TV1_SVIDEOb1 0x08 4577 #define ATOM_S0_TV1_SCARTb1 0x40 4578 #define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) 4579 4580 #define ATOM_S0_CVb1 0x10 4581 #define ATOM_S0_CV_DINb1 0x20 4582 #define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) 4583 4584 #define ATOM_S0_DFP1b2 0x01 4585 #define ATOM_S0_DFP2b2 0x02 4586 #define ATOM_S0_LCD1b2 0x04 4587 #define ATOM_S0_LCD2b2 0x08 4588 #define ATOM_S0_DFP6b2 0x10 4589 #define ATOM_S0_DFP3b2 0x20 4590 #define ATOM_S0_DFP4b2 0x40 4591 #define ATOM_S0_DFP5b2 0x80 4592 4593 4594 #define ATOM_S0_THERMAL_STATE_MASKb3 0x1C 4595 #define ATOM_S0_THERMAL_STATE_SHIFTb3 2 4596 4597 #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 4598 #define ATOM_S0_LCD1_SHIFT 18 4599 4600 // BIOS_1_SCRATCH Definition 4601 #define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL 4602 #define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L 4603 4604 // BIOS_2_SCRATCH Definition 4605 #define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL 4606 #define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L 4607 #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 4608 4609 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L 4610 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 4611 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L 4612 4613 #define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L 4614 #define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L 4615 4616 #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 4617 #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 4618 #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 4619 #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 4620 #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 4621 #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L 4622 4623 4624 //Byte aligned definition for BIOS usage 4625 #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F 4626 #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF 4627 #define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 4628 4629 #define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF 4630 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C 4631 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10 4632 #define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 4633 #define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 4634 4635 4636 // BIOS_3_SCRATCH Definition 4637 #define ATOM_S3_CRT1_ACTIVE 0x00000001L 4638 #define ATOM_S3_LCD1_ACTIVE 0x00000002L 4639 #define ATOM_S3_TV1_ACTIVE 0x00000004L 4640 #define ATOM_S3_DFP1_ACTIVE 0x00000008L 4641 #define ATOM_S3_CRT2_ACTIVE 0x00000010L 4642 #define ATOM_S3_LCD2_ACTIVE 0x00000020L 4643 #define ATOM_S3_DFP6_ACTIVE 0x00000040L 4644 #define ATOM_S3_DFP2_ACTIVE 0x00000080L 4645 #define ATOM_S3_CV_ACTIVE 0x00000100L 4646 #define ATOM_S3_DFP3_ACTIVE 0x00000200L 4647 #define ATOM_S3_DFP4_ACTIVE 0x00000400L 4648 #define ATOM_S3_DFP5_ACTIVE 0x00000800L 4649 4650 #define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL 4651 4652 #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L 4653 #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L 4654 4655 #define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L 4656 #define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L 4657 #define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L 4658 #define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L 4659 #define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L 4660 #define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L 4661 #define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L 4662 #define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L 4663 #define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L 4664 #define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L 4665 #define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L 4666 #define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L 4667 4668 #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L 4669 #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L 4670 //Below two definitions are not supported in pplib, but in the old powerplay in DAL 4671 #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L 4672 #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L 4673 4674 //Byte aligned definition for BIOS usage 4675 #define ATOM_S3_CRT1_ACTIVEb0 0x01 4676 #define ATOM_S3_LCD1_ACTIVEb0 0x02 4677 #define ATOM_S3_TV1_ACTIVEb0 0x04 4678 #define ATOM_S3_DFP1_ACTIVEb0 0x08 4679 #define ATOM_S3_CRT2_ACTIVEb0 0x10 4680 #define ATOM_S3_LCD2_ACTIVEb0 0x20 4681 #define ATOM_S3_DFP6_ACTIVEb0 0x40 4682 #define ATOM_S3_DFP2_ACTIVEb0 0x80 4683 #define ATOM_S3_CV_ACTIVEb1 0x01 4684 #define ATOM_S3_DFP3_ACTIVEb1 0x02 4685 #define ATOM_S3_DFP4_ACTIVEb1 0x04 4686 #define ATOM_S3_DFP5_ACTIVEb1 0x08 4687 4688 #define ATOM_S3_ACTIVE_CRTC1w0 0xFFF 4689 4690 #define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 4691 #define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 4692 #define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 4693 #define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 4694 #define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 4695 #define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 4696 #define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 4697 #define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 4698 #define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 4699 #define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 4700 #define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 4701 #define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 4702 4703 #define ATOM_S3_ACTIVE_CRTC2w1 0xFFF 4704 4705 // BIOS_4_SCRATCH Definition 4706 #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL 4707 #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L 4708 #define ATOM_S4_LCD1_REFRESH_SHIFT 8 4709 4710 //Byte aligned definition for BIOS usage 4711 #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF 4712 #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 4713 #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 4714 4715 // BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! 4716 #define ATOM_S5_DOS_REQ_CRT1b0 0x01 4717 #define ATOM_S5_DOS_REQ_LCD1b0 0x02 4718 #define ATOM_S5_DOS_REQ_TV1b0 0x04 4719 #define ATOM_S5_DOS_REQ_DFP1b0 0x08 4720 #define ATOM_S5_DOS_REQ_CRT2b0 0x10 4721 #define ATOM_S5_DOS_REQ_LCD2b0 0x20 4722 #define ATOM_S5_DOS_REQ_DFP6b0 0x40 4723 #define ATOM_S5_DOS_REQ_DFP2b0 0x80 4724 #define ATOM_S5_DOS_REQ_CVb1 0x01 4725 #define ATOM_S5_DOS_REQ_DFP3b1 0x02 4726 #define ATOM_S5_DOS_REQ_DFP4b1 0x04 4727 #define ATOM_S5_DOS_REQ_DFP5b1 0x08 4728 4729 #define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF 4730 4731 #define ATOM_S5_DOS_REQ_CRT1 0x0001 4732 #define ATOM_S5_DOS_REQ_LCD1 0x0002 4733 #define ATOM_S5_DOS_REQ_TV1 0x0004 4734 #define ATOM_S5_DOS_REQ_DFP1 0x0008 4735 #define ATOM_S5_DOS_REQ_CRT2 0x0010 4736 #define ATOM_S5_DOS_REQ_LCD2 0x0020 4737 #define ATOM_S5_DOS_REQ_DFP6 0x0040 4738 #define ATOM_S5_DOS_REQ_DFP2 0x0080 4739 #define ATOM_S5_DOS_REQ_CV 0x0100 4740 #define ATOM_S5_DOS_REQ_DFP3 0x0200 4741 #define ATOM_S5_DOS_REQ_DFP4 0x0400 4742 #define ATOM_S5_DOS_REQ_DFP5 0x0800 4743 4744 #define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 4745 #define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 4746 #define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 4747 #define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 4748 #define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ 4749 (ATOM_S5_DOS_FORCE_CVb3<<8)) 4750 4751 // BIOS_6_SCRATCH Definition 4752 #define ATOM_S6_DEVICE_CHANGE 0x00000001L 4753 #define ATOM_S6_SCALER_CHANGE 0x00000002L 4754 #define ATOM_S6_LID_CHANGE 0x00000004L 4755 #define ATOM_S6_DOCKING_CHANGE 0x00000008L 4756 #define ATOM_S6_ACC_MODE 0x00000010L 4757 #define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L 4758 #define ATOM_S6_LID_STATE 0x00000040L 4759 #define ATOM_S6_DOCK_STATE 0x00000080L 4760 #define ATOM_S6_CRITICAL_STATE 0x00000100L 4761 #define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L 4762 #define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L 4763 #define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L 4764 #define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD 4765 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD 4766 4767 #define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion 4768 #define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion 4769 4770 #define ATOM_S6_ACC_REQ_CRT1 0x00010000L 4771 #define ATOM_S6_ACC_REQ_LCD1 0x00020000L 4772 #define ATOM_S6_ACC_REQ_TV1 0x00040000L 4773 #define ATOM_S6_ACC_REQ_DFP1 0x00080000L 4774 #define ATOM_S6_ACC_REQ_CRT2 0x00100000L 4775 #define ATOM_S6_ACC_REQ_LCD2 0x00200000L 4776 #define ATOM_S6_ACC_REQ_DFP6 0x00400000L 4777 #define ATOM_S6_ACC_REQ_DFP2 0x00800000L 4778 #define ATOM_S6_ACC_REQ_CV 0x01000000L 4779 #define ATOM_S6_ACC_REQ_DFP3 0x02000000L 4780 #define ATOM_S6_ACC_REQ_DFP4 0x04000000L 4781 #define ATOM_S6_ACC_REQ_DFP5 0x08000000L 4782 4783 #define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L 4784 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L 4785 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L 4786 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L 4787 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L 4788 4789 //Byte aligned definition for BIOS usage 4790 #define ATOM_S6_DEVICE_CHANGEb0 0x01 4791 #define ATOM_S6_SCALER_CHANGEb0 0x02 4792 #define ATOM_S6_LID_CHANGEb0 0x04 4793 #define ATOM_S6_DOCKING_CHANGEb0 0x08 4794 #define ATOM_S6_ACC_MODEb0 0x10 4795 #define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 4796 #define ATOM_S6_LID_STATEb0 0x40 4797 #define ATOM_S6_DOCK_STATEb0 0x80 4798 #define ATOM_S6_CRITICAL_STATEb1 0x01 4799 #define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 4800 #define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 4801 #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 4802 #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 4803 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 4804 4805 #define ATOM_S6_ACC_REQ_CRT1b2 0x01 4806 #define ATOM_S6_ACC_REQ_LCD1b2 0x02 4807 #define ATOM_S6_ACC_REQ_TV1b2 0x04 4808 #define ATOM_S6_ACC_REQ_DFP1b2 0x08 4809 #define ATOM_S6_ACC_REQ_CRT2b2 0x10 4810 #define ATOM_S6_ACC_REQ_LCD2b2 0x20 4811 #define ATOM_S6_ACC_REQ_DFP6b2 0x40 4812 #define ATOM_S6_ACC_REQ_DFP2b2 0x80 4813 #define ATOM_S6_ACC_REQ_CVb3 0x01 4814 #define ATOM_S6_ACC_REQ_DFP3b3 0x02 4815 #define ATOM_S6_ACC_REQ_DFP4b3 0x04 4816 #define ATOM_S6_ACC_REQ_DFP5b3 0x08 4817 4818 #define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 4819 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 4820 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 4821 #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 4822 #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 4823 4824 #define ATOM_S6_DEVICE_CHANGE_SHIFT 0 4825 #define ATOM_S6_SCALER_CHANGE_SHIFT 1 4826 #define ATOM_S6_LID_CHANGE_SHIFT 2 4827 #define ATOM_S6_DOCKING_CHANGE_SHIFT 3 4828 #define ATOM_S6_ACC_MODE_SHIFT 4 4829 #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 4830 #define ATOM_S6_LID_STATE_SHIFT 6 4831 #define ATOM_S6_DOCK_STATE_SHIFT 7 4832 #define ATOM_S6_CRITICAL_STATE_SHIFT 8 4833 #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 4834 #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 4835 #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 4836 #define ATOM_S6_REQ_SCALER_SHIFT 12 4837 #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 4838 #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 4839 #define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 4840 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 4841 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 4842 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 4843 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 4844 4845 // BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! 4846 #define ATOM_S7_DOS_MODE_TYPEb0 0x03 4847 #define ATOM_S7_DOS_MODE_VGAb0 0x00 4848 #define ATOM_S7_DOS_MODE_VESAb0 0x01 4849 #define ATOM_S7_DOS_MODE_EXTb0 0x02 4850 #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C 4851 #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 4852 #define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 4853 #define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF 4854 4855 #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 4856 4857 // BIOS_8_SCRATCH Definition 4858 #define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF 4859 #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 4860 4861 #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 4862 #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 4863 4864 // BIOS_9_SCRATCH Definition 4865 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 4866 #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF 4867 #endif 4868 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK 4869 #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 4870 #endif 4871 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 4872 #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 4873 #endif 4874 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 4875 #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 4876 #endif 4877 4878 4879 #define ATOM_FLAG_SET 0x20 4880 #define ATOM_FLAG_CLEAR 0 4881 #define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) 4882 #define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) 4883 #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) 4884 #define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) 4885 #define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) 4886 4887 #define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) 4888 #define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) 4889 4890 #define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) 4891 #define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) 4892 #define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) 4893 4894 #define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) 4895 #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) 4896 #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) 4897 4898 #define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) 4899 #define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) 4900 4901 #define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) 4902 #define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) 4903 4904 #define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) 4905 #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) 4906 4907 #define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 4908 4909 #define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 4910 4911 #define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) 4912 #define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) 4913 #define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) 4914 #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) 4915 4916 /****************************************************************************/ 4917 //Portion II: Definitinos only used in Driver 4918 /****************************************************************************/ 4919 4920 // Macros used by driver 4921 #ifdef __cplusplus 4922 #define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT)) 4923 4924 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F) 4925 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F) 4926 #else // not __cplusplus 4927 #define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) 4928 4929 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) 4930 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) 4931 #endif // __cplusplus 4932 4933 #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION 4934 #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION 4935 4936 /****************************************************************************/ 4937 //Portion III: Definitinos only used in VBIOS 4938 /****************************************************************************/ 4939 #define ATOM_DAC_SRC 0x80 4940 #define ATOM_SRC_DAC1 0 4941 #define ATOM_SRC_DAC2 0x80 4942 4943 typedef struct _MEMORY_PLLINIT_PARAMETERS 4944 { 4945 ULONG ulTargetMemoryClock; //In 10Khz unit 4946 UCHAR ucAction; //not define yet 4947 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte 4948 UCHAR ucFbDiv; //FB value 4949 UCHAR ucPostDiv; //Post div 4950 }MEMORY_PLLINIT_PARAMETERS; 4951 4952 #define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS 4953 4954 4955 #define GPIO_PIN_WRITE 0x01 4956 #define GPIO_PIN_READ 0x00 4957 4958 typedef struct _GPIO_PIN_CONTROL_PARAMETERS 4959 { 4960 UCHAR ucGPIO_ID; //return value, read from GPIO pins 4961 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update 4962 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask 4963 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write 4964 }GPIO_PIN_CONTROL_PARAMETERS; 4965 4966 typedef struct _ENABLE_SCALER_PARAMETERS 4967 { 4968 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 4969 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION 4970 UCHAR ucTVStandard; // 4971 UCHAR ucPadding[1]; 4972 }ENABLE_SCALER_PARAMETERS; 4973 #define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS 4974 4975 //ucEnable: 4976 #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 4977 #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 4978 #define SCALER_ENABLE_2TAP_ALPHA_MODE 2 4979 #define SCALER_ENABLE_MULTITAP_MODE 3 4980 4981 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS 4982 { 4983 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position 4984 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset 4985 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset 4986 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 4987 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 4988 }ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; 4989 4990 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION 4991 { 4992 ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; 4993 ENABLE_CRTC_PARAMETERS sReserved; 4994 }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; 4995 4996 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS 4997 { 4998 USHORT usHight; // Image Hight 4999 USHORT usWidth; // Image Width 5000 UCHAR ucSurface; // Surface 1 or 2 5001 UCHAR ucPadding[3]; 5002 }ENABLE_GRAPH_SURFACE_PARAMETERS; 5003 5004 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 5005 { 5006 USHORT usHight; // Image Hight 5007 USHORT usWidth; // Image Width 5008 UCHAR ucSurface; // Surface 1 or 2 5009 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 5010 UCHAR ucPadding[2]; 5011 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; 5012 5013 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 5014 { 5015 USHORT usHight; // Image Hight 5016 USHORT usWidth; // Image Width 5017 UCHAR ucSurface; // Surface 1 or 2 5018 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 5019 USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. 5020 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; 5021 5022 typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION 5023 { 5024 ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; 5025 ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one 5026 }ENABLE_GRAPH_SURFACE_PS_ALLOCATION; 5027 5028 typedef struct _MEMORY_CLEAN_UP_PARAMETERS 5029 { 5030 USHORT usMemoryStart; //in 8Kb boundary, offset from memory base address 5031 USHORT usMemorySize; //8Kb blocks aligned 5032 }MEMORY_CLEAN_UP_PARAMETERS; 5033 #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS 5034 5035 typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS 5036 { 5037 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 5038 USHORT usY_Size; 5039 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS; 5040 5041 typedef struct _INDIRECT_IO_ACCESS 5042 { 5043 ATOM_COMMON_TABLE_HEADER sHeader; 5044 UCHAR IOAccessSequence[256]; 5045 } INDIRECT_IO_ACCESS; 5046 5047 #define INDIRECT_READ 0x00 5048 #define INDIRECT_WRITE 0x80 5049 5050 #define INDIRECT_IO_MM 0 5051 #define INDIRECT_IO_PLL 1 5052 #define INDIRECT_IO_MC 2 5053 #define INDIRECT_IO_PCIE 3 5054 #define INDIRECT_IO_PCIEP 4 5055 #define INDIRECT_IO_NBMISC 5 5056 5057 #define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ 5058 #define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE 5059 #define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ 5060 #define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE 5061 #define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ 5062 #define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE 5063 #define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ 5064 #define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE 5065 #define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ 5066 #define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE 5067 5068 typedef struct _ATOM_OEM_INFO 5069 { 5070 ATOM_COMMON_TABLE_HEADER sHeader; 5071 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 5072 }ATOM_OEM_INFO; 5073 5074 typedef struct _ATOM_TV_MODE 5075 { 5076 UCHAR ucVMode_Num; //Video mode number 5077 UCHAR ucTV_Mode_Num; //Internal TV mode number 5078 }ATOM_TV_MODE; 5079 5080 typedef struct _ATOM_BIOS_INT_TVSTD_MODE 5081 { 5082 ATOM_COMMON_TABLE_HEADER sHeader; 5083 USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table 5084 USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table 5085 USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table 5086 USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 5087 USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 5088 }ATOM_BIOS_INT_TVSTD_MODE; 5089 5090 5091 typedef struct _ATOM_TV_MODE_SCALER_PTR 5092 { 5093 USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients 5094 USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients 5095 UCHAR ucTV_Mode_Num; 5096 }ATOM_TV_MODE_SCALER_PTR; 5097 5098 typedef struct _ATOM_STANDARD_VESA_TIMING 5099 { 5100 ATOM_COMMON_TABLE_HEADER sHeader; 5101 ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation 5102 }ATOM_STANDARD_VESA_TIMING; 5103 5104 5105 typedef struct _ATOM_STD_FORMAT 5106 { 5107 USHORT usSTD_HDisp; 5108 USHORT usSTD_VDisp; 5109 USHORT usSTD_RefreshRate; 5110 USHORT usReserved; 5111 }ATOM_STD_FORMAT; 5112 5113 typedef struct _ATOM_VESA_TO_EXTENDED_MODE 5114 { 5115 USHORT usVESA_ModeNumber; 5116 USHORT usExtendedModeNumber; 5117 }ATOM_VESA_TO_EXTENDED_MODE; 5118 5119 typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT 5120 { 5121 ATOM_COMMON_TABLE_HEADER sHeader; 5122 ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; 5123 }ATOM_VESA_TO_INTENAL_MODE_LUT; 5124 5125 /*************** ATOM Memory Related Data Structure ***********************/ 5126 typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ 5127 UCHAR ucMemoryType; 5128 UCHAR ucMemoryVendor; 5129 UCHAR ucAdjMCId; 5130 UCHAR ucDynClkId; 5131 ULONG ulDllResetClkRange; 5132 }ATOM_MEMORY_VENDOR_BLOCK; 5133 5134 5135 typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ 5136 #if ATOM_BIG_ENDIAN 5137 ULONG ucMemBlkId:8; 5138 ULONG ulMemClockRange:24; 5139 #else 5140 ULONG ulMemClockRange:24; 5141 ULONG ucMemBlkId:8; 5142 #endif 5143 }ATOM_MEMORY_SETTING_ID_CONFIG; 5144 5145 typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS 5146 { 5147 ATOM_MEMORY_SETTING_ID_CONFIG slAccess; 5148 ULONG ulAccess; 5149 }ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; 5150 5151 5152 typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ 5153 ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; 5154 ULONG aulMemData[1]; 5155 }ATOM_MEMORY_SETTING_DATA_BLOCK; 5156 5157 5158 typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ 5159 USHORT usRegIndex; // MC register index 5160 UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf 5161 }ATOM_INIT_REG_INDEX_FORMAT; 5162 5163 5164 typedef struct _ATOM_INIT_REG_BLOCK{ 5165 USHORT usRegIndexTblSize; //size of asRegIndexBuf 5166 USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK 5167 ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; 5168 ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; 5169 }ATOM_INIT_REG_BLOCK; 5170 5171 #define END_OF_REG_INDEX_BLOCK 0x0ffff 5172 #define END_OF_REG_DATA_BLOCK 0x00000000 5173 #define ATOM_INIT_REG_MASK_FLAG 0x80 5174 #define CLOCK_RANGE_HIGHEST 0x00ffffff 5175 5176 #define VALUE_DWORD SIZEOF ULONG 5177 #define VALUE_SAME_AS_ABOVE 0 5178 #define VALUE_MASK_DWORD 0x84 5179 5180 #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) 5181 #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) 5182 #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) 5183 //#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code 5184 #define ACCESS_PLACEHOLDER 0x80 5185 5186 typedef struct _ATOM_MC_INIT_PARAM_TABLE 5187 { 5188 ATOM_COMMON_TABLE_HEADER sHeader; 5189 USHORT usAdjustARB_SEQDataOffset; 5190 USHORT usMCInitMemTypeTblOffset; 5191 USHORT usMCInitCommonTblOffset; 5192 USHORT usMCInitPowerDownTblOffset; 5193 ULONG ulARB_SEQDataBuf[32]; 5194 ATOM_INIT_REG_BLOCK asMCInitMemType; 5195 ATOM_INIT_REG_BLOCK asMCInitCommon; 5196 }ATOM_MC_INIT_PARAM_TABLE; 5197 5198 5199 #define _4Mx16 0x2 5200 #define _4Mx32 0x3 5201 #define _8Mx16 0x12 5202 #define _8Mx32 0x13 5203 #define _16Mx16 0x22 5204 #define _16Mx32 0x23 5205 #define _32Mx16 0x32 5206 #define _32Mx32 0x33 5207 #define _64Mx8 0x41 5208 #define _64Mx16 0x42 5209 #define _64Mx32 0x43 5210 #define _128Mx8 0x51 5211 #define _128Mx16 0x52 5212 #define _256Mx8 0x61 5213 5214 #define SAMSUNG 0x1 5215 #define INFINEON 0x2 5216 #define ELPIDA 0x3 5217 #define ETRON 0x4 5218 #define NANYA 0x5 5219 #define HYNIX 0x6 5220 #define MOSEL 0x7 5221 #define WINBOND 0x8 5222 #define ESMT 0x9 5223 #define MICRON 0xF 5224 5225 #define QIMONDA INFINEON 5226 #define PROMOS MOSEL 5227 #define KRETON INFINEON 5228 #define ELIXIR NANYA 5229 5230 /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// 5231 5232 #define UCODE_ROM_START_ADDRESS 0x1b800 5233 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode 5234 5235 //uCode block header for reference 5236 5237 typedef struct _MCuCodeHeader 5238 { 5239 ULONG ulSignature; 5240 UCHAR ucRevision; 5241 UCHAR ucChecksum; 5242 UCHAR ucReserved1; 5243 UCHAR ucReserved2; 5244 USHORT usParametersLength; 5245 USHORT usUCodeLength; 5246 USHORT usReserved1; 5247 USHORT usReserved2; 5248 } MCuCodeHeader; 5249 5250 ////////////////////////////////////////////////////////////////////////////////// 5251 5252 #define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 5253 5254 #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF 5255 typedef struct _ATOM_VRAM_MODULE_V1 5256 { 5257 ULONG ulReserved; 5258 USHORT usEMRSValue; 5259 USHORT usMRSValue; 5260 USHORT usReserved; 5261 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 5262 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; 5263 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender 5264 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 5265 UCHAR ucRow; // Number of Row,in power of 2; 5266 UCHAR ucColumn; // Number of Column,in power of 2; 5267 UCHAR ucBank; // Nunber of Bank; 5268 UCHAR ucRank; // Number of Rank, in power of 2 5269 UCHAR ucChannelNum; // Number of channel; 5270 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 5271 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 5272 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 5273 UCHAR ucReserved[2]; 5274 }ATOM_VRAM_MODULE_V1; 5275 5276 5277 typedef struct _ATOM_VRAM_MODULE_V2 5278 { 5279 ULONG ulReserved; 5280 ULONG ulFlags; // To enable/disable functionalities based on memory type 5281 ULONG ulEngineClock; // Override of default engine clock for particular memory type 5282 ULONG ulMemoryClock; // Override of default memory clock for particular memory type 5283 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 5284 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 5285 USHORT usEMRSValue; 5286 USHORT usMRSValue; 5287 USHORT usReserved; 5288 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 5289 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 5290 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 5291 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 5292 UCHAR ucRow; // Number of Row,in power of 2; 5293 UCHAR ucColumn; // Number of Column,in power of 2; 5294 UCHAR ucBank; // Nunber of Bank; 5295 UCHAR ucRank; // Number of Rank, in power of 2 5296 UCHAR ucChannelNum; // Number of channel; 5297 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 5298 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 5299 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 5300 UCHAR ucRefreshRateFactor; 5301 UCHAR ucReserved[3]; 5302 }ATOM_VRAM_MODULE_V2; 5303 5304 5305 typedef struct _ATOM_MEMORY_TIMING_FORMAT 5306 { 5307 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 5308 union{ 5309 USHORT usMRS; // mode register 5310 USHORT usDDR3_MR0; 5311 }; 5312 union{ 5313 USHORT usEMRS; // extended mode register 5314 USHORT usDDR3_MR1; 5315 }; 5316 UCHAR ucCL; // CAS latency 5317 UCHAR ucWL; // WRITE Latency 5318 UCHAR uctRAS; // tRAS 5319 UCHAR uctRC; // tRC 5320 UCHAR uctRFC; // tRFC 5321 UCHAR uctRCDR; // tRCDR 5322 UCHAR uctRCDW; // tRCDW 5323 UCHAR uctRP; // tRP 5324 UCHAR uctRRD; // tRRD 5325 UCHAR uctWR; // tWR 5326 UCHAR uctWTR; // tWTR 5327 UCHAR uctPDIX; // tPDIX 5328 UCHAR uctFAW; // tFAW 5329 UCHAR uctAOND; // tAOND 5330 union 5331 { 5332 struct { 5333 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 5334 UCHAR ucReserved; 5335 }; 5336 USHORT usDDR3_MR2; 5337 }; 5338 }ATOM_MEMORY_TIMING_FORMAT; 5339 5340 5341 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 5342 { 5343 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 5344 USHORT usMRS; // mode register 5345 USHORT usEMRS; // extended mode register 5346 UCHAR ucCL; // CAS latency 5347 UCHAR ucWL; // WRITE Latency 5348 UCHAR uctRAS; // tRAS 5349 UCHAR uctRC; // tRC 5350 UCHAR uctRFC; // tRFC 5351 UCHAR uctRCDR; // tRCDR 5352 UCHAR uctRCDW; // tRCDW 5353 UCHAR uctRP; // tRP 5354 UCHAR uctRRD; // tRRD 5355 UCHAR uctWR; // tWR 5356 UCHAR uctWTR; // tWTR 5357 UCHAR uctPDIX; // tPDIX 5358 UCHAR uctFAW; // tFAW 5359 UCHAR uctAOND; // tAOND 5360 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 5361 ////////////////////////////////////GDDR parameters/////////////////////////////////// 5362 UCHAR uctCCDL; // 5363 UCHAR uctCRCRL; // 5364 UCHAR uctCRCWL; // 5365 UCHAR uctCKE; // 5366 UCHAR uctCKRSE; // 5367 UCHAR uctCKRSX; // 5368 UCHAR uctFAW32; // 5369 UCHAR ucMR5lo; // 5370 UCHAR ucMR5hi; // 5371 UCHAR ucTerminator; 5372 }ATOM_MEMORY_TIMING_FORMAT_V1; 5373 5374 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 5375 { 5376 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 5377 USHORT usMRS; // mode register 5378 USHORT usEMRS; // extended mode register 5379 UCHAR ucCL; // CAS latency 5380 UCHAR ucWL; // WRITE Latency 5381 UCHAR uctRAS; // tRAS 5382 UCHAR uctRC; // tRC 5383 UCHAR uctRFC; // tRFC 5384 UCHAR uctRCDR; // tRCDR 5385 UCHAR uctRCDW; // tRCDW 5386 UCHAR uctRP; // tRP 5387 UCHAR uctRRD; // tRRD 5388 UCHAR uctWR; // tWR 5389 UCHAR uctWTR; // tWTR 5390 UCHAR uctPDIX; // tPDIX 5391 UCHAR uctFAW; // tFAW 5392 UCHAR uctAOND; // tAOND 5393 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 5394 ////////////////////////////////////GDDR parameters/////////////////////////////////// 5395 UCHAR uctCCDL; // 5396 UCHAR uctCRCRL; // 5397 UCHAR uctCRCWL; // 5398 UCHAR uctCKE; // 5399 UCHAR uctCKRSE; // 5400 UCHAR uctCKRSX; // 5401 UCHAR uctFAW32; // 5402 UCHAR ucMR4lo; // 5403 UCHAR ucMR4hi; // 5404 UCHAR ucMR5lo; // 5405 UCHAR ucMR5hi; // 5406 UCHAR ucTerminator; 5407 UCHAR ucReserved; 5408 }ATOM_MEMORY_TIMING_FORMAT_V2; 5409 5410 typedef struct _ATOM_MEMORY_FORMAT 5411 { 5412 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock 5413 union{ 5414 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 5415 USHORT usDDR3_Reserved; // Not used for DDR3 memory 5416 }; 5417 union{ 5418 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 5419 USHORT usDDR3_MR3; // Used for DDR3 memory 5420 }; 5421 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 5422 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 5423 UCHAR ucRow; // Number of Row,in power of 2; 5424 UCHAR ucColumn; // Number of Column,in power of 2; 5425 UCHAR ucBank; // Nunber of Bank; 5426 UCHAR ucRank; // Number of Rank, in power of 2 5427 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 5428 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) 5429 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms 5430 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 5431 UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble 5432 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc 5433 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock 5434 }ATOM_MEMORY_FORMAT; 5435 5436 5437 typedef struct _ATOM_VRAM_MODULE_V3 5438 { 5439 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination 5440 USHORT usSize; // size of ATOM_VRAM_MODULE_V3 5441 USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage 5442 USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage 5443 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 5444 UCHAR ucChannelNum; // board dependent parameter:Number of channel; 5445 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit 5446 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv 5447 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 5448 UCHAR ucFlag; // To enable/disable functionalities based on memory type 5449 ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec 5450 }ATOM_VRAM_MODULE_V3; 5451 5452 5453 //ATOM_VRAM_MODULE_V3.ucNPL_RT 5454 #define NPL_RT_MASK 0x0f 5455 #define BATTERY_ODT_MASK 0xc0 5456 5457 #define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 5458 5459 typedef struct _ATOM_VRAM_MODULE_V4 5460 { 5461 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 5462 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 5463 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 5464 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 5465 USHORT usReserved; 5466 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 5467 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 5468 UCHAR ucChannelNum; // Number of channels present in this module config 5469 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 5470 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 5471 UCHAR ucFlag; // To enable/disable functionalities based on memory type 5472 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 5473 UCHAR ucVREFI; // board dependent parameter 5474 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 5475 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 5476 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 5477 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 5478 UCHAR ucReserved[3]; 5479 5480 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 5481 union{ 5482 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 5483 USHORT usDDR3_Reserved; 5484 }; 5485 union{ 5486 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 5487 USHORT usDDR3_MR3; // Used for DDR3 memory 5488 }; 5489 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 5490 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 5491 UCHAR ucReserved2[2]; 5492 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 5493 }ATOM_VRAM_MODULE_V4; 5494 5495 #define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 5496 #define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 5497 #define VRAM_MODULE_V4_MISC_BL_MASK 0x4 5498 #define VRAM_MODULE_V4_MISC_BL8 0x4 5499 #define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 5500 5501 typedef struct _ATOM_VRAM_MODULE_V5 5502 { 5503 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 5504 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 5505 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 5506 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 5507 USHORT usReserved; 5508 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 5509 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 5510 UCHAR ucChannelNum; // Number of channels present in this module config 5511 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 5512 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 5513 UCHAR ucFlag; // To enable/disable functionalities based on memory type 5514 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 5515 UCHAR ucVREFI; // board dependent parameter 5516 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 5517 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 5518 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 5519 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 5520 UCHAR ucReserved[3]; 5521 5522 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 5523 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 5524 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 5525 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 5526 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 5527 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 5528 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 5529 ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 5530 }ATOM_VRAM_MODULE_V5; 5531 5532 typedef struct _ATOM_VRAM_MODULE_V6 5533 { 5534 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 5535 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 5536 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 5537 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 5538 USHORT usReserved; 5539 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 5540 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 5541 UCHAR ucChannelNum; // Number of channels present in this module config 5542 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 5543 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 5544 UCHAR ucFlag; // To enable/disable functionalities based on memory type 5545 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 5546 UCHAR ucVREFI; // board dependent parameter 5547 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 5548 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 5549 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 5550 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 5551 UCHAR ucReserved[3]; 5552 5553 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 5554 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 5555 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 5556 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 5557 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 5558 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 5559 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 5560 ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 5561 }ATOM_VRAM_MODULE_V6; 5562 5563 typedef struct _ATOM_VRAM_MODULE_V7 5564 { 5565 // Design Specific Values 5566 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP 5567 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 5568 USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 5569 USHORT usReserved; 5570 UCHAR ucExtMemoryID; // Current memory module ID 5571 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 5572 UCHAR ucChannelNum; // Number of mem. channels supported in this module 5573 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 5574 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 5575 UCHAR ucReserve; // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now. 5576 UCHAR ucMisc; // RANK_OF_THISMEMORY etc. 5577 UCHAR ucVREFI; // Not used. 5578 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2. 5579 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 5580 UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 5581 UCHAR ucReserved[3]; 5582 // Memory Module specific values 5583 USHORT usEMRS2Value; // EMRS2/MR2 Value. 5584 USHORT usEMRS3Value; // EMRS3/MR3 Value. 5585 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code 5586 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 5587 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory 5588 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 5589 char strMemPNString[20]; // part number end with '0'. 5590 }ATOM_VRAM_MODULE_V7; 5591 5592 typedef struct _ATOM_VRAM_INFO_V2 5593 { 5594 ATOM_COMMON_TABLE_HEADER sHeader; 5595 UCHAR ucNumOfVRAMModule; 5596 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 5597 }ATOM_VRAM_INFO_V2; 5598 5599 typedef struct _ATOM_VRAM_INFO_V3 5600 { 5601 ATOM_COMMON_TABLE_HEADER sHeader; 5602 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 5603 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 5604 USHORT usRerseved; 5605 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 5606 UCHAR ucNumOfVRAMModule; 5607 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 5608 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 5609 // ATOM_INIT_REG_BLOCK aMemAdjust; 5610 }ATOM_VRAM_INFO_V3; 5611 5612 #define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 5613 5614 typedef struct _ATOM_VRAM_INFO_V4 5615 { 5616 ATOM_COMMON_TABLE_HEADER sHeader; 5617 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 5618 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 5619 USHORT usRerseved; 5620 UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 5621 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] 5622 UCHAR ucReservde[4]; 5623 UCHAR ucNumOfVRAMModule; 5624 ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 5625 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 5626 // ATOM_INIT_REG_BLOCK aMemAdjust; 5627 }ATOM_VRAM_INFO_V4; 5628 5629 typedef struct _ATOM_VRAM_INFO_HEADER_V2_1 5630 { 5631 ATOM_COMMON_TABLE_HEADER sHeader; 5632 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 5633 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 5634 USHORT usReserved[4]; 5635 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module 5636 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list 5637 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version 5638 UCHAR ucReserved; 5639 ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 5640 }ATOM_VRAM_INFO_HEADER_V2_1; 5641 5642 5643 typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO 5644 { 5645 ATOM_COMMON_TABLE_HEADER sHeader; 5646 UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator 5647 }ATOM_VRAM_GPIO_DETECTION_INFO; 5648 5649 5650 typedef struct _ATOM_MEMORY_TRAINING_INFO 5651 { 5652 ATOM_COMMON_TABLE_HEADER sHeader; 5653 UCHAR ucTrainingLoop; 5654 UCHAR ucReserved[3]; 5655 ATOM_INIT_REG_BLOCK asMemTrainingSetting; 5656 }ATOM_MEMORY_TRAINING_INFO; 5657 5658 5659 typedef struct SW_I2C_CNTL_DATA_PARAMETERS 5660 { 5661 UCHAR ucControl; 5662 UCHAR ucData; 5663 UCHAR ucSatus; 5664 UCHAR ucTemp; 5665 } SW_I2C_CNTL_DATA_PARAMETERS; 5666 5667 #define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS 5668 5669 typedef struct _SW_I2C_IO_DATA_PARAMETERS 5670 { 5671 USHORT GPIO_Info; 5672 UCHAR ucAct; 5673 UCHAR ucData; 5674 } SW_I2C_IO_DATA_PARAMETERS; 5675 5676 #define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS 5677 5678 /****************************SW I2C CNTL DEFINITIONS**********************/ 5679 #define SW_I2C_IO_RESET 0 5680 #define SW_I2C_IO_GET 1 5681 #define SW_I2C_IO_DRIVE 2 5682 #define SW_I2C_IO_SET 3 5683 #define SW_I2C_IO_START 4 5684 5685 #define SW_I2C_IO_CLOCK 0 5686 #define SW_I2C_IO_DATA 0x80 5687 5688 #define SW_I2C_IO_ZERO 0 5689 #define SW_I2C_IO_ONE 0x100 5690 5691 #define SW_I2C_CNTL_READ 0 5692 #define SW_I2C_CNTL_WRITE 1 5693 #define SW_I2C_CNTL_START 2 5694 #define SW_I2C_CNTL_STOP 3 5695 #define SW_I2C_CNTL_OPEN 4 5696 #define SW_I2C_CNTL_CLOSE 5 5697 #define SW_I2C_CNTL_WRITE1BIT 6 5698 5699 //==============================VESA definition Portion=============================== 5700 #define VESA_OEM_PRODUCT_REV "01.00" 5701 #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support 5702 #define VESA_MODE_WIN_ATTRIBUTE 7 5703 #define VESA_WIN_SIZE 64 5704 5705 typedef struct _PTR_32_BIT_STRUCTURE 5706 { 5707 USHORT Offset16; 5708 USHORT Segment16; 5709 } PTR_32_BIT_STRUCTURE; 5710 5711 typedef union _PTR_32_BIT_UNION 5712 { 5713 PTR_32_BIT_STRUCTURE SegmentOffset; 5714 ULONG Ptr32_Bit; 5715 } PTR_32_BIT_UNION; 5716 5717 typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE 5718 { 5719 UCHAR VbeSignature[4]; 5720 USHORT VbeVersion; 5721 PTR_32_BIT_UNION OemStringPtr; 5722 UCHAR Capabilities[4]; 5723 PTR_32_BIT_UNION VideoModePtr; 5724 USHORT TotalMemory; 5725 } VBE_1_2_INFO_BLOCK_UPDATABLE; 5726 5727 5728 typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE 5729 { 5730 VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; 5731 USHORT OemSoftRev; 5732 PTR_32_BIT_UNION OemVendorNamePtr; 5733 PTR_32_BIT_UNION OemProductNamePtr; 5734 PTR_32_BIT_UNION OemProductRevPtr; 5735 } VBE_2_0_INFO_BLOCK_UPDATABLE; 5736 5737 typedef union _VBE_VERSION_UNION 5738 { 5739 VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; 5740 VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; 5741 } VBE_VERSION_UNION; 5742 5743 typedef struct _VBE_INFO_BLOCK 5744 { 5745 VBE_VERSION_UNION UpdatableVBE_Info; 5746 UCHAR Reserved[222]; 5747 UCHAR OemData[256]; 5748 } VBE_INFO_BLOCK; 5749 5750 typedef struct _VBE_FP_INFO 5751 { 5752 USHORT HSize; 5753 USHORT VSize; 5754 USHORT FPType; 5755 UCHAR RedBPP; 5756 UCHAR GreenBPP; 5757 UCHAR BlueBPP; 5758 UCHAR ReservedBPP; 5759 ULONG RsvdOffScrnMemSize; 5760 ULONG RsvdOffScrnMEmPtr; 5761 UCHAR Reserved[14]; 5762 } VBE_FP_INFO; 5763 5764 typedef struct _VESA_MODE_INFO_BLOCK 5765 { 5766 // Mandatory information for all VBE revisions 5767 USHORT ModeAttributes; // dw ? ; mode attributes 5768 UCHAR WinAAttributes; // db ? ; window A attributes 5769 UCHAR WinBAttributes; // db ? ; window B attributes 5770 USHORT WinGranularity; // dw ? ; window granularity 5771 USHORT WinSize; // dw ? ; window size 5772 USHORT WinASegment; // dw ? ; window A start segment 5773 USHORT WinBSegment; // dw ? ; window B start segment 5774 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function 5775 USHORT BytesPerScanLine;// dw ? ; bytes per scan line 5776 5777 //; Mandatory information for VBE 1.2 and above 5778 USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters 5779 USHORT YResolution; // dw ? ; vertical resolution in pixels or characters 5780 UCHAR XCharSize; // db ? ; character cell width in pixels 5781 UCHAR YCharSize; // db ? ; character cell height in pixels 5782 UCHAR NumberOfPlanes; // db ? ; number of memory planes 5783 UCHAR BitsPerPixel; // db ? ; bits per pixel 5784 UCHAR NumberOfBanks; // db ? ; number of banks 5785 UCHAR MemoryModel; // db ? ; memory model type 5786 UCHAR BankSize; // db ? ; bank size in KB 5787 UCHAR NumberOfImagePages;// db ? ; number of images 5788 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function 5789 5790 //; Direct Color fields(required for direct/6 and YUV/7 memory models) 5791 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits 5792 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask 5793 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits 5794 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask 5795 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits 5796 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask 5797 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits 5798 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask 5799 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes 5800 5801 //; Mandatory information for VBE 2.0 and above 5802 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer 5803 ULONG Reserved_1; // dd 0 ; reserved - always set to 0 5804 USHORT Reserved_2; // dw 0 ; reserved - always set to 0 5805 5806 //; Mandatory information for VBE 3.0 and above 5807 USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes 5808 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes 5809 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes 5810 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) 5811 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) 5812 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) 5813 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) 5814 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) 5815 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) 5816 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) 5817 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) 5818 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode 5819 UCHAR Reserved; // db 190 dup (0) 5820 } VESA_MODE_INFO_BLOCK; 5821 5822 // BIOS function CALLS 5823 #define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code 5824 #define ATOM_BIOS_FUNCTION_COP_MODE 0x00 5825 #define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 5826 #define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 5827 #define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 5828 #define ATOM_BIOS_FUNCTION_GET_DDC 0x0B 5829 #define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E 5830 #define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F 5831 #define ATOM_BIOS_FUNCTION_STV_STD 0x16 5832 #define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 5833 #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 5834 5835 #define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 5836 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 5837 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 5838 #define ATOM_BIOS_FUNCTION_HW_ICON 0x8A 5839 #define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B 5840 #define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 5841 #define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 5842 5843 #define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D 5844 #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E 5845 #define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F 5846 #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 5847 #define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 5848 #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state 5849 #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state 5850 #define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 5851 #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 5852 #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported 5853 5854 5855 #define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS 5856 #define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 5857 #define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 5858 #define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. 5859 #define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY 5860 #define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND 5861 #define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF 5862 #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) 5863 5864 #define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L 5865 #define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L 5866 #define ATOM_BIOS_REG_LOW_MASK 0x000000FFL 5867 5868 // structure used for VBIOS only 5869 5870 //DispOutInfoTable 5871 typedef struct _ASIC_TRANSMITTER_INFO 5872 { 5873 USHORT usTransmitterObjId; 5874 USHORT usSupportDevice; 5875 UCHAR ucTransmitterCmdTblId; 5876 UCHAR ucConfig; 5877 UCHAR ucEncoderID; //available 1st encoder ( default ) 5878 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) 5879 UCHAR uc2ndEncoderID; 5880 UCHAR ucReserved; 5881 }ASIC_TRANSMITTER_INFO; 5882 5883 #define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01 5884 #define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02 5885 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4 5886 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00 5887 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04 5888 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40 5889 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44 5890 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80 5891 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84 5892 5893 typedef struct _ASIC_ENCODER_INFO 5894 { 5895 UCHAR ucEncoderID; 5896 UCHAR ucEncoderConfig; 5897 USHORT usEncoderCmdTblId; 5898 }ASIC_ENCODER_INFO; 5899 5900 typedef struct _ATOM_DISP_OUT_INFO 5901 { 5902 ATOM_COMMON_TABLE_HEADER sHeader; 5903 USHORT ptrTransmitterInfo; 5904 USHORT ptrEncoderInfo; 5905 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 5906 ASIC_ENCODER_INFO asEncoderInfo[1]; 5907 }ATOM_DISP_OUT_INFO; 5908 5909 typedef struct _ATOM_DISP_OUT_INFO_V2 5910 { 5911 ATOM_COMMON_TABLE_HEADER sHeader; 5912 USHORT ptrTransmitterInfo; 5913 USHORT ptrEncoderInfo; 5914 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 5915 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 5916 ASIC_ENCODER_INFO asEncoderInfo[1]; 5917 }ATOM_DISP_OUT_INFO_V2; 5918 5919 // DispDevicePriorityInfo 5920 typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO 5921 { 5922 ATOM_COMMON_TABLE_HEADER sHeader; 5923 USHORT asDevicePriority[16]; 5924 }ATOM_DISPLAY_DEVICE_PRIORITY_INFO; 5925 5926 //ProcessAuxChannelTransactionTable 5927 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 5928 { 5929 USHORT lpAuxRequest; 5930 USHORT lpDataOut; 5931 UCHAR ucChannelID; 5932 union 5933 { 5934 UCHAR ucReplyStatus; 5935 UCHAR ucDelay; 5936 }; 5937 UCHAR ucDataOutLen; 5938 UCHAR ucReserved; 5939 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; 5940 5941 //ProcessAuxChannelTransactionTable 5942 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 5943 { 5944 USHORT lpAuxRequest; 5945 USHORT lpDataOut; 5946 UCHAR ucChannelID; 5947 union 5948 { 5949 UCHAR ucReplyStatus; 5950 UCHAR ucDelay; 5951 }; 5952 UCHAR ucDataOutLen; 5953 UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 5954 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; 5955 5956 #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 5957 5958 //GetSinkType 5959 5960 typedef struct _DP_ENCODER_SERVICE_PARAMETERS 5961 { 5962 USHORT ucLinkClock; 5963 union 5964 { 5965 UCHAR ucConfig; // for DP training command 5966 UCHAR ucI2cId; // use for GET_SINK_TYPE command 5967 }; 5968 UCHAR ucAction; 5969 UCHAR ucStatus; 5970 UCHAR ucLaneNum; 5971 UCHAR ucReserved[2]; 5972 }DP_ENCODER_SERVICE_PARAMETERS; 5973 5974 // ucAction 5975 #define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 5976 /* obselete */ 5977 #define ATOM_DP_ACTION_TRAINING_START 0x02 5978 #define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03 5979 #define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04 5980 #define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05 5981 #define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06 5982 #define ATOM_DP_ACTION_BLANKING 0x07 5983 5984 // ucConfig 5985 #define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03 5986 #define ATOM_DP_CONFIG_DIG1_ENCODER 0x00 5987 #define ATOM_DP_CONFIG_DIG2_ENCODER 0x01 5988 #define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02 5989 #define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04 5990 #define ATOM_DP_CONFIG_LINK_A 0x00 5991 #define ATOM_DP_CONFIG_LINK_B 0x04 5992 /* /obselete */ 5993 #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 5994 5995 5996 typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 5997 { 5998 USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 5999 UCHAR ucAuxId; 6000 UCHAR ucAction; 6001 UCHAR ucSinkType; // Iput and Output parameters. 6002 UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 6003 UCHAR ucReserved[2]; 6004 }DP_ENCODER_SERVICE_PARAMETERS_V2; 6005 6006 typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 6007 { 6008 DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam; 6009 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam; 6010 }DP_ENCODER_SERVICE_PS_ALLOCATION_V2; 6011 6012 // ucAction 6013 #define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01 6014 #define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02 6015 6016 6017 // DP_TRAINING_TABLE 6018 #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR 6019 #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) 6020 #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) 6021 #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) 6022 #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) 6023 #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) 6024 #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) 6025 #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) 6026 #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) 6027 #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) 6028 #define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) 6029 #define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) 6030 #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) 6031 6032 typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 6033 { 6034 UCHAR ucI2CSpeed; 6035 union 6036 { 6037 UCHAR ucRegIndex; 6038 UCHAR ucStatus; 6039 }; 6040 USHORT lpI2CDataOut; 6041 UCHAR ucFlag; 6042 UCHAR ucTransBytes; 6043 UCHAR ucSlaveAddr; 6044 UCHAR ucLineNumber; 6045 }PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; 6046 6047 #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 6048 6049 //ucFlag 6050 #define HW_I2C_WRITE 1 6051 #define HW_I2C_READ 0 6052 #define I2C_2BYTE_ADDR 0x02 6053 6054 typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 6055 { 6056 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... 6057 UCHAR ucReserved[3]; 6058 }SET_HWBLOCK_INSTANCE_PARAMETER_V2; 6059 6060 #define HWBLKINST_INSTANCE_MASK 0x07 6061 #define HWBLKINST_HWBLK_MASK 0xF0 6062 #define HWBLKINST_HWBLK_SHIFT 0x04 6063 6064 //ucHWBlock 6065 #define SELECT_DISP_ENGINE 0 6066 #define SELECT_DISP_PLL 1 6067 #define SELECT_DCIO_UNIPHY_LINK0 2 6068 #define SELECT_DCIO_UNIPHY_LINK1 3 6069 #define SELECT_DCIO_IMPCAL 4 6070 #define SELECT_DCIO_DIG 6 6071 #define SELECT_CRTC_PIXEL_RATE 7 6072 #define SELECT_VGA_BLK 8 6073 6074 /****************************************************************************/ 6075 //Portion VI: Definitinos for vbios MC scratch registers that driver used 6076 /****************************************************************************/ 6077 6078 #define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 6079 #define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 6080 #define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 6081 #define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 6082 #define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 6083 #define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 6084 #define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 6085 6086 /****************************************************************************/ 6087 //Portion VI: Definitinos being oboselete 6088 /****************************************************************************/ 6089 6090 //========================================================================================== 6091 //Remove the definitions below when driver is ready! 6092 typedef struct _ATOM_DAC_INFO 6093 { 6094 ATOM_COMMON_TABLE_HEADER sHeader; 6095 USHORT usMaxFrequency; // in 10kHz unit 6096 USHORT usReserved; 6097 }ATOM_DAC_INFO; 6098 6099 6100 typedef struct _COMPASSIONATE_DATA 6101 { 6102 ATOM_COMMON_TABLE_HEADER sHeader; 6103 6104 //============================== DAC1 portion 6105 UCHAR ucDAC1_BG_Adjustment; 6106 UCHAR ucDAC1_DAC_Adjustment; 6107 USHORT usDAC1_FORCE_Data; 6108 //============================== DAC2 portion 6109 UCHAR ucDAC2_CRT2_BG_Adjustment; 6110 UCHAR ucDAC2_CRT2_DAC_Adjustment; 6111 USHORT usDAC2_CRT2_FORCE_Data; 6112 USHORT usDAC2_CRT2_MUX_RegisterIndex; 6113 UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 6114 UCHAR ucDAC2_NTSC_BG_Adjustment; 6115 UCHAR ucDAC2_NTSC_DAC_Adjustment; 6116 USHORT usDAC2_TV1_FORCE_Data; 6117 USHORT usDAC2_TV1_MUX_RegisterIndex; 6118 UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 6119 UCHAR ucDAC2_CV_BG_Adjustment; 6120 UCHAR ucDAC2_CV_DAC_Adjustment; 6121 USHORT usDAC2_CV_FORCE_Data; 6122 USHORT usDAC2_CV_MUX_RegisterIndex; 6123 UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 6124 UCHAR ucDAC2_PAL_BG_Adjustment; 6125 UCHAR ucDAC2_PAL_DAC_Adjustment; 6126 USHORT usDAC2_TV2_FORCE_Data; 6127 }COMPASSIONATE_DATA; 6128 6129 /****************************Supported Device Info Table Definitions**********************/ 6130 // ucConnectInfo: 6131 // [7:4] - connector type 6132 // = 1 - VGA connector 6133 // = 2 - DVI-I 6134 // = 3 - DVI-D 6135 // = 4 - DVI-A 6136 // = 5 - SVIDEO 6137 // = 6 - COMPOSITE 6138 // = 7 - LVDS 6139 // = 8 - DIGITAL LINK 6140 // = 9 - SCART 6141 // = 0xA - HDMI_type A 6142 // = 0xB - HDMI_type B 6143 // = 0xE - Special case1 (DVI+DIN) 6144 // Others=TBD 6145 // [3:0] - DAC Associated 6146 // = 0 - no DAC 6147 // = 1 - DACA 6148 // = 2 - DACB 6149 // = 3 - External DAC 6150 // Others=TBD 6151 // 6152 6153 typedef struct _ATOM_CONNECTOR_INFO 6154 { 6155 #if ATOM_BIG_ENDIAN 6156 UCHAR bfConnectorType:4; 6157 UCHAR bfAssociatedDAC:4; 6158 #else 6159 UCHAR bfAssociatedDAC:4; 6160 UCHAR bfConnectorType:4; 6161 #endif 6162 }ATOM_CONNECTOR_INFO; 6163 6164 typedef union _ATOM_CONNECTOR_INFO_ACCESS 6165 { 6166 ATOM_CONNECTOR_INFO sbfAccess; 6167 UCHAR ucAccess; 6168 }ATOM_CONNECTOR_INFO_ACCESS; 6169 6170 typedef struct _ATOM_CONNECTOR_INFO_I2C 6171 { 6172 ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; 6173 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 6174 }ATOM_CONNECTOR_INFO_I2C; 6175 6176 6177 typedef struct _ATOM_SUPPORTED_DEVICES_INFO 6178 { 6179 ATOM_COMMON_TABLE_HEADER sHeader; 6180 USHORT usDeviceSupport; 6181 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; 6182 }ATOM_SUPPORTED_DEVICES_INFO; 6183 6184 #define NO_INT_SRC_MAPPED 0xFF 6185 6186 typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP 6187 { 6188 UCHAR ucIntSrcBitmap; 6189 }ATOM_CONNECTOR_INC_SRC_BITMAP; 6190 6191 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 6192 { 6193 ATOM_COMMON_TABLE_HEADER sHeader; 6194 USHORT usDeviceSupport; 6195 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 6196 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 6197 }ATOM_SUPPORTED_DEVICES_INFO_2; 6198 6199 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 6200 { 6201 ATOM_COMMON_TABLE_HEADER sHeader; 6202 USHORT usDeviceSupport; 6203 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; 6204 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; 6205 }ATOM_SUPPORTED_DEVICES_INFO_2d1; 6206 6207 #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 6208 6209 6210 6211 typedef struct _ATOM_MISC_CONTROL_INFO 6212 { 6213 USHORT usFrequency; 6214 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control 6215 UCHAR ucPLL_DutyCycle; // PLL duty cycle control 6216 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control 6217 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control 6218 }ATOM_MISC_CONTROL_INFO; 6219 6220 6221 #define ATOM_MAX_MISC_INFO 4 6222 6223 typedef struct _ATOM_TMDS_INFO 6224 { 6225 ATOM_COMMON_TABLE_HEADER sHeader; 6226 USHORT usMaxFrequency; // in 10Khz 6227 ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; 6228 }ATOM_TMDS_INFO; 6229 6230 6231 typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE 6232 { 6233 UCHAR ucTVStandard; //Same as TV standards defined above, 6234 UCHAR ucPadding[1]; 6235 }ATOM_ENCODER_ANALOG_ATTRIBUTE; 6236 6237 typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE 6238 { 6239 UCHAR ucAttribute; //Same as other digital encoder attributes defined above 6240 UCHAR ucPadding[1]; 6241 }ATOM_ENCODER_DIGITAL_ATTRIBUTE; 6242 6243 typedef union _ATOM_ENCODER_ATTRIBUTE 6244 { 6245 ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; 6246 ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; 6247 }ATOM_ENCODER_ATTRIBUTE; 6248 6249 6250 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS 6251 { 6252 USHORT usPixelClock; 6253 USHORT usEncoderID; 6254 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. 6255 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 6256 ATOM_ENCODER_ATTRIBUTE usDevAttr; 6257 }DVO_ENCODER_CONTROL_PARAMETERS; 6258 6259 typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION 6260 { 6261 DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; 6262 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 6263 }DVO_ENCODER_CONTROL_PS_ALLOCATION; 6264 6265 6266 #define ATOM_XTMDS_ASIC_SI164_ID 1 6267 #define ATOM_XTMDS_ASIC_SI178_ID 2 6268 #define ATOM_XTMDS_ASIC_TFP513_ID 3 6269 #define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 6270 #define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 6271 #define ATOM_XTMDS_MVPU_FPGA 0x00000004 6272 6273 6274 typedef struct _ATOM_XTMDS_INFO 6275 { 6276 ATOM_COMMON_TABLE_HEADER sHeader; 6277 USHORT usSingleLinkMaxFrequency; 6278 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip 6279 UCHAR ucXtransimitterID; 6280 UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported 6281 UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters 6282 // due to design. This ID is used to alert driver that the sequence is not "standard"! 6283 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip 6284 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip 6285 }ATOM_XTMDS_INFO; 6286 6287 typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS 6288 { 6289 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off 6290 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... 6291 UCHAR ucPadding[2]; 6292 }DFP_DPMS_STATUS_CHANGE_PARAMETERS; 6293 6294 /****************************Legacy Power Play Table Definitions **********************/ 6295 6296 //Definitions for ulPowerPlayMiscInfo 6297 #define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L 6298 #define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L 6299 #define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L 6300 6301 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L 6302 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L 6303 6304 #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L 6305 6306 #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L 6307 #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L 6308 #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program 6309 6310 #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L 6311 #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L 6312 #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L 6313 #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L 6314 #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L 6315 #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L 6316 #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L 6317 6318 #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L 6319 #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L 6320 #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L 6321 #define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L 6322 #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L 6323 6324 #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved 6325 #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 6326 6327 #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L 6328 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L 6329 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L 6330 #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic 6331 #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic 6332 #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode 6333 6334 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) 6335 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 6336 #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L 6337 6338 #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L 6339 #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L 6340 #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L 6341 #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L 6342 #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L 6343 #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L 6344 #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. 6345 //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback 6346 #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L 6347 #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L 6348 #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L 6349 6350 //ucTableFormatRevision=1 6351 //ucTableContentRevision=1 6352 typedef struct _ATOM_POWERMODE_INFO 6353 { 6354 ULONG ulMiscInfo; //The power level should be arranged in ascending order 6355 ULONG ulReserved1; // must set to 0 6356 ULONG ulReserved2; // must set to 0 6357 USHORT usEngineClock; 6358 USHORT usMemoryClock; 6359 UCHAR ucVoltageDropIndex; // index to GPIO table 6360 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 6361 UCHAR ucMinTemperature; 6362 UCHAR ucMaxTemperature; 6363 UCHAR ucNumPciELanes; // number of PCIE lanes 6364 }ATOM_POWERMODE_INFO; 6365 6366 //ucTableFormatRevision=2 6367 //ucTableContentRevision=1 6368 typedef struct _ATOM_POWERMODE_INFO_V2 6369 { 6370 ULONG ulMiscInfo; //The power level should be arranged in ascending order 6371 ULONG ulMiscInfo2; 6372 ULONG ulEngineClock; 6373 ULONG ulMemoryClock; 6374 UCHAR ucVoltageDropIndex; // index to GPIO table 6375 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 6376 UCHAR ucMinTemperature; 6377 UCHAR ucMaxTemperature; 6378 UCHAR ucNumPciELanes; // number of PCIE lanes 6379 }ATOM_POWERMODE_INFO_V2; 6380 6381 //ucTableFormatRevision=2 6382 //ucTableContentRevision=2 6383 typedef struct _ATOM_POWERMODE_INFO_V3 6384 { 6385 ULONG ulMiscInfo; //The power level should be arranged in ascending order 6386 ULONG ulMiscInfo2; 6387 ULONG ulEngineClock; 6388 ULONG ulMemoryClock; 6389 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table 6390 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 6391 UCHAR ucMinTemperature; 6392 UCHAR ucMaxTemperature; 6393 UCHAR ucNumPciELanes; // number of PCIE lanes 6394 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table 6395 }ATOM_POWERMODE_INFO_V3; 6396 6397 6398 #define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 6399 6400 #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 6401 #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 6402 6403 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 6404 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 6405 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 6406 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 6407 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 6408 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 6409 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog 6410 6411 6412 typedef struct _ATOM_POWERPLAY_INFO 6413 { 6414 ATOM_COMMON_TABLE_HEADER sHeader; 6415 UCHAR ucOverdriveThermalController; 6416 UCHAR ucOverdriveI2cLine; 6417 UCHAR ucOverdriveIntBitmap; 6418 UCHAR ucOverdriveControllerAddress; 6419 UCHAR ucSizeOfPowerModeEntry; 6420 UCHAR ucNumOfPowerModeEntries; 6421 ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 6422 }ATOM_POWERPLAY_INFO; 6423 6424 typedef struct _ATOM_POWERPLAY_INFO_V2 6425 { 6426 ATOM_COMMON_TABLE_HEADER sHeader; 6427 UCHAR ucOverdriveThermalController; 6428 UCHAR ucOverdriveI2cLine; 6429 UCHAR ucOverdriveIntBitmap; 6430 UCHAR ucOverdriveControllerAddress; 6431 UCHAR ucSizeOfPowerModeEntry; 6432 UCHAR ucNumOfPowerModeEntries; 6433 ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 6434 }ATOM_POWERPLAY_INFO_V2; 6435 6436 typedef struct _ATOM_POWERPLAY_INFO_V3 6437 { 6438 ATOM_COMMON_TABLE_HEADER sHeader; 6439 UCHAR ucOverdriveThermalController; 6440 UCHAR ucOverdriveI2cLine; 6441 UCHAR ucOverdriveIntBitmap; 6442 UCHAR ucOverdriveControllerAddress; 6443 UCHAR ucSizeOfPowerModeEntry; 6444 UCHAR ucNumOfPowerModeEntries; 6445 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 6446 }ATOM_POWERPLAY_INFO_V3; 6447 6448 /* New PPlib */ 6449 /**************************************************************************/ 6450 typedef struct _ATOM_PPLIB_THERMALCONTROLLER 6451 6452 { 6453 UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_* 6454 UCHAR ucI2cLine; // as interpreted by DAL I2C 6455 UCHAR ucI2cAddress; 6456 UCHAR ucFanParameters; // Fan Control Parameters. 6457 UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only. 6458 UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only. 6459 UCHAR ucReserved; // ---- 6460 UCHAR ucFlags; // to be defined 6461 } ATOM_PPLIB_THERMALCONTROLLER; 6462 6463 #define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f 6464 #define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller. 6465 6466 #define ATOM_PP_THERMALCONTROLLER_NONE 0 6467 #define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib 6468 #define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib 6469 #define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib 6470 #define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib 6471 #define ATOM_PP_THERMALCONTROLLER_LM64 5 6472 #define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib 6473 #define ATOM_PP_THERMALCONTROLLER_RV6xx 7 6474 #define ATOM_PP_THERMALCONTROLLER_RV770 8 6475 #define ATOM_PP_THERMALCONTROLLER_ADT7473 9 6476 #define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11 6477 #define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12 6478 #define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen. 6479 #define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally 6480 #define ATOM_PP_THERMALCONTROLLER_NISLANDS 15 6481 6482 // Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal. 6483 // We probably should reserve the bit 0x80 for this use. 6484 // To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here). 6485 // The driver can pick the correct internal controller based on the ASIC. 6486 6487 #define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller 6488 #define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller 6489 6490 typedef struct _ATOM_PPLIB_STATE 6491 { 6492 UCHAR ucNonClockStateIndex; 6493 UCHAR ucClockStateIndices[1]; // variable-sized 6494 } ATOM_PPLIB_STATE; 6495 6496 typedef struct _ATOM_PPLIB_FANTABLE 6497 { 6498 UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same. 6499 UCHAR ucTHyst; // Temperature hysteresis. Integer. 6500 USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. 6501 USHORT usTMed; // The middle temperature where we change slopes. 6502 USHORT usTHigh; // The high point above TMed for adjusting the second slope. 6503 USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments). 6504 USHORT usPWMMed; // The PWM value (in percent) at TMed. 6505 USHORT usPWMHigh; // The PWM value at THigh. 6506 } ATOM_PPLIB_FANTABLE; 6507 6508 typedef struct _ATOM_PPLIB_EXTENDEDHEADER 6509 { 6510 USHORT usSize; 6511 ULONG ulMaxEngineClock; // For Overdrive. 6512 ULONG ulMaxMemoryClock; // For Overdrive. 6513 // Add extra system parameters here, always adjust size to include all fields. 6514 } ATOM_PPLIB_EXTENDEDHEADER; 6515 6516 //// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps 6517 #define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 6518 #define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 6519 #define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 6520 #define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 6521 #define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 6522 #define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 6523 #define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 6524 #define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 6525 #define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 6526 #define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 6527 #define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 6528 #define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 6529 #define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 6530 #define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. 6531 #define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). 6532 #define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC. 6533 #define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. 6534 #define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. 6535 6536 typedef struct _ATOM_PPLIB_POWERPLAYTABLE 6537 { 6538 ATOM_COMMON_TABLE_HEADER sHeader; 6539 6540 UCHAR ucDataRevision; 6541 6542 UCHAR ucNumStates; 6543 UCHAR ucStateEntrySize; 6544 UCHAR ucClockInfoSize; 6545 UCHAR ucNonClockSize; 6546 6547 // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures 6548 USHORT usStateArrayOffset; 6549 6550 // offset from start of this table to array of ASIC-specific structures, 6551 // currently ATOM_PPLIB_CLOCK_INFO. 6552 USHORT usClockInfoArrayOffset; 6553 6554 // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO 6555 USHORT usNonClockInfoArrayOffset; 6556 6557 USHORT usBackbiasTime; // in microseconds 6558 USHORT usVoltageTime; // in microseconds 6559 USHORT usTableSize; //the size of this structure, or the extended structure 6560 6561 ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_* 6562 6563 ATOM_PPLIB_THERMALCONTROLLER sThermalController; 6564 6565 USHORT usBootClockInfoOffset; 6566 USHORT usBootNonClockInfoOffset; 6567 6568 } ATOM_PPLIB_POWERPLAYTABLE; 6569 6570 typedef struct _ATOM_PPLIB_POWERPLAYTABLE2 6571 { 6572 ATOM_PPLIB_POWERPLAYTABLE basicTable; 6573 UCHAR ucNumCustomThermalPolicy; 6574 USHORT usCustomThermalPolicyArrayOffset; 6575 }ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2; 6576 6577 typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 6578 { 6579 ATOM_PPLIB_POWERPLAYTABLE2 basicTable2; 6580 USHORT usFormatID; // To be used ONLY by PPGen. 6581 USHORT usFanTableOffset; 6582 USHORT usExtendendedHeaderOffset; 6583 } ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3; 6584 6585 typedef struct _ATOM_PPLIB_POWERPLAYTABLE4 6586 { 6587 ATOM_PPLIB_POWERPLAYTABLE3 basicTable3; 6588 ULONG ulGoldenPPID; // PPGen use only 6589 ULONG ulGoldenRevision; // PPGen use only 6590 USHORT usVddcDependencyOnSCLKOffset; 6591 USHORT usVddciDependencyOnMCLKOffset; 6592 USHORT usVddcDependencyOnMCLKOffset; 6593 USHORT usMaxClockVoltageOnDCOffset; 6594 USHORT usReserved[2]; 6595 } ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4; 6596 6597 typedef struct _ATOM_PPLIB_POWERPLAYTABLE5 6598 { 6599 ATOM_PPLIB_POWERPLAYTABLE4 basicTable4; 6600 ULONG ulTDPLimit; 6601 ULONG ulNearTDPLimit; 6602 ULONG ulSQRampingThreshold; 6603 USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table 6604 ULONG ulCACLeakage; // TBD, this parameter is still under discussion. Change to ulReserved if not needed. 6605 ULONG ulReserved; 6606 } ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5; 6607 6608 //// ATOM_PPLIB_NONCLOCK_INFO::usClassification 6609 #define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 6610 #define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 6611 #define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0 6612 #define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 6613 #define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 6614 #define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 6615 // 2, 4, 6, 7 are reserved 6616 6617 #define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 6618 #define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 6619 #define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 6620 #define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 6621 #define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 6622 #define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 6623 #define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 6624 #define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 6625 #define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 6626 #define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 6627 #define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 6628 #define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 6629 #define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 6630 6631 //// ATOM_PPLIB_NONCLOCK_INFO::usClassification2 6632 #define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001 6633 #define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002 6634 6635 //// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings 6636 #define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 6637 #define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002 6638 6639 // 0 is 2.5Gb/s, 1 is 5Gb/s 6640 #define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004 6641 #define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2 6642 6643 // lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec 6644 #define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8 6645 #define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3 6646 6647 // lookup into reduced refresh-rate table 6648 #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00 6649 #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8 6650 6651 #define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0 6652 #define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1 6653 // 2-15 TBD as needed. 6654 6655 #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000 6656 #define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000 6657 #define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000 6658 #define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 6659 6660 //memory related flags 6661 #define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000 6662 6663 //M3 Arb //2bits, current 3 sets of parameters in total 6664 #define ATOM_PPLIB_M3ARB_MASK 0x00060000 6665 #define ATOM_PPLIB_M3ARB_SHIFT 17 6666 6667 #define ATOM_PPLIB_ENABLE_DRR 0x00080000 6668 6669 // remaining 16 bits are reserved 6670 typedef struct _ATOM_PPLIB_THERMAL_STATE 6671 { 6672 UCHAR ucMinTemperature; 6673 UCHAR ucMaxTemperature; 6674 UCHAR ucThermalAction; 6675 }ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE; 6676 6677 // Contained in an array starting at the offset 6678 // in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset. 6679 // referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex 6680 #define ATOM_PPLIB_NONCLOCKINFO_VER1 12 6681 #define ATOM_PPLIB_NONCLOCKINFO_VER2 24 6682 typedef struct _ATOM_PPLIB_NONCLOCK_INFO 6683 { 6684 USHORT usClassification; 6685 UCHAR ucMinTemperature; 6686 UCHAR ucMaxTemperature; 6687 ULONG ulCapsAndSettings; 6688 UCHAR ucRequiredPower; 6689 USHORT usClassification2; 6690 ULONG ulVCLK; 6691 ULONG ulDCLK; 6692 UCHAR ucUnused[5]; 6693 } ATOM_PPLIB_NONCLOCK_INFO; 6694 6695 // Contained in an array starting at the offset 6696 // in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset. 6697 // referenced from ATOM_PPLIB_STATE::ucClockStateIndices 6698 typedef struct _ATOM_PPLIB_R600_CLOCK_INFO 6699 { 6700 USHORT usEngineClockLow; 6701 UCHAR ucEngineClockHigh; 6702 6703 USHORT usMemoryClockLow; 6704 UCHAR ucMemoryClockHigh; 6705 6706 USHORT usVDDC; 6707 USHORT usUnused1; 6708 USHORT usUnused2; 6709 6710 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* 6711 6712 } ATOM_PPLIB_R600_CLOCK_INFO; 6713 6714 // ulFlags in ATOM_PPLIB_R600_CLOCK_INFO 6715 #define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1 6716 #define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2 6717 #define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4 6718 #define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8 6719 #define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16 6720 #define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0). 6721 6722 typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO 6723 { 6724 USHORT usEngineClockLow; 6725 UCHAR ucEngineClockHigh; 6726 6727 USHORT usMemoryClockLow; 6728 UCHAR ucMemoryClockHigh; 6729 6730 USHORT usVDDC; 6731 USHORT usVDDCI; 6732 USHORT usUnused; 6733 6734 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* 6735 6736 } ATOM_PPLIB_EVERGREEN_CLOCK_INFO; 6737 6738 typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO 6739 6740 { 6741 USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600). 6742 UCHAR ucLowEngineClockHigh; 6743 USHORT usHighEngineClockLow; // High Engine clock in MHz. 6744 UCHAR ucHighEngineClockHigh; 6745 USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants. 6746 UCHAR ucMemoryClockHigh; // Currentyl unused. 6747 UCHAR ucPadding; // For proper alignment and size. 6748 USHORT usVDDC; // For the 780, use: None, Low, High, Variable 6749 UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} 6750 UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requirement. 6751 USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). 6752 ULONG ulFlags; 6753 } ATOM_PPLIB_RS780_CLOCK_INFO; 6754 6755 #define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 6756 #define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 6757 #define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 6758 #define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 6759 6760 #define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. 6761 #define ATOM_PPLIB_RS780_SPMCLK_LOW 1 6762 #define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 6763 6764 #define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 6765 #define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 6766 #define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 6767 6768 typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{ 6769 USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz 6770 UCHAR ucEngineClockHigh; //clockfrequency >> 16. 6771 UCHAR vddcIndex; //2-bit vddc index; 6772 UCHAR leakage; //please use 8-bit absolute value, not the 6-bit % value 6773 //please initalize to 0 6774 UCHAR rsv; 6775 //please initalize to 0 6776 USHORT rsv1; 6777 //please initialize to 0s 6778 ULONG rsv2[2]; 6779 }ATOM_PPLIB_SUMO_CLOCK_INFO; 6780 6781 6782 6783 typedef struct _ATOM_PPLIB_STATE_V2 6784 { 6785 //number of valid dpm levels in this state; Driver uses it to calculate the whole 6786 //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR) 6787 UCHAR ucNumDPMLevels; 6788 6789 //a index to the array of nonClockInfos 6790 UCHAR nonClockInfoIndex; 6791 /** 6792 * Driver will read the first ucNumDPMLevels in this array 6793 */ 6794 UCHAR clockInfoIndex[1]; 6795 } ATOM_PPLIB_STATE_V2; 6796 6797 typedef struct StateArray{ 6798 //how many states we have 6799 UCHAR ucNumEntries; 6800 6801 ATOM_PPLIB_STATE_V2 states[1]; 6802 }StateArray; 6803 6804 6805 typedef struct ClockInfoArray{ 6806 //how many clock levels we have 6807 UCHAR ucNumEntries; 6808 6809 //sizeof(ATOM_PPLIB_SUMO_CLOCK_INFO) 6810 UCHAR ucEntrySize; 6811 6812 //this is for Sumo 6813 ATOM_PPLIB_SUMO_CLOCK_INFO clockInfo[1]; 6814 }ClockInfoArray; 6815 6816 typedef struct NonClockInfoArray{ 6817 6818 //how many non-clock levels we have. normally should be same as number of states 6819 UCHAR ucNumEntries; 6820 //sizeof(ATOM_PPLIB_NONCLOCK_INFO) 6821 UCHAR ucEntrySize; 6822 6823 ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1]; 6824 }NonClockInfoArray; 6825 6826 typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record 6827 { 6828 USHORT usClockLow; 6829 UCHAR ucClockHigh; 6830 USHORT usVoltage; 6831 }ATOM_PPLIB_Clock_Voltage_Dependency_Record; 6832 6833 typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table 6834 { 6835 UCHAR ucNumEntries; // Number of entries. 6836 ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries. 6837 }ATOM_PPLIB_Clock_Voltage_Dependency_Table; 6838 6839 typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record 6840 { 6841 USHORT usSclkLow; 6842 UCHAR ucSclkHigh; 6843 USHORT usMclkLow; 6844 UCHAR ucMclkHigh; 6845 USHORT usVddc; 6846 USHORT usVddci; 6847 }ATOM_PPLIB_Clock_Voltage_Limit_Record; 6848 6849 typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table 6850 { 6851 UCHAR ucNumEntries; // Number of entries. 6852 ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries. 6853 }ATOM_PPLIB_Clock_Voltage_Limit_Table; 6854 6855 /**************************************************************************/ 6856 6857 6858 // Following definitions are for compatibility issue in different SW components. 6859 #define ATOM_MASTER_DATA_TABLE_REVISION 0x01 6860 #define Object_Info Object_Header 6861 #define AdjustARB_SEQ MC_InitParameter 6862 #define VRAM_GPIO_DetectionInfo VoltageObjectInfo 6863 #define ASIC_VDDCI_Info ASIC_ProfilingInfo 6864 #define ASIC_MVDDQ_Info MemoryTrainingInfo 6865 #define SS_Info PPLL_SS_Info 6866 #define ASIC_MVDDC_Info ASIC_InternalSS_Info 6867 #define DispDevicePriorityInfo SaveRestoreInfo 6868 #define DispOutInfo TV_VideoMode 6869 6870 6871 #define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE 6872 #define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE 6873 6874 //New device naming, remove them when both DAL/VBIOS is ready 6875 #define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 6876 #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS 6877 6878 #define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 6879 #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS 6880 6881 #define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS 6882 #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION 6883 6884 #define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT 6885 #define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT 6886 6887 #define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX 6888 #define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX 6889 6890 #define ATOM_DEVICE_DFP2I_INDEX 0x00000009 6891 #define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) 6892 6893 #define ATOM_S0_DFP1I ATOM_S0_DFP1 6894 #define ATOM_S0_DFP1X ATOM_S0_DFP2 6895 6896 #define ATOM_S0_DFP2I 0x00200000L 6897 #define ATOM_S0_DFP2Ib2 0x20 6898 6899 #define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE 6900 #define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE 6901 6902 #define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L 6903 #define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 6904 6905 #define ATOM_S3_DFP2I_ACTIVEb1 0x02 6906 6907 #define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE 6908 #define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE 6909 6910 #define ATOM_S3_DFP2I_ACTIVE 0x00000200L 6911 6912 #define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE 6913 #define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE 6914 #define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L 6915 6916 #define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 6917 #define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 6918 6919 #define ATOM_S5_DOS_REQ_DFP2I 0x0200 6920 #define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 6921 #define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 6922 6923 #define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 6924 #define ATOM_S6_ACC_REQ_DFP2I 0x02000000L 6925 6926 #define TMDS1XEncoderControl DVOEncoderControl 6927 #define DFP1XOutputControl DVOOutputControl 6928 6929 #define ExternalDFPOutputControl DFP1XOutputControl 6930 #define EnableExternalTMDS_Encoder TMDS1XEncoderControl 6931 6932 #define DFP1IOutputControl TMDSAOutputControl 6933 #define DFP2IOutputControl LVTMAOutputControl 6934 6935 #define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 6936 #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 6937 6938 #define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 6939 #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 6940 6941 #define ucDac1Standard ucDacStandard 6942 #define ucDac2Standard ucDacStandard 6943 6944 #define TMDS1EncoderControl TMDSAEncoderControl 6945 #define TMDS2EncoderControl LVTMAEncoderControl 6946 6947 #define DFP1OutputControl TMDSAOutputControl 6948 #define DFP2OutputControl LVTMAOutputControl 6949 #define CRT1OutputControl DAC1OutputControl 6950 #define CRT2OutputControl DAC2OutputControl 6951 6952 //These two lines will be removed for sure in a few days, will follow up with Michael V. 6953 #define EnableLVDS_SS EnableSpreadSpectrumOnPPLL 6954 #define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL 6955 6956 //#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 6957 //#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 6958 //#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 6959 //#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 6960 //#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 6961 6962 #define ATOM_S6_ACC_REQ_TV2 0x00400000L 6963 #define ATOM_DEVICE_TV2_INDEX 0x00000006 6964 #define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) 6965 #define ATOM_S0_TV2 0x00100000L 6966 #define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE 6967 #define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE 6968 6969 // 6970 #define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 6971 #define ATOM_S2_LCD1_DPMS_STATE 0x00020000L 6972 #define ATOM_S2_TV1_DPMS_STATE 0x00040000L 6973 #define ATOM_S2_DFP1_DPMS_STATE 0x00080000L 6974 #define ATOM_S2_CRT2_DPMS_STATE 0x00100000L 6975 #define ATOM_S2_LCD2_DPMS_STATE 0x00200000L 6976 #define ATOM_S2_TV2_DPMS_STATE 0x00400000L 6977 #define ATOM_S2_DFP2_DPMS_STATE 0x00800000L 6978 #define ATOM_S2_CV_DPMS_STATE 0x01000000L 6979 #define ATOM_S2_DFP3_DPMS_STATE 0x02000000L 6980 #define ATOM_S2_DFP4_DPMS_STATE 0x04000000L 6981 #define ATOM_S2_DFP5_DPMS_STATE 0x08000000L 6982 6983 #define ATOM_S2_CRT1_DPMS_STATEb2 0x01 6984 #define ATOM_S2_LCD1_DPMS_STATEb2 0x02 6985 #define ATOM_S2_TV1_DPMS_STATEb2 0x04 6986 #define ATOM_S2_DFP1_DPMS_STATEb2 0x08 6987 #define ATOM_S2_CRT2_DPMS_STATEb2 0x10 6988 #define ATOM_S2_LCD2_DPMS_STATEb2 0x20 6989 #define ATOM_S2_TV2_DPMS_STATEb2 0x40 6990 #define ATOM_S2_DFP2_DPMS_STATEb2 0x80 6991 #define ATOM_S2_CV_DPMS_STATEb3 0x01 6992 #define ATOM_S2_DFP3_DPMS_STATEb3 0x02 6993 #define ATOM_S2_DFP4_DPMS_STATEb3 0x04 6994 #define ATOM_S2_DFP5_DPMS_STATEb3 0x08 6995 6996 #define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20 6997 #define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40 6998 #define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80 6999 7000 /*********************************************************************************/ 7001 7002 #pragma pack() // BIOS data must use byte aligment 7003 7004 #endif /* _ATOMBIOS_H */ 7005