1 /* 2 * Contains the definition of registers common to all PowerPC variants. 3 * If a register definition has been changed in a different PowerPC 4 * variant, we will case it in #ifndef XXX ... #endif, and have the 5 * number used in the Programming Environments Manual For 32-Bit 6 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here. 7 */ 8 9 #ifndef _ASM_POWERPC_REG_H 10 #define _ASM_POWERPC_REG_H 11 #ifdef __KERNEL__ 12 13 #include <linux/stringify.h> 14 #include <asm/cputable.h> 15 16 /* Pickup Book E specific registers. */ 17 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) 18 #include <asm/reg_booke.h> 19 #endif /* CONFIG_BOOKE || CONFIG_40x */ 20 21 #ifdef CONFIG_FSL_EMB_PERFMON 22 #include <asm/reg_fsl_emb.h> 23 #endif 24 25 #ifdef CONFIG_8xx 26 #include <asm/reg_8xx.h> 27 #endif /* CONFIG_8xx */ 28 29 #define MSR_SF_LG 63 /* Enable 64 bit mode */ 30 #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ 31 #define MSR_HV_LG 60 /* Hypervisor state */ 32 #define MSR_VEC_LG 25 /* Enable AltiVec */ 33 #define MSR_VSX_LG 23 /* Enable VSX */ 34 #define MSR_POW_LG 18 /* Enable Power Management */ 35 #define MSR_WE_LG 18 /* Wait State Enable */ 36 #define MSR_TGPR_LG 17 /* TLB Update registers in use */ 37 #define MSR_CE_LG 17 /* Critical Interrupt Enable */ 38 #define MSR_ILE_LG 16 /* Interrupt Little Endian */ 39 #define MSR_EE_LG 15 /* External Interrupt Enable */ 40 #define MSR_PR_LG 14 /* Problem State / Privilege Level */ 41 #define MSR_FP_LG 13 /* Floating Point enable */ 42 #define MSR_ME_LG 12 /* Machine Check Enable */ 43 #define MSR_FE0_LG 11 /* Floating Exception mode 0 */ 44 #define MSR_SE_LG 10 /* Single Step */ 45 #define MSR_BE_LG 9 /* Branch Trace */ 46 #define MSR_DE_LG 9 /* Debug Exception Enable */ 47 #define MSR_FE1_LG 8 /* Floating Exception mode 1 */ 48 #define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */ 49 #define MSR_IR_LG 5 /* Instruction Relocate */ 50 #define MSR_DR_LG 4 /* Data Relocate */ 51 #define MSR_PE_LG 3 /* Protection Enable */ 52 #define MSR_PX_LG 2 /* Protection Exclusive Mode */ 53 #define MSR_PMM_LG 2 /* Performance monitor */ 54 #define MSR_RI_LG 1 /* Recoverable Exception */ 55 #define MSR_LE_LG 0 /* Little Endian */ 56 57 #ifdef __ASSEMBLY__ 58 #define __MASK(X) (1<<(X)) 59 #else 60 #define __MASK(X) (1UL<<(X)) 61 #endif 62 63 #ifdef CONFIG_PPC64 64 #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */ 65 #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */ 66 #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */ 67 #else 68 /* so tests for these bits fail on 32-bit */ 69 #define MSR_SF 0 70 #define MSR_ISF 0 71 #define MSR_HV 0 72 #endif 73 74 #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */ 75 #define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */ 76 #define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */ 77 #define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */ 78 #define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */ 79 #define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */ 80 #define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */ 81 #define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */ 82 #define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */ 83 #define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */ 84 #define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */ 85 #define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */ 86 #define MSR_SE __MASK(MSR_SE_LG) /* Single Step */ 87 #define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */ 88 #define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */ 89 #define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */ 90 #define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */ 91 #define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */ 92 #define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */ 93 #define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */ 94 #define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */ 95 #ifndef MSR_PMM 96 #define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */ 97 #endif 98 #define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */ 99 #define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */ 100 101 #if defined(CONFIG_PPC_BOOK3S_64) 102 /* Server variant */ 103 #define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV 104 #define MSR_KERNEL MSR_ | MSR_SF 105 #define MSR_USER32 MSR_ | MSR_PR | MSR_EE 106 #define MSR_USER64 MSR_USER32 | MSR_SF 107 #elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx) 108 /* Default MSR for kernel mode. */ 109 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR) 110 #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) 111 #endif 112 113 /* Floating Point Status and Control Register (FPSCR) Fields */ 114 #define FPSCR_FX 0x80000000 /* FPU exception summary */ 115 #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ 116 #define FPSCR_VX 0x20000000 /* Invalid operation summary */ 117 #define FPSCR_OX 0x10000000 /* Overflow exception summary */ 118 #define FPSCR_UX 0x08000000 /* Underflow exception summary */ 119 #define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */ 120 #define FPSCR_XX 0x02000000 /* Inexact exception summary */ 121 #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ 122 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ 123 #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ 124 #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ 125 #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ 126 #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ 127 #define FPSCR_FR 0x00040000 /* Fraction rounded */ 128 #define FPSCR_FI 0x00020000 /* Fraction inexact */ 129 #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ 130 #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ 131 #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ 132 #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ 133 #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ 134 #define FPSCR_VE 0x00000080 /* Invalid op exception enable */ 135 #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ 136 #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ 137 #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ 138 #define FPSCR_XE 0x00000008 /* FP inexact exception enable */ 139 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ 140 #define FPSCR_RN 0x00000003 /* FPU rounding control */ 141 142 /* Bit definitions for SPEFSCR. */ 143 #define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */ 144 #define SPEFSCR_OVH 0x40000000 /* Integer overflow high */ 145 #define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */ 146 #define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */ 147 #define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */ 148 #define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */ 149 #define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */ 150 #define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */ 151 #define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */ 152 #define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */ 153 #define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */ 154 #define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */ 155 #define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */ 156 #define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */ 157 #define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */ 158 #define SPEFSCR_OV 0x00004000 /* Integer overflow */ 159 #define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */ 160 #define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */ 161 #define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */ 162 #define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */ 163 #define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */ 164 #define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */ 165 #define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */ 166 #define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */ 167 #define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */ 168 #define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */ 169 #define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */ 170 #define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */ 171 172 /* Special Purpose Registers (SPRNs)*/ 173 174 #ifdef CONFIG_40x 175 #define SPRN_PID 0x3B1 /* Process ID */ 176 #else 177 #define SPRN_PID 0x030 /* Process ID */ 178 #ifdef CONFIG_BOOKE 179 #define SPRN_PID0 SPRN_PID/* Process ID Register 0 */ 180 #endif 181 #endif 182 183 #define SPRN_CTR 0x009 /* Count Register */ 184 #define SPRN_DSCR 0x11 185 #define SPRN_CTRLF 0x088 186 #define SPRN_CTRLT 0x098 187 #define CTRL_CT 0xc0000000 /* current thread */ 188 #define CTRL_CT0 0x80000000 /* thread 0 */ 189 #define CTRL_CT1 0x40000000 /* thread 1 */ 190 #define CTRL_TE 0x00c00000 /* thread enable */ 191 #define CTRL_RUNLATCH 0x1 192 #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ 193 #define DABR_TRANSLATION (1UL << 2) 194 #define DABR_DATA_WRITE (1UL << 1) 195 #define DABR_DATA_READ (1UL << 0) 196 #define SPRN_DABR2 0x13D /* e300 */ 197 #define SPRN_DABRX 0x3F7 /* Data Address Breakpoint Register Extension */ 198 #define DABRX_USER (1UL << 0) 199 #define DABRX_KERNEL (1UL << 1) 200 #define SPRN_DAR 0x013 /* Data Address Register */ 201 #define SPRN_DBCR 0x136 /* e300 Data Breakpoint Control Reg */ 202 #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ 203 #define DSISR_NOHPTE 0x40000000 /* no translation found */ 204 #define DSISR_PROTFAULT 0x08000000 /* protection fault */ 205 #define DSISR_ISSTORE 0x02000000 /* access was a store */ 206 #define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */ 207 #define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */ 208 #define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */ 209 #define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */ 210 #define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */ 211 #define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */ 212 #define SPRN_SPURR 0x134 /* Scaled PURR */ 213 #define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ 214 #define SPRN_LPCR 0x13E /* LPAR Control Register */ 215 #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ 216 #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ 217 #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ 218 #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ 219 #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ 220 #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ 221 #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ 222 #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ 223 #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ 224 #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ 225 #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ 226 #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ 227 #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ 228 #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ 229 #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ 230 #define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */ 231 232 #define SPRN_DEC 0x016 /* Decrement Register */ 233 #define SPRN_DER 0x095 /* Debug Enable Regsiter */ 234 #define DER_RSTE 0x40000000 /* Reset Interrupt */ 235 #define DER_CHSTPE 0x20000000 /* Check Stop */ 236 #define DER_MCIE 0x10000000 /* Machine Check Interrupt */ 237 #define DER_EXTIE 0x02000000 /* External Interrupt */ 238 #define DER_ALIE 0x01000000 /* Alignment Interrupt */ 239 #define DER_PRIE 0x00800000 /* Program Interrupt */ 240 #define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */ 241 #define DER_DECIE 0x00200000 /* Decrementer Interrupt */ 242 #define DER_SYSIE 0x00040000 /* System Call Interrupt */ 243 #define DER_TRE 0x00020000 /* Trace Interrupt */ 244 #define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */ 245 #define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */ 246 #define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */ 247 #define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */ 248 #define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */ 249 #define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */ 250 #define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */ 251 #define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */ 252 #define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */ 253 #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ 254 #define SPRN_EAR 0x11A /* External Address Register */ 255 #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ 256 #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ 257 #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ 258 #define HID0_EMCP (1<<31) /* Enable Machine Check pin */ 259 #define HID0_EBA (1<<29) /* Enable Bus Address Parity */ 260 #define HID0_EBD (1<<28) /* Enable Bus Data Parity */ 261 #define HID0_SBCLK (1<<27) 262 #define HID0_EICE (1<<26) 263 #define HID0_TBEN (1<<26) /* Timebase enable - 745x */ 264 #define HID0_ECLK (1<<25) 265 #define HID0_PAR (1<<24) 266 #define HID0_STEN (1<<24) /* Software table search enable - 745x */ 267 #define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */ 268 #define HID0_DOZE (1<<23) 269 #define HID0_NAP (1<<22) 270 #define HID0_SLEEP (1<<21) 271 #define HID0_DPM (1<<20) 272 #define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */ 273 #define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */ 274 #define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/ 275 #define HID0_ICE (1<<15) /* Instruction Cache Enable */ 276 #define HID0_DCE (1<<14) /* Data Cache Enable */ 277 #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ 278 #define HID0_DLOCK (1<<12) /* Data Cache Lock */ 279 #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ 280 #define HID0_DCI (1<<10) /* Data Cache Invalidate */ 281 #define HID0_SPD (1<<9) /* Speculative disable */ 282 #define HID0_DAPUEN (1<<8) /* Debug APU enable */ 283 #define HID0_SGE (1<<7) /* Store Gathering Enable */ 284 #define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ 285 #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ 286 #define HID0_LRSTK (1<<4) /* Link register stack - 745x */ 287 #define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */ 288 #define HID0_ABE (1<<3) /* Address Broadcast Enable */ 289 #define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */ 290 #define HID0_BHTE (1<<2) /* Branch History Table Enable */ 291 #define HID0_BTCD (1<<1) /* Branch target cache disable */ 292 #define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */ 293 #define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */ 294 295 #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ 296 #ifdef CONFIG_6xx 297 #define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */ 298 #define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */ 299 #define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */ 300 #define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */ 301 #define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */ 302 #define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */ 303 #define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */ 304 #define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */ 305 #define HID1_PS (1<<16) /* 750FX PLL selection */ 306 #endif 307 #define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */ 308 #define SPRN_HID2_GEKKO 0x398 /* Gekko HID2 Register */ 309 #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ 310 #define SPRN_IABR2 0x3FA /* 83xx */ 311 #define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */ 312 #define SPRN_HID4 0x3F4 /* 970 HID4 */ 313 #define SPRN_HID4_GEKKO 0x3F3 /* Gekko HID4 */ 314 #define SPRN_HID5 0x3F6 /* 970 HID5 */ 315 #define SPRN_HID6 0x3F9 /* BE HID 6 */ 316 #define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */ 317 #define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */ 318 #define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */ 319 #define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */ 320 #define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */ 321 #define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */ 322 #define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */ 323 #define SPRN_TSC 0x3FD /* Thread switch control on others */ 324 #define SPRN_TST 0x3FC /* Thread switch timeout on others */ 325 #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2) 326 #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ 327 #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ 328 #endif 329 #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ 330 #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ 331 #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ 332 #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ 333 #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ 334 #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ 335 #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ 336 #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ 337 #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ 338 #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ 339 #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ 340 #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ 341 #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ 342 #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ 343 #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ 344 #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ 345 #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ 346 #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ 347 #define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */ 348 #define ICTRL_EICE 0x08000000 /* enable icache parity errs */ 349 #define ICTRL_EDC 0x04000000 /* enable dcache parity errs */ 350 #define ICTRL_EICP 0x00000100 /* enable icache par. check */ 351 #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ 352 #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ 353 #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ 354 #define SPRN_L2CR2 0x3f8 355 #define L2CR_L2E 0x80000000 /* L2 enable */ 356 #define L2CR_L2PE 0x40000000 /* L2 parity enable */ 357 #define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */ 358 #define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */ 359 #define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */ 360 #define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */ 361 #define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */ 362 #define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */ 363 #define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */ 364 #define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */ 365 #define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */ 366 #define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */ 367 #define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */ 368 #define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */ 369 #define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */ 370 #define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */ 371 #define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */ 372 #define L2CR_L2DO 0x00400000 /* L2 data only */ 373 #define L2CR_L2I 0x00200000 /* L2 global invalidate */ 374 #define L2CR_L2CTL 0x00100000 /* L2 RAM control */ 375 #define L2CR_L2WT 0x00080000 /* L2 write-through */ 376 #define L2CR_L2TS 0x00040000 /* L2 test support */ 377 #define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */ 378 #define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */ 379 #define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */ 380 #define L2CR_L2SL 0x00008000 /* L2 DLL slow */ 381 #define L2CR_L2DF 0x00004000 /* L2 differential clock */ 382 #define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */ 383 #define L2CR_L2IP 0x00000001 /* L2 GI in progress */ 384 #define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */ 385 #define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */ 386 #define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */ 387 #define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */ 388 #define SPRN_L3CR 0x3FA /* Level 3 Cache Control Regsiter */ 389 #define L3CR_L3E 0x80000000 /* L3 enable */ 390 #define L3CR_L3PE 0x40000000 /* L3 data parity enable */ 391 #define L3CR_L3APE 0x20000000 /* L3 addr parity enable */ 392 #define L3CR_L3SIZ 0x10000000 /* L3 size */ 393 #define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */ 394 #define L3CR_L3RES 0x04000000 /* L3 special reserved bit */ 395 #define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */ 396 #define L3CR_L3IO 0x00400000 /* L3 instruction only */ 397 #define L3CR_L3SPO 0x00040000 /* L3 sample point override */ 398 #define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */ 399 #define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */ 400 #define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */ 401 #define L3CR_L3HWF 0x00000800 /* L3 hardware flush */ 402 #define L3CR_L3I 0x00000400 /* L3 global invalidate */ 403 #define L3CR_L3RT 0x00000300 /* L3 SRAM type */ 404 #define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */ 405 #define L3CR_L3DO 0x00000040 /* L3 data only mode */ 406 #define L3CR_PMEN 0x00000004 /* L3 private memory enable */ 407 #define L3CR_PMSIZ 0x00000001 /* L3 private memory size */ 408 409 #define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */ 410 #define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */ 411 #define SPRN_LDSTCR 0x3f8 /* Load/Store control register */ 412 #define SPRN_LDSTDB 0x3f4 /* */ 413 #define SPRN_LR 0x008 /* Link Register */ 414 #ifndef SPRN_PIR 415 #define SPRN_PIR 0x3FF /* Processor Identification Register */ 416 #endif 417 #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ 418 #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ 419 #define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */ 420 #define SPRN_PVR 0x11F /* Processor Version Register */ 421 #define SPRN_RPA 0x3D6 /* Required Physical Address Register */ 422 #define SPRN_SDA 0x3BF /* Sampled Data Address Register */ 423 #define SPRN_SDR1 0x019 /* MMU Hash Base Register */ 424 #define SPRN_ASR 0x118 /* Address Space Register */ 425 #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ 426 #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ 427 #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ 428 #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ 429 #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ 430 #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ 431 #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ 432 #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ 433 #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ 434 #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ 435 #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ 436 #define SRR1_WAKEMASK 0x00380000 /* reason for wakeup */ 437 #define SRR1_WAKERESET 0x00380000 /* System reset */ 438 #define SRR1_WAKESYSERR 0x00300000 /* System error */ 439 #define SRR1_WAKEEE 0x00200000 /* External interrupt */ 440 #define SRR1_WAKEMT 0x00280000 /* mtctrl */ 441 #define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */ 442 #define SRR1_WAKETHERM 0x00100000 /* Thermal management interrupt */ 443 #define SRR1_PROGFPE 0x00100000 /* Floating Point Enabled */ 444 #define SRR1_PROGPRIV 0x00040000 /* Privileged instruction */ 445 #define SRR1_PROGTRAP 0x00020000 /* Trap */ 446 #define SRR1_PROGADDR 0x00010000 /* SRR0 contains subsequent addr */ 447 #define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */ 448 #define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */ 449 450 #define SPRN_TBCTL 0x35f /* PA6T Timebase control register */ 451 #define TBCTL_FREEZE 0x0000000000000000ull /* Freeze all tbs */ 452 #define TBCTL_RESTART 0x0000000100000000ull /* Restart all tbs */ 453 #define TBCTL_UPDATE_UPPER 0x0000000200000000ull /* Set upper 32 bits */ 454 #define TBCTL_UPDATE_LOWER 0x0000000300000000ull /* Set lower 32 bits */ 455 456 #ifndef SPRN_SVR 457 #define SPRN_SVR 0x11E /* System Version Register */ 458 #endif 459 #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ 460 /* these bits were defined in inverted endian sense originally, ugh, confusing */ 461 #define THRM1_TIN (1 << 31) 462 #define THRM1_TIV (1 << 30) 463 #define THRM1_THRES(x) ((x&0x7f)<<23) 464 #define THRM3_SITV(x) ((x&0x3fff)<<1) 465 #define THRM1_TID (1<<2) 466 #define THRM1_TIE (1<<1) 467 #define THRM1_V (1<<0) 468 #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ 469 #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ 470 #define THRM3_E (1<<0) 471 #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ 472 #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ 473 #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ 474 #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ 475 #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ 476 #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ 477 #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ 478 #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ 479 #define SPRN_VRSAVE 0x100 /* Vector Register Save Register */ 480 #define SPRN_XER 0x001 /* Fixed Point Exception Register */ 481 482 #define SPRN_MMCR0_GEKKO 0x3B8 /* Gekko Monitor Mode Control Register 0 */ 483 #define SPRN_MMCR1_GEKKO 0x3BC /* Gekko Monitor Mode Control Register 1 */ 484 #define SPRN_PMC1_GEKKO 0x3B9 /* Gekko Performance Monitor Control 1 */ 485 #define SPRN_PMC2_GEKKO 0x3BA /* Gekko Performance Monitor Control 2 */ 486 #define SPRN_PMC3_GEKKO 0x3BD /* Gekko Performance Monitor Control 3 */ 487 #define SPRN_PMC4_GEKKO 0x3BE /* Gekko Performance Monitor Control 4 */ 488 #define SPRN_WPAR_GEKKO 0x399 /* Gekko Write Pipe Address Register */ 489 490 #define SPRN_SCOMC 0x114 /* SCOM Access Control */ 491 #define SPRN_SCOMD 0x115 /* SCOM Access DATA */ 492 493 /* Performance monitor SPRs */ 494 #ifdef CONFIG_PPC64 495 #define SPRN_MMCR0 795 496 #define MMCR0_FC 0x80000000UL /* freeze counters */ 497 #define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */ 498 #define MMCR0_KERNEL_DISABLE MMCR0_FCS 499 #define MMCR0_FCP 0x20000000UL /* freeze in problem state */ 500 #define MMCR0_PROBLEM_DISABLE MMCR0_FCP 501 #define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */ 502 #define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */ 503 #define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */ 504 #define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */ 505 #define MMCR0_TBEE 0x00400000UL /* time base exception enable */ 506 #define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ 507 #define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/ 508 #define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ 509 #define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */ 510 #define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */ 511 #define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */ 512 #define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */ 513 #define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */ 514 #define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */ 515 #define SPRN_MMCR1 798 516 #define SPRN_MMCRA 0x312 517 #define MMCRA_SDSYNC 0x80000000UL /* SDAR synced with SIAR */ 518 #define MMCRA_SDAR_DCACHE_MISS 0x40000000UL 519 #define MMCRA_SDAR_ERAT_MISS 0x20000000UL 520 #define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */ 521 #define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */ 522 #define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */ 523 #define MMCRA_SLOT_SHIFT 24 524 #define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */ 525 #define POWER6_MMCRA_SDSYNC 0x0000080000000000ULL /* SDAR/SIAR synced */ 526 #define POWER6_MMCRA_SIHV 0x0000040000000000ULL 527 #define POWER6_MMCRA_SIPR 0x0000020000000000ULL 528 #define POWER6_MMCRA_THRM 0x00000020UL 529 #define POWER6_MMCRA_OTHER 0x0000000EUL 530 #define SPRN_PMC1 787 531 #define SPRN_PMC2 788 532 #define SPRN_PMC3 789 533 #define SPRN_PMC4 790 534 #define SPRN_PMC5 791 535 #define SPRN_PMC6 792 536 #define SPRN_PMC7 793 537 #define SPRN_PMC8 794 538 #define SPRN_SIAR 780 539 #define SPRN_SDAR 781 540 541 #define SPRN_PA6T_MMCR0 795 542 #define PA6T_MMCR0_EN0 0x0000000000000001UL 543 #define PA6T_MMCR0_EN1 0x0000000000000002UL 544 #define PA6T_MMCR0_EN2 0x0000000000000004UL 545 #define PA6T_MMCR0_EN3 0x0000000000000008UL 546 #define PA6T_MMCR0_EN4 0x0000000000000010UL 547 #define PA6T_MMCR0_EN5 0x0000000000000020UL 548 #define PA6T_MMCR0_SUPEN 0x0000000000000040UL 549 #define PA6T_MMCR0_PREN 0x0000000000000080UL 550 #define PA6T_MMCR0_HYPEN 0x0000000000000100UL 551 #define PA6T_MMCR0_FCM0 0x0000000000000200UL 552 #define PA6T_MMCR0_FCM1 0x0000000000000400UL 553 #define PA6T_MMCR0_INTGEN 0x0000000000000800UL 554 #define PA6T_MMCR0_INTEN0 0x0000000000001000UL 555 #define PA6T_MMCR0_INTEN1 0x0000000000002000UL 556 #define PA6T_MMCR0_INTEN2 0x0000000000004000UL 557 #define PA6T_MMCR0_INTEN3 0x0000000000008000UL 558 #define PA6T_MMCR0_INTEN4 0x0000000000010000UL 559 #define PA6T_MMCR0_INTEN5 0x0000000000020000UL 560 #define PA6T_MMCR0_DISCNT 0x0000000000040000UL 561 #define PA6T_MMCR0_UOP 0x0000000000080000UL 562 #define PA6T_MMCR0_TRG 0x0000000000100000UL 563 #define PA6T_MMCR0_TRGEN 0x0000000000200000UL 564 #define PA6T_MMCR0_TRGREG 0x0000000001600000UL 565 #define PA6T_MMCR0_SIARLOG 0x0000000002000000UL 566 #define PA6T_MMCR0_SDARLOG 0x0000000004000000UL 567 #define PA6T_MMCR0_PROEN 0x0000000008000000UL 568 #define PA6T_MMCR0_PROLOG 0x0000000010000000UL 569 #define PA6T_MMCR0_DAMEN2 0x0000000020000000UL 570 #define PA6T_MMCR0_DAMEN3 0x0000000040000000UL 571 #define PA6T_MMCR0_DAMEN4 0x0000000080000000UL 572 #define PA6T_MMCR0_DAMEN5 0x0000000100000000UL 573 #define PA6T_MMCR0_DAMSEL2 0x0000000200000000UL 574 #define PA6T_MMCR0_DAMSEL3 0x0000000400000000UL 575 #define PA6T_MMCR0_DAMSEL4 0x0000000800000000UL 576 #define PA6T_MMCR0_DAMSEL5 0x0000001000000000UL 577 #define PA6T_MMCR0_HANDDIS 0x0000002000000000UL 578 #define PA6T_MMCR0_PCTEN 0x0000004000000000UL 579 #define PA6T_MMCR0_SOCEN 0x0000008000000000UL 580 #define PA6T_MMCR0_SOCMOD 0x0000010000000000UL 581 582 #define SPRN_PA6T_MMCR1 798 583 #define PA6T_MMCR1_ES2 0x00000000000000ffUL 584 #define PA6T_MMCR1_ES3 0x000000000000ff00UL 585 #define PA6T_MMCR1_ES4 0x0000000000ff0000UL 586 #define PA6T_MMCR1_ES5 0x00000000ff000000UL 587 588 #define SPRN_PA6T_UPMC0 771 /* User PerfMon Counter 0 */ 589 #define SPRN_PA6T_UPMC1 772 /* ... */ 590 #define SPRN_PA6T_UPMC2 773 591 #define SPRN_PA6T_UPMC3 774 592 #define SPRN_PA6T_UPMC4 775 593 #define SPRN_PA6T_UPMC5 776 594 #define SPRN_PA6T_UMMCR0 779 /* User Monitor Mode Control Register 0 */ 595 #define SPRN_PA6T_SIAR 780 /* Sampled Instruction Address */ 596 #define SPRN_PA6T_UMMCR1 782 /* User Monitor Mode Control Register 1 */ 597 #define SPRN_PA6T_SIER 785 /* Sampled Instruction Event Register */ 598 #define SPRN_PA6T_PMC0 787 599 #define SPRN_PA6T_PMC1 788 600 #define SPRN_PA6T_PMC2 789 601 #define SPRN_PA6T_PMC3 790 602 #define SPRN_PA6T_PMC4 791 603 #define SPRN_PA6T_PMC5 792 604 #define SPRN_PA6T_TSR0 793 /* Timestamp Register 0 */ 605 #define SPRN_PA6T_TSR1 794 /* Timestamp Register 1 */ 606 #define SPRN_PA6T_TSR2 799 /* Timestamp Register 2 */ 607 #define SPRN_PA6T_TSR3 784 /* Timestamp Register 3 */ 608 609 #define SPRN_PA6T_IER 981 /* Icache Error Register */ 610 #define SPRN_PA6T_DER 982 /* Dcache Error Register */ 611 #define SPRN_PA6T_BER 862 /* BIU Error Address Register */ 612 #define SPRN_PA6T_MER 849 /* MMU Error Register */ 613 614 #define SPRN_PA6T_IMA0 880 /* Instruction Match Array 0 */ 615 #define SPRN_PA6T_IMA1 881 /* ... */ 616 #define SPRN_PA6T_IMA2 882 617 #define SPRN_PA6T_IMA3 883 618 #define SPRN_PA6T_IMA4 884 619 #define SPRN_PA6T_IMA5 885 620 #define SPRN_PA6T_IMA6 886 621 #define SPRN_PA6T_IMA7 887 622 #define SPRN_PA6T_IMA8 888 623 #define SPRN_PA6T_IMA9 889 624 #define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */ 625 #define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */ 626 #define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */ 627 #define SPRN_BKMK 1020 /* Cell Bookmark Register */ 628 #define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */ 629 630 631 #else /* 32-bit */ 632 #define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */ 633 #define MMCR0_FC 0x80000000UL /* freeze counters */ 634 #define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */ 635 #define MMCR0_FCP 0x20000000UL /* freeze in problem state */ 636 #define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */ 637 #define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */ 638 #define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */ 639 #define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */ 640 #define MMCR0_TBEE 0x00400000UL /* time base exception enable */ 641 #define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/ 642 #define MMCR0_PMCnCE 0x00004000UL /* count enable for all but PMC 1*/ 643 #define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */ 644 #define MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */ 645 #define MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */ 646 647 #define SPRN_MMCR1 956 648 #define MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */ 649 #define MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */ 650 #define MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */ 651 #define MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */ 652 #define SPRN_MMCR2 944 653 #define SPRN_PMC1 953 /* Performance Counter Register 1 */ 654 #define SPRN_PMC2 954 /* Performance Counter Register 2 */ 655 #define SPRN_PMC3 957 /* Performance Counter Register 3 */ 656 #define SPRN_PMC4 958 /* Performance Counter Register 4 */ 657 #define SPRN_PMC5 945 /* Performance Counter Register 5 */ 658 #define SPRN_PMC6 946 /* Performance Counter Register 6 */ 659 660 #define SPRN_SIAR 955 /* Sampled Instruction Address Register */ 661 662 /* Bit definitions for MMCR0 and PMC1 / PMC2. */ 663 #define MMCR0_PMC1_CYCLES (1 << 7) 664 #define MMCR0_PMC1_ICACHEMISS (5 << 7) 665 #define MMCR0_PMC1_DTLB (6 << 7) 666 #define MMCR0_PMC2_DCACHEMISS 0x6 667 #define MMCR0_PMC2_CYCLES 0x1 668 #define MMCR0_PMC2_ITLB 0x7 669 #define MMCR0_PMC2_LOADMISSTIME 0x5 670 #endif 671 672 /* 673 * SPRG usage: 674 * 675 * All 64-bit: 676 * - SPRG1 stores PACA pointer 677 * 678 * 64-bit server: 679 * - SPRG0 unused (reserved for HV on Power4) 680 * - SPRG2 scratch for exception vectors 681 * - SPRG3 unused (user visible) 682 * 683 * 64-bit embedded 684 * - SPRG0 generic exception scratch 685 * - SPRG2 TLB exception stack 686 * - SPRG3 unused (user visible) 687 * - SPRG4 unused (user visible) 688 * - SPRG6 TLB miss scratch (user visible, sorry !) 689 * - SPRG7 critical exception scratch 690 * - SPRG8 machine check exception scratch 691 * - SPRG9 debug exception scratch 692 * 693 * All 32-bit: 694 * - SPRG3 current thread_info pointer 695 * (virtual on BookE, physical on others) 696 * 697 * 32-bit classic: 698 * - SPRG0 scratch for exception vectors 699 * - SPRG1 scratch for exception vectors 700 * - SPRG2 indicator that we are in RTAS 701 * - SPRG4 (603 only) pseudo TLB LRU data 702 * 703 * 32-bit 40x: 704 * - SPRG0 scratch for exception vectors 705 * - SPRG1 scratch for exception vectors 706 * - SPRG2 scratch for exception vectors 707 * - SPRG4 scratch for exception vectors (not 403) 708 * - SPRG5 scratch for exception vectors (not 403) 709 * - SPRG6 scratch for exception vectors (not 403) 710 * - SPRG7 scratch for exception vectors (not 403) 711 * 712 * 32-bit 440 and FSL BookE: 713 * - SPRG0 scratch for exception vectors 714 * - SPRG1 scratch for exception vectors (*) 715 * - SPRG2 scratch for crit interrupts handler 716 * - SPRG4 scratch for exception vectors 717 * - SPRG5 scratch for exception vectors 718 * - SPRG6 scratch for machine check handler 719 * - SPRG7 scratch for exception vectors 720 * - SPRG9 scratch for debug vectors (e500 only) 721 * 722 * Additionally, BookE separates "read" and "write" 723 * of those registers. That allows to use the userspace 724 * readable variant for reads, which can avoid a fault 725 * with KVM type virtualization. 726 * 727 * (*) Under KVM, the host SPRG1 is used to point to 728 * the current VCPU data structure 729 * 730 * 32-bit 8xx: 731 * - SPRG0 scratch for exception vectors 732 * - SPRG1 scratch for exception vectors 733 * - SPRG2 apparently unused but initialized 734 * 735 */ 736 #ifdef CONFIG_PPC64 737 #define SPRN_SPRG_PACA SPRN_SPRG1 738 #else 739 #define SPRN_SPRG_THREAD SPRN_SPRG3 740 #endif 741 742 #ifdef CONFIG_PPC_BOOK3S_64 743 #define SPRN_SPRG_SCRATCH0 SPRN_SPRG2 744 #endif 745 746 #ifdef CONFIG_PPC_BOOK3E_64 747 #define SPRN_SPRG_MC_SCRATCH SPRN_SPRG8 748 #define SPRN_SPRG_CRIT_SCRATCH SPRN_SPRG7 749 #define SPRN_SPRG_DBG_SCRATCH SPRN_SPRG9 750 #define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2 751 #define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6 752 #define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0 753 #endif 754 755 #ifdef CONFIG_PPC_BOOK3S_32 756 #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 757 #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 758 #define SPRN_SPRG_RTAS SPRN_SPRG2 759 #define SPRN_SPRG_603_LRU SPRN_SPRG4 760 #endif 761 762 #ifdef CONFIG_40x 763 #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 764 #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 765 #define SPRN_SPRG_SCRATCH2 SPRN_SPRG2 766 #define SPRN_SPRG_SCRATCH3 SPRN_SPRG4 767 #define SPRN_SPRG_SCRATCH4 SPRN_SPRG5 768 #define SPRN_SPRG_SCRATCH5 SPRN_SPRG6 769 #define SPRN_SPRG_SCRATCH6 SPRN_SPRG7 770 #endif 771 772 #ifdef CONFIG_BOOKE 773 #define SPRN_SPRG_RSCRATCH0 SPRN_SPRG0 774 #define SPRN_SPRG_WSCRATCH0 SPRN_SPRG0 775 #define SPRN_SPRG_RSCRATCH1 SPRN_SPRG1 776 #define SPRN_SPRG_WSCRATCH1 SPRN_SPRG1 777 #define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2 778 #define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2 779 #define SPRN_SPRG_RSCRATCH2 SPRN_SPRG4R 780 #define SPRN_SPRG_WSCRATCH2 SPRN_SPRG4W 781 #define SPRN_SPRG_RSCRATCH3 SPRN_SPRG5R 782 #define SPRN_SPRG_WSCRATCH3 SPRN_SPRG5W 783 #define SPRN_SPRG_RSCRATCH_MC SPRN_SPRG6R 784 #define SPRN_SPRG_WSCRATCH_MC SPRN_SPRG6W 785 #define SPRN_SPRG_RSCRATCH4 SPRN_SPRG7R 786 #define SPRN_SPRG_WSCRATCH4 SPRN_SPRG7W 787 #ifdef CONFIG_E200 788 #define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG6R 789 #define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG6W 790 #else 791 #define SPRN_SPRG_RSCRATCH_DBG SPRN_SPRG9 792 #define SPRN_SPRG_WSCRATCH_DBG SPRN_SPRG9 793 #endif 794 #define SPRN_SPRG_RVCPU SPRN_SPRG1 795 #define SPRN_SPRG_WVCPU SPRN_SPRG1 796 #endif 797 798 #ifdef CONFIG_8xx 799 #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 800 #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 801 #endif 802 803 /* 804 * An mtfsf instruction with the L bit set. On CPUs that support this a 805 * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored. 806 * 807 * Until binutils gets the new form of mtfsf, hardwire the instruction. 808 */ 809 #ifdef CONFIG_PPC64 810 #define MTFSF_L(REG) \ 811 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25)) 812 #else 813 #define MTFSF_L(REG) mtfsf 0xff, (REG) 814 #endif 815 816 /* Processor Version Register (PVR) field extraction */ 817 818 #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ 819 #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ 820 821 #define __is_processor(pv) (PVR_VER(mfspr(SPRN_PVR)) == (pv)) 822 823 /* 824 * IBM has further subdivided the standard PowerPC 16-bit version and 825 * revision subfields of the PVR for the PowerPC 403s into the following: 826 */ 827 828 #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ 829 #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ 830 #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ 831 #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ 832 #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ 833 #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ 834 835 /* Processor Version Numbers */ 836 837 #define PVR_403GA 0x00200000 838 #define PVR_403GB 0x00200100 839 #define PVR_403GC 0x00200200 840 #define PVR_403GCX 0x00201400 841 #define PVR_405GP 0x40110000 842 #define PVR_476 0x11a52000 843 #define PVR_STB03XXX 0x40310000 844 #define PVR_NP405H 0x41410000 845 #define PVR_NP405L 0x41610000 846 #define PVR_601 0x00010000 847 #define PVR_602 0x00050000 848 #define PVR_603 0x00030000 849 #define PVR_603e 0x00060000 850 #define PVR_603ev 0x00070000 851 #define PVR_603r 0x00071000 852 #define PVR_604 0x00040000 853 #define PVR_604e 0x00090000 854 #define PVR_604r 0x000A0000 855 #define PVR_620 0x00140000 856 #define PVR_740 0x00080000 857 #define PVR_750 PVR_740 858 #define PVR_740P 0x10080000 859 #define PVR_750P PVR_740P 860 #define PVR_7400 0x000C0000 861 #define PVR_7410 0x800C0000 862 #define PVR_7450 0x80000000 863 #define PVR_8540 0x80200000 864 #define PVR_8560 0x80200000 865 #define PVR_VER_E500V1 0x8020 866 #define PVR_VER_E500V2 0x8021 867 /* 868 * For the 8xx processors, all of them report the same PVR family for 869 * the PowerPC core. The various versions of these processors must be 870 * differentiated by the version number in the Communication Processor 871 * Module (CPM). 872 */ 873 #define PVR_821 0x00500000 874 #define PVR_823 PVR_821 875 #define PVR_850 PVR_821 876 #define PVR_860 PVR_821 877 #define PVR_8240 0x00810100 878 #define PVR_8245 0x80811014 879 #define PVR_8260 PVR_8240 880 881 /* 476 Simulator seems to currently have the PVR of the 602... */ 882 #define PVR_476_ISS 0x00052000 883 884 /* 64-bit processors */ 885 /* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */ 886 #define PV_NORTHSTAR 0x0033 887 #define PV_PULSAR 0x0034 888 #define PV_POWER4 0x0035 889 #define PV_ICESTAR 0x0036 890 #define PV_SSTAR 0x0037 891 #define PV_POWER4p 0x0038 892 #define PV_970 0x0039 893 #define PV_POWER5 0x003A 894 #define PV_POWER5p 0x003B 895 #define PV_POWER7 0x003F 896 #define PV_970FX 0x003C 897 #define PV_630 0x0040 898 #define PV_630p 0x0041 899 #define PV_970MP 0x0044 900 #define PV_970GX 0x0045 901 #define PV_BE 0x0070 902 #define PV_PA6T 0x0090 903 904 /* Macros for setting and retrieving special purpose registers */ 905 #ifndef __ASSEMBLY__ 906 #define mfmsr() ({unsigned long rval; \ 907 asm volatile("mfmsr %0" : "=r" (rval)); rval;}) 908 #ifdef CONFIG_PPC_BOOK3S_64 909 #define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \ 910 : : "r" (v) : "memory") 911 #define mtmsrd(v) __mtmsrd((v), 0) 912 #define mtmsr(v) mtmsrd(v) 913 #else 914 #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v) : "memory") 915 #endif 916 917 #define mfspr(rn) ({unsigned long rval; \ 918 asm volatile("mfspr %0," __stringify(rn) \ 919 : "=r" (rval)); rval;}) 920 #define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)\ 921 : "memory") 922 923 #ifdef __powerpc64__ 924 #ifdef CONFIG_PPC_CELL 925 #define mftb() ({unsigned long rval; \ 926 asm volatile( \ 927 "90: mftb %0;\n" \ 928 "97: cmpwi %0,0;\n" \ 929 " beq- 90b;\n" \ 930 "99:\n" \ 931 ".section __ftr_fixup,\"a\"\n" \ 932 ".align 3\n" \ 933 "98:\n" \ 934 " .llong %1\n" \ 935 " .llong %1\n" \ 936 " .llong 97b-98b\n" \ 937 " .llong 99b-98b\n" \ 938 " .llong 0\n" \ 939 " .llong 0\n" \ 940 ".previous" \ 941 : "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG)); rval;}) 942 #else 943 #define mftb() ({unsigned long rval; \ 944 asm volatile("mftb %0" : "=r" (rval)); rval;}) 945 #endif /* !CONFIG_PPC_CELL */ 946 947 #else /* __powerpc64__ */ 948 949 #define mftbl() ({unsigned long rval; \ 950 asm volatile("mftbl %0" : "=r" (rval)); rval;}) 951 #define mftbu() ({unsigned long rval; \ 952 asm volatile("mftbu %0" : "=r" (rval)); rval;}) 953 #endif /* !__powerpc64__ */ 954 955 #define mttbl(v) asm volatile("mttbl %0":: "r"(v)) 956 #define mttbu(v) asm volatile("mttbu %0":: "r"(v)) 957 958 #ifdef CONFIG_PPC32 959 #define mfsrin(v) ({unsigned int rval; \ 960 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \ 961 rval;}) 962 #endif 963 964 #define proc_trap() asm volatile("trap") 965 966 #ifdef CONFIG_PPC64 967 968 extern void ppc64_runlatch_on(void); 969 extern void __ppc64_runlatch_off(void); 970 971 #define ppc64_runlatch_off() \ 972 do { \ 973 if (cpu_has_feature(CPU_FTR_CTRL) && \ 974 test_thread_flag(TIF_RUNLATCH)) \ 975 __ppc64_runlatch_off(); \ 976 } while (0) 977 978 extern unsigned long scom970_read(unsigned int address); 979 extern void scom970_write(unsigned int address, unsigned long value); 980 981 #else 982 #define ppc64_runlatch_on() 983 #define ppc64_runlatch_off() 984 985 #endif /* CONFIG_PPC64 */ 986 987 #define __get_SP() ({unsigned long sp; \ 988 asm volatile("mr %0,1": "=r" (sp)); sp;}) 989 990 struct pt_regs; 991 992 extern void ppc_save_regs(struct pt_regs *regs); 993 994 #endif /* __ASSEMBLY__ */ 995 #endif /* __KERNEL__ */ 996 #endif /* _ASM_POWERPC_REG_H */ 997