1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2005-2009 Cavium Networks 7 */ 8 9 #ifndef __PCI_OCTEON_H__ 10 #define __PCI_OCTEON_H__ 11 12 #include <linux/pci.h> 13 14 /* Some PCI cards require delays when accessing config space. */ 15 #define PCI_CONFIG_SPACE_DELAY 10000 16 17 /* 18 * The physical memory base mapped by BAR1. 256MB at the end of the 19 * first 4GB. 20 */ 21 #define CVMX_PCIE_BAR1_PHYS_BASE ((1ull << 32) - (1ull << 28)) 22 #define CVMX_PCIE_BAR1_PHYS_SIZE (1ull << 28) 23 24 /* 25 * The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2, 26 * place BAR1 so it is the same for both. 27 */ 28 #define CVMX_PCIE_BAR1_RC_BASE (1ull << 41) 29 30 /* 31 * pcibios_map_irq() is defined inside pci-octeon.c. All it does is 32 * call the Octeon specific version pointed to by this variable. This 33 * function needs to change for PCI or PCIe based hosts. 34 */ 35 extern int (*octeon_pcibios_map_irq)(const struct pci_dev *dev, 36 u8 slot, u8 pin); 37 38 /* 39 * For PCI (not PCIe) the BAR2 base address. 40 */ 41 #define OCTEON_BAR2_PCI_ADDRESS 0x8000000000ull 42 43 /* 44 * For PCI (not PCIe) the base of the memory mapped by BAR1 45 */ 46 extern u64 octeon_bar1_pci_phys; 47 48 /* 49 * The following defines are used when octeon_dma_bar_type = 50 * OCTEON_DMA_BAR_TYPE_BIG 51 */ 52 #define OCTEON_PCI_BAR1_HOLE_BITS 5 53 #define OCTEON_PCI_BAR1_HOLE_SIZE (1ul<<(OCTEON_PCI_BAR1_HOLE_BITS+3)) 54 55 enum octeon_dma_bar_type { 56 OCTEON_DMA_BAR_TYPE_INVALID, 57 OCTEON_DMA_BAR_TYPE_SMALL, 58 OCTEON_DMA_BAR_TYPE_BIG, 59 OCTEON_DMA_BAR_TYPE_PCIE 60 }; 61 62 /* 63 * This tells the DMA mapping system in dma-octeon.c how to map PCI 64 * DMA addresses. 65 */ 66 extern enum octeon_dma_bar_type octeon_dma_bar_type; 67 68 #endif 69