1 #ifndef BCM63XX_REGS_H_ 2 #define BCM63XX_REGS_H_ 3 4 /************************************************************************* 5 * _REG relative to RSET_PERF 6 *************************************************************************/ 7 8 /* Chip Identifier / Revision register */ 9 #define PERF_REV_REG 0x0 10 #define REV_CHIPID_SHIFT 16 11 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) 12 #define REV_REVID_SHIFT 0 13 #define REV_REVID_MASK (0xffff << REV_REVID_SHIFT) 14 15 /* Clock Control register */ 16 #define PERF_CKCTL_REG 0x4 17 18 #define CKCTL_6338_ADSLPHY_EN (1 << 0) 19 #define CKCTL_6338_MPI_EN (1 << 1) 20 #define CKCTL_6338_DRAM_EN (1 << 2) 21 #define CKCTL_6338_ENET_EN (1 << 4) 22 #define CKCTL_6338_USBS_EN (1 << 4) 23 #define CKCTL_6338_SAR_EN (1 << 5) 24 #define CKCTL_6338_SPI_EN (1 << 9) 25 26 #define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \ 27 CKCTL_6338_MPI_EN | \ 28 CKCTL_6338_ENET_EN | \ 29 CKCTL_6338_SAR_EN | \ 30 CKCTL_6338_SPI_EN) 31 32 #define CKCTL_6345_CPU_EN (1 << 0) 33 #define CKCTL_6345_BUS_EN (1 << 1) 34 #define CKCTL_6345_EBI_EN (1 << 2) 35 #define CKCTL_6345_UART_EN (1 << 3) 36 #define CKCTL_6345_ADSLPHY_EN (1 << 4) 37 #define CKCTL_6345_ENET_EN (1 << 7) 38 #define CKCTL_6345_USBH_EN (1 << 8) 39 40 #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \ 41 CKCTL_6345_USBH_EN | \ 42 CKCTL_6345_ADSLPHY_EN) 43 44 #define CKCTL_6348_ADSLPHY_EN (1 << 0) 45 #define CKCTL_6348_MPI_EN (1 << 1) 46 #define CKCTL_6348_SDRAM_EN (1 << 2) 47 #define CKCTL_6348_M2M_EN (1 << 3) 48 #define CKCTL_6348_ENET_EN (1 << 4) 49 #define CKCTL_6348_SAR_EN (1 << 5) 50 #define CKCTL_6348_USBS_EN (1 << 6) 51 #define CKCTL_6348_USBH_EN (1 << 8) 52 #define CKCTL_6348_SPI_EN (1 << 9) 53 54 #define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \ 55 CKCTL_6348_M2M_EN | \ 56 CKCTL_6348_ENET_EN | \ 57 CKCTL_6348_SAR_EN | \ 58 CKCTL_6348_USBS_EN | \ 59 CKCTL_6348_USBH_EN | \ 60 CKCTL_6348_SPI_EN) 61 62 #define CKCTL_6358_ENET_EN (1 << 4) 63 #define CKCTL_6358_ADSLPHY_EN (1 << 5) 64 #define CKCTL_6358_PCM_EN (1 << 8) 65 #define CKCTL_6358_SPI_EN (1 << 9) 66 #define CKCTL_6358_USBS_EN (1 << 10) 67 #define CKCTL_6358_SAR_EN (1 << 11) 68 #define CKCTL_6358_EMUSB_EN (1 << 17) 69 #define CKCTL_6358_ENET0_EN (1 << 18) 70 #define CKCTL_6358_ENET1_EN (1 << 19) 71 #define CKCTL_6358_USBSU_EN (1 << 20) 72 #define CKCTL_6358_EPHY_EN (1 << 21) 73 74 #define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \ 75 CKCTL_6358_ADSLPHY_EN | \ 76 CKCTL_6358_PCM_EN | \ 77 CKCTL_6358_SPI_EN | \ 78 CKCTL_6358_USBS_EN | \ 79 CKCTL_6358_SAR_EN | \ 80 CKCTL_6358_EMUSB_EN | \ 81 CKCTL_6358_ENET0_EN | \ 82 CKCTL_6358_ENET1_EN | \ 83 CKCTL_6358_USBSU_EN | \ 84 CKCTL_6358_EPHY_EN) 85 86 /* System PLL Control register */ 87 #define PERF_SYS_PLL_CTL_REG 0x8 88 #define SYS_PLL_SOFT_RESET 0x1 89 90 /* Interrupt Mask register */ 91 #define PERF_IRQMASK_REG 0xc 92 #define PERF_IRQSTAT_REG 0x10 93 94 /* Interrupt Status register */ 95 #define PERF_IRQSTAT_REG 0x10 96 97 /* External Interrupt Configuration register */ 98 #define PERF_EXTIRQ_CFG_REG 0x14 99 #define EXTIRQ_CFG_SENSE(x) (1 << (x)) 100 #define EXTIRQ_CFG_STAT(x) (1 << (x + 5)) 101 #define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10)) 102 #define EXTIRQ_CFG_MASK(x) (1 << (x + 15)) 103 #define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20)) 104 #define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25)) 105 106 #define EXTIRQ_CFG_CLEAR_ALL (0xf << 10) 107 #define EXTIRQ_CFG_MASK_ALL (0xf << 15) 108 109 /* Soft Reset register */ 110 #define PERF_SOFTRESET_REG 0x28 111 112 #define SOFTRESET_6338_SPI_MASK (1 << 0) 113 #define SOFTRESET_6338_ENET_MASK (1 << 2) 114 #define SOFTRESET_6338_USBH_MASK (1 << 3) 115 #define SOFTRESET_6338_USBS_MASK (1 << 4) 116 #define SOFTRESET_6338_ADSL_MASK (1 << 5) 117 #define SOFTRESET_6338_DMAMEM_MASK (1 << 6) 118 #define SOFTRESET_6338_SAR_MASK (1 << 7) 119 #define SOFTRESET_6338_ACLC_MASK (1 << 8) 120 #define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10) 121 #define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \ 122 SOFTRESET_6338_ENET_MASK | \ 123 SOFTRESET_6338_USBH_MASK | \ 124 SOFTRESET_6338_USBS_MASK | \ 125 SOFTRESET_6338_ADSL_MASK | \ 126 SOFTRESET_6338_DMAMEM_MASK | \ 127 SOFTRESET_6338_SAR_MASK | \ 128 SOFTRESET_6338_ACLC_MASK | \ 129 SOFTRESET_6338_ADSLMIPSPLL_MASK) 130 131 #define SOFTRESET_6348_SPI_MASK (1 << 0) 132 #define SOFTRESET_6348_ENET_MASK (1 << 2) 133 #define SOFTRESET_6348_USBH_MASK (1 << 3) 134 #define SOFTRESET_6348_USBS_MASK (1 << 4) 135 #define SOFTRESET_6348_ADSL_MASK (1 << 5) 136 #define SOFTRESET_6348_DMAMEM_MASK (1 << 6) 137 #define SOFTRESET_6348_SAR_MASK (1 << 7) 138 #define SOFTRESET_6348_ACLC_MASK (1 << 8) 139 #define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10) 140 141 #define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \ 142 SOFTRESET_6348_ENET_MASK | \ 143 SOFTRESET_6348_USBH_MASK | \ 144 SOFTRESET_6348_USBS_MASK | \ 145 SOFTRESET_6348_ADSL_MASK | \ 146 SOFTRESET_6348_DMAMEM_MASK | \ 147 SOFTRESET_6348_SAR_MASK | \ 148 SOFTRESET_6348_ACLC_MASK | \ 149 SOFTRESET_6348_ADSLMIPSPLL_MASK) 150 151 /* MIPS PLL control register */ 152 #define PERF_MIPSPLLCTL_REG 0x34 153 #define MIPSPLLCTL_N1_SHIFT 20 154 #define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT) 155 #define MIPSPLLCTL_N2_SHIFT 15 156 #define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT) 157 #define MIPSPLLCTL_M1REF_SHIFT 12 158 #define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT) 159 #define MIPSPLLCTL_M2REF_SHIFT 9 160 #define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT) 161 #define MIPSPLLCTL_M1CPU_SHIFT 6 162 #define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT) 163 #define MIPSPLLCTL_M1BUS_SHIFT 3 164 #define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT) 165 #define MIPSPLLCTL_M2BUS_SHIFT 0 166 #define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT) 167 168 /* ADSL PHY PLL Control register */ 169 #define PERF_ADSLPLLCTL_REG 0x38 170 #define ADSLPLLCTL_N1_SHIFT 20 171 #define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT) 172 #define ADSLPLLCTL_N2_SHIFT 15 173 #define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT) 174 #define ADSLPLLCTL_M1REF_SHIFT 12 175 #define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT) 176 #define ADSLPLLCTL_M2REF_SHIFT 9 177 #define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT) 178 #define ADSLPLLCTL_M1CPU_SHIFT 6 179 #define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT) 180 #define ADSLPLLCTL_M1BUS_SHIFT 3 181 #define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT) 182 #define ADSLPLLCTL_M2BUS_SHIFT 0 183 #define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT) 184 185 #define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus) \ 186 (((n1) << ADSLPLLCTL_N1_SHIFT) | \ 187 ((n2) << ADSLPLLCTL_N2_SHIFT) | \ 188 ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \ 189 ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \ 190 ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \ 191 ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \ 192 ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT)) 193 194 195 /************************************************************************* 196 * _REG relative to RSET_TIMER 197 *************************************************************************/ 198 199 #define BCM63XX_TIMER_COUNT 4 200 #define TIMER_T0_ID 0 201 #define TIMER_T1_ID 1 202 #define TIMER_T2_ID 2 203 #define TIMER_WDT_ID 3 204 205 /* Timer irqstat register */ 206 #define TIMER_IRQSTAT_REG 0 207 #define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x)) 208 #define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0) 209 #define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1) 210 #define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2) 211 #define TIMER_IRQSTAT_WDT_CAUSE (1 << 3) 212 #define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8)) 213 #define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8) 214 #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9) 215 #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10) 216 217 /* Timer control register */ 218 #define TIMER_CTLx_REG(x) (0x4 + (x * 4)) 219 #define TIMER_CTL0_REG 0x4 220 #define TIMER_CTL1_REG 0x8 221 #define TIMER_CTL2_REG 0xC 222 #define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff) 223 #define TIMER_CTL_MONOTONIC_MASK (1 << 30) 224 #define TIMER_CTL_ENABLE_MASK (1 << 31) 225 226 227 /************************************************************************* 228 * _REG relative to RSET_WDT 229 *************************************************************************/ 230 231 /* Watchdog default count register */ 232 #define WDT_DEFVAL_REG 0x0 233 234 /* Watchdog control register */ 235 #define WDT_CTL_REG 0x4 236 237 /* Watchdog control register constants */ 238 #define WDT_START_1 (0xff00) 239 #define WDT_START_2 (0x00ff) 240 #define WDT_STOP_1 (0xee00) 241 #define WDT_STOP_2 (0x00ee) 242 243 /* Watchdog reset length register */ 244 #define WDT_RSTLEN_REG 0x8 245 246 247 /************************************************************************* 248 * _REG relative to RSET_UARTx 249 *************************************************************************/ 250 251 /* UART Control Register */ 252 #define UART_CTL_REG 0x0 253 #define UART_CTL_RXTMOUTCNT_SHIFT 0 254 #define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT) 255 #define UART_CTL_RSTTXDN_SHIFT 5 256 #define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT) 257 #define UART_CTL_RSTRXFIFO_SHIFT 6 258 #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT) 259 #define UART_CTL_RSTTXFIFO_SHIFT 7 260 #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT) 261 #define UART_CTL_STOPBITS_SHIFT 8 262 #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT) 263 #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT) 264 #define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT) 265 #define UART_CTL_BITSPERSYM_SHIFT 12 266 #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT) 267 #define UART_CTL_XMITBRK_SHIFT 14 268 #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT) 269 #define UART_CTL_RSVD_SHIFT 15 270 #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT) 271 #define UART_CTL_RXPAREVEN_SHIFT 16 272 #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT) 273 #define UART_CTL_RXPAREN_SHIFT 17 274 #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT) 275 #define UART_CTL_TXPAREVEN_SHIFT 18 276 #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT) 277 #define UART_CTL_TXPAREN_SHIFT 18 278 #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT) 279 #define UART_CTL_LOOPBACK_SHIFT 20 280 #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT) 281 #define UART_CTL_RXEN_SHIFT 21 282 #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT) 283 #define UART_CTL_TXEN_SHIFT 22 284 #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT) 285 #define UART_CTL_BRGEN_SHIFT 23 286 #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT) 287 288 /* UART Baudword register */ 289 #define UART_BAUD_REG 0x4 290 291 /* UART Misc Control register */ 292 #define UART_MCTL_REG 0x8 293 #define UART_MCTL_DTR_SHIFT 0 294 #define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT) 295 #define UART_MCTL_RTS_SHIFT 1 296 #define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT) 297 #define UART_MCTL_RXFIFOTHRESH_SHIFT 8 298 #define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT) 299 #define UART_MCTL_TXFIFOTHRESH_SHIFT 12 300 #define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT) 301 #define UART_MCTL_RXFIFOFILL_SHIFT 16 302 #define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT) 303 #define UART_MCTL_TXFIFOFILL_SHIFT 24 304 #define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT) 305 306 /* UART External Input Configuration register */ 307 #define UART_EXTINP_REG 0xc 308 #define UART_EXTINP_RI_SHIFT 0 309 #define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT) 310 #define UART_EXTINP_CTS_SHIFT 1 311 #define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT) 312 #define UART_EXTINP_DCD_SHIFT 2 313 #define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT) 314 #define UART_EXTINP_DSR_SHIFT 3 315 #define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT) 316 #define UART_EXTINP_IRSTAT(x) (1 << (x + 4)) 317 #define UART_EXTINP_IRMASK(x) (1 << (x + 8)) 318 #define UART_EXTINP_IR_RI 0 319 #define UART_EXTINP_IR_CTS 1 320 #define UART_EXTINP_IR_DCD 2 321 #define UART_EXTINP_IR_DSR 3 322 #define UART_EXTINP_RI_NOSENSE_SHIFT 16 323 #define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT) 324 #define UART_EXTINP_CTS_NOSENSE_SHIFT 17 325 #define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT) 326 #define UART_EXTINP_DCD_NOSENSE_SHIFT 18 327 #define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT) 328 #define UART_EXTINP_DSR_NOSENSE_SHIFT 19 329 #define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT) 330 331 /* UART Interrupt register */ 332 #define UART_IR_REG 0x10 333 #define UART_IR_MASK(x) (1 << (x + 16)) 334 #define UART_IR_STAT(x) (1 << (x)) 335 #define UART_IR_EXTIP 0 336 #define UART_IR_TXUNDER 1 337 #define UART_IR_TXOVER 2 338 #define UART_IR_TXTRESH 3 339 #define UART_IR_TXRDLATCH 4 340 #define UART_IR_TXEMPTY 5 341 #define UART_IR_RXUNDER 6 342 #define UART_IR_RXOVER 7 343 #define UART_IR_RXTIMEOUT 8 344 #define UART_IR_RXFULL 9 345 #define UART_IR_RXTHRESH 10 346 #define UART_IR_RXNOTEMPTY 11 347 #define UART_IR_RXFRAMEERR 12 348 #define UART_IR_RXPARERR 13 349 #define UART_IR_RXBRK 14 350 #define UART_IR_TXDONE 15 351 352 /* UART Fifo register */ 353 #define UART_FIFO_REG 0x14 354 #define UART_FIFO_VALID_SHIFT 0 355 #define UART_FIFO_VALID_MASK 0xff 356 #define UART_FIFO_FRAMEERR_SHIFT 8 357 #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT) 358 #define UART_FIFO_PARERR_SHIFT 9 359 #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT) 360 #define UART_FIFO_BRKDET_SHIFT 10 361 #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT) 362 #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \ 363 UART_FIFO_PARERR_MASK | \ 364 UART_FIFO_BRKDET_MASK) 365 366 367 /************************************************************************* 368 * _REG relative to RSET_GPIO 369 *************************************************************************/ 370 371 /* GPIO registers */ 372 #define GPIO_CTL_HI_REG 0x0 373 #define GPIO_CTL_LO_REG 0x4 374 #define GPIO_DATA_HI_REG 0x8 375 #define GPIO_DATA_LO_REG 0xC 376 377 /* GPIO mux registers and constants */ 378 #define GPIO_MODE_REG 0x18 379 380 #define GPIO_MODE_6348_G4_DIAG 0x00090000 381 #define GPIO_MODE_6348_G4_UTOPIA 0x00080000 382 #define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000 383 #define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000 384 #define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000 385 #define GPIO_MODE_6348_G3_DIAG 0x00009000 386 #define GPIO_MODE_6348_G3_UTOPIA 0x00008000 387 #define GPIO_MODE_6348_G3_EXT_MII 0x00007000 388 #define GPIO_MODE_6348_G2_DIAG 0x00000900 389 #define GPIO_MODE_6348_G2_PCI 0x00000500 390 #define GPIO_MODE_6348_G1_DIAG 0x00000090 391 #define GPIO_MODE_6348_G1_UTOPIA 0x00000080 392 #define GPIO_MODE_6348_G1_SPI_UART 0x00000060 393 #define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060 394 #define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040 395 #define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020 396 #define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010 397 #define GPIO_MODE_6348_G0_DIAG 0x00000009 398 #define GPIO_MODE_6348_G0_EXT_MII 0x00000007 399 400 #define GPIO_MODE_6358_EXTRACS (1 << 5) 401 #define GPIO_MODE_6358_UART1 (1 << 6) 402 #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7) 403 #define GPIO_MODE_6358_SERIAL_LED (1 << 10) 404 #define GPIO_MODE_6358_UTOPIA (1 << 12) 405 406 407 /************************************************************************* 408 * _REG relative to RSET_ENET 409 *************************************************************************/ 410 411 /* Receiver Configuration register */ 412 #define ENET_RXCFG_REG 0x0 413 #define ENET_RXCFG_ALLMCAST_SHIFT 1 414 #define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT) 415 #define ENET_RXCFG_PROMISC_SHIFT 3 416 #define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT) 417 #define ENET_RXCFG_LOOPBACK_SHIFT 4 418 #define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT) 419 #define ENET_RXCFG_ENFLOW_SHIFT 5 420 #define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT) 421 422 /* Receive Maximum Length register */ 423 #define ENET_RXMAXLEN_REG 0x4 424 #define ENET_RXMAXLEN_SHIFT 0 425 #define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT) 426 427 /* Transmit Maximum Length register */ 428 #define ENET_TXMAXLEN_REG 0x8 429 #define ENET_TXMAXLEN_SHIFT 0 430 #define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT) 431 432 /* MII Status/Control register */ 433 #define ENET_MIISC_REG 0x10 434 #define ENET_MIISC_MDCFREQDIV_SHIFT 0 435 #define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT) 436 #define ENET_MIISC_PREAMBLEEN_SHIFT 7 437 #define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT) 438 439 /* MII Data register */ 440 #define ENET_MIIDATA_REG 0x14 441 #define ENET_MIIDATA_DATA_SHIFT 0 442 #define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT) 443 #define ENET_MIIDATA_TA_SHIFT 16 444 #define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT) 445 #define ENET_MIIDATA_REG_SHIFT 18 446 #define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT) 447 #define ENET_MIIDATA_PHYID_SHIFT 23 448 #define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT) 449 #define ENET_MIIDATA_OP_READ_MASK (0x6 << 28) 450 #define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28) 451 452 /* Ethernet Interrupt Mask register */ 453 #define ENET_IRMASK_REG 0x18 454 455 /* Ethernet Interrupt register */ 456 #define ENET_IR_REG 0x1c 457 #define ENET_IR_MII (1 << 0) 458 #define ENET_IR_MIB (1 << 1) 459 #define ENET_IR_FLOWC (1 << 2) 460 461 /* Ethernet Control register */ 462 #define ENET_CTL_REG 0x2c 463 #define ENET_CTL_ENABLE_SHIFT 0 464 #define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT) 465 #define ENET_CTL_DISABLE_SHIFT 1 466 #define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT) 467 #define ENET_CTL_SRESET_SHIFT 2 468 #define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT) 469 #define ENET_CTL_EPHYSEL_SHIFT 3 470 #define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT) 471 472 /* Transmit Control register */ 473 #define ENET_TXCTL_REG 0x30 474 #define ENET_TXCTL_FD_SHIFT 0 475 #define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT) 476 477 /* Transmit Watermask register */ 478 #define ENET_TXWMARK_REG 0x34 479 #define ENET_TXWMARK_WM_SHIFT 0 480 #define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT) 481 482 /* MIB Control register */ 483 #define ENET_MIBCTL_REG 0x38 484 #define ENET_MIBCTL_RDCLEAR_SHIFT 0 485 #define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT) 486 487 /* Perfect Match Data Low register */ 488 #define ENET_PML_REG(x) (0x58 + (x) * 8) 489 #define ENET_PMH_REG(x) (0x5c + (x) * 8) 490 #define ENET_PMH_DATAVALID_SHIFT 16 491 #define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT) 492 493 /* MIB register */ 494 #define ENET_MIB_REG(x) (0x200 + (x) * 4) 495 #define ENET_MIB_REG_COUNT 55 496 497 498 /************************************************************************* 499 * _REG relative to RSET_ENETDMA 500 *************************************************************************/ 501 502 /* Controller Configuration Register */ 503 #define ENETDMA_CFG_REG (0x0) 504 #define ENETDMA_CFG_EN_SHIFT 0 505 #define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT) 506 #define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1)) 507 508 /* Flow Control Descriptor Low Threshold register */ 509 #define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6) 510 511 /* Flow Control Descriptor High Threshold register */ 512 #define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6) 513 514 /* Flow Control Descriptor Buffer Alloca Threshold register */ 515 #define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6) 516 #define ENETDMA_BUFALLOC_FORCE_SHIFT 31 517 #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT) 518 519 /* Channel Configuration register */ 520 #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10) 521 #define ENETDMA_CHANCFG_EN_SHIFT 0 522 #define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT) 523 #define ENETDMA_CHANCFG_PKTHALT_SHIFT 1 524 #define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT) 525 526 /* Interrupt Control/Status register */ 527 #define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10) 528 #define ENETDMA_IR_BUFDONE_MASK (1 << 0) 529 #define ENETDMA_IR_PKTDONE_MASK (1 << 1) 530 #define ENETDMA_IR_NOTOWNER_MASK (1 << 2) 531 532 /* Interrupt Mask register */ 533 #define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10) 534 535 /* Maximum Burst Length */ 536 #define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10) 537 538 /* Ring Start Address register */ 539 #define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10) 540 541 /* State Ram Word 2 */ 542 #define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10) 543 544 /* State Ram Word 3 */ 545 #define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10) 546 547 /* State Ram Word 4 */ 548 #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10) 549 550 551 /************************************************************************* 552 * _REG relative to RSET_OHCI_PRIV 553 *************************************************************************/ 554 555 #define OHCI_PRIV_REG 0x0 556 #define OHCI_PRIV_PORT1_HOST_SHIFT 0 557 #define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT) 558 #define OHCI_PRIV_REG_SWAP_SHIFT 3 559 #define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT) 560 561 562 /************************************************************************* 563 * _REG relative to RSET_USBH_PRIV 564 *************************************************************************/ 565 566 #define USBH_PRIV_SWAP_REG 0x0 567 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 568 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) 569 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 570 #define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT) 571 #define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1 572 #define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT) 573 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 574 #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) 575 576 #define USBH_PRIV_TEST_REG 0x24 577 578 579 /************************************************************************* 580 * _REG relative to RSET_MPI 581 *************************************************************************/ 582 583 /* well known (hard wired) chip select */ 584 #define MPI_CS_PCMCIA_COMMON 4 585 #define MPI_CS_PCMCIA_ATTR 5 586 #define MPI_CS_PCMCIA_IO 6 587 588 /* Chip select base register */ 589 #define MPI_CSBASE_REG(x) (0x0 + (x) * 8) 590 #define MPI_CSBASE_BASE_SHIFT 13 591 #define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT) 592 #define MPI_CSBASE_SIZE_SHIFT 0 593 #define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT) 594 595 #define MPI_CSBASE_SIZE_8K 0 596 #define MPI_CSBASE_SIZE_16K 1 597 #define MPI_CSBASE_SIZE_32K 2 598 #define MPI_CSBASE_SIZE_64K 3 599 #define MPI_CSBASE_SIZE_128K 4 600 #define MPI_CSBASE_SIZE_256K 5 601 #define MPI_CSBASE_SIZE_512K 6 602 #define MPI_CSBASE_SIZE_1M 7 603 #define MPI_CSBASE_SIZE_2M 8 604 #define MPI_CSBASE_SIZE_4M 9 605 #define MPI_CSBASE_SIZE_8M 10 606 #define MPI_CSBASE_SIZE_16M 11 607 #define MPI_CSBASE_SIZE_32M 12 608 #define MPI_CSBASE_SIZE_64M 13 609 #define MPI_CSBASE_SIZE_128M 14 610 #define MPI_CSBASE_SIZE_256M 15 611 612 /* Chip select control register */ 613 #define MPI_CSCTL_REG(x) (0x4 + (x) * 8) 614 #define MPI_CSCTL_ENABLE_MASK (1 << 0) 615 #define MPI_CSCTL_WAIT_SHIFT 1 616 #define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT) 617 #define MPI_CSCTL_DATA16_MASK (1 << 4) 618 #define MPI_CSCTL_SYNCMODE_MASK (1 << 7) 619 #define MPI_CSCTL_TSIZE_MASK (1 << 8) 620 #define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10) 621 #define MPI_CSCTL_SETUP_SHIFT 16 622 #define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT) 623 #define MPI_CSCTL_HOLD_SHIFT 20 624 #define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT) 625 626 /* PCI registers */ 627 #define MPI_SP0_RANGE_REG 0x100 628 #define MPI_SP0_REMAP_REG 0x104 629 #define MPI_SP0_REMAP_ENABLE_MASK (1 << 0) 630 #define MPI_SP1_RANGE_REG 0x10C 631 #define MPI_SP1_REMAP_REG 0x110 632 #define MPI_SP1_REMAP_ENABLE_MASK (1 << 0) 633 634 #define MPI_L2PCFG_REG 0x11C 635 #define MPI_L2PCFG_CFG_TYPE_SHIFT 0 636 #define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT) 637 #define MPI_L2PCFG_REG_SHIFT 2 638 #define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT) 639 #define MPI_L2PCFG_FUNC_SHIFT 8 640 #define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT) 641 #define MPI_L2PCFG_DEVNUM_SHIFT 11 642 #define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT) 643 #define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30) 644 #define MPI_L2PCFG_CFG_SEL_MASK (1 << 31) 645 646 #define MPI_L2PMEMRANGE1_REG 0x120 647 #define MPI_L2PMEMBASE1_REG 0x124 648 #define MPI_L2PMEMREMAP1_REG 0x128 649 #define MPI_L2PMEMRANGE2_REG 0x12C 650 #define MPI_L2PMEMBASE2_REG 0x130 651 #define MPI_L2PMEMREMAP2_REG 0x134 652 #define MPI_L2PIORANGE_REG 0x138 653 #define MPI_L2PIOBASE_REG 0x13C 654 #define MPI_L2PIOREMAP_REG 0x140 655 #define MPI_L2P_BASE_MASK (0xffff8000) 656 #define MPI_L2PREMAP_ENABLED_MASK (1 << 0) 657 #define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2) 658 659 #define MPI_PCIMODESEL_REG 0x144 660 #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0) 661 #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1) 662 #define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2) 663 #define MPI_PCIMODESEL_PREFETCH_SHIFT 4 664 #define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT) 665 666 #define MPI_LOCBUSCTL_REG 0x14C 667 #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0) 668 #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1) 669 670 #define MPI_LOCINT_REG 0x150 671 #define MPI_LOCINT_MASK(x) (1 << (x + 16)) 672 #define MPI_LOCINT_STAT(x) (1 << (x)) 673 #define MPI_LOCINT_DIR_FAILED 6 674 #define MPI_LOCINT_EXT_PCI_INT 7 675 #define MPI_LOCINT_SERR 8 676 #define MPI_LOCINT_CSERR 9 677 678 #define MPI_PCICFGCTL_REG 0x178 679 #define MPI_PCICFGCTL_CFGADDR_SHIFT 2 680 #define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT) 681 #define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7) 682 683 #define MPI_PCICFGDATA_REG 0x17C 684 685 /* PCI host bridge custom register */ 686 #define BCMPCI_REG_TIMERS 0x40 687 #define REG_TIMER_TRDY_SHIFT 0 688 #define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT) 689 #define REG_TIMER_RETRY_SHIFT 8 690 #define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT) 691 692 693 /************************************************************************* 694 * _REG relative to RSET_PCMCIA 695 *************************************************************************/ 696 697 #define PCMCIA_C1_REG 0x0 698 #define PCMCIA_C1_CD1_MASK (1 << 0) 699 #define PCMCIA_C1_CD2_MASK (1 << 1) 700 #define PCMCIA_C1_VS1_MASK (1 << 2) 701 #define PCMCIA_C1_VS2_MASK (1 << 3) 702 #define PCMCIA_C1_VS1OE_MASK (1 << 6) 703 #define PCMCIA_C1_VS2OE_MASK (1 << 7) 704 #define PCMCIA_C1_CBIDSEL_SHIFT (8) 705 #define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT) 706 #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13) 707 #define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14) 708 #define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15) 709 #define PCMCIA_C1_RESET_MASK (1 << 18) 710 711 #define PCMCIA_C2_REG 0x8 712 #define PCMCIA_C2_DATA16_MASK (1 << 0) 713 #define PCMCIA_C2_BYTESWAP_MASK (1 << 1) 714 #define PCMCIA_C2_RWCOUNT_SHIFT 2 715 #define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT) 716 #define PCMCIA_C2_INACTIVE_SHIFT 8 717 #define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT) 718 #define PCMCIA_C2_SETUP_SHIFT 16 719 #define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT) 720 #define PCMCIA_C2_HOLD_SHIFT 24 721 #define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT) 722 723 724 /************************************************************************* 725 * _REG relative to RSET_SDRAM 726 *************************************************************************/ 727 728 #define SDRAM_CFG_REG 0x0 729 #define SDRAM_CFG_ROW_SHIFT 4 730 #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT) 731 #define SDRAM_CFG_COL_SHIFT 6 732 #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT) 733 #define SDRAM_CFG_32B_SHIFT 10 734 #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT) 735 #define SDRAM_CFG_BANK_SHIFT 13 736 #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) 737 738 #define SDRAM_PRIO_REG 0x2C 739 #define SDRAM_PRIO_MIPS_SHIFT 29 740 #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT) 741 #define SDRAM_PRIO_ADSL_SHIFT 30 742 #define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT) 743 #define SDRAM_PRIO_EN_SHIFT 31 744 #define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT) 745 746 747 /************************************************************************* 748 * _REG relative to RSET_MEMC 749 *************************************************************************/ 750 751 #define MEMC_CFG_REG 0x4 752 #define MEMC_CFG_32B_SHIFT 1 753 #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT) 754 #define MEMC_CFG_COL_SHIFT 3 755 #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT) 756 #define MEMC_CFG_ROW_SHIFT 6 757 #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT) 758 759 760 /************************************************************************* 761 * _REG relative to RSET_DDR 762 *************************************************************************/ 763 764 #define DDR_DMIPSPLLCFG_REG 0x18 765 #define DMIPSPLLCFG_M1_SHIFT 0 766 #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT) 767 #define DMIPSPLLCFG_N1_SHIFT 23 768 #define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT) 769 #define DMIPSPLLCFG_N2_SHIFT 29 770 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) 771 772 #endif /* BCM63XX_REGS_H_ */ 773