1 /* 2 * 3 * BRIEF MODULE DESCRIPTION 4 * Include file for Alchemy Semiconductor's Au1k CPU. 5 * 6 * Copyright 2004 Embedded Edge, LLC 7 * dan@embeddededge.com 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * You should have received a copy of the GNU General Public License along 26 * with this program; if not, write to the Free Software Foundation, Inc., 27 * 675 Mass Ave, Cambridge, MA 02139, USA. 28 */ 29 30 /* Specifics for the Au1xxx Programmable Serial Controllers, first 31 * seen in the AU1550 part. 32 */ 33 #ifndef _AU1000_PSC_H_ 34 #define _AU1000_PSC_H_ 35 36 /* The PSC base addresses. */ 37 #ifdef CONFIG_SOC_AU1550 38 #define PSC0_BASE_ADDR 0xb1a00000 39 #define PSC1_BASE_ADDR 0xb1b00000 40 #define PSC2_BASE_ADDR 0xb0a00000 41 #define PSC3_BASE_ADDR 0xb0b00000 42 #endif 43 44 #ifdef CONFIG_SOC_AU1200 45 #define PSC0_BASE_ADDR 0xb1a00000 46 #define PSC1_BASE_ADDR 0xb1b00000 47 #endif 48 49 /* 50 * The PSC select and control registers are common to all protocols. 51 */ 52 #define PSC_SEL_OFFSET 0x00000000 53 #define PSC_CTRL_OFFSET 0x00000004 54 55 #define PSC_SEL_CLK_MASK (3 << 4) 56 #define PSC_SEL_CLK_INTCLK (0 << 4) 57 #define PSC_SEL_CLK_EXTCLK (1 << 4) 58 #define PSC_SEL_CLK_SERCLK (2 << 4) 59 60 #define PSC_SEL_PS_MASK 0x00000007 61 #define PSC_SEL_PS_DISABLED 0 62 #define PSC_SEL_PS_SPIMODE 2 63 #define PSC_SEL_PS_I2SMODE 3 64 #define PSC_SEL_PS_AC97MODE 4 65 #define PSC_SEL_PS_SMBUSMODE 5 66 67 #define PSC_CTRL_DISABLE 0 68 #define PSC_CTRL_SUSPEND 2 69 #define PSC_CTRL_ENABLE 3 70 71 /* AC97 Registers. */ 72 #define PSC_AC97CFG_OFFSET 0x00000008 73 #define PSC_AC97MSK_OFFSET 0x0000000c 74 #define PSC_AC97PCR_OFFSET 0x00000010 75 #define PSC_AC97STAT_OFFSET 0x00000014 76 #define PSC_AC97EVNT_OFFSET 0x00000018 77 #define PSC_AC97TXRX_OFFSET 0x0000001c 78 #define PSC_AC97CDC_OFFSET 0x00000020 79 #define PSC_AC97RST_OFFSET 0x00000024 80 #define PSC_AC97GPO_OFFSET 0x00000028 81 #define PSC_AC97GPI_OFFSET 0x0000002c 82 83 #define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET) 84 #define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET) 85 #define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET) 86 #define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET) 87 #define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET) 88 #define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET) 89 #define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET) 90 #define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET) 91 #define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET) 92 #define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET) 93 #define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET) 94 #define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET) 95 96 /* AC97 Config Register. */ 97 #define PSC_AC97CFG_RT_MASK (3 << 30) 98 #define PSC_AC97CFG_RT_FIFO1 (0 << 30) 99 #define PSC_AC97CFG_RT_FIFO2 (1 << 30) 100 #define PSC_AC97CFG_RT_FIFO4 (2 << 30) 101 #define PSC_AC97CFG_RT_FIFO8 (3 << 30) 102 103 #define PSC_AC97CFG_TT_MASK (3 << 28) 104 #define PSC_AC97CFG_TT_FIFO1 (0 << 28) 105 #define PSC_AC97CFG_TT_FIFO2 (1 << 28) 106 #define PSC_AC97CFG_TT_FIFO4 (2 << 28) 107 #define PSC_AC97CFG_TT_FIFO8 (3 << 28) 108 109 #define PSC_AC97CFG_DD_DISABLE (1 << 27) 110 #define PSC_AC97CFG_DE_ENABLE (1 << 26) 111 #define PSC_AC97CFG_SE_ENABLE (1 << 25) 112 113 #define PSC_AC97CFG_LEN_MASK (0xf << 21) 114 #define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11) 115 #define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1) 116 #define PSC_AC97CFG_GE_ENABLE (1) 117 118 /* Enable slots 3-12. */ 119 #define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11)) 120 #define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1)) 121 122 /* 123 * The word length equation is ((x) * 2) + 2, so choose 'x' appropriately. 124 * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the 125 * arithmetic in the macro. 126 */ 127 #define PSC_AC97CFG_SET_LEN(x) (((((x) - 2) / 2) & 0xf) << 21) 128 #define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2) 129 130 /* AC97 Mask Register. */ 131 #define PSC_AC97MSK_GR (1 << 25) 132 #define PSC_AC97MSK_CD (1 << 24) 133 #define PSC_AC97MSK_RR (1 << 13) 134 #define PSC_AC97MSK_RO (1 << 12) 135 #define PSC_AC97MSK_RU (1 << 11) 136 #define PSC_AC97MSK_TR (1 << 10) 137 #define PSC_AC97MSK_TO (1 << 9) 138 #define PSC_AC97MSK_TU (1 << 8) 139 #define PSC_AC97MSK_RD (1 << 5) 140 #define PSC_AC97MSK_TD (1 << 4) 141 #define PSC_AC97MSK_ALLMASK (PSC_AC97MSK_GR | PSC_AC97MSK_CD | \ 142 PSC_AC97MSK_RR | PSC_AC97MSK_RO | \ 143 PSC_AC97MSK_RU | PSC_AC97MSK_TR | \ 144 PSC_AC97MSK_TO | PSC_AC97MSK_TU | \ 145 PSC_AC97MSK_RD | PSC_AC97MSK_TD) 146 147 /* AC97 Protocol Control Register. */ 148 #define PSC_AC97PCR_RC (1 << 6) 149 #define PSC_AC97PCR_RP (1 << 5) 150 #define PSC_AC97PCR_RS (1 << 4) 151 #define PSC_AC97PCR_TC (1 << 2) 152 #define PSC_AC97PCR_TP (1 << 1) 153 #define PSC_AC97PCR_TS (1 << 0) 154 155 /* AC97 Status register (read only). */ 156 #define PSC_AC97STAT_CB (1 << 26) 157 #define PSC_AC97STAT_CP (1 << 25) 158 #define PSC_AC97STAT_CR (1 << 24) 159 #define PSC_AC97STAT_RF (1 << 13) 160 #define PSC_AC97STAT_RE (1 << 12) 161 #define PSC_AC97STAT_RR (1 << 11) 162 #define PSC_AC97STAT_TF (1 << 10) 163 #define PSC_AC97STAT_TE (1 << 9) 164 #define PSC_AC97STAT_TR (1 << 8) 165 #define PSC_AC97STAT_RB (1 << 5) 166 #define PSC_AC97STAT_TB (1 << 4) 167 #define PSC_AC97STAT_DI (1 << 2) 168 #define PSC_AC97STAT_DR (1 << 1) 169 #define PSC_AC97STAT_SR (1 << 0) 170 171 /* AC97 Event Register. */ 172 #define PSC_AC97EVNT_GR (1 << 25) 173 #define PSC_AC97EVNT_CD (1 << 24) 174 #define PSC_AC97EVNT_RR (1 << 13) 175 #define PSC_AC97EVNT_RO (1 << 12) 176 #define PSC_AC97EVNT_RU (1 << 11) 177 #define PSC_AC97EVNT_TR (1 << 10) 178 #define PSC_AC97EVNT_TO (1 << 9) 179 #define PSC_AC97EVNT_TU (1 << 8) 180 #define PSC_AC97EVNT_RD (1 << 5) 181 #define PSC_AC97EVNT_TD (1 << 4) 182 183 /* CODEC Command Register. */ 184 #define PSC_AC97CDC_RD (1 << 25) 185 #define PSC_AC97CDC_ID_MASK (3 << 23) 186 #define PSC_AC97CDC_INDX_MASK (0x7f << 16) 187 #define PSC_AC97CDC_ID(x) (((x) & 0x03) << 23) 188 #define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16) 189 190 /* AC97 Reset Control Register. */ 191 #define PSC_AC97RST_RST (1 << 1) 192 #define PSC_AC97RST_SNC (1 << 0) 193 194 /* PSC in I2S Mode. */ 195 typedef struct psc_i2s { 196 u32 psc_sel; 197 u32 psc_ctrl; 198 u32 psc_i2scfg; 199 u32 psc_i2smsk; 200 u32 psc_i2spcr; 201 u32 psc_i2sstat; 202 u32 psc_i2sevent; 203 u32 psc_i2stxrx; 204 u32 psc_i2sudf; 205 } psc_i2s_t; 206 207 #define PSC_I2SCFG_OFFSET 0x08 208 #define PSC_I2SMASK_OFFSET 0x0C 209 #define PSC_I2SPCR_OFFSET 0x10 210 #define PSC_I2SSTAT_OFFSET 0x14 211 #define PSC_I2SEVENT_OFFSET 0x18 212 #define PSC_I2SRXTX_OFFSET 0x1C 213 #define PSC_I2SUDF_OFFSET 0x20 214 215 /* I2S Config Register. */ 216 #define PSC_I2SCFG_RT_MASK (3 << 30) 217 #define PSC_I2SCFG_RT_FIFO1 (0 << 30) 218 #define PSC_I2SCFG_RT_FIFO2 (1 << 30) 219 #define PSC_I2SCFG_RT_FIFO4 (2 << 30) 220 #define PSC_I2SCFG_RT_FIFO8 (3 << 30) 221 222 #define PSC_I2SCFG_TT_MASK (3 << 28) 223 #define PSC_I2SCFG_TT_FIFO1 (0 << 28) 224 #define PSC_I2SCFG_TT_FIFO2 (1 << 28) 225 #define PSC_I2SCFG_TT_FIFO4 (2 << 28) 226 #define PSC_I2SCFG_TT_FIFO8 (3 << 28) 227 228 #define PSC_I2SCFG_DD_DISABLE (1 << 27) 229 #define PSC_I2SCFG_DE_ENABLE (1 << 26) 230 #define PSC_I2SCFG_SET_WS(x) (((((x) / 2) - 1) & 0x7f) << 16) 231 #define PSC_I2SCFG_WS(n) ((n & 0xFF) << 16) 232 #define PSC_I2SCFG_WS_MASK (PSC_I2SCFG_WS(0x3F)) 233 #define PSC_I2SCFG_WI (1 << 15) 234 235 #define PSC_I2SCFG_DIV_MASK (3 << 13) 236 #define PSC_I2SCFG_DIV2 (0 << 13) 237 #define PSC_I2SCFG_DIV4 (1 << 13) 238 #define PSC_I2SCFG_DIV8 (2 << 13) 239 #define PSC_I2SCFG_DIV16 (3 << 13) 240 241 #define PSC_I2SCFG_BI (1 << 12) 242 #define PSC_I2SCFG_BUF (1 << 11) 243 #define PSC_I2SCFG_MLJ (1 << 10) 244 #define PSC_I2SCFG_XM (1 << 9) 245 246 /* The word length equation is simply LEN+1. */ 247 #define PSC_I2SCFG_SET_LEN(x) ((((x) - 1) & 0x1f) << 4) 248 #define PSC_I2SCFG_GET_LEN(x) ((((x) >> 4) & 0x1f) + 1) 249 250 #define PSC_I2SCFG_LB (1 << 2) 251 #define PSC_I2SCFG_MLF (1 << 1) 252 #define PSC_I2SCFG_MS (1 << 0) 253 254 /* I2S Mask Register. */ 255 #define PSC_I2SMSK_RR (1 << 13) 256 #define PSC_I2SMSK_RO (1 << 12) 257 #define PSC_I2SMSK_RU (1 << 11) 258 #define PSC_I2SMSK_TR (1 << 10) 259 #define PSC_I2SMSK_TO (1 << 9) 260 #define PSC_I2SMSK_TU (1 << 8) 261 #define PSC_I2SMSK_RD (1 << 5) 262 #define PSC_I2SMSK_TD (1 << 4) 263 #define PSC_I2SMSK_ALLMASK (PSC_I2SMSK_RR | PSC_I2SMSK_RO | \ 264 PSC_I2SMSK_RU | PSC_I2SMSK_TR | \ 265 PSC_I2SMSK_TO | PSC_I2SMSK_TU | \ 266 PSC_I2SMSK_RD | PSC_I2SMSK_TD) 267 268 /* I2S Protocol Control Register. */ 269 #define PSC_I2SPCR_RC (1 << 6) 270 #define PSC_I2SPCR_RP (1 << 5) 271 #define PSC_I2SPCR_RS (1 << 4) 272 #define PSC_I2SPCR_TC (1 << 2) 273 #define PSC_I2SPCR_TP (1 << 1) 274 #define PSC_I2SPCR_TS (1 << 0) 275 276 /* I2S Status register (read only). */ 277 #define PSC_I2SSTAT_RF (1 << 13) 278 #define PSC_I2SSTAT_RE (1 << 12) 279 #define PSC_I2SSTAT_RR (1 << 11) 280 #define PSC_I2SSTAT_TF (1 << 10) 281 #define PSC_I2SSTAT_TE (1 << 9) 282 #define PSC_I2SSTAT_TR (1 << 8) 283 #define PSC_I2SSTAT_RB (1 << 5) 284 #define PSC_I2SSTAT_TB (1 << 4) 285 #define PSC_I2SSTAT_DI (1 << 2) 286 #define PSC_I2SSTAT_DR (1 << 1) 287 #define PSC_I2SSTAT_SR (1 << 0) 288 289 /* I2S Event Register. */ 290 #define PSC_I2SEVNT_RR (1 << 13) 291 #define PSC_I2SEVNT_RO (1 << 12) 292 #define PSC_I2SEVNT_RU (1 << 11) 293 #define PSC_I2SEVNT_TR (1 << 10) 294 #define PSC_I2SEVNT_TO (1 << 9) 295 #define PSC_I2SEVNT_TU (1 << 8) 296 #define PSC_I2SEVNT_RD (1 << 5) 297 #define PSC_I2SEVNT_TD (1 << 4) 298 299 /* PSC in SPI Mode. */ 300 typedef struct psc_spi { 301 u32 psc_sel; 302 u32 psc_ctrl; 303 u32 psc_spicfg; 304 u32 psc_spimsk; 305 u32 psc_spipcr; 306 u32 psc_spistat; 307 u32 psc_spievent; 308 u32 psc_spitxrx; 309 } psc_spi_t; 310 311 /* SPI Config Register. */ 312 #define PSC_SPICFG_RT_MASK (3 << 30) 313 #define PSC_SPICFG_RT_FIFO1 (0 << 30) 314 #define PSC_SPICFG_RT_FIFO2 (1 << 30) 315 #define PSC_SPICFG_RT_FIFO4 (2 << 30) 316 #define PSC_SPICFG_RT_FIFO8 (3 << 30) 317 318 #define PSC_SPICFG_TT_MASK (3 << 28) 319 #define PSC_SPICFG_TT_FIFO1 (0 << 28) 320 #define PSC_SPICFG_TT_FIFO2 (1 << 28) 321 #define PSC_SPICFG_TT_FIFO4 (2 << 28) 322 #define PSC_SPICFG_TT_FIFO8 (3 << 28) 323 324 #define PSC_SPICFG_DD_DISABLE (1 << 27) 325 #define PSC_SPICFG_DE_ENABLE (1 << 26) 326 #define PSC_SPICFG_CLR_BAUD(x) ((x) & ~((0x3f) << 15)) 327 #define PSC_SPICFG_SET_BAUD(x) (((x) & 0x3f) << 15) 328 329 #define PSC_SPICFG_SET_DIV(x) (((x) & 0x03) << 13) 330 #define PSC_SPICFG_DIV2 0 331 #define PSC_SPICFG_DIV4 1 332 #define PSC_SPICFG_DIV8 2 333 #define PSC_SPICFG_DIV16 3 334 335 #define PSC_SPICFG_BI (1 << 12) 336 #define PSC_SPICFG_PSE (1 << 11) 337 #define PSC_SPICFG_CGE (1 << 10) 338 #define PSC_SPICFG_CDE (1 << 9) 339 340 #define PSC_SPICFG_CLR_LEN(x) ((x) & ~((0x1f) << 4)) 341 #define PSC_SPICFG_SET_LEN(x) (((x-1) & 0x1f) << 4) 342 343 #define PSC_SPICFG_LB (1 << 3) 344 #define PSC_SPICFG_MLF (1 << 1) 345 #define PSC_SPICFG_MO (1 << 0) 346 347 /* SPI Mask Register. */ 348 #define PSC_SPIMSK_MM (1 << 16) 349 #define PSC_SPIMSK_RR (1 << 13) 350 #define PSC_SPIMSK_RO (1 << 12) 351 #define PSC_SPIMSK_RU (1 << 11) 352 #define PSC_SPIMSK_TR (1 << 10) 353 #define PSC_SPIMSK_TO (1 << 9) 354 #define PSC_SPIMSK_TU (1 << 8) 355 #define PSC_SPIMSK_SD (1 << 5) 356 #define PSC_SPIMSK_MD (1 << 4) 357 #define PSC_SPIMSK_ALLMASK (PSC_SPIMSK_MM | PSC_SPIMSK_RR | \ 358 PSC_SPIMSK_RO | PSC_SPIMSK_TO | \ 359 PSC_SPIMSK_TU | PSC_SPIMSK_SD | \ 360 PSC_SPIMSK_MD) 361 362 /* SPI Protocol Control Register. */ 363 #define PSC_SPIPCR_RC (1 << 6) 364 #define PSC_SPIPCR_SP (1 << 5) 365 #define PSC_SPIPCR_SS (1 << 4) 366 #define PSC_SPIPCR_TC (1 << 2) 367 #define PSC_SPIPCR_MS (1 << 0) 368 369 /* SPI Status register (read only). */ 370 #define PSC_SPISTAT_RF (1 << 13) 371 #define PSC_SPISTAT_RE (1 << 12) 372 #define PSC_SPISTAT_RR (1 << 11) 373 #define PSC_SPISTAT_TF (1 << 10) 374 #define PSC_SPISTAT_TE (1 << 9) 375 #define PSC_SPISTAT_TR (1 << 8) 376 #define PSC_SPISTAT_SB (1 << 5) 377 #define PSC_SPISTAT_MB (1 << 4) 378 #define PSC_SPISTAT_DI (1 << 2) 379 #define PSC_SPISTAT_DR (1 << 1) 380 #define PSC_SPISTAT_SR (1 << 0) 381 382 /* SPI Event Register. */ 383 #define PSC_SPIEVNT_MM (1 << 16) 384 #define PSC_SPIEVNT_RR (1 << 13) 385 #define PSC_SPIEVNT_RO (1 << 12) 386 #define PSC_SPIEVNT_RU (1 << 11) 387 #define PSC_SPIEVNT_TR (1 << 10) 388 #define PSC_SPIEVNT_TO (1 << 9) 389 #define PSC_SPIEVNT_TU (1 << 8) 390 #define PSC_SPIEVNT_SD (1 << 5) 391 #define PSC_SPIEVNT_MD (1 << 4) 392 393 /* Transmit register control. */ 394 #define PSC_SPITXRX_LC (1 << 29) 395 #define PSC_SPITXRX_SR (1 << 28) 396 397 /* PSC in SMBus (I2C) Mode. */ 398 typedef struct psc_smb { 399 u32 psc_sel; 400 u32 psc_ctrl; 401 u32 psc_smbcfg; 402 u32 psc_smbmsk; 403 u32 psc_smbpcr; 404 u32 psc_smbstat; 405 u32 psc_smbevnt; 406 u32 psc_smbtxrx; 407 u32 psc_smbtmr; 408 } psc_smb_t; 409 410 /* SMBus Config Register. */ 411 #define PSC_SMBCFG_RT_MASK (3 << 30) 412 #define PSC_SMBCFG_RT_FIFO1 (0 << 30) 413 #define PSC_SMBCFG_RT_FIFO2 (1 << 30) 414 #define PSC_SMBCFG_RT_FIFO4 (2 << 30) 415 #define PSC_SMBCFG_RT_FIFO8 (3 << 30) 416 417 #define PSC_SMBCFG_TT_MASK (3 << 28) 418 #define PSC_SMBCFG_TT_FIFO1 (0 << 28) 419 #define PSC_SMBCFG_TT_FIFO2 (1 << 28) 420 #define PSC_SMBCFG_TT_FIFO4 (2 << 28) 421 #define PSC_SMBCFG_TT_FIFO8 (3 << 28) 422 423 #define PSC_SMBCFG_DD_DISABLE (1 << 27) 424 #define PSC_SMBCFG_DE_ENABLE (1 << 26) 425 426 #define PSC_SMBCFG_SET_DIV(x) (((x) & 0x03) << 13) 427 #define PSC_SMBCFG_DIV2 0 428 #define PSC_SMBCFG_DIV4 1 429 #define PSC_SMBCFG_DIV8 2 430 #define PSC_SMBCFG_DIV16 3 431 432 #define PSC_SMBCFG_GCE (1 << 9) 433 #define PSC_SMBCFG_SFM (1 << 8) 434 435 #define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1) 436 437 /* SMBus Mask Register. */ 438 #define PSC_SMBMSK_DN (1 << 30) 439 #define PSC_SMBMSK_AN (1 << 29) 440 #define PSC_SMBMSK_AL (1 << 28) 441 #define PSC_SMBMSK_RR (1 << 13) 442 #define PSC_SMBMSK_RO (1 << 12) 443 #define PSC_SMBMSK_RU (1 << 11) 444 #define PSC_SMBMSK_TR (1 << 10) 445 #define PSC_SMBMSK_TO (1 << 9) 446 #define PSC_SMBMSK_TU (1 << 8) 447 #define PSC_SMBMSK_SD (1 << 5) 448 #define PSC_SMBMSK_MD (1 << 4) 449 #define PSC_SMBMSK_ALLMASK (PSC_SMBMSK_DN | PSC_SMBMSK_AN | \ 450 PSC_SMBMSK_AL | PSC_SMBMSK_RR | \ 451 PSC_SMBMSK_RO | PSC_SMBMSK_TO | \ 452 PSC_SMBMSK_TU | PSC_SMBMSK_SD | \ 453 PSC_SMBMSK_MD) 454 455 /* SMBus Protocol Control Register. */ 456 #define PSC_SMBPCR_DC (1 << 2) 457 #define PSC_SMBPCR_MS (1 << 0) 458 459 /* SMBus Status register (read only). */ 460 #define PSC_SMBSTAT_BB (1 << 28) 461 #define PSC_SMBSTAT_RF (1 << 13) 462 #define PSC_SMBSTAT_RE (1 << 12) 463 #define PSC_SMBSTAT_RR (1 << 11) 464 #define PSC_SMBSTAT_TF (1 << 10) 465 #define PSC_SMBSTAT_TE (1 << 9) 466 #define PSC_SMBSTAT_TR (1 << 8) 467 #define PSC_SMBSTAT_SB (1 << 5) 468 #define PSC_SMBSTAT_MB (1 << 4) 469 #define PSC_SMBSTAT_DI (1 << 2) 470 #define PSC_SMBSTAT_DR (1 << 1) 471 #define PSC_SMBSTAT_SR (1 << 0) 472 473 /* SMBus Event Register. */ 474 #define PSC_SMBEVNT_DN (1 << 30) 475 #define PSC_SMBEVNT_AN (1 << 29) 476 #define PSC_SMBEVNT_AL (1 << 28) 477 #define PSC_SMBEVNT_RR (1 << 13) 478 #define PSC_SMBEVNT_RO (1 << 12) 479 #define PSC_SMBEVNT_RU (1 << 11) 480 #define PSC_SMBEVNT_TR (1 << 10) 481 #define PSC_SMBEVNT_TO (1 << 9) 482 #define PSC_SMBEVNT_TU (1 << 8) 483 #define PSC_SMBEVNT_SD (1 << 5) 484 #define PSC_SMBEVNT_MD (1 << 4) 485 #define PSC_SMBEVNT_ALLCLR (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | \ 486 PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | \ 487 PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | \ 488 PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \ 489 PSC_SMBEVNT_MD) 490 491 /* Transmit register control. */ 492 #define PSC_SMBTXRX_RSR (1 << 28) 493 #define PSC_SMBTXRX_STP (1 << 29) 494 #define PSC_SMBTXRX_DATAMASK 0xff 495 496 /* SMBus protocol timers register. */ 497 #define PSC_SMBTMR_SET_TH(x) (((x) & 0x03) << 30) 498 #define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25) 499 #define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20) 500 #define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15) 501 #define PSC_SMBTMR_SET_SU(x) (((x) & 0x1f) << 10) 502 #define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5) 503 #define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0) 504 505 #endif /* _AU1000_PSC_H_ */ 506