1 /* 2 * Atheros AR71XX/AR724X/AR913X SoC register definitions 3 * 4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> 5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 6 * 7 * Parts of this file are based on Atheros' 2.6.15 BSP 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License version 2 as published 11 * by the Free Software Foundation. 12 */ 13 14 #ifndef __ASM_MACH_AR71XX_REGS_H 15 #define __ASM_MACH_AR71XX_REGS_H 16 17 #include <linux/types.h> 18 #include <linux/init.h> 19 #include <linux/io.h> 20 #include <linux/bitops.h> 21 22 #define AR71XX_APB_BASE 0x18000000 23 #define AR71XX_SPI_BASE 0x1f000000 24 #define AR71XX_SPI_SIZE 0x01000000 25 26 #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) 27 #define AR71XX_DDR_CTRL_SIZE 0x100 28 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) 29 #define AR71XX_UART_SIZE 0x100 30 #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) 31 #define AR71XX_GPIO_SIZE 0x100 32 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) 33 #define AR71XX_PLL_SIZE 0x100 34 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) 35 #define AR71XX_RESET_SIZE 0x100 36 37 #define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) 38 #define AR913X_WMAC_SIZE 0x30000 39 40 /* 41 * DDR_CTRL block 42 */ 43 #define AR71XX_DDR_REG_PCI_WIN0 0x7c 44 #define AR71XX_DDR_REG_PCI_WIN1 0x80 45 #define AR71XX_DDR_REG_PCI_WIN2 0x84 46 #define AR71XX_DDR_REG_PCI_WIN3 0x88 47 #define AR71XX_DDR_REG_PCI_WIN4 0x8c 48 #define AR71XX_DDR_REG_PCI_WIN5 0x90 49 #define AR71XX_DDR_REG_PCI_WIN6 0x94 50 #define AR71XX_DDR_REG_PCI_WIN7 0x98 51 #define AR71XX_DDR_REG_FLUSH_GE0 0x9c 52 #define AR71XX_DDR_REG_FLUSH_GE1 0xa0 53 #define AR71XX_DDR_REG_FLUSH_USB 0xa4 54 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8 55 56 #define AR724X_DDR_REG_FLUSH_GE0 0x7c 57 #define AR724X_DDR_REG_FLUSH_GE1 0x80 58 #define AR724X_DDR_REG_FLUSH_USB 0x84 59 #define AR724X_DDR_REG_FLUSH_PCIE 0x88 60 61 #define AR913X_DDR_REG_FLUSH_GE0 0x7c 62 #define AR913X_DDR_REG_FLUSH_GE1 0x80 63 #define AR913X_DDR_REG_FLUSH_USB 0x84 64 #define AR913X_DDR_REG_FLUSH_WMAC 0x88 65 66 /* 67 * PLL block 68 */ 69 #define AR71XX_PLL_REG_CPU_CONFIG 0x00 70 #define AR71XX_PLL_REG_SEC_CONFIG 0x04 71 #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 72 #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 73 74 #define AR71XX_PLL_DIV_SHIFT 3 75 #define AR71XX_PLL_DIV_MASK 0x1f 76 #define AR71XX_CPU_DIV_SHIFT 16 77 #define AR71XX_CPU_DIV_MASK 0x3 78 #define AR71XX_DDR_DIV_SHIFT 18 79 #define AR71XX_DDR_DIV_MASK 0x3 80 #define AR71XX_AHB_DIV_SHIFT 20 81 #define AR71XX_AHB_DIV_MASK 0x7 82 83 #define AR724X_PLL_REG_CPU_CONFIG 0x00 84 #define AR724X_PLL_REG_PCIE_CONFIG 0x18 85 86 #define AR724X_PLL_DIV_SHIFT 0 87 #define AR724X_PLL_DIV_MASK 0x3ff 88 #define AR724X_PLL_REF_DIV_SHIFT 10 89 #define AR724X_PLL_REF_DIV_MASK 0xf 90 #define AR724X_AHB_DIV_SHIFT 19 91 #define AR724X_AHB_DIV_MASK 0x1 92 #define AR724X_DDR_DIV_SHIFT 22 93 #define AR724X_DDR_DIV_MASK 0x3 94 95 #define AR913X_PLL_REG_CPU_CONFIG 0x00 96 #define AR913X_PLL_REG_ETH_CONFIG 0x04 97 #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 98 #define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 99 100 #define AR913X_PLL_DIV_SHIFT 0 101 #define AR913X_PLL_DIV_MASK 0x3ff 102 #define AR913X_DDR_DIV_SHIFT 22 103 #define AR913X_DDR_DIV_MASK 0x3 104 #define AR913X_AHB_DIV_SHIFT 19 105 #define AR913X_AHB_DIV_MASK 0x1 106 107 /* 108 * RESET block 109 */ 110 #define AR71XX_RESET_REG_TIMER 0x00 111 #define AR71XX_RESET_REG_TIMER_RELOAD 0x04 112 #define AR71XX_RESET_REG_WDOG_CTRL 0x08 113 #define AR71XX_RESET_REG_WDOG 0x0c 114 #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 115 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 116 #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 117 #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c 118 #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 119 #define AR71XX_RESET_REG_RESET_MODULE 0x24 120 #define AR71XX_RESET_REG_PERFC_CTRL 0x2c 121 #define AR71XX_RESET_REG_PERFC0 0x30 122 #define AR71XX_RESET_REG_PERFC1 0x34 123 #define AR71XX_RESET_REG_REV_ID 0x90 124 125 #define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 126 #define AR913X_RESET_REG_RESET_MODULE 0x1c 127 #define AR913X_RESET_REG_PERF_CTRL 0x20 128 #define AR913X_RESET_REG_PERFC0 0x24 129 #define AR913X_RESET_REG_PERFC1 0x28 130 131 #define AR724X_RESET_REG_RESET_MODULE 0x1c 132 133 #define MISC_INT_DMA BIT(7) 134 #define MISC_INT_OHCI BIT(6) 135 #define MISC_INT_PERFC BIT(5) 136 #define MISC_INT_WDOG BIT(4) 137 #define MISC_INT_UART BIT(3) 138 #define MISC_INT_GPIO BIT(2) 139 #define MISC_INT_ERROR BIT(1) 140 #define MISC_INT_TIMER BIT(0) 141 142 #define AR71XX_RESET_EXTERNAL BIT(28) 143 #define AR71XX_RESET_FULL_CHIP BIT(24) 144 #define AR71XX_RESET_CPU_NMI BIT(21) 145 #define AR71XX_RESET_CPU_COLD BIT(20) 146 #define AR71XX_RESET_DMA BIT(19) 147 #define AR71XX_RESET_SLIC BIT(18) 148 #define AR71XX_RESET_STEREO BIT(17) 149 #define AR71XX_RESET_DDR BIT(16) 150 #define AR71XX_RESET_GE1_MAC BIT(13) 151 #define AR71XX_RESET_GE1_PHY BIT(12) 152 #define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) 153 #define AR71XX_RESET_GE0_MAC BIT(9) 154 #define AR71XX_RESET_GE0_PHY BIT(8) 155 #define AR71XX_RESET_USB_OHCI_DLL BIT(6) 156 #define AR71XX_RESET_USB_HOST BIT(5) 157 #define AR71XX_RESET_USB_PHY BIT(4) 158 #define AR71XX_RESET_PCI_BUS BIT(1) 159 #define AR71XX_RESET_PCI_CORE BIT(0) 160 161 #define AR724X_RESET_GE1_MDIO BIT(23) 162 #define AR724X_RESET_GE0_MDIO BIT(22) 163 #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) 164 #define AR724X_RESET_PCIE_PHY BIT(7) 165 #define AR724X_RESET_PCIE BIT(6) 166 #define AR724X_RESET_OHCI_DLL BIT(3) 167 168 #define AR913X_RESET_AMBA2WMAC BIT(22) 169 170 #define REV_ID_MAJOR_MASK 0xfff0 171 #define REV_ID_MAJOR_AR71XX 0x00a0 172 #define REV_ID_MAJOR_AR913X 0x00b0 173 #define REV_ID_MAJOR_AR7240 0x00c0 174 #define REV_ID_MAJOR_AR7241 0x0100 175 #define REV_ID_MAJOR_AR7242 0x1100 176 177 #define AR71XX_REV_ID_MINOR_MASK 0x3 178 #define AR71XX_REV_ID_MINOR_AR7130 0x0 179 #define AR71XX_REV_ID_MINOR_AR7141 0x1 180 #define AR71XX_REV_ID_MINOR_AR7161 0x2 181 #define AR71XX_REV_ID_REVISION_MASK 0x3 182 #define AR71XX_REV_ID_REVISION_SHIFT 2 183 184 #define AR913X_REV_ID_MINOR_MASK 0x3 185 #define AR913X_REV_ID_MINOR_AR9130 0x0 186 #define AR913X_REV_ID_MINOR_AR9132 0x1 187 #define AR913X_REV_ID_REVISION_MASK 0x3 188 #define AR913X_REV_ID_REVISION_SHIFT 2 189 190 #define AR724X_REV_ID_REVISION_MASK 0x3 191 192 /* 193 * SPI block 194 */ 195 #define AR71XX_SPI_REG_FS 0x00 /* Function Select */ 196 #define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ 197 #define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ 198 #define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ 199 200 #define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ 201 202 #define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */ 203 #define AR71XX_SPI_CTRL_DIV_MASK 0x3f 204 205 #define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ 206 #define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ 207 #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) 208 #define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) 209 #define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) 210 #define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) 211 #define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ 212 AR71XX_SPI_IOC_CS2) 213 214 /* 215 * GPIO block 216 */ 217 #define AR71XX_GPIO_REG_OE 0x00 218 #define AR71XX_GPIO_REG_IN 0x04 219 #define AR71XX_GPIO_REG_OUT 0x08 220 #define AR71XX_GPIO_REG_SET 0x0c 221 #define AR71XX_GPIO_REG_CLEAR 0x10 222 #define AR71XX_GPIO_REG_INT_MODE 0x14 223 #define AR71XX_GPIO_REG_INT_TYPE 0x18 224 #define AR71XX_GPIO_REG_INT_POLARITY 0x1c 225 #define AR71XX_GPIO_REG_INT_PENDING 0x20 226 #define AR71XX_GPIO_REG_INT_ENABLE 0x24 227 #define AR71XX_GPIO_REG_FUNC 0x28 228 229 #define AR71XX_GPIO_COUNT 16 230 #define AR724X_GPIO_COUNT 18 231 #define AR913X_GPIO_COUNT 22 232 233 #endif /* __ASM_MACH_AR71XX_REGS_H */ 234