1config SYMBOL_PREFIX 2 string 3 default "_" 4 5config MMU 6 def_bool n 7 8config FPU 9 def_bool n 10 11config RWSEM_GENERIC_SPINLOCK 12 def_bool y 13 14config RWSEM_XCHGADD_ALGORITHM 15 def_bool n 16 17config BLACKFIN 18 def_bool y 19 select HAVE_ARCH_KGDB 20 select HAVE_ARCH_TRACEHOOK 21 select HAVE_DYNAMIC_FTRACE 22 select HAVE_FTRACE_MCOUNT_RECORD 23 select HAVE_FUNCTION_GRAPH_TRACER 24 select HAVE_FUNCTION_TRACER 25 select HAVE_FUNCTION_TRACE_MCOUNT_TEST 26 select HAVE_IDE 27 select HAVE_KERNEL_GZIP if RAMKERNEL 28 select HAVE_KERNEL_BZIP2 if RAMKERNEL 29 select HAVE_KERNEL_LZMA if RAMKERNEL 30 select HAVE_KERNEL_LZO if RAMKERNEL 31 select HAVE_OPROFILE 32 select ARCH_WANT_OPTIONAL_GPIOLIB 33 select HAVE_GENERIC_HARDIRQS 34 select GENERIC_ATOMIC64 35 select GENERIC_IRQ_PROBE 36 select IRQ_PER_CPU if SMP 37 38config GENERIC_CSUM 39 def_bool y 40 41config GENERIC_BUG 42 def_bool y 43 depends on BUG 44 45config ZONE_DMA 46 def_bool y 47 48config GENERIC_FIND_NEXT_BIT 49 def_bool y 50 51config GENERIC_GPIO 52 def_bool y 53 54config FORCE_MAX_ZONEORDER 55 int 56 default "14" 57 58config GENERIC_CALIBRATE_DELAY 59 def_bool y 60 61config LOCKDEP_SUPPORT 62 def_bool y 63 64config STACKTRACE_SUPPORT 65 def_bool y 66 67config TRACE_IRQFLAGS_SUPPORT 68 def_bool y 69 70source "init/Kconfig" 71 72source "kernel/Kconfig.preempt" 73 74source "kernel/Kconfig.freezer" 75 76menu "Blackfin Processor Options" 77 78comment "Processor and Board Settings" 79 80choice 81 prompt "CPU" 82 default BF533 83 84config BF512 85 bool "BF512" 86 help 87 BF512 Processor Support. 88 89config BF514 90 bool "BF514" 91 help 92 BF514 Processor Support. 93 94config BF516 95 bool "BF516" 96 help 97 BF516 Processor Support. 98 99config BF518 100 bool "BF518" 101 help 102 BF518 Processor Support. 103 104config BF522 105 bool "BF522" 106 help 107 BF522 Processor Support. 108 109config BF523 110 bool "BF523" 111 help 112 BF523 Processor Support. 113 114config BF524 115 bool "BF524" 116 help 117 BF524 Processor Support. 118 119config BF525 120 bool "BF525" 121 help 122 BF525 Processor Support. 123 124config BF526 125 bool "BF526" 126 help 127 BF526 Processor Support. 128 129config BF527 130 bool "BF527" 131 help 132 BF527 Processor Support. 133 134config BF531 135 bool "BF531" 136 help 137 BF531 Processor Support. 138 139config BF532 140 bool "BF532" 141 help 142 BF532 Processor Support. 143 144config BF533 145 bool "BF533" 146 help 147 BF533 Processor Support. 148 149config BF534 150 bool "BF534" 151 help 152 BF534 Processor Support. 153 154config BF536 155 bool "BF536" 156 help 157 BF536 Processor Support. 158 159config BF537 160 bool "BF537" 161 help 162 BF537 Processor Support. 163 164config BF538 165 bool "BF538" 166 help 167 BF538 Processor Support. 168 169config BF539 170 bool "BF539" 171 help 172 BF539 Processor Support. 173 174config BF542_std 175 bool "BF542" 176 help 177 BF542 Processor Support. 178 179config BF542M 180 bool "BF542m" 181 help 182 BF542 Processor Support. 183 184config BF544_std 185 bool "BF544" 186 help 187 BF544 Processor Support. 188 189config BF544M 190 bool "BF544m" 191 help 192 BF544 Processor Support. 193 194config BF547_std 195 bool "BF547" 196 help 197 BF547 Processor Support. 198 199config BF547M 200 bool "BF547m" 201 help 202 BF547 Processor Support. 203 204config BF548_std 205 bool "BF548" 206 help 207 BF548 Processor Support. 208 209config BF548M 210 bool "BF548m" 211 help 212 BF548 Processor Support. 213 214config BF549_std 215 bool "BF549" 216 help 217 BF549 Processor Support. 218 219config BF549M 220 bool "BF549m" 221 help 222 BF549 Processor Support. 223 224config BF561 225 bool "BF561" 226 help 227 BF561 Processor Support. 228 229endchoice 230 231config SMP 232 depends on BF561 233 select TICKSOURCE_CORETMR 234 bool "Symmetric multi-processing support" 235 ---help--- 236 This enables support for systems with more than one CPU, 237 like the dual core BF561. If you have a system with only one 238 CPU, say N. If you have a system with more than one CPU, say Y. 239 240 If you don't know what to do here, say N. 241 242config NR_CPUS 243 int 244 depends on SMP 245 default 2 if BF561 246 247config HOTPLUG_CPU 248 bool "Support for hot-pluggable CPUs" 249 depends on SMP && HOTPLUG 250 default y 251 252config HAVE_LEGACY_PER_CPU_AREA 253 def_bool y 254 depends on SMP 255 256config BF_REV_MIN 257 int 258 default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) 259 default 2 if (BF537 || BF536 || BF534) 260 default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) 261 default 4 if (BF538 || BF539) 262 263config BF_REV_MAX 264 int 265 default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) 266 default 3 if (BF537 || BF536 || BF534 || BF54xM) 267 default 5 if (BF561 || BF538 || BF539) 268 default 6 if (BF533 || BF532 || BF531) 269 270choice 271 prompt "Silicon Rev" 272 default BF_REV_0_0 if (BF51x || BF52x) 273 default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) 274 default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) 275 276config BF_REV_0_0 277 bool "0.0" 278 depends on (BF51x || BF52x || (BF54x && !BF54xM)) 279 280config BF_REV_0_1 281 bool "0.1" 282 depends on (BF51x || BF52x || (BF54x && !BF54xM)) 283 284config BF_REV_0_2 285 bool "0.2" 286 depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) 287 288config BF_REV_0_3 289 bool "0.3" 290 depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) 291 292config BF_REV_0_4 293 bool "0.4" 294 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) 295 296config BF_REV_0_5 297 bool "0.5" 298 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) 299 300config BF_REV_0_6 301 bool "0.6" 302 depends on (BF533 || BF532 || BF531) 303 304config BF_REV_ANY 305 bool "any" 306 307config BF_REV_NONE 308 bool "none" 309 310endchoice 311 312config BF53x 313 bool 314 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) 315 default y 316 317config MEM_MT48LC64M4A2FB_7E 318 bool 319 depends on (BFIN533_STAMP) 320 default y 321 322config MEM_MT48LC16M16A2TG_75 323 bool 324 depends on (BFIN533_EZKIT || BFIN561_EZKIT \ 325 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \ 326 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \ 327 || BFIN527_BLUETECHNIX_CM) 328 default y 329 330config MEM_MT48LC32M8A2_75 331 bool 332 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) 333 default y 334 335config MEM_MT48LC8M32B2B5_7 336 bool 337 depends on (BFIN561_BLUETECHNIX_CM) 338 default y 339 340config MEM_MT48LC32M16A2TG_75 341 bool 342 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL) 343 default y 344 345config MEM_MT48H32M16LFCJ_75 346 bool 347 depends on (BFIN526_EZBRD) 348 default y 349 350source "arch/blackfin/mach-bf518/Kconfig" 351source "arch/blackfin/mach-bf527/Kconfig" 352source "arch/blackfin/mach-bf533/Kconfig" 353source "arch/blackfin/mach-bf561/Kconfig" 354source "arch/blackfin/mach-bf537/Kconfig" 355source "arch/blackfin/mach-bf538/Kconfig" 356source "arch/blackfin/mach-bf548/Kconfig" 357 358menu "Board customizations" 359 360config CMDLINE_BOOL 361 bool "Default bootloader kernel arguments" 362 363config CMDLINE 364 string "Initial kernel command string" 365 depends on CMDLINE_BOOL 366 default "console=ttyBF0,57600" 367 help 368 If you don't have a boot loader capable of passing a command line string 369 to the kernel, you may specify one here. As a minimum, you should specify 370 the memory size and the root device (e.g., mem=8M, root=/dev/nfs). 371 372config BOOT_LOAD 373 hex "Kernel load address for booting" 374 default "0x1000" 375 range 0x1000 0x20000000 376 help 377 This option allows you to set the load address of the kernel. 378 This can be useful if you are on a board which has a small amount 379 of memory or you wish to reserve some memory at the beginning of 380 the address space. 381 382 Note that you need to keep this value above 4k (0x1000) as this 383 memory region is used to capture NULL pointer references as well 384 as some core kernel functions. 385 386config ROM_BASE 387 hex "Kernel ROM Base" 388 depends on ROMKERNEL 389 default "0x20040040" 390 range 0x20000000 0x20400000 if !(BF54x || BF561) 391 range 0x20000000 0x30000000 if (BF54x || BF561) 392 help 393 Make sure your ROM base does not include any file-header 394 information that is prepended to the kernel. 395 396 For example, the bootable U-Boot format (created with 397 mkimage) has a 64 byte header (0x40). So while the image 398 you write to flash might start at say 0x20080000, you have 399 to add 0x40 to get the kernel's ROM base as it will come 400 after the header. 401 402comment "Clock/PLL Setup" 403 404config CLKIN_HZ 405 int "Frequency of the crystal on the board in Hz" 406 default "10000000" if BFIN532_IP0X 407 default "11059200" if BFIN533_STAMP 408 default "24576000" if PNAV10 409 default "25000000" # most people use this 410 default "27000000" if BFIN533_EZKIT 411 default "30000000" if BFIN561_EZKIT 412 default "24000000" if BFIN527_AD7160EVAL 413 help 414 The frequency of CLKIN crystal oscillator on the board in Hz. 415 Warning: This value should match the crystal on the board. Otherwise, 416 peripherals won't work properly. 417 418config BFIN_KERNEL_CLOCK 419 bool "Re-program Clocks while Kernel boots?" 420 default n 421 help 422 This option decides if kernel clocks are re-programed from the 423 bootloader settings. If the clocks are not set, the SDRAM settings 424 are also not changed, and the Bootloader does 100% of the hardware 425 configuration. 426 427config PLL_BYPASS 428 bool "Bypass PLL" 429 depends on BFIN_KERNEL_CLOCK 430 default n 431 432config CLKIN_HALF 433 bool "Half Clock In" 434 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) 435 default n 436 help 437 If this is set the clock will be divided by 2, before it goes to the PLL. 438 439config VCO_MULT 440 int "VCO Multiplier" 441 depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) 442 range 1 64 443 default "22" if BFIN533_EZKIT 444 default "45" if BFIN533_STAMP 445 default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) 446 default "22" if BFIN533_BLUETECHNIX_CM 447 default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) 448 default "20" if BFIN561_EZKIT 449 default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) 450 default "25" if BFIN527_AD7160EVAL 451 help 452 This controls the frequency of the on-chip PLL. This can be between 1 and 64. 453 PLL Frequency = (Crystal Frequency) * (this setting) 454 455choice 456 prompt "Core Clock Divider" 457 depends on BFIN_KERNEL_CLOCK 458 default CCLK_DIV_1 459 help 460 This sets the frequency of the core. It can be 1, 2, 4 or 8 461 Core Frequency = (PLL frequency) / (this setting) 462 463config CCLK_DIV_1 464 bool "1" 465 466config CCLK_DIV_2 467 bool "2" 468 469config CCLK_DIV_4 470 bool "4" 471 472config CCLK_DIV_8 473 bool "8" 474endchoice 475 476config SCLK_DIV 477 int "System Clock Divider" 478 depends on BFIN_KERNEL_CLOCK 479 range 1 15 480 default 5 481 help 482 This sets the frequency of the system clock (including SDRAM or DDR). 483 This can be between 1 and 15 484 System Clock = (PLL frequency) / (this setting) 485 486choice 487 prompt "DDR SDRAM Chip Type" 488 depends on BFIN_KERNEL_CLOCK 489 depends on BF54x 490 default MEM_MT46V32M16_5B 491 492config MEM_MT46V32M16_6T 493 bool "MT46V32M16_6T" 494 495config MEM_MT46V32M16_5B 496 bool "MT46V32M16_5B" 497endchoice 498 499choice 500 prompt "DDR/SDRAM Timing" 501 depends on BFIN_KERNEL_CLOCK 502 default BFIN_KERNEL_CLOCK_MEMINIT_CALC 503 help 504 This option allows you to specify Blackfin SDRAM/DDR Timing parameters 505 The calculated SDRAM timing parameters may not be 100% 506 accurate - This option is therefore marked experimental. 507 508config BFIN_KERNEL_CLOCK_MEMINIT_CALC 509 bool "Calculate Timings (EXPERIMENTAL)" 510 depends on EXPERIMENTAL 511 512config BFIN_KERNEL_CLOCK_MEMINIT_SPEC 513 bool "Provide accurate Timings based on target SCLK" 514 help 515 Please consult the Blackfin Hardware Reference Manuals as well 516 as the memory device datasheet. 517 http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram 518endchoice 519 520menu "Memory Init Control" 521 depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC 522 523config MEM_DDRCTL0 524 depends on BF54x 525 hex "DDRCTL0" 526 default 0x0 527 528config MEM_DDRCTL1 529 depends on BF54x 530 hex "DDRCTL1" 531 default 0x0 532 533config MEM_DDRCTL2 534 depends on BF54x 535 hex "DDRCTL2" 536 default 0x0 537 538config MEM_EBIU_DDRQUE 539 depends on BF54x 540 hex "DDRQUE" 541 default 0x0 542 543config MEM_SDRRC 544 depends on !BF54x 545 hex "SDRRC" 546 default 0x0 547 548config MEM_SDGCTL 549 depends on !BF54x 550 hex "SDGCTL" 551 default 0x0 552endmenu 553 554# 555# Max & Min Speeds for various Chips 556# 557config MAX_VCO_HZ 558 int 559 default 400000000 if BF512 560 default 400000000 if BF514 561 default 400000000 if BF516 562 default 400000000 if BF518 563 default 400000000 if BF522 564 default 600000000 if BF523 565 default 400000000 if BF524 566 default 600000000 if BF525 567 default 400000000 if BF526 568 default 600000000 if BF527 569 default 400000000 if BF531 570 default 400000000 if BF532 571 default 750000000 if BF533 572 default 500000000 if BF534 573 default 400000000 if BF536 574 default 600000000 if BF537 575 default 533333333 if BF538 576 default 533333333 if BF539 577 default 600000000 if BF542 578 default 533333333 if BF544 579 default 600000000 if BF547 580 default 600000000 if BF548 581 default 533333333 if BF549 582 default 600000000 if BF561 583 584config MIN_VCO_HZ 585 int 586 default 50000000 587 588config MAX_SCLK_HZ 589 int 590 default 133333333 591 592config MIN_SCLK_HZ 593 int 594 default 27000000 595 596comment "Kernel Timer/Scheduler" 597 598source kernel/Kconfig.hz 599 600config GENERIC_CLOCKEVENTS 601 bool "Generic clock events" 602 default y 603 604menu "Clock event device" 605 depends on GENERIC_CLOCKEVENTS 606config TICKSOURCE_GPTMR0 607 bool "GPTimer0" 608 depends on !SMP 609 select BFIN_GPTIMERS 610 611config TICKSOURCE_CORETMR 612 bool "Core timer" 613 default y 614endmenu 615 616menu "Clock souce" 617 depends on GENERIC_CLOCKEVENTS 618config CYCLES_CLOCKSOURCE 619 bool "CYCLES" 620 default y 621 depends on !BFIN_SCRATCH_REG_CYCLES 622 depends on !SMP 623 help 624 If you say Y here, you will enable support for using the 'cycles' 625 registers as a clock source. Doing so means you will be unable to 626 safely write to the 'cycles' register during runtime. You will 627 still be able to read it (such as for performance monitoring), but 628 writing the registers will most likely crash the kernel. 629 630config GPTMR0_CLOCKSOURCE 631 bool "GPTimer0" 632 select BFIN_GPTIMERS 633 depends on !TICKSOURCE_GPTMR0 634endmenu 635 636config ARCH_USES_GETTIMEOFFSET 637 depends on !GENERIC_CLOCKEVENTS 638 def_bool y 639 640source kernel/time/Kconfig 641 642comment "Misc" 643 644choice 645 prompt "Blackfin Exception Scratch Register" 646 default BFIN_SCRATCH_REG_RETN 647 help 648 Select the resource to reserve for the Exception handler: 649 - RETN: Non-Maskable Interrupt (NMI) 650 - RETE: Exception Return (JTAG/ICE) 651 - CYCLES: Performance counter 652 653 If you are unsure, please select "RETN". 654 655config BFIN_SCRATCH_REG_RETN 656 bool "RETN" 657 help 658 Use the RETN register in the Blackfin exception handler 659 as a stack scratch register. This means you cannot 660 safely use NMI on the Blackfin while running Linux, but 661 you can debug the system with a JTAG ICE and use the 662 CYCLES performance registers. 663 664 If you are unsure, please select "RETN". 665 666config BFIN_SCRATCH_REG_RETE 667 bool "RETE" 668 help 669 Use the RETE register in the Blackfin exception handler 670 as a stack scratch register. This means you cannot 671 safely use a JTAG ICE while debugging a Blackfin board, 672 but you can safely use the CYCLES performance registers 673 and the NMI. 674 675 If you are unsure, please select "RETN". 676 677config BFIN_SCRATCH_REG_CYCLES 678 bool "CYCLES" 679 help 680 Use the CYCLES register in the Blackfin exception handler 681 as a stack scratch register. This means you cannot 682 safely use the CYCLES performance registers on a Blackfin 683 board at anytime, but you can debug the system with a JTAG 684 ICE and use the NMI. 685 686 If you are unsure, please select "RETN". 687 688endchoice 689 690endmenu 691 692 693menu "Blackfin Kernel Optimizations" 694 695comment "Memory Optimizations" 696 697config I_ENTRY_L1 698 bool "Locate interrupt entry code in L1 Memory" 699 default y 700 depends on !SMP 701 help 702 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked 703 into L1 instruction memory. (less latency) 704 705config EXCPT_IRQ_SYSC_L1 706 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" 707 default y 708 depends on !SMP 709 help 710 If enabled, the entire ASM lowlevel exception and interrupt entry code 711 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. 712 (less latency) 713 714config DO_IRQ_L1 715 bool "Locate frequently called do_irq dispatcher function in L1 Memory" 716 default y 717 depends on !SMP 718 help 719 If enabled, the frequently called do_irq dispatcher function is linked 720 into L1 instruction memory. (less latency) 721 722config CORE_TIMER_IRQ_L1 723 bool "Locate frequently called timer_interrupt() function in L1 Memory" 724 default y 725 depends on !SMP 726 help 727 If enabled, the frequently called timer_interrupt() function is linked 728 into L1 instruction memory. (less latency) 729 730config IDLE_L1 731 bool "Locate frequently idle function in L1 Memory" 732 default y 733 depends on !SMP 734 help 735 If enabled, the frequently called idle function is linked 736 into L1 instruction memory. (less latency) 737 738config SCHEDULE_L1 739 bool "Locate kernel schedule function in L1 Memory" 740 default y 741 depends on !SMP 742 help 743 If enabled, the frequently called kernel schedule is linked 744 into L1 instruction memory. (less latency) 745 746config ARITHMETIC_OPS_L1 747 bool "Locate kernel owned arithmetic functions in L1 Memory" 748 default y 749 depends on !SMP 750 help 751 If enabled, arithmetic functions are linked 752 into L1 instruction memory. (less latency) 753 754config ACCESS_OK_L1 755 bool "Locate access_ok function in L1 Memory" 756 default y 757 depends on !SMP 758 help 759 If enabled, the access_ok function is linked 760 into L1 instruction memory. (less latency) 761 762config MEMSET_L1 763 bool "Locate memset function in L1 Memory" 764 default y 765 depends on !SMP 766 help 767 If enabled, the memset function is linked 768 into L1 instruction memory. (less latency) 769 770config MEMCPY_L1 771 bool "Locate memcpy function in L1 Memory" 772 default y 773 depends on !SMP 774 help 775 If enabled, the memcpy function is linked 776 into L1 instruction memory. (less latency) 777 778config STRCMP_L1 779 bool "locate strcmp function in L1 Memory" 780 default y 781 depends on !SMP 782 help 783 If enabled, the strcmp function is linked 784 into L1 instruction memory (less latency). 785 786config STRNCMP_L1 787 bool "locate strncmp function in L1 Memory" 788 default y 789 depends on !SMP 790 help 791 If enabled, the strncmp function is linked 792 into L1 instruction memory (less latency). 793 794config STRCPY_L1 795 bool "locate strcpy function in L1 Memory" 796 default y 797 depends on !SMP 798 help 799 If enabled, the strcpy function is linked 800 into L1 instruction memory (less latency). 801 802config STRNCPY_L1 803 bool "locate strncpy function in L1 Memory" 804 default y 805 depends on !SMP 806 help 807 If enabled, the strncpy function is linked 808 into L1 instruction memory (less latency). 809 810config SYS_BFIN_SPINLOCK_L1 811 bool "Locate sys_bfin_spinlock function in L1 Memory" 812 default y 813 depends on !SMP 814 help 815 If enabled, sys_bfin_spinlock function is linked 816 into L1 instruction memory. (less latency) 817 818config IP_CHECKSUM_L1 819 bool "Locate IP Checksum function in L1 Memory" 820 default n 821 depends on !SMP 822 help 823 If enabled, the IP Checksum function is linked 824 into L1 instruction memory. (less latency) 825 826config CACHELINE_ALIGNED_L1 827 bool "Locate cacheline_aligned data to L1 Data Memory" 828 default y if !BF54x 829 default n if BF54x 830 depends on !SMP && !BF531 831 help 832 If enabled, cacheline_aligned data is linked 833 into L1 data memory. (less latency) 834 835config SYSCALL_TAB_L1 836 bool "Locate Syscall Table L1 Data Memory" 837 default n 838 depends on !SMP && !BF531 839 help 840 If enabled, the Syscall LUT is linked 841 into L1 data memory. (less latency) 842 843config CPLB_SWITCH_TAB_L1 844 bool "Locate CPLB Switch Tables L1 Data Memory" 845 default n 846 depends on !SMP && !BF531 847 help 848 If enabled, the CPLB Switch Tables are linked 849 into L1 data memory. (less latency) 850 851config ICACHE_FLUSH_L1 852 bool "Locate icache flush funcs in L1 Inst Memory" 853 default y 854 help 855 If enabled, the Blackfin icache flushing functions are linked 856 into L1 instruction memory. 857 858 Note that this might be required to address anomalies, but 859 these functions are pretty small, so it shouldn't be too bad. 860 If you are using a processor affected by an anomaly, the build 861 system will double check for you and prevent it. 862 863config DCACHE_FLUSH_L1 864 bool "Locate dcache flush funcs in L1 Inst Memory" 865 default y 866 depends on !SMP 867 help 868 If enabled, the Blackfin dcache flushing functions are linked 869 into L1 instruction memory. 870 871config APP_STACK_L1 872 bool "Support locating application stack in L1 Scratch Memory" 873 default y 874 depends on !SMP 875 help 876 If enabled the application stack can be located in L1 877 scratch memory (less latency). 878 879 Currently only works with FLAT binaries. 880 881config EXCEPTION_L1_SCRATCH 882 bool "Locate exception stack in L1 Scratch Memory" 883 default n 884 depends on !SMP && !APP_STACK_L1 885 help 886 Whenever an exception occurs, use the L1 Scratch memory for 887 stack storage. You cannot place the stacks of FLAT binaries 888 in L1 when using this option. 889 890 If you don't use L1 Scratch, then you should say Y here. 891 892comment "Speed Optimizations" 893config BFIN_INS_LOWOVERHEAD 894 bool "ins[bwl] low overhead, higher interrupt latency" 895 default y 896 depends on !SMP 897 help 898 Reads on the Blackfin are speculative. In Blackfin terms, this means 899 they can be interrupted at any time (even after they have been issued 900 on to the external bus), and re-issued after the interrupt occurs. 901 For memory - this is not a big deal, since memory does not change if 902 it sees a read. 903 904 If a FIFO is sitting on the end of the read, it will see two reads, 905 when the core only sees one since the FIFO receives both the read 906 which is cancelled (and not delivered to the core) and the one which 907 is re-issued (which is delivered to the core). 908 909 To solve this, interrupts are turned off before reads occur to 910 I/O space. This option controls which the overhead/latency of 911 controlling interrupts during this time 912 "n" turns interrupts off every read 913 (higher overhead, but lower interrupt latency) 914 "y" turns interrupts off every loop 915 (low overhead, but longer interrupt latency) 916 917 default behavior is to leave this set to on (type "Y"). If you are experiencing 918 interrupt latency issues, it is safe and OK to turn this off. 919 920endmenu 921 922choice 923 prompt "Kernel executes from" 924 help 925 Choose the memory type that the kernel will be running in. 926 927config RAMKERNEL 928 bool "RAM" 929 help 930 The kernel will be resident in RAM when running. 931 932config ROMKERNEL 933 bool "ROM" 934 help 935 The kernel will be resident in FLASH/ROM when running. 936 937endchoice 938 939# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both 940config XIP_KERNEL 941 bool 942 default y 943 depends on ROMKERNEL 944 945source "mm/Kconfig" 946 947config BFIN_GPTIMERS 948 tristate "Enable Blackfin General Purpose Timers API" 949 default n 950 help 951 Enable support for the General Purpose Timers API. If you 952 are unsure, say N. 953 954 To compile this driver as a module, choose M here: the module 955 will be called gptimers. 956 957choice 958 prompt "Uncached DMA region" 959 default DMA_UNCACHED_1M 960config DMA_UNCACHED_4M 961 bool "Enable 4M DMA region" 962config DMA_UNCACHED_2M 963 bool "Enable 2M DMA region" 964config DMA_UNCACHED_1M 965 bool "Enable 1M DMA region" 966config DMA_UNCACHED_512K 967 bool "Enable 512K DMA region" 968config DMA_UNCACHED_256K 969 bool "Enable 256K DMA region" 970config DMA_UNCACHED_128K 971 bool "Enable 128K DMA region" 972config DMA_UNCACHED_NONE 973 bool "Disable DMA region" 974endchoice 975 976 977comment "Cache Support" 978 979config BFIN_ICACHE 980 bool "Enable ICACHE" 981 default y 982config BFIN_EXTMEM_ICACHEABLE 983 bool "Enable ICACHE for external memory" 984 depends on BFIN_ICACHE 985 default y 986config BFIN_L2_ICACHEABLE 987 bool "Enable ICACHE for L2 SRAM" 988 depends on BFIN_ICACHE 989 depends on BF54x || BF561 990 default n 991 992config BFIN_DCACHE 993 bool "Enable DCACHE" 994 default y 995config BFIN_DCACHE_BANKA 996 bool "Enable only 16k BankA DCACHE - BankB is SRAM" 997 depends on BFIN_DCACHE && !BF531 998 default n 999config BFIN_EXTMEM_DCACHEABLE 1000 bool "Enable DCACHE for external memory" 1001 depends on BFIN_DCACHE 1002 default y 1003choice 1004 prompt "External memory DCACHE policy" 1005 depends on BFIN_EXTMEM_DCACHEABLE 1006 default BFIN_EXTMEM_WRITEBACK if !SMP 1007 default BFIN_EXTMEM_WRITETHROUGH if SMP 1008config BFIN_EXTMEM_WRITEBACK 1009 bool "Write back" 1010 depends on !SMP 1011 help 1012 Write Back Policy: 1013 Cached data will be written back to SDRAM only when needed. 1014 This can give a nice increase in performance, but beware of 1015 broken drivers that do not properly invalidate/flush their 1016 cache. 1017 1018 Write Through Policy: 1019 Cached data will always be written back to SDRAM when the 1020 cache is updated. This is a completely safe setting, but 1021 performance is worse than Write Back. 1022 1023 If you are unsure of the options and you want to be safe, 1024 then go with Write Through. 1025 1026config BFIN_EXTMEM_WRITETHROUGH 1027 bool "Write through" 1028 help 1029 Write Back Policy: 1030 Cached data will be written back to SDRAM only when needed. 1031 This can give a nice increase in performance, but beware of 1032 broken drivers that do not properly invalidate/flush their 1033 cache. 1034 1035 Write Through Policy: 1036 Cached data will always be written back to SDRAM when the 1037 cache is updated. This is a completely safe setting, but 1038 performance is worse than Write Back. 1039 1040 If you are unsure of the options and you want to be safe, 1041 then go with Write Through. 1042 1043endchoice 1044 1045config BFIN_L2_DCACHEABLE 1046 bool "Enable DCACHE for L2 SRAM" 1047 depends on BFIN_DCACHE 1048 depends on (BF54x || BF561) && !SMP 1049 default n 1050choice 1051 prompt "L2 SRAM DCACHE policy" 1052 depends on BFIN_L2_DCACHEABLE 1053 default BFIN_L2_WRITEBACK 1054config BFIN_L2_WRITEBACK 1055 bool "Write back" 1056 1057config BFIN_L2_WRITETHROUGH 1058 bool "Write through" 1059endchoice 1060 1061 1062comment "Memory Protection Unit" 1063config MPU 1064 bool "Enable the memory protection unit (EXPERIMENTAL)" 1065 default n 1066 help 1067 Use the processor's MPU to protect applications from accessing 1068 memory they do not own. This comes at a performance penalty 1069 and is recommended only for debugging. 1070 1071comment "Asynchronous Memory Configuration" 1072 1073menu "EBIU_AMGCTL Global Control" 1074config C_AMCKEN 1075 bool "Enable CLKOUT" 1076 default y 1077 1078config C_CDPRIO 1079 bool "DMA has priority over core for ext. accesses" 1080 default n 1081 1082config C_B0PEN 1083 depends on BF561 1084 bool "Bank 0 16 bit packing enable" 1085 default y 1086 1087config C_B1PEN 1088 depends on BF561 1089 bool "Bank 1 16 bit packing enable" 1090 default y 1091 1092config C_B2PEN 1093 depends on BF561 1094 bool "Bank 2 16 bit packing enable" 1095 default y 1096 1097config C_B3PEN 1098 depends on BF561 1099 bool "Bank 3 16 bit packing enable" 1100 default n 1101 1102choice 1103 prompt "Enable Asynchronous Memory Banks" 1104 default C_AMBEN_ALL 1105 1106config C_AMBEN 1107 bool "Disable All Banks" 1108 1109config C_AMBEN_B0 1110 bool "Enable Bank 0" 1111 1112config C_AMBEN_B0_B1 1113 bool "Enable Bank 0 & 1" 1114 1115config C_AMBEN_B0_B1_B2 1116 bool "Enable Bank 0 & 1 & 2" 1117 1118config C_AMBEN_ALL 1119 bool "Enable All Banks" 1120endchoice 1121endmenu 1122 1123menu "EBIU_AMBCTL Control" 1124config BANK_0 1125 hex "Bank 0 (AMBCTL0.L)" 1126 default 0x7BB0 1127 help 1128 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are 1129 used to control the Asynchronous Memory Bank 0 settings. 1130 1131config BANK_1 1132 hex "Bank 1 (AMBCTL0.H)" 1133 default 0x7BB0 1134 default 0x5558 if BF54x 1135 help 1136 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are 1137 used to control the Asynchronous Memory Bank 1 settings. 1138 1139config BANK_2 1140 hex "Bank 2 (AMBCTL1.L)" 1141 default 0x7BB0 1142 help 1143 These are the low 16 bits of the EBIU_AMBCTL1 MMR which are 1144 used to control the Asynchronous Memory Bank 2 settings. 1145 1146config BANK_3 1147 hex "Bank 3 (AMBCTL1.H)" 1148 default 0x99B3 1149 help 1150 These are the high 16 bits of the EBIU_AMBCTL1 MMR which are 1151 used to control the Asynchronous Memory Bank 3 settings. 1152 1153endmenu 1154 1155config EBIU_MBSCTLVAL 1156 hex "EBIU Bank Select Control Register" 1157 depends on BF54x 1158 default 0 1159 1160config EBIU_MODEVAL 1161 hex "Flash Memory Mode Control Register" 1162 depends on BF54x 1163 default 1 1164 1165config EBIU_FCTLVAL 1166 hex "Flash Memory Bank Control Register" 1167 depends on BF54x 1168 default 6 1169endmenu 1170 1171############################################################################# 1172menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" 1173 1174config PCI 1175 bool "PCI support" 1176 depends on BROKEN 1177 help 1178 Support for PCI bus. 1179 1180source "drivers/pci/Kconfig" 1181 1182source "drivers/pcmcia/Kconfig" 1183 1184source "drivers/pci/hotplug/Kconfig" 1185 1186endmenu 1187 1188menu "Executable file formats" 1189 1190source "fs/Kconfig.binfmt" 1191 1192endmenu 1193 1194menu "Power management options" 1195 1196source "kernel/power/Kconfig" 1197 1198config ARCH_SUSPEND_POSSIBLE 1199 def_bool y 1200 1201choice 1202 prompt "Standby Power Saving Mode" 1203 depends on PM 1204 default PM_BFIN_SLEEP_DEEPER 1205config PM_BFIN_SLEEP_DEEPER 1206 bool "Sleep Deeper" 1207 help 1208 Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic 1209 power dissipation by disabling the clock to the processor core (CCLK). 1210 Furthermore, Standby sets the internal power supply voltage (VDDINT) 1211 to 0.85 V to provide the greatest power savings, while preserving the 1212 processor state. 1213 The PLL and system clock (SCLK) continue to operate at a very low 1214 frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, 1215 the SDRAM is put into Self Refresh Mode. Typically an external event 1216 such as GPIO interrupt or RTC activity wakes up the processor. 1217 Various Peripherals such as UART, SPORT, PPI may not function as 1218 normal during Sleep Deeper, due to the reduced SCLK frequency. 1219 When in the sleep mode, system DMA access to L1 memory is not supported. 1220 1221 If unsure, select "Sleep Deeper". 1222 1223config PM_BFIN_SLEEP 1224 bool "Sleep" 1225 help 1226 Sleep Mode (High Power Savings) - The sleep mode reduces power 1227 dissipation by disabling the clock to the processor core (CCLK). 1228 The PLL and system clock (SCLK), however, continue to operate in 1229 this mode. Typically an external event or RTC activity will wake 1230 up the processor. When in the sleep mode, system DMA access to L1 1231 memory is not supported. 1232 1233 If unsure, select "Sleep Deeper". 1234endchoice 1235 1236comment "Possible Suspend Mem / Hibernate Wake-Up Sources" 1237 depends on PM 1238 1239config PM_BFIN_WAKE_PH6 1240 bool "Allow Wake-Up from on-chip PHY or PH6 GP" 1241 depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) 1242 default n 1243 help 1244 Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) 1245 1246config PM_BFIN_WAKE_GP 1247 bool "Allow Wake-Up from GPIOs" 1248 depends on PM && BF54x 1249 default n 1250 help 1251 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) 1252 (all processors, except ADSP-BF549). This option sets 1253 the general-purpose wake-up enable (GPWE) control bit to enable 1254 wake-up upon detection of an active low signal on the /GPW (PH7) pin. 1255 On ADSP-BF549 this option enables the the same functionality on the 1256 /MRXON pin also PH7. 1257 1258endmenu 1259 1260menu "CPU Frequency scaling" 1261 1262source "drivers/cpufreq/Kconfig" 1263 1264config BFIN_CPU_FREQ 1265 bool 1266 depends on CPU_FREQ 1267 select CPU_FREQ_TABLE 1268 default y 1269 1270config CPU_VOLTAGE 1271 bool "CPU Voltage scaling" 1272 depends on EXPERIMENTAL 1273 depends on CPU_FREQ 1274 default n 1275 help 1276 Say Y here if you want CPU voltage scaling according to the CPU frequency. 1277 This option violates the PLL BYPASS recommendation in the Blackfin Processor 1278 manuals. There is a theoretical risk that during VDDINT transitions 1279 the PLL may unlock. 1280 1281endmenu 1282 1283source "net/Kconfig" 1284 1285source "drivers/Kconfig" 1286 1287source "drivers/firmware/Kconfig" 1288 1289source "fs/Kconfig" 1290 1291source "arch/blackfin/Kconfig.debug" 1292 1293source "security/Kconfig" 1294 1295source "crypto/Kconfig" 1296 1297source "lib/Kconfig" 1298