1 /*
2 * arch/arm/plat-omap/include/mach/mcbsp.h
3 *
4 * Defines for Multi-Channel Buffered Serial Port
5 *
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Author: Steve Johnson
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24 #ifndef __ASM_ARCH_OMAP_MCBSP_H
25 #define __ASM_ARCH_OMAP_MCBSP_H
26
27 #include <linux/completion.h>
28 #include <linux/spinlock.h>
29
30 #include <mach/hardware.h>
31 #include <plat/clock.h>
32
33 /* macro for building platform_device for McBSP ports */
34 #define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \
35 static struct platform_device omap_mcbsp##port_nr = { \
36 .name = "omap-mcbsp-dai", \
37 .id = OMAP_MCBSP##port_nr, \
38 }
39
40 #define MCBSP_CONFIG_TYPE2 0x2
41 #define MCBSP_CONFIG_TYPE3 0x3
42 #define MCBSP_CONFIG_TYPE4 0x4
43
44 #define OMAP7XX_MCBSP1_BASE 0xfffb1000
45 #define OMAP7XX_MCBSP2_BASE 0xfffb1800
46
47 #define OMAP1510_MCBSP1_BASE 0xe1011800
48 #define OMAP1510_MCBSP2_BASE 0xfffb1000
49 #define OMAP1510_MCBSP3_BASE 0xe1017000
50
51 #define OMAP1610_MCBSP1_BASE 0xe1011800
52 #define OMAP1610_MCBSP2_BASE 0xfffb1000
53 #define OMAP1610_MCBSP3_BASE 0xe1017000
54
55 #ifdef CONFIG_ARCH_OMAP1
56
57 #define OMAP_MCBSP_REG_DRR2 0x00
58 #define OMAP_MCBSP_REG_DRR1 0x02
59 #define OMAP_MCBSP_REG_DXR2 0x04
60 #define OMAP_MCBSP_REG_DXR1 0x06
61 #define OMAP_MCBSP_REG_DRR 0x02
62 #define OMAP_MCBSP_REG_DXR 0x06
63 #define OMAP_MCBSP_REG_SPCR2 0x08
64 #define OMAP_MCBSP_REG_SPCR1 0x0a
65 #define OMAP_MCBSP_REG_RCR2 0x0c
66 #define OMAP_MCBSP_REG_RCR1 0x0e
67 #define OMAP_MCBSP_REG_XCR2 0x10
68 #define OMAP_MCBSP_REG_XCR1 0x12
69 #define OMAP_MCBSP_REG_SRGR2 0x14
70 #define OMAP_MCBSP_REG_SRGR1 0x16
71 #define OMAP_MCBSP_REG_MCR2 0x18
72 #define OMAP_MCBSP_REG_MCR1 0x1a
73 #define OMAP_MCBSP_REG_RCERA 0x1c
74 #define OMAP_MCBSP_REG_RCERB 0x1e
75 #define OMAP_MCBSP_REG_XCERA 0x20
76 #define OMAP_MCBSP_REG_XCERB 0x22
77 #define OMAP_MCBSP_REG_PCR0 0x24
78 #define OMAP_MCBSP_REG_RCERC 0x26
79 #define OMAP_MCBSP_REG_RCERD 0x28
80 #define OMAP_MCBSP_REG_XCERC 0x2A
81 #define OMAP_MCBSP_REG_XCERD 0x2C
82 #define OMAP_MCBSP_REG_RCERE 0x2E
83 #define OMAP_MCBSP_REG_RCERF 0x30
84 #define OMAP_MCBSP_REG_XCERE 0x32
85 #define OMAP_MCBSP_REG_XCERF 0x34
86 #define OMAP_MCBSP_REG_RCERG 0x36
87 #define OMAP_MCBSP_REG_RCERH 0x38
88 #define OMAP_MCBSP_REG_XCERG 0x3A
89 #define OMAP_MCBSP_REG_XCERH 0x3C
90
91 /* Dummy defines, these are not available on omap1 */
92 #define OMAP_MCBSP_REG_XCCR 0x00
93 #define OMAP_MCBSP_REG_RCCR 0x00
94
95 #else
96
97 #define OMAP_MCBSP_REG_DRR2 0x00
98 #define OMAP_MCBSP_REG_DRR1 0x04
99 #define OMAP_MCBSP_REG_DXR2 0x08
100 #define OMAP_MCBSP_REG_DXR1 0x0C
101 #define OMAP_MCBSP_REG_DRR 0x00
102 #define OMAP_MCBSP_REG_DXR 0x08
103 #define OMAP_MCBSP_REG_SPCR2 0x10
104 #define OMAP_MCBSP_REG_SPCR1 0x14
105 #define OMAP_MCBSP_REG_RCR2 0x18
106 #define OMAP_MCBSP_REG_RCR1 0x1C
107 #define OMAP_MCBSP_REG_XCR2 0x20
108 #define OMAP_MCBSP_REG_XCR1 0x24
109 #define OMAP_MCBSP_REG_SRGR2 0x28
110 #define OMAP_MCBSP_REG_SRGR1 0x2C
111 #define OMAP_MCBSP_REG_MCR2 0x30
112 #define OMAP_MCBSP_REG_MCR1 0x34
113 #define OMAP_MCBSP_REG_RCERA 0x38
114 #define OMAP_MCBSP_REG_RCERB 0x3C
115 #define OMAP_MCBSP_REG_XCERA 0x40
116 #define OMAP_MCBSP_REG_XCERB 0x44
117 #define OMAP_MCBSP_REG_PCR0 0x48
118 #define OMAP_MCBSP_REG_RCERC 0x4C
119 #define OMAP_MCBSP_REG_RCERD 0x50
120 #define OMAP_MCBSP_REG_XCERC 0x54
121 #define OMAP_MCBSP_REG_XCERD 0x58
122 #define OMAP_MCBSP_REG_RCERE 0x5C
123 #define OMAP_MCBSP_REG_RCERF 0x60
124 #define OMAP_MCBSP_REG_XCERE 0x64
125 #define OMAP_MCBSP_REG_XCERF 0x68
126 #define OMAP_MCBSP_REG_RCERG 0x6C
127 #define OMAP_MCBSP_REG_RCERH 0x70
128 #define OMAP_MCBSP_REG_XCERG 0x74
129 #define OMAP_MCBSP_REG_XCERH 0x78
130 #define OMAP_MCBSP_REG_SYSCON 0x8C
131 #define OMAP_MCBSP_REG_THRSH2 0x90
132 #define OMAP_MCBSP_REG_THRSH1 0x94
133 #define OMAP_MCBSP_REG_IRQST 0xA0
134 #define OMAP_MCBSP_REG_IRQEN 0xA4
135 #define OMAP_MCBSP_REG_WAKEUPEN 0xA8
136 #define OMAP_MCBSP_REG_XCCR 0xAC
137 #define OMAP_MCBSP_REG_RCCR 0xB0
138 #define OMAP_MCBSP_REG_XBUFFSTAT 0xB4
139 #define OMAP_MCBSP_REG_RBUFFSTAT 0xB8
140 #define OMAP_MCBSP_REG_SSELCR 0xBC
141
142 #define OMAP_ST_REG_REV 0x00
143 #define OMAP_ST_REG_SYSCONFIG 0x10
144 #define OMAP_ST_REG_IRQSTATUS 0x18
145 #define OMAP_ST_REG_IRQENABLE 0x1C
146 #define OMAP_ST_REG_SGAINCR 0x24
147 #define OMAP_ST_REG_SFIRCR 0x28
148 #define OMAP_ST_REG_SSELCR 0x2C
149
150 #endif
151
152 /************************** McBSP SPCR1 bit definitions ***********************/
153 #define RRST 0x0001
154 #define RRDY 0x0002
155 #define RFULL 0x0004
156 #define RSYNC_ERR 0x0008
157 #define RINTM(value) ((value)<<4) /* bits 4:5 */
158 #define ABIS 0x0040
159 #define DXENA 0x0080
160 #define CLKSTP(value) ((value)<<11) /* bits 11:12 */
161 #define RJUST(value) ((value)<<13) /* bits 13:14 */
162 #define ALB 0x8000
163 #define DLB 0x8000
164
165 /************************** McBSP SPCR2 bit definitions ***********************/
166 #define XRST 0x0001
167 #define XRDY 0x0002
168 #define XEMPTY 0x0004
169 #define XSYNC_ERR 0x0008
170 #define XINTM(value) ((value)<<4) /* bits 4:5 */
171 #define GRST 0x0040
172 #define FRST 0x0080
173 #define SOFT 0x0100
174 #define FREE 0x0200
175
176 /************************** McBSP PCR bit definitions *************************/
177 #define CLKRP 0x0001
178 #define CLKXP 0x0002
179 #define FSRP 0x0004
180 #define FSXP 0x0008
181 #define DR_STAT 0x0010
182 #define DX_STAT 0x0020
183 #define CLKS_STAT 0x0040
184 #define SCLKME 0x0080
185 #define CLKRM 0x0100
186 #define CLKXM 0x0200
187 #define FSRM 0x0400
188 #define FSXM 0x0800
189 #define RIOEN 0x1000
190 #define XIOEN 0x2000
191 #define IDLE_EN 0x4000
192
193 /************************** McBSP RCR1 bit definitions ************************/
194 #define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
195 #define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
196
197 /************************** McBSP XCR1 bit definitions ************************/
198 #define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
199 #define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
200
201 /*************************** McBSP RCR2 bit definitions ***********************/
202 #define RDATDLY(value) (value) /* Bits 0:1 */
203 #define RFIG 0x0004
204 #define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
205 #define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
206 #define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
207 #define RPHASE 0x8000
208
209 /*************************** McBSP XCR2 bit definitions ***********************/
210 #define XDATDLY(value) (value) /* Bits 0:1 */
211 #define XFIG 0x0004
212 #define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
213 #define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
214 #define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
215 #define XPHASE 0x8000
216
217 /************************* McBSP SRGR1 bit definitions ************************/
218 #define CLKGDV(value) (value) /* Bits 0:7 */
219 #define FWID(value) ((value)<<8) /* Bits 8:15 */
220
221 /************************* McBSP SRGR2 bit definitions ************************/
222 #define FPER(value) (value) /* Bits 0:11 */
223 #define FSGM 0x1000
224 #define CLKSM 0x2000
225 #define CLKSP 0x4000
226 #define GSYNC 0x8000
227
228 /************************* McBSP MCR1 bit definitions *************************/
229 #define RMCM 0x0001
230 #define RCBLK(value) ((value)<<2) /* Bits 2:4 */
231 #define RPABLK(value) ((value)<<5) /* Bits 5:6 */
232 #define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
233
234 /************************* McBSP MCR2 bit definitions *************************/
235 #define XMCM(value) (value) /* Bits 0:1 */
236 #define XCBLK(value) ((value)<<2) /* Bits 2:4 */
237 #define XPABLK(value) ((value)<<5) /* Bits 5:6 */
238 #define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
239
240 /*********************** McBSP XCCR bit definitions *************************/
241 #define EXTCLKGATE 0x8000
242 #define PPCONNECT 0x4000
243 #define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
244 #define XFULL_CYCLE 0x0800
245 #define DILB 0x0020
246 #define XDMAEN 0x0008
247 #define XDISABLE 0x0001
248
249 /********************** McBSP RCCR bit definitions *************************/
250 #define RFULL_CYCLE 0x0800
251 #define RDMAEN 0x0008
252 #define RDISABLE 0x0001
253
254 /********************** McBSP SYSCONFIG bit definitions ********************/
255 #define CLOCKACTIVITY(value) ((value)<<8)
256 #define SIDLEMODE(value) ((value)<<3)
257 #define ENAWAKEUP 0x0004
258 #define SOFTRST 0x0002
259
260 /********************** McBSP SSELCR bit definitions ***********************/
261 #define SIDETONEEN 0x0400
262
263 /********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
264 #define ST_AUTOIDLE 0x0001
265
266 /********************** McBSP Sidetone SGAINCR bit definitions *************/
267 #define ST_CH1GAIN(value) ((value<<16)) /* Bits 16:31 */
268 #define ST_CH0GAIN(value) (value) /* Bits 0:15 */
269
270 /********************** McBSP Sidetone SFIRCR bit definitions **************/
271 #define ST_FIRCOEFF(value) (value) /* Bits 0:15 */
272
273 /********************** McBSP Sidetone SSELCR bit definitions **************/
274 #define ST_COEFFWRDONE 0x0004
275 #define ST_COEFFWREN 0x0002
276 #define ST_SIDETONEEN 0x0001
277
278 /********************** McBSP DMA operating modes **************************/
279 #define MCBSP_DMA_MODE_ELEMENT 0
280 #define MCBSP_DMA_MODE_THRESHOLD 1
281 #define MCBSP_DMA_MODE_FRAME 2
282
283 /********************** McBSP WAKEUPEN bit definitions *********************/
284 #define XEMPTYEOFEN 0x4000
285 #define XRDYEN 0x0400
286 #define XEOFEN 0x0200
287 #define XFSXEN 0x0100
288 #define XSYNCERREN 0x0080
289 #define RRDYEN 0x0008
290 #define REOFEN 0x0004
291 #define RFSREN 0x0002
292 #define RSYNCERREN 0x0001
293
294 /* CLKR signal muxing options */
295 #define CLKR_SRC_CLKR 0
296 #define CLKR_SRC_CLKX 1
297
298 /* FSR signal muxing options */
299 #define FSR_SRC_FSR 0
300 #define FSR_SRC_FSX 1
301
302 /* McBSP functional clock sources */
303 #define MCBSP_CLKS_PRCM_SRC 0
304 #define MCBSP_CLKS_PAD_SRC 1
305
306 /* we don't do multichannel for now */
307 struct omap_mcbsp_reg_cfg {
308 u16 spcr2;
309 u16 spcr1;
310 u16 rcr2;
311 u16 rcr1;
312 u16 xcr2;
313 u16 xcr1;
314 u16 srgr2;
315 u16 srgr1;
316 u16 mcr2;
317 u16 mcr1;
318 u16 pcr0;
319 u16 rcerc;
320 u16 rcerd;
321 u16 xcerc;
322 u16 xcerd;
323 u16 rcere;
324 u16 rcerf;
325 u16 xcere;
326 u16 xcerf;
327 u16 rcerg;
328 u16 rcerh;
329 u16 xcerg;
330 u16 xcerh;
331 u16 xccr;
332 u16 rccr;
333 };
334
335 typedef enum {
336 OMAP_MCBSP1 = 0,
337 OMAP_MCBSP2,
338 OMAP_MCBSP3,
339 OMAP_MCBSP4,
340 OMAP_MCBSP5
341 } omap_mcbsp_id;
342
343 typedef int __bitwise omap_mcbsp_io_type_t;
344 #define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
345 #define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
346
347 typedef enum {
348 OMAP_MCBSP_WORD_8 = 0,
349 OMAP_MCBSP_WORD_12,
350 OMAP_MCBSP_WORD_16,
351 OMAP_MCBSP_WORD_20,
352 OMAP_MCBSP_WORD_24,
353 OMAP_MCBSP_WORD_32,
354 } omap_mcbsp_word_length;
355
356 typedef enum {
357 OMAP_MCBSP_CLK_RISING = 0,
358 OMAP_MCBSP_CLK_FALLING,
359 } omap_mcbsp_clk_polarity;
360
361 typedef enum {
362 OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
363 OMAP_MCBSP_FS_ACTIVE_LOW,
364 } omap_mcbsp_fs_polarity;
365
366 typedef enum {
367 OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
368 OMAP_MCBSP_CLK_STP_MODE_DELAY,
369 } omap_mcbsp_clk_stp_mode;
370
371
372 /******* SPI specific mode **********/
373 typedef enum {
374 OMAP_MCBSP_SPI_MASTER = 0,
375 OMAP_MCBSP_SPI_SLAVE,
376 } omap_mcbsp_spi_mode;
377
378 struct omap_mcbsp_spi_cfg {
379 omap_mcbsp_spi_mode spi_mode;
380 omap_mcbsp_clk_polarity rx_clock_polarity;
381 omap_mcbsp_clk_polarity tx_clock_polarity;
382 omap_mcbsp_fs_polarity fsx_polarity;
383 u8 clk_div;
384 omap_mcbsp_clk_stp_mode clk_stp_mode;
385 omap_mcbsp_word_length word_length;
386 };
387
388 /* Platform specific configuration */
389 struct omap_mcbsp_ops {
390 void (*request)(unsigned int);
391 void (*free)(unsigned int);
392 int (*set_clks_src)(u8, u8);
393 };
394
395 struct omap_mcbsp_platform_data {
396 unsigned long phys_base;
397 u8 dma_rx_sync, dma_tx_sync;
398 u16 rx_irq, tx_irq;
399 struct omap_mcbsp_ops *ops;
400 #ifdef CONFIG_ARCH_OMAP3
401 /* Sidetone block for McBSP 2 and 3 */
402 unsigned long phys_base_st;
403 #endif
404 u16 buffer_size;
405 unsigned int mcbsp_config_type;
406 };
407
408 struct omap_mcbsp_st_data {
409 void __iomem *io_base_st;
410 bool running;
411 bool enabled;
412 s16 taps[128]; /* Sidetone filter coefficients */
413 int nr_taps; /* Number of filter coefficients in use */
414 s16 ch0gain;
415 s16 ch1gain;
416 };
417
418 struct omap_mcbsp {
419 struct device *dev;
420 unsigned long phys_base;
421 unsigned long phys_dma_base;
422 void __iomem *io_base;
423 u8 id;
424 u8 free;
425 omap_mcbsp_word_length rx_word_length;
426 omap_mcbsp_word_length tx_word_length;
427
428 omap_mcbsp_io_type_t io_type; /* IRQ or poll */
429 /* IRQ based TX/RX */
430 int rx_irq;
431 int tx_irq;
432
433 /* DMA stuff */
434 u8 dma_rx_sync;
435 short dma_rx_lch;
436 u8 dma_tx_sync;
437 short dma_tx_lch;
438
439 /* Completion queues */
440 struct completion tx_irq_completion;
441 struct completion rx_irq_completion;
442 struct completion tx_dma_completion;
443 struct completion rx_dma_completion;
444
445 /* Protect the field .free, while checking if the mcbsp is in use */
446 spinlock_t lock;
447 struct omap_mcbsp_platform_data *pdata;
448 struct clk *fclk;
449 #ifdef CONFIG_ARCH_OMAP3
450 struct omap_mcbsp_st_data *st_data;
451 int dma_op_mode;
452 u16 max_tx_thres;
453 u16 max_rx_thres;
454 #endif
455 void *reg_cache;
456 unsigned int mcbsp_config_type;
457 };
458
459 /**
460 * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod
461 * @sidetone: name of the sidetone device
462 */
463 struct omap_mcbsp_dev_attr {
464 const char *sidetone;
465 };
466
467 extern struct omap_mcbsp **mcbsp_ptr;
468 extern int omap_mcbsp_count, omap_mcbsp_cache_size;
469
470 #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
471 #define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
472
473 int omap_mcbsp_init(void);
474 void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
475 struct omap_mcbsp_platform_data *config, int size);
476 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
477 #ifdef CONFIG_ARCH_OMAP3
478 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
479 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
480 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
481 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
482 u16 omap_mcbsp_get_fifo_size(unsigned int id);
483 u16 omap_mcbsp_get_tx_delay(unsigned int id);
484 u16 omap_mcbsp_get_rx_delay(unsigned int id);
485 int omap_mcbsp_get_dma_op_mode(unsigned int id);
486 #else
omap_mcbsp_set_tx_threshold(unsigned int id,u16 threshold)487 static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
488 { }
omap_mcbsp_set_rx_threshold(unsigned int id,u16 threshold)489 static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
490 { }
omap_mcbsp_get_max_tx_threshold(unsigned int id)491 static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
omap_mcbsp_get_max_rx_threshold(unsigned int id)492 static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
omap_mcbsp_get_fifo_size(unsigned int id)493 static inline u16 omap_mcbsp_get_fifo_size(unsigned int id) { return 0; }
omap_mcbsp_get_tx_delay(unsigned int id)494 static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; }
omap_mcbsp_get_rx_delay(unsigned int id)495 static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; }
omap_mcbsp_get_dma_op_mode(unsigned int id)496 static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
497 #endif
498 int omap_mcbsp_request(unsigned int id);
499 void omap_mcbsp_free(unsigned int id);
500 void omap_mcbsp_start(unsigned int id, int tx, int rx);
501 void omap_mcbsp_stop(unsigned int id, int tx, int rx);
502 void omap_mcbsp_xmit_word(unsigned int id, u32 word);
503 u32 omap_mcbsp_recv_word(unsigned int id);
504
505 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
506 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
507 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
508 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
509
510
511 /* McBSP functional clock source changing function */
512 extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
513 /* SPI specific API */
514 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
515
516 /* Polled read/write functions */
517 int omap_mcbsp_pollread(unsigned int id, u16 * buf);
518 int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
519 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
520
521 /* McBSP signal muxing API */
522 void omap2_mcbsp1_mux_clkr_src(u8 mux);
523 void omap2_mcbsp1_mux_fsr_src(u8 mux);
524
525 int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
526 int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
527
528 #ifdef CONFIG_ARCH_OMAP3
529 /* Sidetone specific API */
530 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
531 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
532 int omap_st_enable(unsigned int id);
533 int omap_st_disable(unsigned int id);
534 int omap_st_is_enabled(unsigned int id);
535 #else
omap_st_set_chgain(unsigned int id,int channel,s16 chgain)536 static inline int omap_st_set_chgain(unsigned int id, int channel,
537 s16 chgain) { return 0; }
omap_st_get_chgain(unsigned int id,int channel,s16 * chgain)538 static inline int omap_st_get_chgain(unsigned int id, int channel,
539 s16 *chgain) { return 0; }
omap_st_enable(unsigned int id)540 static inline int omap_st_enable(unsigned int id) { return 0; }
omap_st_disable(unsigned int id)541 static inline int omap_st_disable(unsigned int id) { return 0; }
omap_st_is_enabled(unsigned int id)542 static inline int omap_st_is_enabled(unsigned int id) { return 0; }
543 #endif
544
545 #endif
546