1 /*
2 * linux/arch/arm/plat-mxc/epit.c
3 *
4 * Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21 #define EPITCR 0x00
22 #define EPITSR 0x04
23 #define EPITLR 0x08
24 #define EPITCMPR 0x0c
25 #define EPITCNR 0x10
26
27 #define EPITCR_EN (1 << 0)
28 #define EPITCR_ENMOD (1 << 1)
29 #define EPITCR_OCIEN (1 << 2)
30 #define EPITCR_RLD (1 << 3)
31 #define EPITCR_PRESC(x) (((x) & 0xfff) << 4)
32 #define EPITCR_SWR (1 << 16)
33 #define EPITCR_IOVW (1 << 17)
34 #define EPITCR_DBGEN (1 << 18)
35 #define EPITCR_WAITEN (1 << 19)
36 #define EPITCR_RES (1 << 20)
37 #define EPITCR_STOPEN (1 << 21)
38 #define EPITCR_OM_DISCON (0 << 22)
39 #define EPITCR_OM_TOGGLE (1 << 22)
40 #define EPITCR_OM_CLEAR (2 << 22)
41 #define EPITCR_OM_SET (3 << 22)
42 #define EPITCR_CLKSRC_OFF (0 << 24)
43 #define EPITCR_CLKSRC_PERIPHERAL (1 << 24)
44 #define EPITCR_CLKSRC_REF_HIGH (1 << 24)
45 #define EPITCR_CLKSRC_REF_LOW (3 << 24)
46
47 #define EPITSR_OCIF (1 << 0)
48
49 #include <linux/interrupt.h>
50 #include <linux/irq.h>
51 #include <linux/clockchips.h>
52 #include <linux/clk.h>
53
54 #include <mach/hardware.h>
55 #include <asm/mach/time.h>
56 #include <mach/common.h>
57
58 static struct clock_event_device clockevent_epit;
59 static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
60
61 static void __iomem *timer_base;
62
epit_irq_disable(void)63 static inline void epit_irq_disable(void)
64 {
65 u32 val;
66
67 val = __raw_readl(timer_base + EPITCR);
68 val &= ~EPITCR_OCIEN;
69 __raw_writel(val, timer_base + EPITCR);
70 }
71
epit_irq_enable(void)72 static inline void epit_irq_enable(void)
73 {
74 u32 val;
75
76 val = __raw_readl(timer_base + EPITCR);
77 val |= EPITCR_OCIEN;
78 __raw_writel(val, timer_base + EPITCR);
79 }
80
epit_irq_acknowledge(void)81 static void epit_irq_acknowledge(void)
82 {
83 __raw_writel(EPITSR_OCIF, timer_base + EPITSR);
84 }
85
epit_read(struct clocksource * cs)86 static cycle_t epit_read(struct clocksource *cs)
87 {
88 return 0 - __raw_readl(timer_base + EPITCNR);
89 }
90
91 static struct clocksource clocksource_epit = {
92 .name = "epit",
93 .rating = 200,
94 .read = epit_read,
95 .mask = CLOCKSOURCE_MASK(32),
96 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
97 };
98
epit_clocksource_init(struct clk * timer_clk)99 static int __init epit_clocksource_init(struct clk *timer_clk)
100 {
101 unsigned int c = clk_get_rate(timer_clk);
102
103 clocksource_register_hz(&clocksource_epit, c);
104
105 return 0;
106 }
107
108 /* clock event */
109
epit_set_next_event(unsigned long evt,struct clock_event_device * unused)110 static int epit_set_next_event(unsigned long evt,
111 struct clock_event_device *unused)
112 {
113 unsigned long tcmp;
114
115 tcmp = __raw_readl(timer_base + EPITCNR);
116
117 __raw_writel(tcmp - evt, timer_base + EPITCMPR);
118
119 return 0;
120 }
121
epit_set_mode(enum clock_event_mode mode,struct clock_event_device * evt)122 static void epit_set_mode(enum clock_event_mode mode,
123 struct clock_event_device *evt)
124 {
125 unsigned long flags;
126
127 /*
128 * The timer interrupt generation is disabled at least
129 * for enough time to call epit_set_next_event()
130 */
131 local_irq_save(flags);
132
133 /* Disable interrupt in GPT module */
134 epit_irq_disable();
135
136 if (mode != clockevent_mode) {
137 /* Set event time into far-far future */
138
139 /* Clear pending interrupt */
140 epit_irq_acknowledge();
141 }
142
143 /* Remember timer mode */
144 clockevent_mode = mode;
145 local_irq_restore(flags);
146
147 switch (mode) {
148 case CLOCK_EVT_MODE_PERIODIC:
149 printk(KERN_ERR "epit_set_mode: Periodic mode is not "
150 "supported for i.MX EPIT\n");
151 break;
152 case CLOCK_EVT_MODE_ONESHOT:
153 /*
154 * Do not put overhead of interrupt enable/disable into
155 * epit_set_next_event(), the core has about 4 minutes
156 * to call epit_set_next_event() or shutdown clock after
157 * mode switching
158 */
159 local_irq_save(flags);
160 epit_irq_enable();
161 local_irq_restore(flags);
162 break;
163 case CLOCK_EVT_MODE_SHUTDOWN:
164 case CLOCK_EVT_MODE_UNUSED:
165 case CLOCK_EVT_MODE_RESUME:
166 /* Left event sources disabled, no more interrupts appear */
167 break;
168 }
169 }
170
171 /*
172 * IRQ handler for the timer
173 */
epit_timer_interrupt(int irq,void * dev_id)174 static irqreturn_t epit_timer_interrupt(int irq, void *dev_id)
175 {
176 struct clock_event_device *evt = &clockevent_epit;
177
178 epit_irq_acknowledge();
179
180 evt->event_handler(evt);
181
182 return IRQ_HANDLED;
183 }
184
185 static struct irqaction epit_timer_irq = {
186 .name = "i.MX EPIT Timer Tick",
187 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
188 .handler = epit_timer_interrupt,
189 };
190
191 static struct clock_event_device clockevent_epit = {
192 .name = "epit",
193 .features = CLOCK_EVT_FEAT_ONESHOT,
194 .shift = 32,
195 .set_mode = epit_set_mode,
196 .set_next_event = epit_set_next_event,
197 .rating = 200,
198 };
199
epit_clockevent_init(struct clk * timer_clk)200 static int __init epit_clockevent_init(struct clk *timer_clk)
201 {
202 unsigned int c = clk_get_rate(timer_clk);
203
204 clockevent_epit.mult = div_sc(c, NSEC_PER_SEC,
205 clockevent_epit.shift);
206 clockevent_epit.max_delta_ns =
207 clockevent_delta2ns(0xfffffffe, &clockevent_epit);
208 clockevent_epit.min_delta_ns =
209 clockevent_delta2ns(0x800, &clockevent_epit);
210
211 clockevent_epit.cpumask = cpumask_of(0);
212
213 clockevents_register_device(&clockevent_epit);
214
215 return 0;
216 }
217
epit_timer_init(struct clk * timer_clk,void __iomem * base,int irq)218 void __init epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
219 {
220 clk_enable(timer_clk);
221
222 timer_base = base;
223
224 /*
225 * Initialise to a known state (all timers off, and timing reset)
226 */
227 __raw_writel(0x0, timer_base + EPITCR);
228
229 __raw_writel(0xffffffff, timer_base + EPITLR);
230 __raw_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
231 timer_base + EPITCR);
232
233 /* init and register the timer to the framework */
234 epit_clocksource_init(timer_clk);
235 epit_clockevent_init(timer_clk);
236
237 /* Make irqs happen */
238 setup_irq(irq, &epit_timer_irq);
239 }
240