1 /* arch/arm/plat-s3c64xx/include/plat/regs-syscon-power.h
2  *
3  * Copyright 2008 Openmoko, Inc.
4  * Copyright 2008 Simtec Electronics
5  *      http://armlinux.simtec.co.uk/
6  *      Ben Dooks <ben@simtec.co.uk>
7  *
8  * S3C64XX - syscon power and sleep control registers
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13 */
14 
15 #ifndef __PLAT_S3C64XX_REGS_SYSCON_POWER_H
16 #define __PLAT_S3C64XX_REGS_SYSCON_POWER_H __FILE__
17 
18 #define S3C64XX_PWR_CFG				S3C_SYSREG(0x804)
19 
20 #define S3C64XX_PWRCFG_OSC_OTG_DISABLE		(1 << 17)
21 #define S3C64XX_PWRCFG_MMC2_DISABLE		(1 << 16)
22 #define S3C64XX_PWRCFG_MMC1_DISABLE		(1 << 15)
23 #define S3C64XX_PWRCFG_MMC0_DISABLE		(1 << 14)
24 #define S3C64XX_PWRCFG_HSI_DISABLE		(1 << 13)
25 #define S3C64XX_PWRCFG_TS_DISABLE		(1 << 12)
26 #define S3C64XX_PWRCFG_RTC_TICK_DISABLE		(1 << 11)
27 #define S3C64XX_PWRCFG_RTC_ALARM_DISABLE	(1 << 10)
28 #define S3C64XX_PWRCFG_MSM_DISABLE		(1 << 9)
29 #define S3C64XX_PWRCFG_KEY_DISABLE		(1 << 8)
30 #define S3C64XX_PWRCFG_BATF_DISABLE		(1 << 7)
31 
32 #define S3C64XX_PWRCFG_CFG_WFI_MASK		(0x3 << 5)
33 #define S3C64XX_PWRCFG_CFG_WFI_SHIFT		(5)
34 #define S3C64XX_PWRCFG_CFG_WFI_IGNORE		(0x0 << 5)
35 #define S3C64XX_PWRCFG_CFG_WFI_IDLE		(0x1 << 5)
36 #define S3C64XX_PWRCFG_CFG_WFI_STOP		(0x2 << 5)
37 #define S3C64XX_PWRCFG_CFG_WFI_SLEEP		(0x3 << 5)
38 
39 #define S3C64XX_PWRCFG_CFG_BATFLT_MASK		(0x3 << 3)
40 #define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT		(3)
41 #define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE	(0x0 << 3)
42 #define S3C64XX_PWRCFG_CFG_BATFLT_IRQ		(0x1 << 3)
43 #define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP		(0x3 << 3)
44 
45 #define S3C64XX_PWRCFG_CFG_BAT_WAKE		(1 << 2)
46 #define S3C64XX_PWRCFG_OSC27_EN			(1 << 0)
47 
48 #define S3C64XX_EINT_MASK			S3C_SYSREG(0x808)
49 
50 #define S3C64XX_NORMAL_CFG			S3C_SYSREG(0x810)
51 
52 #define S3C64XX_NORMALCFG_IROM_ON		(1 << 30)
53 #define S3C64XX_NORMALCFG_DOMAIN_ETM_ON		(1 << 16)
54 #define S3C64XX_NORMALCFG_DOMAIN_S_ON		(1 << 15)
55 #define S3C64XX_NORMALCFG_DOMAIN_F_ON		(1 << 14)
56 #define S3C64XX_NORMALCFG_DOMAIN_P_ON		(1 << 13)
57 #define S3C64XX_NORMALCFG_DOMAIN_I_ON		(1 << 12)
58 #define S3C64XX_NORMALCFG_DOMAIN_G_ON		(1 << 10)
59 #define S3C64XX_NORMALCFG_DOMAIN_V_ON		(1 << 9)
60 
61 #define S3C64XX_STOP_CFG			S3C_SYSREG(0x814)
62 
63 #define S3C64XX_STOPCFG_MEMORY_ARM_ON		(1 << 29)
64 #define S3C64XX_STOPCFG_TOP_MEMORY_ON		(1 << 20)
65 #define S3C64XX_STOPCFG_ARM_LOGIC_ON		(1 << 17)
66 #define S3C64XX_STOPCFG_TOP_LOGIC_ON		(1 << 8)
67 #define S3C64XX_STOPCFG_OSC_EN			(1 << 0)
68 
69 #define S3C64XX_SLEEP_CFG			S3C_SYSREG(0x818)
70 
71 #define S3C64XX_SLEEPCFG_OSC_EN			(1 << 0)
72 
73 #define S3C64XX_STOP_MEM_CFG			S3C_SYSREG(0x81c)
74 
75 #define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN	(1 << 6)
76 #define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN	(1 << 5)
77 #define S3C64XX_STOPMEMCFG_OTG_RETAIN		(1 << 4)
78 #define S3C64XX_STOPMEMCFG_HSMCC_RETAIN		(1 << 3)
79 #define S3C64XX_STOPMEMCFG_IROM_RETAIN		(1 << 2)
80 #define S3C64XX_STOPMEMCFG_IRDA_RETAIN		(1 << 1)
81 #define S3C64XX_STOPMEMCFG_NFCON_RETAIN		(1 << 0)
82 
83 #define S3C64XX_OSC_STABLE			S3C_SYSREG(0x824)
84 #define S3C64XX_PWR_STABLE			S3C_SYSREG(0x828)
85 
86 #define S3C64XX_WAKEUP_STAT			S3C_SYSREG(0x908)
87 
88 #define S3C64XX_WAKEUPSTAT_MMC2			(1 << 11)
89 #define S3C64XX_WAKEUPSTAT_MMC1			(1 << 10)
90 #define S3C64XX_WAKEUPSTAT_MMC0			(1 << 9)
91 #define S3C64XX_WAKEUPSTAT_HSI			(1 << 8)
92 #define S3C64XX_WAKEUPSTAT_BATFLT		(1 << 6)
93 #define S3C64XX_WAKEUPSTAT_MSM			(1 << 5)
94 #define S3C64XX_WAKEUPSTAT_KEY			(1 << 4)
95 #define S3C64XX_WAKEUPSTAT_TS			(1 << 3)
96 #define S3C64XX_WAKEUPSTAT_RTC_TICK		(1 << 2)
97 #define S3C64XX_WAKEUPSTAT_RTC_ALARM		(1 << 1)
98 #define S3C64XX_WAKEUPSTAT_EINT			(1 << 0)
99 
100 #define S3C64XX_BLK_PWR_STAT			S3C_SYSREG(0x90c)
101 
102 #define S3C64XX_BLKPWRSTAT_G			(1 << 7)
103 #define S3C64XX_BLKPWRSTAT_ETM			(1 << 6)
104 #define S3C64XX_BLKPWRSTAT_S			(1 << 5)
105 #define S3C64XX_BLKPWRSTAT_F			(1 << 4)
106 #define S3C64XX_BLKPWRSTAT_P			(1 << 3)
107 #define S3C64XX_BLKPWRSTAT_I			(1 << 2)
108 #define S3C64XX_BLKPWRSTAT_V			(1 << 1)
109 #define S3C64XX_BLKPWRSTAT_TOP			(1 << 0)
110 
111 #define S3C64XX_INFORM0				S3C_SYSREG(0xA00)
112 #define S3C64XX_INFORM1				S3C_SYSREG(0xA04)
113 #define S3C64XX_INFORM2				S3C_SYSREG(0xA08)
114 #define S3C64XX_INFORM3				S3C_SYSREG(0xA0C)
115 
116 #endif /* __PLAT_S3C64XX_REGS_SYSCON_POWER_H */
117